33 GHz to 40 GHz, GaAs, pHEMT, MMIC, 1 W
Power Amplifier with Power Detector
Data Sheet
HMC7229CHIPS
Rev. 0 Document Feedback
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FEATURES
32 dBm PSAT with 22% PAE
P1dB POUT: 31.5 dBm
High OIP3: 39.5 dBm
High gain: 24.5 dB
50 Ω matched input/output
APPLICATIONS
Point to point radios
Point to multipoint Radio
VSAT and SATCOM
GENERAL DESCRIPTION
The HMC7229CHIPS is a four-stage, gallium arsenide (GaAs),
pseudomorphic high electron mobility transfer (pHEMT),
monolithic microwave integrated circuit (MMIC), 1 W power
amplifier with an integrated temperature compensated on-chip
power detector, operating between 33 GHz and 40 GHz. The
HMC7229CHIPS provides a typical range of 23 dB to 24.5 dB of
gain and a range of 30 dBm to 32 dBm of saturated output power
(PSAT) with 12% to 22% (typical) power added efficiency (PAE)
range across a band of 33 GHz to 40 GHz from a 6 V supply. With
an excellent OIP3 with a range of 37 dBm to 39.5 dBm across a
band of 33 GHz to 40 GHz, the HMC7229CHIPS is ideal for linear
applications such as high capacity point to point or point to
multipoint radios or very small aperture terminal (VSAT)/satellite
communications (SATCOM) applications demanding 32 dBm of
efficient saturated output power. The radio frequency (RF) input/
output ports are internally matched and dc blocked for easy
integration into higher level assemblies.
FUNCTIONAL BLOCK DIAGRAM
HMC7229CHIPS
V
DD4
V
DD3
V
DD1
V
DD2
V
GG1
V
DD8
V
DD7
V
DD5
V
DD6
V
GG2
V
REF
V
DET
RFIN RFOUT
2
1 8
9
3 4 5 6
7
14 13 12 11 10
14566-001
Figure 1.
HMC7229CHIPS Data Sheet
Rev. 0 | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
33 GHz to 35 GHz Frequency Range ......................................... 3
35 GHz to 37 GHz Frequency Range ......................................... 3
37 GHz to 40 GHz Frequency Range ......................................... 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Interface Schematics..................................................................... 7
Typical Performance Characteristics ..............................................8
Theory of Operation ...................................................................... 12
Applications Information .............................................................. 13
Mounting and Bonding Techniques for Millimeter Wave
GaAs MMICs .............................................................................. 13
Handling Precautions ................................................................ 13
Mounting ..................................................................................... 13
Biasing Procedures ..................................................................... 13
Typical Application Circuit ....................................................... 14
Assembly Diagram ..................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
REVISION HISTORY
6/2016—Revision 0: Initial Version
Data Sheet HMC7229CHIPS
Rev. 0 | Page 3 of 16
SPECIFICATIONS
33 GHz TO 35 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 33 35 GHz
GAIN 21 23 dB
Gain Variation Over Temperature 0.035 dB/°C
RETURN LOSS
Input 7 dB
Output 15 dB
OUTPUT
Output Power for 1 dB Compression P1dB 29.5 31.5 dBm
Saturated Output Power PSAT 32 dBm
Power Added Efficiency PAE PAE taken at saturated output power 22 %
Output Third-Order Intercept
OIP3
Measurement taken at P
OUT
/tone = 20 dBm
39.5
dBm
SUPPLY CURRENT IDQ 3 800 1200 mA
SUPPLY VOLTAGE VDD 5 6 V
1 Recommended bias conditions.
2 Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
35 GHz TO 37 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 35 37 GHz
GAIN 22.5 24.5 dB
Gain Variation Over Temperature 0.044 dB/°C
RETURN LOSS
Input 9.5 dB
Output 20 dB
OUTPUT
Output Power for 1 dB Compression P1dB 28.5 30.5 dBm
Saturated Output Power PSAT 31 dBm
Power Added Efficiency PAE PAE taken at saturated output power 16 %
Output Third-Order Intercept OIP3 Measurement taken at POUT/tone = 20 dBm 39 dBm
SUPPLY CURRENT IDQ3 800 1200 mA
SUPPLY VOLTAGE VDD 5 6 V
1 Recommended bias conditions.
2Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
HMC7229CHIPS Data Sheet
Rev. 0 | Page 4 of 16
37 GHz TO 40 GHz FREQUENCY RANGE
TA = 25°C, VDD = VDD1 = VDD2 = VDD3 = VDD4 = VDD5 = VDD6 = VDD7 = VDD8 = 6 V, IDQ = 1200 mA.1, 2
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 37 40 GHz
GAIN 21.5 23.5 dB
Gain Variation Over Temperature 0.045 dB/°C
RETURN LOSS
Input 9.5 dB
Output
13
dB
OUTPUT
Output Power for 1 dB Compression P1dB 27.5 29.5 dBm
Saturated Output Power PSAT 30 dBm
Power Added Efficiency PAE PAE taken at saturated output power 12 %
Output Third-Order Intercept OIP3 Measurement taken at POUT/tone = 20 dBm 37 dBm
SUPPLY CURRENT IDQ3 800 1200 mA
SUPPLY VOLTAGE VDD 5 6 V
1 Recommended bias conditions.
2 Adjust the VGGx supply voltage between −2 V and 0 V to achieve IDQ = 1200 mA.
3 IDQ is the drain current without applying RF power.
Data Sheet HMC7229CHIPS
Rev. 0 | Page 5 of 16
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Rating
Drain Bias Voltage (VDD) 7 V
RF Input Power (RFIN)
21 dBm
Channel Temperature 175°C
Continuous Power Dissipation (PDISS),
TA = 85°C (Derate 107 mW/°C Above 85°C)
9.7 W
Thermal Resistance, θJC (Channel to
Bottom Die)
9.3°C/W
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −55°C to +85°C
ESD Sensitivity, Human Body Model (HBM) Class 0, passed 150 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
HMC7229CHIPS Data Sheet
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD4
VDD3
VDD1 VDD2
VGG1
VDD8
VDD7
VDD5 VDD6
VGG2
VREF
HMC7229CHIPS
VDET
RFIN RFOUT
2
1 8
9
3 4 5 6
7
14 13 12 11 10
14566-002
Figure 2. Pad Configuration
Table 5. Pad Function Descriptions
Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω.
2, 14 VGG1, VGG2 Gate Controls for the Power Amplifier. Adjust the VGG1 or VGG2 supply voltage to achieve recommended bias
current. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required.
3 to 6,
10 to 13
VDD1 to VDD8 Drain Bias Voltages. External 100 pF, 10 nF, and 4.7 μF bypass capacitors are required.
7 VREF DC Voltage of the Diode. This pad is biased through an external detector circuit used for temperature
compensation of VDET (see Figure 36).
8 RFOUT RF Output. This pin is ac-coupled and matched to 50 Ω.
9 VDET DC Voltage Representing the RF Output Power. This pad is rectified by the diode that is biased through
an external resistor (see Figure 36).
Die Bottom GND Die Bottom. The die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
Data Sheet HMC7229CHIPS
Rev. 0 | Page 7 of 16
INTERFACE SCHEMATICS
RFIN
14566-003
Figure 3. RFIN Interface Schematic
14566-004
VGG1, VGG2
Figure 4. VGG1,VGG2 Interface Schematic
14566-005
V
DD1
TO V
DD8
Figure 5. VDD1 to VDD8 Interface Schematic
14566-006
V
REF
Figure 6. VREF Interface Schematic
RFOUT
14566-007
Figure 7. RFOUT Interface Schematic
14566-008
VDET
Figure 8. VDET Interface Schematic
14566-009
GND
Figure 9. GND Interface Schematic
HMC7229CHIPS Data Sheet
Rev. 0 | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–30
–20
–10
0
10
20
30
32 33 34 35 36 37 38 39 40 41
RESPONSE (dB)
FREQUENCY ( GHz)
S21
S11
S22
14566-010
Figure 10. Response Gain and Return Loss vs. Frequency
–20
–15
–10
–5
0
33 34 35 36 37 38 39 40
INPUT RETURN LOSS (dB)
FREQUENCY (GHz)
14566-011
+25°C
+85°C
–55°C
Figure 11. Input Return Loss vs. Frequency at Various Temperatures
24
26
28
30
32
34
33 34 35 36 37 38 39 40
P1d B ( dBm)
FREQUENCY ( GHz)
+25°C
+85°C
–55°C
14566-012
Figure 12. P1dB vs. Frequency at Various Temperatures
18
20
22
24
26
28
30
33 34 35 36 37 38 39 40
GAI N (dB)
FRE Q UE NCY ( GHz)
+25°C
+85°C
–55°C
14566-013
Figure 13. Gain vs. Frequency at Various Temperatures
–30
–25
–20
–15
–10
–5
0
33 34 35 36 37 38 39 40
OUTPUT RE TURN L OSS ( dB)
+25°C
+85°C
–55°C
FRE Q UE NCY ( GHz)
14566-014
Figure 14. Output Return Loss vs. Frequency at Various Temperatures
33 34 35 36 37 38 39 40
FREQUENCY (GHz)
24
26
28
30
32
34
P1d B ( dBm)
5.0V
5.5V
6.0V
14566-015
Figure 15. P1dB vs. Frequency at Various Supply Voltages
Data Sheet HMC7229CHIPS
Rev. 0 | Page 9 of 16
33 34 35 3637 38 39 40
FREQUENCY(GHz)
24
26
28
30
32
34
P
SAT
(d Bm)
14566-016
+25°C
+85°C
–55°C
Figure 16. PSAT vs. Frequency at Various Temperatures
33 34 35 36 37 38 39 40
FREQUENCY (GHz)
24
26
28
30
32
34
P1dB (dBm)
14566-017
1000mA
1200mA
800mA
Figure 17. P1dB vs. Frequency at Various Supply Currents
1045
1100
1155
1210
1265
1320
1375
1430
0
5
10
15
20
25
30
35
–10 –8 –6 –4 –2 0 2 4 6 8 10 12
IDD ( mA)
POUT (d Bm) , G AIN (dB), PAE ( %)
INPUT POW E R ( dBm)
POUT
GAIN
PAE
IDD
14566-018
Figure 18. Power Compression at 34 GHz
(IDD is Drain Current With RF Power Applied)
33 34 35 36 37 3839 40
FREQUENCY (GHz)
24
26
28
30
32
34
P
SAT
(d Bm)
14566-019
5.0V
5.5V
6.0V
Figure 19. PSAT vs. Frequency at Various Supply Voltages
33 34 35 36 37 38 39 40
FREQUENCY (GHz)
24
26
28
30
32
34
PSAT (d Bm)
14566-020
1000mA
1200mA
800mA
Figure 20. PSAT vs. Frequency at Various Supply Currents
1145
1200
1255
1310
1365
1420
1475
1530
0
5
10
15
20
25
30
35
–10 –8 –6 –4 –2 0 2 4 6 8 10 12
IDD ( mA)
POUT (d Bm) , G AIN (dB), PAE ( %)
INPUT POW E R ( dBm)
POUT
GAIN
PAE
IDD
14566-021
Figure 21. Power Compression at 39 GHz
HMC7229CHIPS Data Sheet
Rev. 0 | Page 10 of 16
30
32
34
36
38
40
42
44
33 34 35 36 37 38 39 40
OI P 3 ( dBm)
FREQUENCY ( GHz)
+25°C
+85°C
–55°C
14566-022
Figure 22. Output IP3 vs. Frequency at Various Temperatures
30
32
34
36
38
40
42
44
33 34 35 36 37 38 39 40
OI P 3 ( dBm)
FREQUENCY ( GHz)
14566-023
1000mA
1200mA
800mA
Figure 23. Output IP3 vs. Frequency at Various Supply Current
20
25
30
35
40
45
50
55
60
10 12 14 16 18 20 22 24
IM 3 ( dBc)
P
OUT
/TONE (dBm)
14566-024
33GHz
34GHz
36GHZ
38GHz
39GHz
40GHz
Figure 24. Third-Order Intermodulation (IM3) vs. POUT/Tone for Various
Frequencies at VDD = 6 V
30
32
34
36
38
40
42
44
33 34 35 36 37 38 39 40
OI P 3 ( dBm)
FREQUENCY ( GHz)
14566-025
5.0V
5.5V
6.0V
Figure 25. Output IP3 vs. Frequency at Various Supply Voltages
20
25
30
35
40
45
50
55
60
10 12 14 16 18 20 22 24
IM 3 ( dBc)
POUT/TONE (dBm)
33GHz
34GHz
36GHZ
38GHz
39GHz
40GHz
14566-026
Figure 26. IM3 vs. POUT/Tone for Various Frequencies at VDD = 5.5 V
20
25
30
35
40
45
50
55
60
10 12 14 16 18 20 22 24
IM 3 ( dBc)
P
OUT
/TONE (dBm)
33GHz
34GHz
36GHZ
38GHz
39GHz
40GHz
14566-027
Figure 27. IM3 vs. POUT/Tone for Various Frequencies at VDD = 5 V
Data Sheet HMC7229CHIPS
Rev. 0 | Page 11 of 16
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
33 34 35 36 37 38 39 40
REVERSE ISOLATION (d B)
FRE Q UE NCY ( GHz)
+25°C
+85°C
–55°C
14566-028
Figure 28. Reverse Isolation vs. Frequency for Various Temperatures
20
23
26
29
32
35
5.0 5.2 5.4 5.6 5.8 6.0
GAI N (dB) , P1dB (dBm), P
SAT
(d Bm)
V
DD
(V)
GAIN
P1dB
P
SAT
14566-029
Figure 29. Gain, P1dB, and PSAT vs Supply Voltage (VDD) at 36 GHz
GAI N (dB) , P1dB (dBm), PSAT ( dBm)
20
23
26
29
32
35
800 900 1000 1100 1200
IDQ ( mA)
GAIN
P1dB
PSAT
14566-030
Figure 30. Gain, P1dB, and PSAT vs. Supply Current (IDQ) at 36 GHz
4.0
4.5
5.0
5.5
6.0
6.5
7.0
7.5
8.0
8.5
9.0
–10 –8 –6 –4 –2 0246810 12 14
POWER DISSIPATI O N (W)
INPUT POW E R ( dBm)
33GHz
34GHz
36GHZ
37GHz
39GHz
40GHz
14566-031
Figure 31. Power Dissipation vs. Input Power for Various Frequencies
at TA = 85°C
0.1m
1m
10m
100m
1
10
–20 –10 010 20 30
V
DET
(V)
OUT P UT POW E R ( dBm)
+25°C
+85°C
–55°C
14566-032
Figure 32. Detector Voltage (VDET) vs. Output Power at 38.5 GHz at Various
Temperatures
0
5
10
15
20
25
PAE (%)
33 34 35 36 37 38 39 40
FREQUENCY ( GHz)
14566-033
Figure 33. PAE at PSAT vs Frequency
HMC7229CHIPS Data Sheet
Rev. 0 | Page 12 of 16
THEORY OF OPERATION
The HMC7229CHIPS is a GaAs, pHEMT, MMIC, 1 W power
amplifier consisting of four gain stages in series. Figure 34
shows a simplified functional block diagram of the
HMC7229CHIPS.
The input signal of the HMC7229CHIPS is evenly divided into
two paths and each path is amplified through the four independent
gain stages. The amplified signals are then combined at the RF
output.
The HMC7229CHIPS has single-ended input and output ports
with impedances nominally matched to 50 Ω internally over the
frequency range from 33 GHz to 40 GHz. Consequently, the
HMC7229CHIPS can be directly inserted into a 50 Ω system
with no impedance matching circuitry required.
Impedences nominally matched to a 50 Ω system also means
that multiple HMC7229CHIPS amplifiers can be cascaded back
to back without external matching circuitr y.
Similarly, multiple HMC7229CHIPS can be used with power
dividers at the RF input and power combiners at the RF output
to obtain higher output power levels.
The input and output impedances are sufficiently stable compared
to the variations in temperature and supply voltage that no
impedance matching compensation is required.
It is critical to supply very low inductance ground connections
to the backside of the HMC7229CHIPS, ensuring stable
operation. Guidance on mounting the HMC7229CHIPS is given
in the Mounting and Bonding Techniques for Millimeter Wave
GaAs MMICs section.
To achieve the best performance from the HMC7229CHIPS
and not to damage the device, do not exceed the absolute
maximum ratings.
14566-034
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VGG1
OR
VGG2
VDD1
VDD5
VDD2
VDD6
VDD3
VDD7
VDD4
VDD8
RFOUTRFIN
Figure 34. Simplified Functional Block Diagram
Data Sheet HMC7229CHIPS
Rev. 0 | Page 13 of 16
APPLICATIONS INFORMATION
MOUNTING AND BONDING TECHNIQUES FOR
MILLIMETER WAVE GaAs MMICs
Attach the HMC7229CHIPS directly to the ground plane
eutectically or with a conductive epoxy. To route the RF signal
to and from the HMC7229CHIPS, use a 50 Ω microstrip
transmission line on 0.127 mm (0.005 inches) thick alumina, thin
film substrates (see Figure 35).
RF GROUND P LANE
0.102mm ( 0. 004") THI CK GaAs MM IC
RIBBO N BOND
0.127mm ( 0. 005") THI CK ALUMINA,
THIN FILM SUBSTRATE
0.076mm
(0.003")
14566-035
Figure 35. Routing RF Signals
To minimize the bond wire length, place microstrip substrates
as close to the HMC7229CHIPS as possible. Typical chip to
substrate spacing is 0.076 mm to 0.152 mm (0.003 inches and
0.006 inches).
HANDLING PRECAUTIONS
To avoid permanent damage to the device, adhere to the following
precautions:
• All bare HMC7229CHIPS ship in either waffle or gel-based
ESD protective containers, sealed in an ESD protective bag.
After opening the sealed ESD protective bag, store all chips in
a dry nitrogen environment.
• Handle the HMC7229CHIPS in a clean environment.
Never use liquid cleaning systems to clean the chip.
• Follow ESD precautions to protect against ESD strikes.
• While applying bias, suppress instrument and bias supply
transients. To minimize inductive pickup, use shielded
signal and bias cables.
• Handle the HMC7229CHIPS along the edges with a vacuum
collet or a sharp pair of bent tweezers. The surface of the chip
has fragile air bridges and must not be touched with a vacuum
collet, tweezers, or fingers.
MOUNTING
The HMC7229CHIPS is back metallized and can be die mounted
onto a system with Au/Sn eutectic preforms or with electrically
conductive epoxy. The mounting surface must be clean and flat.
Eutectic Die Attach
It is best to use an 80% Au/20% Sn preform with a work surface
temperature of 255°C and a tool temperature of 265°C. When the
work surface is 255°C and tool temperature is 265°C, 90% nitrogen/
10% hydrogen gas is applied to the work surface, maintain the
tool tip temperature at 290°C. Do not expose the HMC7229CHIPS
to a temperature greater than 320°C for more than 20 sec. No
more than 3 sec of scrubbing is required for attachment.
Epoxy Die Attach
The ABLETHERM 2600BT is recommended for chip attachment.
Apply a minimum amount of epoxy to the mounting surface so
a thin epoxy fillet is observed around the perimeter of the
HMC7229CHIPS after placing the device into position on
the surface. Cure the epoxy per the schedule provided by the
manufacturer.
Wire Bonding
RF bonds made with 0.003 in. × 0.0005 in. Au ribbon are recom-
mended for the RF ports. These bonds must be thermosonically
bonded with a force of 40 g to 60 g. DC bonds of 1 mil (0.025 mm)
diameter, thermosonically bonded, are recommended. Create ball
bonds with a force of 40 g to 50 g and wedge bonds with a force of
18 g to 22 g. Create all bonds with a nominal stage temperature of
150°C. Apply a minimum amount of ultrasonic energy to achieve
reliable bonds. Keep all bonds as short as possible, less than 12 mil
(0.31 mm).
BIASING PROCEDURES
The basic connections for operating the HMC7229CHIPS are
shown in the Typical Application Circuit section and the Theory
of Operation section. The RF input and RF output are ac-coupled
by internal dc block capacitors. Follow the recommended bias
sequencing to avoid damaging the amplifier.
The amplifier gate bias can be supplied using either the VGG1 pin
or VGG2 pin. Use the VDD1 to VDD8 pins while applying the drain bias
to the amplifier. Tes ting to gather data for the HMC7229CHIPS
data sheet used the VGG1 pin with the VDD1 to VDD8 pins connected
together.
Use the following recommended bias sequence during power-up:
1. Connect GND to RF/dc ground.
2. Set VGG1 or VGG2 to −2 V.
3. Set VDD1 to VDD8 to 6 V.
4. Increase VGG1 or VGG2 to achieve a typical IDQ = 1200 mA.
5. Apply an RF signal the device.
Use the following recommended bias sequence during power-
down:
1. Turn off the RF signal
2. Decrease VGG1 or VGG2 to −2 V to achieve IDQ = 0 mA.
3. Decrease VDD1, VDD2, VDD3, and VDD4 to 0 V.
4. Increase VGG1 or VGG2 to 0 V.
HMC7229CHIPS Data Sheet
Rev. 0 | Page 14 of 16
The bias conditions listed at VDD = 6 V, IDQ = 1200 is a
recommended operating point to receive optimum performance
from the HMC7229CHIPS. The data used in this data sheet is
taken with the recommended bias conditions (see the
Specifications section).
Using the HMC7229CHIPS in a different bias condition may
provide different performance than the performance shown in
the Typical Performance Characteristics section.
The VDET and VREF pins are the output pins for the internal
power detector. The VDET pin is the dc voltage output pin
representing the RF output power rectified by the internal
diode, biased through an external resistor.
The VREF pin is the dc voltage output pin representing the
reference diode voltage, which is biased through an external
resistor. The reference diode voltage compensates the temperature
variation effects on both the VREF and VDET diodes. Figure 36
shows a suggested circuit to read out the output voltage in
correlation with the RF output power.
TYPICAL APPLICATION CIRCUIT
SUGGES TED CIRCUI T
–5V
+5V
+5V
VREF VOUT = VREF – VDET
VDET
0.1µF
0.1µF
0.1µF
100pF
100pF
100pF
100pF
100pF
10kΩ
10kΩ
100kΩ
10kΩ 10kΩ
100kΩ
4.7µF +
4.7µF +
4.7µF +4.7µF
+
4.7µF
+
4.7µF +
0.1µF 100pF
100pF
100pF
100pF
100pF
0.1µF
0.1µF
VDD7, VDD8
RFOUT
RFIN
HMC7229CHIPS
1
2
14
3
13
4
12
5
11
6
10
7
98
VDD5, VDD6
VDD1, VDD2 VDD3, VDD4
OPTION 2
VGG2
OPTION 1
VGG1
14566-036
Figure 36. Typical Application Circuit
Data Sheet HMC7229CHIPS
Rev. 0 | Page 15 of 16
ASSEMBLY DIAGRAM
14566-037
Figure 37. Assembly Diagram
HMC7229CHIPS Data Sheet
Rev. 0 | Page 16 of 16
OUTLINE DIMENSIONS
07-29-2016-A
0.0178
0.102
0.0102
0.0813
2.380
0.890
0.130
0.130
2.794 0.102
SIDE VIEW
18
2345
1112
13
14
6
10
7
9
0.150
0.150
0.150
0.150
0.150
0.201
0.201
0.201
0.201
0.201
0.391
0.391
0.350
0.1500.150
0.216
0.135
0.851
0.350
0.350
Figure 38. 14-Pad Bare Die [CHIP]
(C-14-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option
HMC7229 −55°C to +85°C 14-Pad Bare Die [CHIP] C-14-4
HMC7229SX −55°C to +85°C 14-Pad Bare Die [CHIP] C-14-4
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