MC74HC4040A - ON Semiconductor

June, 2005 − Rev. 5 1Publication Order Number:

MC74HC4040A/D

MC74HC4040A

12−Stage Binary Ripple

Counter

High−Performance Silicon−Gate CMOS

The MC74C4040A is identical in pinout to the standard CMOS

MC14040. The device inputs are compatible with standard CMOS

outputs; with pullup resistors, they are compatible with LSTTL

outputs.

This device consists of 12 master−slave flip−flops. The output of

each flip−flop feeds the next and the frequency at each output is half of

that of the preceding one. The state counter advances on the

negative−going edge of the Clock input. Reset is asynchronous and

active−high.

State changes of the Q outputs do not occur simultaneously because

of internal ripple delays. Therefore, decoded output signals are subject

to decoding spikes and may have to be gated with the Clock of the

HC4040A for some designs.

Features

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2.0 to 6.0 V

•Low Input Current: 1 mA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance With JEDEC Standard No. 7A Requirements

•Chip Complexity: 398 FETs or 99.5 Equivalent Gates

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

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MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

16 PDIP−16

N SUFFIX

CASE 648

MC74HC4040AN

AWLYYWWG

HC4040AG

AWLYWW

HC40

40A

ALYWG

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G = Pb−Free Package

G= Pb−Free Package

(Note: Microdot may be in either location)

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

74HC4040A

ALYWG

SOEIAJ−16

F SUFFIX

CASE 966

MC74HC4040A

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Figure 1. Logic Diagram

Q10

Clock 10

Reset 11 Pin 16 = VCC

Pin 8 = GND

1516 14 13 12 11 10

21 34567

VCC

Q11 Q10 Q8 Q9 Reset Clock Q1

Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND

Figure 2. Pinout: 16−Lead Plastic Package

(Top View)

Q11

Q12

FUNCTION TABLE

Clock Reset Output State

No Charge

Advance to Next State

All Outputs Are Low

ORDERING INFORMATION

Device Package Shipping†

MC74HC4040AN PDIP−16 2000 Units / Box

MC74HC4040ANG PDIP−16

(Pb−Free) 2000 Units / Box

MC74HC4040AD SOIC−16 48 Units / Rail

MC74HC4040ADG SOIC−16

(Pb−Free) 48 Units / Rail

MC74HC4040ADR2 SOIC−16 2500 Units / Reel

MC74HC4040ADR2G SOIC−16

(Pb−Free) 2500 Units / Reel

MC74HC4040ADTR2 TSSOP−16* 2500 Units / Reel

MC74HC4040ADTR2G TSSOP−16* 2500 Units / Reel

MC74HC4040AF SOEIAJ−16 50 Units / Rail

MC74HC4040AFG SOEIAJ−16

(Pb−Free) 50 Units / Rail

MC74HC4040AFEL SOEIAJ−16 2000 Units / Reel

MC74HC4040AFELG SOEIAJ−16

(Pb−Free) 2000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HC4040A

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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, Plastic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

750

500

450

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature Range

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

ÎÎÎÎÎ

ÎÎÎ

ÎÎÎÎÎ

260

ÎÎÎ

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

† Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

For high frequency or heavy load considerations, see Chapter 2 of the ON Semic onduc tor High−Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature Range, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

600

500

400

ÎÎÎ

DC CHARACTERISTICS (Voltages Referenced to GND)

Symbo

Parameter Condition VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

VIH Minimum High−Level Input Voltage Vout = 0.1V or VCC −0.1V

|Iout| ≤ 20mA2.0

3.0

4.5

6.0

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

1.50

2.10

3.15

4.20

VIL Maximum Low−Level Input Voltage Vout = 0.1V or VCC − 0.1V

|Iout| ≤ 20mA2.0

3.0

4.5

6.0

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

0.50

0.90

1.35

1.80

VOH Minimum High−Level Output Voltage Vin = VIH or VIL

|Iout| ≤ 20mA2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

2.48

3.98

5.48

2.34

3.84

5.34

2.20

3.70

5.20

VOL Maximum Low−Level Output Voltage Vin = VIH or VIL

|Iout| ≤ 20mA2.0

4.5

6.0

0.1

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74HC4040A

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DC CHARACTERISTICS (Voltages Referenced to GND)

Symbol Unit

Guaranteed Limit

VCC

ConditionParameter

Symbol Unit

≤125°C≤85°C−55 to 25°C

VCC

ConditionParameter

Vin = VIH or VIL |Iout| ≤ 2.4mA

|Iout| ≤ 4.0mA

|Iout| ≤ 5.2mA

3.0

4.5

6.0

0.26

0.33

0.40

Iin Maximum Input Leakage Current Vin = VCC or GND 6.0 ±0.1 ±1.0 ±1.0 mA

ICC Maximum Quiescent Supply

Current (per Package) Vin = VCC or GND

Iout = 0mA6.0 4 40 160 mA

NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)

Symbo

Parameter VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

fmax Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 4) 2.0

3.0

4.5

6.0

9.0

8.0

MHz

tPLH,

tPHL Maximum Propagation Delay, Clock to Q1*

(Figures 1 and 4) 2.0

3.0

4.5

6.0

106

115

tPHL Maximum Propagation Delay, Reset to Any Q

(Figures 2 and 4) 2.0

3.0

4.5

6.0

tPLH,

tPHL Maximum Propagation Delay, Qn to Qn+1

(Figures 3 and 4) 2.0

3.0

4.5

6.0

tTLH,

tTHL Maximum Output Transition Time, Any Output

(Figures 1 and 4) 2.0

3.0

4.5

6.0

110

Cin Maximum Input Capacitance 10 10 10 pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconduc tor High−S peed CMOS Data Book (DL129/D).

* For TA = 25°C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:

VCC = 2.0 V: tP = [93.7 + 59.3 (n−1)] ns VCC = 4.5 V: tP = [30.25 + 14.6 (n−1)] ns

VCC = 3.0 V: tP = [61.5 + 34.4 (n−1)] ns VCC = 6.0V: tP = [24.4 + 12 (n−1)] ns

CPD Power Dissipation Capacitance (Per Package)*

Typical @ 25°C, VCC = 5.0 V

*Used t o determine the no− load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of t h e

ON Semiconductor High−S peed CMOS Data Book (DL129/D) .

MC74HC4040A

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TIMING REQUIREMENTS (Input tr = tf = 6 ns)

Symbo

Parameter VCC

Guaranteed Limit

Unit

−55 to 25°C≤85°C≤125°C

trec Minimum Recovery Time, Reset Inactive to Clock

(Figure 2) 2.0

3.0

4.5

6.0

twMinimum Pulse Width, Clock

(Figure 1) 2.0

3.0

4.5

6.0

twMinimum Pulse Width, Reset

(Figure 2) 2.0

3.0

4.5

6.0

tr, tfMaximum Input Rise and Fall Times

(Figure 1) 2.0

3.0

4.5

6.0

1000

800

500

400

1000

800

500

400

1000

800

500

400

NOTE:Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High−Speed CMOS Data Book

(DL129/D).

PIN DESCRIPTIONS

INPUTS

Clock (Pin 10)

Negative−edge triggering clock input. A high−to−low

transition on this input advances the state of the counter.

Reset (Pin 11)

Active−high reset. A high level applied to this input

asynchronously resets the counter to its zero state, thus

forcing all Q outputs low.

OUTPUTS

Q1 thru Q12 (Pins 9, 7, 6, 5, 3, 2, 4, 13, 12, 14, 15, 1)

Active−high outputs. Each Qn output divides the Clock

input frequency by 2N.

SWITCHING WAVEFORMS

Clock

VCC

GND

90%

50%

10%

90%

50%

10%

tPHL

1/fMAX

tPLH

tTLH tTHL

Clock

VCC

GND

trec

50%

Figure 3.

Reset

VCC

GND

50%

Any Q 50%

tPHL

Figure 4.

MC74HC4040A

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SWITCHING WAVEFORMS (continued)

50%

VCC

GND

50%

Qn+1

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 5. Figure 6. Test Circuit

tPLH tPHL

Figure 7. Expanded Logic Diagram

Clock 10 C

Reset 11

Q10

Q11

Q12

Q4 = Pin 5

Q5 = Pin 3

Q6 = Pin 2

Q7 = Pin 4

Q8 = Pin 13

Q9 = Pin 12

VCC = Pin 16

GND = Pin 8

MC74HC4040A

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Clock

Reset

1 2 4 8 16 32 64 128 256 512 1024 2048 4096

Q10

Q11

Figure 8. Timing Diagram

Q12

APPLICATIONS INFORMATION

Time−Base Generator

A 60Hz sinewave obtained through a 100 K resistor

connected to a 120 Vac power line through a step down

transformer is applied to the input of the MC54/74HC14A,

Schmitt-trigger inverter. The HC14A squares−up the input

waveform and feeds the HC4040A. Selecting outputs Q5,

Q10, Q11, and Q12 causes a reset every 3600 clocks. The

HC20 decodes the counter outputs, produces a single

(narrow) output pulse, and resets the binary counter. The

resulting output frequency is 1.0 pulse/minute.

HC4040A

Figure 9. Time−Base Generator

Clock Q5

Q10

Q11

Q12

VCC

1/2

HC20

1/2

HC20

1.0 Pulse/Minute

Output

≥20pF

1.0M

120Vac

60Hz

NOTE: Ground MUST be isolated

by a transformer or

opto−isolator for safety

reasons.

MC74HC4040A

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PACKAGE DIMENSIONS

PDIP−16

N SUFFIX

CASE 648−08

ISSUE T

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE J

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

HGD

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

MC74HC4040A

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PACKAGE DIMENSIONS

TSSOP−16

DT SUFFIX

CASE 948F−01

ISSUE A

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉÉ

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

MC74HC4040A

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PACKAGE DIMENSIONS

SOEIAJ−16

F SUFFIX

CASE 966−01

ISSUE O

DIM MIN MAX MIN MAX

INCHES

−−− 2.05 −−− 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.18 0.27 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

−−− 0.78 −−− 0.031

_10 _0

_10 _

LEQ1

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005) 0.10 (0.004)

16 9

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MC74HC4040A/D

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