Synchronous Demodulator and Configurable Analog Filter ADA2200 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD ADA2200 INP 8 INN LPF OUTP PROGRAM FILTER OUTN fM CLKIN XOUT /2m fSI /8 VOCM 90 fSO /2n+1 CLOCK GEN CONTROL REGISTERS SYNCO GND RCLK/SDO SPI/I2C MASTER RST VCM SCLK/SCL SDIO/SDA CS/A0 BOOT 12295-001 Demodulates signal input bandwidths to 30 kHz Programmable filter enables variable bandwidths Filter tracks input carrier frequency Programmable reference clock frequency Flexible system interface Single-ended/differential signal inputs and outputs Rail-to-rail outputs directly drive analog-to-digital converters (ADCs) Phase detection sensitivity of 9.3mREL rms Configurable with 3-wire and 4-wire serial port interface (SPI) or seamless boot from I2C EEPROMs Very low power operation 395 A at fCLKIN = 500 kHz Single supply: 2.7 V to 3.6 V Specified temperature range: -40C to +85C 16-lead TSSOP package Figure 1. APPLICATIONS Synchronous demodulation Sensor signal conditioning Lock-in amplifiers Phase detectors Precision tunable filters Signal recovery Control systems GENERAL DESCRIPTION The ADA2200 is a sampled analog technology1 synchronous demodulator for signal conditioning in industrial, medical, and communications applications. The ADA2200 is an analog input, sampled analog output device. The signal processing is performed entirely in the analog domain by charge sharing among capacitors, which eliminates the effects of quantization noise and rounding errors. The ADA2200 includes an analog domain, low-pass decimation filter, a programmable infinite impulse response (IIR) filter, and a mixer. This combination of features reduces ADC sample rates and lowers the downstream digital signal processing requirements. The ADA2200 acts as a precision filter when the demodulation function is disabled. The filter has a programmable bandwidth and tunable center frequency. The filter characteristics are highly stable over temperature, supply, and process variation. Single-ended and differential signal interfaces are possible on both input and output terminals, simplifying the connection to other 1 components of the signal chain. The low power consumption and rail-to-rail operation is ideal for battery-powered and low voltage systems. The ADA2200 can be programmed over its SPI-compatible serial port or can automatically boot from the EEPROM through its I2C interface. On-chip clock generation produces a mixing signal with a programmable frequency and phase. In addition, the ADA2200 synchronization output signal eases interfacing to other sampled systems, such as data converters and multiplexers. The ADA2200 is available in a 16-lead TSSOP package. Its performance is specified over the industrial temperature range of -40C to +85C. Note that throughout this data sheet, multifunction pins, such as SCLK/SCL, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. Patent pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADA2200 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input and Output Amplifiers .................................................... 15 Applications ....................................................................................... 1 Applications Information .............................................................. 16 Functional Block Diagram .............................................................. 1 Amplitude Measurements ......................................................... 16 General Description ......................................................................... 1 Phase Measurements.................................................................. 16 Revision History ............................................................................... 2 Amplitude and Phase Measurements ...................................... 16 Specifications..................................................................................... 3 Analog Output Systems ............................................................. 17 SPI Timing Characteristics ......................................................... 4 Interfacing to ADCs ................................................................... 17 Absolute Maximum Ratings ............................................................ 7 Lock-In Amplifier Application ................................................. 17 Thermal Resistance ...................................................................... 7 Interfacing to Microcontrollers ................................................ 18 ESD Caution .................................................................................. 7 EEPROM Boot Configuration .................................................. 18 Pin Configuration and Function Descriptions ............................. 8 Power Dissipation....................................................................... 18 Typical Performance Characteristics ............................................. 9 Device Configuration .................................................................... 19 Terminology .................................................................................... 10 Serial Port Operation ................................................................. 19 Theory of Operation ...................................................................... 11 Data Format ................................................................................ 19 Synchronous Demodulation Basics ......................................... 11 Serial Port Pin Descriptions ...................................................... 19 ADA2200 Architecture .............................................................. 12 Serial Port Options ..................................................................... 19 Decimation Filter........................................................................ 12 Booting from EEPROM ............................................................ 20 IIR Filter....................................................................................... 13 Device Configuration Register Map and Descriptions ............. 21 Mixer ............................................................................................ 13 Outline Dimensions ....................................................................... 24 Clocking Options ....................................................................... 14 Ordering Guide............................................................................... 24 REVISION HISTORY 8/14--Revision 0: Initial Version Rev. 0 | Page 2 of 24 Data Sheet ADA2200 SPECIFICATIONS VDD = 3.3 V, VOCM = VDD/2, fCLKIN = fSI = 500 kHz, default register configuration, differential input/output, RL = 1 M to GND, TA = 25C, unless otherwise noted. Table 1. Parameter SYNCHRONOUS DEMODULATION Conversion Gain1 Average Temperature Drift Output Offset, Shorted Inputs Average Temperature Drift Power Supply Sensitivity Measurement Noise Phase Delay (DELAY)1 Average Temperature Drift Phase Measurement Noise Shorted Input Noise Common-Mode Rejection2 Demodulation Signal Bandwidth INPUT CHARACTERISTICS Input Voltage Range Common-Mode Input Voltage Range Single-Ended Input Voltage Range Reference Input Signal Input Input Impedance3 Input Signal Bandwidth (-3 dB) OUTPUT CHARACTERISTICS Output Voltage Range Short-Circuit Current Common-Mode Output (VOCM) Voltage Average Temperature Drift Output Settling Time, to 0.1% of Final Value DEFAULT FILTER CHARACTERISTICS Center Frequency (fC) Quality Factor (Q) Pass Band Gain TOTAL HARMONIC DISTORTION (THD) Second Through Fifth Harmonics CLOCKING CHARACTERISTICS CLKIN Frequency Range (fCLKIN) Maximum CLKIN Frequency Test Conditions/Comments Measurements are cycle mean values,1 4 V p-p differential, fIN = 7.8125 kHz Min Typ Max Unit 1.02 1.055 5 1.09 V/V rms ppm/C mV V/C mV/V V rms -39 Change in output over change in VDD Input signal at 83REL1 Input signal relative to RCLK Input signal at 83REL 0.1 Hz to 10 Hz 0 kHz to 1 kHz offset from fMOD fCLKIN = 1 MHz INP or INN to GND 4 V p-p differential input +39 6.5 0.5 240 83 70 9.3 300 75 30 0.3 VOCM - 0.2 VDD - 0.3 VOCM + 0.2 V V VOCM - 0.2 VOCM - 1.0 VOCM + 0.2 VOCM + 1.0 V V k MHz VDD - 0.3 V mA 1.67 V V/C s INP to INN Input sample and hold circuit Each output, RL = 10 k to GND 80 4 0.3 OUTP or OUTN to GND 15 1.63 3.7 V output step, RLOAD = 10 k||10 pF, fCLKIN = 125 kHz Mixing disabled, VIN = 4 V p-p differential fC = fSO/8 fC/(filter 3 dB bandwidth) fIN = 7.8125 kHz Filter configuration = LPF at fNYQ/6, fIN = 850 Hz, VIN = 4 V p-p differential input TA = -40C to +85C CLKIN DIV[2:0] = 256 CLKIN DIV[2:0] = 64 CLKIN DIV[2:0] = 16 CLKIN DIV[2:0] = 1 While booting from EEPROM Rev. 0 | Page 3 of 24 REL REL/C mREL rms V p-p dB kHz 2.56 0.64 0.16 0.01 1.65 9 15 7.8125 1.9 1.05 kHz Hz/Hz V/V -80 dBc 20 20 16 1 12.8 MHz MHz MHz MHz MHz ADA2200 Data Sheet Parameter DIGITAL I/O Logic Thresholds Input Voltage Low High Output Voltage Low High Maximum Output Current Input Leakage Internal Pull-Up Resistance Test Conditions/Comments Min Typ Max Unit 0.8 V V 0.4 40 V V mA A k 500 2 2 k pF pF All inputs/outputs 2.0 While sinking 200 A While sourcing 200 A Sink or source VDD - 0.4 8 1 BOOT and RST only CRYSTAL OSCILLATOR Internal Feedback Resistor CLKIN Capacitance XOUT Capacitance POWER REQUIREMENTS Power Supply Voltage Range Total Supply Current Consumption 2.7 395 3.6 485 V A See the Terminology section. Common-mode signal swept from fMOD - 1 kHz to fMOD + 1 kHz. Output measured at frequency offset from fMOD. For example, a common-mode signal at fMOD - 500 Hz is measured at 500 Hz. 3 The input impedance is equal to a 4 pF capacitor switched at fCLKIN. Therefore, the input impedance = 1012/(2fCLKIN x 4). 1 2 SPI TIMING CHARACTERISTICS VDD = 2.7 V to 3.6 V, default register configuration, TA = -40 to +85C, unless otherwise noted. Table 2. SPI Timing Parameter fSCLK tCS Test Conditions/Comments 50% 5% duty cycle CS to SCLK edge tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS SCLK low pulse width SCLK high pulse width Data output valid after SCLK edge Data input setup time before SCLK edge Data input hold time after SCLK edge Data output fall time Data output rise time SCLK rise time SCLK fall time Data output valid after CS edge CS high after SCLK edge Min Typ Max 20 2 10 10 20 2 2 1 1 10 10 1 2 Rev. 0 | Page 4 of 24 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns Data Sheet ADA2200 CS tCS tSFS tSL SCLK tSH tSF tDAV tDF SDO (MISO) MSB SDIO (MOSI) tSR tDR DATA BITS MSB IN LSB DATA BITS LSB IN 12295-003 tDSU tDHD Figure 2. SPI Read Timing Diagram (SPI Master Read from the ADA2200) CS tSFS tCS SCLK tSL tSH tSF SDIO (MOSI) MSB IN DATA BITS tSR LSB IN 12295-004 tDSU tDHD Figure 3. SPI Write Timing Diagram (SPI Master Write to the ADA2200) Table 3. EEPROM Master I2C Boot Timing Parameter1 BOOT Load from BOOT Complete RST to BOOT Setup Time BOOT Pulse Width t2 t3 RESET Minimum RST Pulse Width t1 START CONDITION BOOT Low Transition to Start Condition t4 1 Symbol CLKIN cycles with CLKIN DIV[2:0] set to 000. Rev. 0 | Page 5 of 24 Min Typical Max Unit 9600 2 1 CLKIN cycles CLKIN cycles CLKIN cycles 25 ns 3 CLKIN cycles ADA2200 Data Sheet t1 RST t2 BOOT t3 t4 SDA START ADDR [1:0] R/W ACK b10001 REGISTER ADDR ACK DATA ACK STOP 12295-005 SCL Figure 4. Load from EEPROM Timing Diagram OUTPUT PHASE90 = 0 OUTPUT PHASE90 = 1 HOLD SAMPLES SAMPLE 0 SAMPLE 0 SAMPLE 1 SAMPLE 1 SAMPLE 2 SAMPLE 2 SAMPLE 3 + 4 HOLD SAMPLES SAMPLE 3 + 4 HOLD SAMPLES SAMPLE 0 SAMPLE 1 CLKIN SYNCO 30 40 50 60 70 80 90 100 Figure 5. CLKIN to RCLK, SYNCO, and OUTP/OUTN Sample Timing Table 4. Output, SYNCO, and RCLK Timing, Default Register Settings Test Conditions/Comments CLKIN to OUTx sample update delay CLKIN to SYNCO delay, rising or falling edge to rising edge SYNCO pulse width CLKIN to RCLK delay, rising edge to rising or falling edge Min Typ 50 Max 40 1/fSI 70 INN/INP t1 INx, OUTx OUTN/OUTP t2 SYNCO t3 t4 RCLK CLKIN 6 7 0 1 2 3 Figure 6. Input, Output, SYNCO, and RCLK Timing Relative to CLKIN Rev. 0 | Page 6 of 24 4 12295-007 Parameter t1 t2 t3 t4 Unit ns ns ns ns 12295-006 RCLK Data Sheet ADA2200 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Supply Voltage Output Short-Circuit Current Duration Maximum Voltage at Any Input Minimum Voltage at Any Input Operational Temperature Range Storage Temperature Range Package Glass Transition Temperature ESD Ratings Human Body Model (HBM) Device Model (FICDM) Machine Model (MM) JA is specified for a device in a natural convection environment, soldered on a 4-layer JEDEC printed circuit board (PCB). Rating 3.9 V Indefinite VDD + 0.3 V GND - 0.3 V -40C to +125C -65C to +150C 150C Table 6. Package 16-Lead TSSOP ESD CAUTION 1000 V 500 V 50 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 7 of 24 JA 100 JC 14.8 Unit C/W ADA2200 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CLKIN 1 15 SCLK/SCL CS/A0 3 14 SDIO/SDA 13 RCLK/SDO 12 VDD BOOT 4 ADA2200 TOP VIEW (Not to Scale) GND 5 INP 6 11 OUTP INN 7 10 OUTN VOCM 8 9 RST 12295-008 16 XOUT 2 SYNCO Figure 7. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mnemonic CLKIN SYNCO CS/A0 BOOT GND INP INN VOCM RST OUTN OUTP VDD RCLK/SDO SDIO/SDA SCLK/SCL XOUT Description System Clock Input. Synchronization Signal Output. Serial Interface Chip Select Input/Boot EEPROM Address 0 Input. Boot from EEPROM Control Input. Power Supply Ground. Noninverting Signal Input. Inverting Signal Input. Common-Mode Voltage Output. Reset Control Input. Inverting Output. Noninverting Output. Positive Supply Input. Reference Clock Output/Serial Interface Data Output (in 4-Wire SPI Mode). Bidirectional Serial Data (Input Only in 4-Wire SPI Mode)/I2C Bidirectional Data. Serial Interface Clock Input/I2C Clock Output. Crystal Driver Output. Place a crystal between this pin and CLKIN, or leave this pin disconnected. Rev. 0 | Page 8 of 24 200 35 150 25 20 15 50 0 -50 10 -100 5 -150 0 78 79 80 81 82 83 84 RELATIVE PHASE (Degrees) -200 0 1 2 3 4 5 6 7 8 9 10 TIME (Seconds) 12295-112 OUTPUT NOISE (V) 100 12295-109 NUMBER OF HITS 30 0 -0.05 -0.10 -0.15 0 10 20 30 40 50 60 TIME (s) PHASE MEASUREMENT ERROR (Degrees) 25 20 15 10 5 0 -10 -270 -240 -210 -180 -150 -120 -90 -60 -30 RELATIVE PHASE (Degrees) 0 30 60 90 12295-114 MAGNITUDE ERROR MAGNITUDE ERROR, OFFSET REMOVED 10 100 1k 10k 100k FREQUENCY (Hz) 1.0 30 MAGNITUDE ERROR (mV) CLKIN = 500kHz 1 35 -5 1k 100 12295-110 -0.20 10k 0.8 12295-113 SETTLING ERROR (%) 0.05 PHASE ERROR PHASE ERROR, OFFSET REMOVED 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -270 -240 -210 -180 -150 -120 -90 -60 -30 RELATIVE PHASE (Degrees) 0 30 60 90 12295-111 NOISE SPECTRAL DENSITY (nV/Hz) 0.10 ADA2200 Data Sheet TERMINOLOGY Cycle Mean The cycle mean is the average of all the output samples (OUTP/OUTN) over one RCLK period. In the default configuration, there are eight output samples per RCLK cycle; thus, the cycle mean is the average of eight consecutive output samples. If the device is reconfigured such that the frequency of RCLK is fSO/4, then the cycle mean is the average of four consecutive output samples. Conversion Gain Conversion gain is calculated as follows: 2 Phase Measurement Transfer Function Figure 15 shows the cycle mean value of the output for a 1 V rms input sine wave as REL is swept from 0 to 360. 1.2 1.0 +Q2 0.8 0.6 CYCLE MEAN VALUE V IN where: I is the offset corrected cycle mean, PHASE90 bit = 0. Q is the offset corrected cycle mean, PHASE90 bit = 1. VIN is the rms value of the input voltage. The offset corrected cycle mean = cycle mean - output offset. 100 150 200 250 -0.4 -1.0 -1.2 0 45 90 135 180 225 RELATIVE PHASE (REL ) 270 315 360 Figure 15. Phase Transfer Function with Phase Delay of 83, 1 V rms Input 300 350 INP/INN 12295-009 PHASE (Degrees) RELATIVE PHASE = 37 0 -0.2 -0.6 RCLK 50 83 0.2 -0.8 Relative Phase (REL) Relative phase is the phase difference between the rising positive zero crossing of a sine wave at the INN/INP inputs relative to the next rising edge of RCLK. 0 0.4 12295-010 Conversion Gain = I Phase Delay (DELAY) The phase delay is the relative phase (REL) that produces a zero cycle mean output value for a sine wave input with a frequency equal to fRCLK. The phase delay is the relative phase value that corresponds to the positive zero crossing of the phase measurement transfer function. Figure 14. Example Showing Relative Phase, REL, of 37 Rev. 0 | Page 10 of 24 Data Sheet ADA2200 THEORY OF OPERATION A carrier signal (fMOD) excites the sensor. This shifts the signal generated by the physical parameter being measured by the sensor to the carrier frequency. This shift allows the desired signal to be placed in a frequency band with lower noise, improving the accuracy of the measurement. A band-pass filter (BPF) removes some of the out of band noise. A synchronous demodulator (or mixer) shifts the signal frequency back to dc. The last stage low-pass filter removes much of the remaining noise. Figure 17 and Figure 18 show the frequency spectrum of the signal at different points in the synchronous demodulator. SAT works on the principle of charge sharing. A sampled analog signal is a stepwise continuous signal without amplitude quantization. This contrasts with a signal sampled by an ADC, which becomes a discrete time signal with quantized amplitude. NOISE AT A With SAT, the input signal is sampled by holding the voltage on a capacitor at the sampling instant. Basic signal processing can then be performed in the analog domain by charge sharing among capacitors. The ADA2200 includes an analog domain low-pass decimation filter, a programmable IIR filter, and a mixer. This combination of features enables reduced ADC sample rates and lowers the downstream digital signal processing requirements if the signal is digitized. NOISE AT B SENSOR SIGNAL AT A, B PHYSICAL PARAMETER 12295-018 The ADA2200 is a synchronous demodulator and tunable filter implemented with sampled analog technology (SAT). Synchronous demodulators, also known as lock-in amplifiers, enable accurate measurement of small ac signals in the presence of noise interference orders of magnitude greater than the signal amplitude. Synchronous demodulators use phase sensitive detection to isolate the component of the signal at a specific reference frequency and phase. Noise at frequencies that are offset from the reference frequency are easily rejected and do not significantly impair the measurement. fREF The output of the ADA2200 can also be used in an all analog signal path. In these applications, add a reconstruction filter following the ADA2200 in the signal path. Figure 17. Output Spectrum of Synchronous Demodulator Before Demodulation SYNCHRONOUS DEMODULATION BASICS Employing synchronous demodulation as a sensor signaling conditioning technique can result in improved sensitivity when compared to other methods. Synchronous demodulation adds two key benefits for recovering small sensor output signals in the presence of noise. The first benefit being the addition of an excitation signal, which enables the sensor output signal to be moved to a lower noise frequency band. The second benefit is that synchronous demodulation enables a simple low-pass filter to remove most of the remaining undesired noise components. SENSOR SIGNAL AT C, D NOISE AT C Figure 16 shows a basic synchronous demodulation system used for measuring the output of a sensor. fREF Figure 18. Output Spectrum of Synchronous Demodulator After Demodulation fMOD A BPF B C Phase Sensitive Detection D SENSOR fREF LPF NOISE Figure 16. Basic Synchronous Demodulator Block Diagram 12295-017 PHYSICAL PARAMETER 12295-019 NOISE AT D Synchronous demodulation uses the principle of phase sensitive detection to separate the signal of interest from unwanted signals. In Figure 16, the mixer performs the phase sensitive detection. The signal at the mixer output (C) is the product of the reference signal and a filtered version of the sensor output (B). If the reference signal is a sine wave, the physical parameter is a constant and there is no noise in the system. The signal at the output of the BPF is a sine wave that can be expressed as VBsin(REFt + B) Rev. 0 | Page 11 of 24 ADA2200 Data Sheet DECIMATION FILTER The output of the mixer (if implemented as a multiplier) is then 1/2VBVREFcos(B - REF) - 1/2VBVREFcos(2REFt + B + REF) The clock signal divider (after CLKIN) determines the input sampling frequency, fSI, of the decimation filter. The decimation filter produces one filtered sample for every eight input samples. Figure 20 shows the wideband frequency response of the decimation filter. Because the filter operates on sampled data, images of the filter appear at multiples of the input sample rate, fSI. The stop band of the decimation filter begins around 1/2 of the output data rate, fSO. Because an image pass band exists around fSI, any undesired signals in the pass band around fSI alias to dc and are indistinguishable from the low frequency input signal. This signal is a dc signal and an ac signal at twice the reference frequency. If the LPF is sufficient to remove the ac signal, the signal at the LPF output (D) is 1/2VBVREFcos(B - REF) The LPF output is a dc signal that is proportional to both the magnitude and phase of the signal at the BPF output (B). When the input amplitude is held constant, the LPF output enables can be used to measure the phase. When the input phase is held constant, the LPF can be used to measure amplitude. To preserve the full dynamic range of the ADA2200, use an input antialiasing filter if noise at frequencies above 7.5 fSI is not lower than the noise floor of the frequencies of interest. A firstorder low-pass filter is usually sufficient for the antialiasing filter. Note that the reference signal is not required to be a pure sine wave. The excitation signal and demodulation signal must only share a common frequency and phase to employ phase sensitive detection. In some applications, it may be possible to use the square wave output from the ADA2200 RCLK output directly. Internal to the ADA2200, the demodulation is performed not by multiplying the REFCLK signal with the input signal, but by holding the output constant for 1/2 the sample output periods. This operation is similar to a half wave demodulation of the input signal. For more information on signal detection using this function, see the Applications Information section. f 0.5fSO 10 VDD 0 ADA2200 -10 PROGRAM FILTER fMOD /8 /2n+1 fSO VOCM 90 VCM RCLK/SDO CLOCK GEN CONTROL REGISTERS SYNCO GND SPI BOOT FROM EEPROM (I2C) RST BOOT -30 -40 -50 -60 SCLK/SCL SDIO/SDA CS/A0 -70 12295-020 XOUT fSI -20 OUTN Figure 19. ADA2200 Architecture -80 -90 0 fSO/4 fSO/2 3fSO/4 FREQUENCY Figure 21. Decimation Filter Transfer Function, fSI = 800 kHz Rev. 0 | Page 12 of 24 fSO 12295-022 8 LPF OUTP GAIN (dB) INP /2m 7.5fSO 8.5fSO 8fSO = fSI Figure 21 shows a more narrow bandwidth view of the decimation transfer function. The stop band of the decimation filter starts at 1/2 of the output sample rate. The stop band rejection of the decimator low-pass filter is approximately 55 dB. The pass band of the decimation filter extends to 1/4th of the output sample rate or 1/32nd of the decimator input sample rate. The signal path for the ADA2200 consists of a high impedance input buffer followed by a fixed low-pass filter (FIR decimation filter), a programmable IIR filter, a mixer function, and a differential pin driver. Figure 19 shows a detailed block diagram of the ADA2200. The signal processing blocks are all implemented using a charge sharing technique. CLKIN 2fSO Figure 20. Decimation Filter Frequency Response ADA2200 ARCHITECTURE INN fSO 12295-021 fSI - f fSI + f Data Sheet ADA2200 IIR FILTER Table 8. IIR Coefficients for the All Pass Filter The IIR block operates at the output sample rate, fSO, which is at 1/8th of the input sample rate (fSI). By default, the IIR filter is configured as a band-pass filter with a center frequency at fSO/8 (fSI/64). This frequency corresponds to the default mixing frequency and assures that input signals in the center of the pass band mix down to dc. Register 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 Figure 22 shows the default frequency response of the IIR filter. 10 0 GAIN (dB) -10 -20 -30 -50 0 0.25 0.50 0.75 1.00 NORMALIZED FREQUENCY (Hz/Nyquist) 12295-023 -40 Figure 22. Default IIR Filter Frequency Response (fSO/8 BPF) If a different frequency response is required, the IIR can be programmed for a different response. Register 0x0011 through Register 0x0027 contain coefficient values that program the filter response. To program the filter, first load the configuration registers (Register 0x0011 through Register 0x0027) with the desired coefficients. The coefficients can then be loaded into the filter by writing 0x03 to Register 0x0010. The IIR filter can be configured for all pass operation by loading the coefficients listed in Table 8. Value 0xC0 0x0F 0x1D 0xD7 0xC0 0x0F 0xC0 0x0F 0x1D 0x97 0x7E 0x88 0xC0 0x0F 0xC0 0x0F 0xC0 0x0F 0x00 0x0E 0x23 0x02 0x24 MIXER The ADA2200 performs the mixing function by holding the output samples constant for 1/2 of the RCLK period. This is similar to a half-wave rectification function except that the output does not return to zero for 1/2 the output period, but retains the value of the previous sample. In the default configuration, there are eight output sample periods during each RCLK cycle. There are four updated output samples while the RCLK signal is high. While RCLK is low, the fourth updated sample is held constant for four additional output sample periods. The timing of the output samples in the default configuration is shown in Table 4. The RCLK divider, RCLK DIV[1:0], can be set to divide fSO by 4. When this mode is selected, four output sample periods occur during each RCLK cycle. Two output samples occur while the RCLK signal is high. While RCLK is low, the second updated sample is held constant for two additional output sample periods. The mixer can be bypassed. When the mixer is bypassed, the output produces an updated sample value every output sample period. Rev. 0 | Page 13 of 24 ADA2200 Data Sheet Phase Shifter CLOCKING OPTIONS It is possible to change the timing of the output samples with respect to RCLK by writing to the PHASE90 bit in Register 0x002A. When the alternative timing option is selected, two output samples are updated while RCLK is low, and two are updated while RCLK is high. The second sample, which is taken while RCLK is high, is held four additional output sample periods. The timing is shown in Figure 5. The ADA2200 has several clocking options to make system integration easier. Clock Dividers The ADA2200 has a pair of on-chip clock dividers to generate the system clocks. The input clock divider, CLKIN DIV[2:0], sets the input sample rate of the decimator (fSI) by dividing the CLKIN signal. The value of CLKIN DIV[2:0] can be set to 1, 16, 64, or 256. Applying a 90 phase shift can be useful in a number of instances. It enables a pair of ADA2200 devices to perform in phase and quadrature demodulation. A 90 phase shift can also be useful in control systems for selecting an appropriate error signal output. The output sample rate (fSO) is always 1/8th of the decimator input sample rate. The RCLK divider, RCLK DIV[1:0], sets the frequency of the mixer frequency, fM (which is also the frequency of RCLK) by dividing fSO by either 4 or 8. Synchronization Pulse Output The ADA2200 generates an output pulse (SYNCO), which can be used by a microprocessor or directly by an ADC to initiate an analog to digital conversion of the ADA2200 output. The SYNCO signal ensures that the ADC sampling occurs at an optimal time during the ADA2200 output sample window. One output sample of the ADA2200 is 8 fSI clock cycles long. The SYNCO pulse is 1 fSI clock cycle in duration. As shown in Figure 24, the SYNCO pulse can be programmed to occur at 1 of 16 different timing offsets. The timing offsets are spaced at 1/2 fSI clock cycle intervals and span the full output sample window. (A) The SYNCO pulse can be inverted, or the SYNCO output can be disabled. The operation of the SYNCO timing generation configuration settings are contained in Register 0x0029. INx, OUTx SYNCO (0) Figure 23. Output Sample Timing Relative to RCLK, (A) PHASE90 = 0, (B) PHASE90 = 1 SYNCO (13) SYNCO (14) SYNCO (15) CLKIN 0 2 4 6 8 10 12 Figure 24. SYNCO Output Timing Relative to OUTP/OUTN, INP/INN, and CLKIN Rev. 0 | Page 14 of 24 12295-025 (B) 12295-024 SYNCO (1) Data Sheet ADA2200 INPUT AND OUTPUT AMPLIFIERS For single-ended outputs, either OUTP or OUTN can be used. Leave the unused output floating. Single-Ended Configurations If a single-ended input configuration is desired, the input signal must have a common-mode voltage near midsupply. Decouple the other inputs to the common-mode voltage of the input signal. Note that differences between the common-mode levels between the INP and INN inputs result in an offset voltage inside the device. Even though the BPF removes the offset, minimize the offset to avoid reducing the available signal swing internal to the device. Differential Configurations Using the ADA2200 in differential mode utilizes the full dynamic range of the device and provides the best noise performance and common-mode rejection. Rev. 0 | Page 15 of 24 ADA2200 Data Sheet APPLICATIONS INFORMATION The signal present at the output of the ADA2200 depends on the amplitude and relative phase of the signal applied at it inputs. When the amplitude or phase is known and constant, any output variations can be attributed to the modulated parameter. Therefore, when the relative phase of the input is constant, the ADA2200 performs amplitude demodulation. When the amplitude is constant, the ADA2200 performs phase demodulation. The sampling and demodulation processes introduce additional frequency components onto the output signal. If the output signal of the ADA2200 is used in the analog domain or if it is sampled asynchronously to the ADA2200 sample clock, these high frequency components can be removed by following the ADA2200 with a reconstruction filter. If the ADA2200 output is sampled synchronously to the ADA2200 output sample rate, an analog reconstruction filter is not required because the ADC inherently rejects sampling artifacts. The frequency artifacts introduced by the demodulation process can be removed by digital filtering. AMPLITUDE MEASUREMENTS If the relative phase of the input signal to the ADA2200 remains constant, the output amplitude is directly proportional to the amplitude of the input signal. Note that the signal gain is a function of the relative phase of the input signal. Figure 15 shows the relationship between the cycle mean output and the relative phase. The cycle mean output voltage is The phase sensitivity also varies with relative phase. The sensitivity is at a maximum when REL = 83. For this reason, the optimal measurement range is for input signals with a relative phase equal to the phase delay of 45. This range provides the highest gain and thus the largest signal-to-noise ratio measurement. This range is also the operating point with the lowest sensitivity to changes in the relative phase. Operating at a relative phase equal to the phase delay of -135 to -225 offers the same gain and measurement accuracy, but with a sign inversion. The phase sensitivity with a 4 V p-p differential input operating with a relative phase that is equal to the phase delay results in a phase sensitivity of 36.6 mV/REL. AMPLITUDE AND PHASE MEASUREMENTS When both the amplitude and relative phase of the input signals are unknown, it is necessary to obtain two orthogonal components of the signal to determine its amplitude, relative phase, or both. These two signal components are referred to as the in-phase (I) and quadrature (Q) components of the signal. A signal with two known rectangular components is represented as a vector or phasor with an associated amplitude and phase (see Figure 25). II I A Q VCYCLEMEAN = Conversion Gain x VIN(RMS) x sin(REL - DEL) = I Therefore, the highest gain, and thus the largest signal-to-noise ratio measurement, is obtained when operating the ADA2200 with REL = DEL + 90 = 173. This value of REL is also the operating point with the lowest sensitivity to changes in the relative phase. Operating with REL = DEL - 90 = -7 offers the same gain and measurement accuracy, but with a sign inversion. PHASE MEASUREMENTS If the amplitude of the input signal to the ADA2200 remains constant, the output amplitude is a function of the relative phase of the input signal. The relative phase can be measured as REL = sin-1(VCYCLEMEAN/(Conversion Gain x VIN(RMS))) + DEL = sin-1(VCYCLEMEAN/(1.05 x VIN(RMS))) + DEL Note that the output voltage scales directly with the input signal amplitude. A full-scale input signal provides the greatest phase sensitivity (V/REL) and thus the largest signal-to-noise ratio measurement. III IV 12295-026 1.05 xVIN(RMS) x sin(REL - DEL) Figure 25. Rectangular and Polar Representation of a Signal If the signal amplitude remains nearly constant for the duration of the measurement, it is possible to measure both the I and the Q components of the signal by toggling the PHASE90 bit between two consecutive measurements. To measure the I component, set the PHASE90 bit to 0. To measure the Q component, set the PHASE90 bit to 1. After both the I and Q components have been obtained, it is possible to separate the effects of the amplitude and phase variations. Then, calculate the magnitude and relative phase using the following formulas: A= I 2 + Q2 REL = cos -1 Q A + DEL Or alternatively REL = sin -1 I A + DEL Rev. 0 | Page 16 of 24 Data Sheet ADA2200 Figure 26 shows an 8-channel system with a 1 MHz aggregate throughput rate. The ADA2200 samples each channel at 1 MSPS and produces filtered samples at an output sample rate of 125 kHz each. The AD7091R-8 is an 8-channel, 1 MHz ADC with multiplexed inputs, which cycle through the eight channels at 125 kHz, producing an aggregate output sample rate of 1 MHz. 1MHz SAMPLE CLOCK CLKIN AD7091R-8 Similar to a digital-to-analog converter (DAC), the output of the ADA2200 is a stepwise continuous output. This waveform contains positive and negative images of the desired signal at multiples of fSO. In most cases, the images are undesired noise components that must be attenuated. The lowest frequency image to appear in the output spectrum appears at a frequency of fSO - fIN. The image amplitude is reduced by the sin(x)/x roll-off. System accuracy requirements may dictate that additional low-pass filtering is required to remove the output sample images. INTERFACING TO ADCS Settling Time Considerations If the ADC is coherently sampling the ADA2200 outputs, design the output filter to ensure that the output samples settle prior to ADC sampling. The output filter does not need to remove the sampling images generated by the ADA2200. The images are inherently rejected by the ADC sampling process. Clock Synchronization In multichannel systems that require simultaneous sampling, the ADA2200 can provide per channel programmable filtering and simultaneous sampling. 12-BIT ADC CS SCLK DOUT DIN CS SCLK MISO MOSI MICROCONTROLLER SEQUENCER 8 CHANNELS SIMULTANEOUSLY SAMPLED AT 125kHz EACH SIMULTANEOUS SAMPLING AND FILTERING Figure 26. ADA2200 in an 8-Channel Simultaneous Sampling Application LOCK-IN AMPLIFIER APPLICATION Figure 27 shows the ADA2200 in a lock-in amplifier application. The 80 kHz master clock signal sets the input sample rate of the decimation filter, fSI. The output sample rate is 10 kHz. In the default configuration, the excitation signal generated by RCLK is 1.25 kHz. This is also the center frequency of the on-chip IIR filter. In many cases, the RCLK signal is buffered to provide a square wave excitation signal to the sensor. It may also be desirable to provide further signal conditioning to provide a sine wave excitation signal to the sensor. A low noise instrumentation amplifier provides sufficient gain to amplify the signal so that the noise floor of the signal into the ADA2200 is above the combined noise floor of the ADA2200 and the ADC referred to the ADA2200 inputs. 3.3V MASTER CLOCK VDD CLKIN SYNCO RCLK/SDO ADA2200 SENSOR EXCITATION CONDITIONING AD8227 The SYNCO output can trigger the ADC sampling process directly, or a microcontroller can use SYNCO to adjust the ADC sampling time. Adjusting the SYNCO pulse timing can maximize the available time for the ADA2200 outputs to settle prior to ADC sampling. Multichannel ADCs ADA2200 CH8 8:1 MUX 12295-028 The bandwidth of the analog reconstruction filter sets the demodulation bandwidth of the analog output. There is a direct trade-off between the noise and demodulation bandwidth. Therefore, it is recommended to ensure that the reconstruction filter cutoff frequency is as low as possible while minimizing the attenuation of the demodulated signal of interest. ADA2200 CH2 Reconstruction Filters IRQ ADA2200 CH1 ANALOG OUTPUT SYSTEMS When the output signal of the ADA2200 is used in the analog domain or if it is sampled asynchronously to the ADA2200 sample clock, it is likely that a reconstruction filter is required. CLK0 SYNCO DUT OR SENSOR INP INN VOCM OUTP AD7170 OUTN GND REF AD8613 Figure 27. Lock-In Amplifier Application In default mode, the ADA2200 produces eight output samples for every cycle of the excitation (RCLK) signal. There are four unique output sample values. The fourth value appears on the output for five consecutive output sample periods. Rev. 0 | Page 17 of 24 12295-029 The inverse sine or inverse cosine functions linearize the relationship between the relative phase of the signal and the measured angle. Because the inverse sine and inverse cosine are only defined in two quadrants, the sign of I and Q must be considered to map the result over the entire 360 range of possible relative phase values. The use of the inverse tangent function is not recommended because the phase measurements become extremely sensitive to noise as the calculated phase approaches 90. ADA2200 Data Sheet There are several ways of digitally processing the output samples to optimize measurement accuracy, bandwidth, and throughput rate. One method is to take the sum of eight samples to return a value. A moving average filter lowers the noise floor of the returned values. The length of the moving average filter is determined by the noise floor and settling time requirements. INTERFACING TO MICROCONTROLLERS The ADA2200 current draw is composed of two main components, the amplifier bias currents and the switched capacitor currents. The amplifier currents are independent of clock frequency; the switched capacitor currents scale in direct proportion to fSI. Figure 30 shows the ADA2200 measured typical current draw at supply voltages of 2.7 V and 3.3 V, as the input clock varies from 1 kHz to 1 MHz, with CLKIN DIV[2:0] = 1. With a 3.3 V supply voltage, the current draw can be estimated with the following equation: The diagram in Figure 28 shows basic circuit configuration driven by a low power microcontroller (the ADuCM361). In this case, the ADA2200 reduces the ADC sampling rate by a factor of 8, and reduces the subsequent signal processing required by the microcontroller. IDD = 290 x 0.2 x fCLKIN A 3.3V where fCLKIN is specified in kHz. AIN0 INN OUTN AIN1 P1.2 P0.6/IRQ2 RST BOOT P1.1 P1.0 475 VREF- AGND ADA2200 VOCM CLKIN XOUT SYNCO 450 425 DVDD_REG AVDD_REG 0.47F x2 P1.7/CS0 P0.3/CS1 P1.6/MOSI0 P0.0/MISO1 P1.4/MISO0 P0.2/MOSI1 P1.5/SCLK0 P0.1/SCLK1 CS/A0 SDIO/SDA RCLK/SDO SCLK/SCL 500 TO HOST, MEMORY OR INTERFACE 350 275 250 0 EEPROM BOOT CONFIGURATION VDD OUTPUT EXCITATION 3.3V RST EEPROM* SCL A0 SDA A1 A2 *AT24C02 OR EQUIVALENT 12295-031 CS/A0 BOOT CLKIN SCLK/SCL SDIO/SDA XOUT GND 400 600 800 1000 Figure 30. Typical Current Draw vs. CLKIN Frequency at VDD = 2.7 V and 3.3 V 3.3V 3.3V 200 CLKIN FREQUENCY (kHz) The diagram in Figure 29 shows a standalone configuration with an EEPROM boot for the ADA2200. The standard oscillator circuit between CLKIN and XOUT generates the clock signal. Holding BOOT low during a power-on reset (POR) forces the ADA2200 to load its configuration from a preprogrammed EEPROM. An EEPROM boot is also initiated by bringing the BOOT pin low while the device in not in reset. OUTP INP OUTN INN VOCM RCLK/SDO 2.7V 300 Figure 28. Fully Programmable Configuration: Interface to Low Power Microcontroller INPUT 375 325 NOTES 1. SOME PIN NAMES OF THE ADuCM361 HAVE BEEN SIMPLIFIED FOR CLARITY. ADA2200 3.3V 400 IDD (A) VDD OUTP 12295-030 INP +VS 0.47F VREF+ AVDD IOVDD 12295-032 ADuCM361 GND POWER DISSIPATION Figure 29. Standalone Configuration Rev. 0 | Page 18 of 24 Data Sheet ADA2200 DEVICE CONFIGURATION The ADA2200 has several registers that can be programmed to customize the device operation. There are two methods for programming the registers: the device can be programmed over the serial port interface, or the I2C master can be used to read the configuration from a serial EEPROM. SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel(R) SSR protocols. The interface allows read/write access to all registers that configure the ADA2200. Single-byte or multiple-byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial port interface can be configured as a single-pin I/O (SDIO) or as two unidirectional pins for input and output (SDIO and SDO). A communication cycle with the ADA2200 has two phases. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first 16 SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle--Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, along with the starting register address for the first byte of the data transfer. The first 16 SCLK rising edges of each communication cycle are used to write the instruction byte into the device. A logic high on the CS/A0 pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next 16 rising SCLK edges represent the instruction bits of the current I/O operation. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte. DATA FORMAT The instruction byte contains the information shown in Table 9. Table 9. Serial Port Instruction Byte MSB I15 R/W I14 A14 I13 A13 I12 A12 ... ... I2 A2 I1 A1 LSB I0 A0 R/W, Bit 15 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A14 to A0, Bit 14 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A14 is the starting byte address. The remaining register addresses are generated by the device based on the LSB first bit (Register 0x0000, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK/SCL) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 20 MHz. All data input is registered on the rising edge of the SCLK signal. All data is driven out on the falling edge of the SCLK signal Chip Select (CS/A0) An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. When the CS/A0 pin is high, the SDO and SDIO signals go to a high impedance state. Keep the CS/A0 pin low throughout the entire communication cycle. Serial Data I/O (SDIO/SDA) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x0000, Bit 3 and Bit 4. The default is Logic 0, configuring the SDIO/SDA pin as unidirectional. Serial Data Output (RCLK/SDO) If the ADA2200 is configured for 4-wire SPI operation, this pin can be used as the serial data output pin. If the device is configured for 3-wire SPI operation, this pin can be used as an output for the reference clock (RCLK) signal. Setting the RCLK select bit (Register 0x002A, Bit 3) high activates the RCLK signal. SERIAL PORT OPTIONS The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB first bit (Register 0x0000, Bit 6). The default is MSB first (LSB first = 0). When the LSB first bit = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes follow from high address to low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. When the LSB first bit = 1, the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes follow from the low address to the high address. In LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle. If the MSB first mode is active, the data address is decremented for each successive read or write operation performed in a multibyte register access. If the LSB first mode is active, the data address increments for each successive read or write operation performed in a multibyte register access. Rev. 0 | Page 19 of 24 ADA2200 Data Sheet INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SDIO R/W A14 A13 A3 A2 A1 A0 D7N D6N D5N D30 D20 D10 D00 12295-033 SCLK Figure 31. Serial Port Interface Timing, MSB First INSTRUCTION CYCLE DATA TRANSFER CYCLE The load cycle completes within 10,000 clock cycles of CLKIN (or CLKIN divided by the current value of CLKIN DIV[2:0] if the load cycle is being initiated by the BOOT pin). CS A0 A1 A2 A12 A13 A14 R/W D00 D10 D20 D4N D5N D6N D7N 12295-034 SCLK SDIO In addition, the LSB of the EEPROM status register indicates whether the load cycle is complete. Logic 1 represents successful completion of the load cycle. Logic 0 represents the occurrence of a timeout violation during the loading cycle. In the event of a timeout or the successful completion of the load from a memory cycle, the ADA2200 I2C master interface disables, and the ADA2200 SPI interface reenables, allowing the user communication access to the device. Figure 32. Serial Port Interface Timing, LSB First BOOTING FROM EEPROM The device can load the internal registers from the EEPROM using the internal I2C master to customize the operation of the ADA2200. To enable this feature, the user must control either the RST pin or the BOOT pin. In either case, the device boots from the EEPROM only when it is out of reset and the master clock is active. Enabling Load from Memory A boot from the EEPROM is initiated by two methods. To initiate loading via the BOOT pin, the device must be out of reset, and the BOOT pin is brought low for a minimum of two clock cycles of the master clock. After it is initiated, the boot completes irrespective of the state of the BOOT pin. To initiate subsequent boots, the BOOT pin must be brought high and then low for a minimum of two clock cycles of the master clock. To initiate loading via the RST pin, the BOOT pin must be low. The RST pin can be tied high and the ADA2200 loads from the EEPROM when the device is powered up and the internal POR cycle completes. To initiate subsequent boots, the ADA2200 can be power cycled or the RST pin can be brought low and then high. Dual Configuration/Dual Device Memory Load The CS/A0 pin allows a single EEPROM device to support a dual configuration for a single ADA2200 device or different configurations for two different ADA2200 devices. To ensure reliable operation, set the CS/A0 pin to the desired state before initiating a boot, and then hold the state for the entire duration of the boot. To configure a single ADA2200 device, the EEPROM must have a word page size that supports a minimum of 32 words, each of 8 bits per word. To support two devices, or a dual configuration for a single device, the EEPROM must have at least two word pages. The ADA2200 configuration data for each device must be allocated to the EEPROM memory within a single word page. Using SPI Master with EEPROM Loading The load from a memory cycle requires an I2C communication bus between the ADA2200 and the EEPROM device; however, the ADA2200 can still be controlled by the SPI interface after the load from the memory cycle is complete. It is recommended that the CS/A0 pin return to logic high after the load from the memory cycle and before the first SPI read or write command. This allows the user to ensure that the proper setup time elapses before the initiation of a SPI read/write command (see Table 2). The SPI interface is disabled while the ADA2200 is loading the EEPROM. Load from Memory Cycle The ADA2200 reads the first 28 bytes of the EEPROM. The first 27 bytes represent the contents to be loaded into Register 0x0011 to Register 0x0027. Byte 28 contains the checksum stored in the EEPROM. The ADA2200 calculates the checksum for the first 27 bytes that it reads back and compares it to the checksum in the EEPROM. The ADA2200 calculated checksum is accessible by reading the EEPROM checksum register (Register 0x002E). If the ADA2200 checksum matches the checksum stored in the EEPROM, the load from the EEPROM was successful. The load from the EEPROM pass or fail status is recorded in the EEPROM status register (Register 0x002F). Rev. 0 | Page 20 of 24 Data Sheet ADA2200 DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map1 Addr. (Hex) 0x0000 0x0006 0x0010 0x0011 to 0x0027 0x0028 Register Name Serial interface Chip type Filter strobe Filter configuration Analog pin configuration Bit 7 Reset Bit 6 LSB first 0 Bit 5 Address increment 0 Bit 4 SDO active 0 0 0 0 0 0 X X X X SYNCO invert Mixer enable Bit 3 SDO active 0 Coefficient[7:0] X Bit 2 Bit 1 Address LSB first increment Die revision[3:0] 0 X INP gain Sync control X X 0x002A Demod control Clock configuration Digital pin configuration X PHASE90 SYNCO output enable X X X X X X X X X X X Core reset Checksum X X X X X X Checksum value[7:0] X EEPROM status X X X X X 0x002C 0x002D 0x002E 0x002F 1 2 Default2 0x00 0x00 (read only) 0x00 See Table 11 0x00 Load coefficients[1:0] 0x0029 0x002B Bit 0 Reset Clock source select SYNCO edge select[3:0] RCLK select CLKIN DIV[2:0] Checksum failed 0x2D VOCM select[2:0] 0x18 RCLK DIV[1:0] Checksum passed 0x02 RCLK/SDO output enable Core reset 0x01 0x00 N/A (read only) N/A (read only) Boot from EEPROM complete X means don't care. N/A means not applicable. Table 11. Device Configuration Register Descriptions Name Serial Interface Chip Type Address (Hex) 0x0000 0x0006 Bits 7 Bit Name Reset Description Writing a 1 to this bit places the device in reset. The device remains in reset until a 0 is written to this bit. All of the configuration registers return to their default values. Default1 0 6 LSB first 0 5 Address increment 4 SDO active 3 2 1 0 [3:0] SDO active Address increment LSB first Reset Die revision[3:0] Serial port communication, LSB or MSB first. 0 = MSB first. 1 = LSB first. Controls address increment mode for multibyte register access. 0 = address decrement. 1 = address increment. 4-wire SPI select. 0 = SDIO operates as a bidirectional input/output. The SDO signal is disabled. 1 = SDIO operates as an input only. The SDO signal is active. This bit is a mirror of Bit 4 in Register 0x0000. This bit is a mirror of Bit 5 in Register 0x0000. This bit is a mirror of Bit 6 in Register 0x0000. This bit is a mirror of Bit 7 in Register 0x0000. Die revision number. Rev. 0 | Page 21 of 24 0 0 0 0 0 0 0000 ADA2200 Name Filter Strobe Filter Configuration Analog Pin Configuration Data Sheet Address (Hex) 0x0010 Bits [7:0] Bit Name Load coefficients[1:0] 0x0011 0x0012 0x0013 0x0014 0x0015 0x0016 0x0017 0x0018 0x0019 0x001A 0x001B 0x001C 0x001D 0x001E 0x001F 0x0020 0x0021 0x0022 0x0023 0x0024 0x0025 0x0026 0x0027 0x0028 [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] 1 Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] Coefficient[7:0] INP gain 0 Clock source select Sync Control 0x0029 5 4 [3:0] SYNCO output enable SYNCO invert SYNCO edge select Demod Control 0x002A 6 PHASE90 4 Mixer enable 3 RCLK select [2:0] VOCM select Description When toggled from 0 to 1, the filter coefficients in configuration Register 0x0011 through Register 0x0027 are loaded into the IIR filter. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. Programmable filter coefficients. 1 = only the INP input signal is sampled. An additional 6 dB of gain is applied to the signal path. Default1 00 0 = device is configured to generate a clock if a crystal or resonator is placed between the XOUT and CLKIN pins. 1 = device is configured to accept a CMOS level clock on the CLKIN pin. The internal XOUT driver is disabled. 1 = enables the SYNCO output pad driver. 1 = inverts the SYNCO signal. These bits select one of 16 different edge locations for the SYNCO pulse relative to the output sample window. See Figure 24 for details. 1 = delays the phase between the RCLK output and the strobe controlling the mixing signal. See Figure 23 for details. 1 = the last sample that is taken while RCLK is active remains held while RCLK is inactive. 0 = sends the SDO signal to the output driver of Pin 13. 1 = sends the RCLK signal to the output driver of Pin 13. 000 = set the VOCM pin to VDD/2. Low power mode. 001 = use the external reference to drive VOCM. 010 = set the VOCM pin to VDD/2. Fast settling mode. 101 = set the VOCM pin to 1.2 V. 0 Rev. 0 | Page 22 of 24 0xC022 0x0F2 0x1D2 0xD72 0xC02 0x0F2 0xC02 0x0F2 0x1D2 0x972 0x7E2 0x882 0xC02 0x0F2 0xC02 0x0F2 0xC02 0x0F2 0x002 0xE02 0x232 0x022 0x242 0 1 0 1101 0 1 1 000 Data Sheet Name Clock Configuration Address (Hex) 0x002B ADA2200 Bits [4:2] Bit Name CLKIN DIV[2:0] [1:0] RCLK DIV[1:0] Description The division factor between fCLKIN and fSI. 000 = divide by 1. 001 = divide by 16. 010 = divide by 64. 100 = divide by 256. These bits set the division factor between fSO and fM. 00 = reserved. 01 = the frequency of RCLK is fSO/4. 10 = the frequency of RCLK is fSO/8. 11 = reserved. 1 = RCLK/SDO output pad driver is enabled. Digital Pin Configuration Core Reset 0x002C 0 0x002D 0 RCLK/SDO output enable Core reset Checksum 0x002E [7:0] Checksum value[7:0] EEPROM Status 0x002F 2 Checksum failed 1 Checksum passed 0 Boot from EEPROM complete 2 NA/ means not applicable. The filter coefficients listed are the default values programmed into the filter on reset. The value read back from the registers is 0x00. VDD ADA2200 BPF INP OUTP 8 0x0028[1] INN S/H fNYQ/4 LPF 0x0024 TO 0x0027 OUTN VOCM 0x002A[4] 0 VOCM GEN 1 0x002A[6] 0x002B[4:2] CLKIN fCLKIN {000,001,010,100} fSI / {1,16,64,256} TRI /8 SYNC GEN fSO {1,0} / {4,8} 0x002A[2:0] 0 0x002B[0] 1 90 fM 1 EN RCLK/SDO 0 RCLK 0x002C[0] 0x002A[3] 0x0029[3:0] 0x0029[4] 0x0028[0] CLKIN 1 XOUT /32 SDO EN 0 EN SPI/I2C MASTER CONTROL REGISTERS SCLK/SCL SDIO/SDA CS/A0 0x0029[5] SYNCO RST Figure 33. Detailed Block Diagram Rev. 0 | Page 23 of 24 BOOT 12295-037 1 1 = puts the device core into reset. The values of the SPI registers are preserved. This does not initiate a boot from the EEPROM. 0 = core reset is deasserted. This is the 8-bit checksum calculated by the ADA2200, performed on the data it reads from the EEPROM. 1 = calculated checksum does not match the checksum byte read from the EEPROM. 1 = calculated checksum matches the checksum byte read from the EEPROM. 1 = boot from the EEPROM has completed. 0 = boot from the EEPROM has timed out. Wait 10,000 clock cycles after the boot is initiated to check for boot completion. Default1 000 10 1 0 N/A N/A N/A N/A ADA2200 Data Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 34. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model1 ADA2200ARUZ ADA2200ARUZ-REEL7 ADA2200-EVALZ ADA2200SDP-EVALZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation board with EEPROM boot Evaluation board with SDP-B interface option Z = RoHS-Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12295-0-8/14(0) Rev. 0 | Page 24 of 24 Package Option RU-16 RU-16 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADA2200ARUZ-REEL7 ADA2200-EVALZ ADA2200SDP-EVALZ