Preliminary User’s Manual
µ
PD78F9221
µ
PD78F9222
78K0S/KA1+
8-Bit Single-Chip Microcontrollers
©
Printed in Japan
Document No. U16898EJ2V0UD00 (2nd edition)
Date Published November 2004 N CP(K)
2003
Preliminary User’s Manual U16898EJ2V0UD
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[MEMO]
Preliminary User’s Manual U16898EJ2V0UD 3
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
Preliminary User’s Manual U16898EJ2V0UD
4
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PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the
United States and Japan.
Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, inc.
The information contained in this document is being issued in advance of the production cycle for the
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•
•
•
•
•
•
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M5D 02. 11-1
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1)
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"Standard":
"Special":
"Specific":
Preliminary User’s Manual U16898EJ2V0UD 5
Regional Information
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
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Some information contained in this document may vary from country to country. Before using any NEC
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Preliminary User’s Manual U16898EJ2V0UD
6
INTRODUCTION
Target Readers This manual is intended for user engineers who wish to understand the functions of
the 78K0S/KA1+ in order to design and develop its application systems and
programs.
The target devices are the following subseries products.
• 78K0S/KA1+:
µ
PD78F9221, 78F9222
Purpose This manual is intended to give users on understanding of the functions described in
the Organization below.
Organization Two manuals are available for the 78K0S/KA1+: this manual and the Instruction
Manual (common to the 78K/0S Series).
78K0S/KA1+
User’s Manual
78K/0S Series
Instructions
User’s Manual
• Pin functions
• Internal block functions
• Interrupts
• Other internal peripheral functions
• Electrical specifications (target values)
• CPU function
• Instruction set
• Instruction description
How to Use This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
◊ To understand the overall functions of 78K0S/KA1+
→ Read this manual in the order of the CONTENTS. The mark shows major
revised points.
◊ How to read register formats
→ For a bit number enclosed in a square, the bit name is defined as a reserved
word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr
directive in the CC78K0S.
◊ To learn the detailed functions of a register whose register name is known
→ See APPENDIX C REGISTER INDEX.
◊ To learn the details of the instruction functions of the 78K/0S Series
→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately
available.
◊ To learn the electrical specifications (target) of the 78K0S/KA1+
→ See CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES).
Preliminary User’s Manual U16898EJ2V0UD 7
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
78K0S/KA1+ User’s Manual This manual
78K/0S Series Instructions User’s Manual U11047E
Documents Related to Development Software Tools (User’s Manuals)
Document Name Document No.
Operation U16656E
Language U14877E
RA78K0S Assembler Package
Structured Assembly Language U11623E
Operation U16654E CC78K0S C Compiler
Language U14872E
ID78K0S-NS Ver. 2.52 Integrated Debugger Operation U16584E
ID78K0S-QB Ver. 2.81 Integrated Debugger Operation U17287E
PM plus Ver. 5.20 U16934E
Documents Related to Development Hardware Tools (User’s Manuals)
Document Name Document No.
IE-78K0S-NS In-Circuit Emulator U13549E
IE-78K0S-NS-A In-Circuit Emulator U15207E
QB-78K0SKX1MINI In-Circuit Emulator U17272E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Preliminary User’s Manual U16898EJ2V0UD
8
Documents Related to Flash Memory Writing
Document Name Document No.
PG-FP4 Flash Memory Programmer User’s Manual U15260E
PG-FPL2 Flash Memory Programmer User’s Manual U17307E
Other Related Documents
Document Name Document No.
SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
Preliminary User’s Manual U16898EJ2V0UD 9
CONTENTS
CHAPTER 1 OVERVIEW.........................................................................................................................14
1.1 Features......................................................................................................................................14
1.2 Application Fields......................................................................................................................14
1.3 Ordering Information.................................................................................................................15
1.4 Pin Configuration (Top View) ...................................................................................................15
1.5 78K0S/Kx1+ Product Lineup.....................................................................................................16
1.6 Block Diagram............................................................................................................................17
1.7 Functional Outline .....................................................................................................................18
CHAPTER 2 PIN FUNCTIONS...............................................................................................................19
2.1 Pin Function List........................................................................................................................19
2.2 Pin Functions .............................................................................................................................21
2.2.1 P20 to P23 (Port 2)......................................................................................................................21
2.2.2 P30, P31, and P34 (Port 3).........................................................................................................21
2.2.3 P40 to P45 (Port 4)......................................................................................................................22
2.2.4 P121 to P123 (Port 12) ................................................................................................... .............22
2.2.5 P130 (Port 13).............................................................................................................................22
2.2.6 RESET........................................................................................................................................22
2.2.7 X1 and X2 ...................................................................................................................................22
2.2.8 AVREF ..........................................................................................................................................23
2.2.9 VDD .............................................................................................................................................23
2.2.10 VSS ..............................................................................................................................................23
2.3 Pin I/O Circuits and Connection of Unused Pins ...................................................................23
CHAPTER 3 CPU ARCHITECTURE......................................................................................................25
3.1 Memory Space............................................................................................................................25
3.1.1 Internal program memory space..................................................................................................27
3.1.2 Internal data memory space........................................................................................................27
3.1.3 Special function register (SFR) area ...........................................................................................28
3.1.4 Data memory addressing............................................................................................................28
3.2 Processor Registers..................................................................................................................30
3.2.1 Control registers..........................................................................................................................30
3.2.2 General-purpose registers...........................................................................................................32
3.2.3 Special function registers (SFRs)........................................................................................ ........33
3.3 Instruction Address Addressing..............................................................................................36
3.3.1 Relative addressing.....................................................................................................................36
3.3.2 Immediate addressing.................................................................................................................37
3.3.3 Table indirect addressing ............................................................................................................37
3.3.4 Register addressing ....................................................................................................................38
3.4 Operand Address Addressing..................................................................................................39
3.4.1 Direct addressing ........................................................................................................................39
3.4.2 Short direct addressing ...............................................................................................................40
3.4.3 Special function register (SFR) addressing.................................................................................41
3.4.4 Register addressing ....................................................................................................................42
3.4.5 Register indirect addressing........................................................................................................43
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3.4.6 Based addressing........................................................................................................................44
3.4.7 Stack addressing.........................................................................................................................44
CHAPTER 4 PORT FUNCTIONS...........................................................................................................45
4.1 Functions of Ports .....................................................................................................................45
4.2 Port Configuration .....................................................................................................................46
4.2.1 Port 2...........................................................................................................................................47
4.2.2 Port 3...........................................................................................................................................48
4.2.3 Port 4...........................................................................................................................................50
4.2.4 Port 12.........................................................................................................................................55
4.2.5 Port 13.........................................................................................................................................57
4.3 Registers Controlling Port Functions......................................................................................57
4.4 Operation of Port Function .......................................................................................................62
4.4.1 Writing to I/O port ........................................................................................................................62
4.4.2 Reading from I/O port..................................................................................................................62
4.4.3 Operations on I/O port.................................................................................................................62
CHAPTER 5 CLOCK GENERATORS...................................................................................................63
5.1 Functions of Clock Generators ................................................................................................63
5.1.1 System clock oscillators ..............................................................................................................63
5.1.2 Clock oscillator for interval time generation.................................................................................63
5.2 Configuration of Clock Generators..........................................................................................64
5.3 Registers Controlling Clock Generators .................................................................................66
5.4 System Clock Oscillators..........................................................................................................69
5.4.1 High-speed Ring-OSC oscillator..................................................................................................69
5.4.2 Crystal/ceramic oscillator.............................................................................................................69
5.4.3 External clock input circuit...........................................................................................................71
5.4.4 Prescaler .....................................................................................................................................71
5.5 Operation of CPU Clock Generator..........................................................................................72
5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware.............................77
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00.............................................................................79
6.1 Functions of 16-Bit Timer/Event Counter 00...........................................................................79
6.2 Configuration of 16-Bit Timer/Event Counter 00 ....................................................................80
6.3 Registers to Control 16-Bit Timer/Event Counter 00..............................................................84
6.4 Operation of 16-Bit Timer/Event Counter 00...........................................................................90
6.4.1 Interval timer operation................................................................................................................90
6.4.2 External event counter operation.................................................................................................93
6.4.3 Pulse width measurement operations..........................................................................................96
6.4.4 Square-wave output operation...................................................................................................104
6.4.5 PPG output operations..............................................................................................................106
6.4.6 One-shot pulse output operation ...............................................................................................109
6.5 Cautions Related to 16-Bit Timer/Event Counter 00.............................................................114
CHAPTER 7 8-BIT TIMER 80..............................................................................................................120
7.1 Function of 8-Bit Timer 80.......................................................................................................120
7.2 Configuration of 8-Bit Timer 80 ..............................................................................................121
7.3 Register Controlling 8-Bit Timer 80........................................................................................123
Preliminary User’s Manual U16898EJ2V0UD 11
7.4 Operation of 8-Bit Timer 80.....................................................................................................124
7.4.1 Operation as interval timer........................................................................................................124
7.5 Notes on 8-Bit Timer 80...........................................................................................................126
CHAPTER 8 8-BIT TIMER H1.............................................................................................................127
8.1 Functions of 8-Bit Timer H1....................................................................................................127
8.2 Configuration of 8-Bit Timer H1 .............................................................................................127
8.3 Registers Controlling 8-Bit Timer H1.....................................................................................130
8.4 Operation of 8-Bit Timer H1....................................................................................................133
8.4.1 Operation as interval timer/square-wave output........................................................................133
8.4.2 Operation as PWM output mode...............................................................................................136
CHAPTER 9 WATCHDOG TIMER.......................................................................................................142
9.1 Functions of Watchdog Timer................................................................................................142
9.2 Configuration of Watchdog Timer..........................................................................................144
9.3 Registers Controlling Watchdog Timer.................................................................................145
9.4 Operation of Watchdog Timer ................................................................................................147
9.4.1 Watchdog timer operation when “low-speed Ring-OSC cannot
be stopped” is selected by option byte......................................................................................147
9.4.2 Watchdog timer operation when “low-speed Ring-OSC can
be stopped by software” is selected by option byte...................................................................149
9.4.3 Watchdog timer operation in STOP mode
(when “low-speed Ring-OSC can be stopped by software” is selected by option byte).............151
9.4.4 Watchdog timer operation in HALT mode
(when “low-speed Ring-OSC can be stopped by software” is selected by option byte).............153
CHAPTER 10 A/D CONVERTER.........................................................................................................154
10.1 Functions of A/D Converter....................................................................................................154
10.2 Configuration of A/D Converter..............................................................................................157
10.3 Registers Used by A/D Converter..........................................................................................158
10.4 A/D Converter Operations.......................................................................................................163
10.4.1 Basic operations of A/D converter.............................................................................................163
10.4.2 Input voltage and conversion results.........................................................................................165
10.4.3 A/D converter operation mode...................................................................................................166
10.5 How to Read A/D Converter Characteristics Table..............................................................168
10.6 Cautions for A/D Converter ....................................................................................................170
CHAPTER 11 SERIAL INTERFACE UART6......................................................................................173
11.1 Functions of Serial Interface UART6 .....................................................................................173
11.2 Configuration of Serial Interface UART6...............................................................................177
11.3 Registers Controlling Serial Interface UART6 ......................................................................180
11.4 Operation of Serial Interface UART6......................................................................................189
11.4.1 Operation stop mode.................................................................................................................189
11.4.2 Asynchronous serial interface (UART) mode ............................................................................190
11.4.3 Dedicated baud rate generator..................................................................................................204
CHAPTER 12 INTERRUPT FUNCTIONS............................................................................................211
12.1 Interrupt Function Types.........................................................................................................211
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12.2 Interrupt Sources and Configuration.....................................................................................212
12.3 Interrupt Function Control Registers.....................................................................................214
12.4 Interrupt Servicing Operation.................................................................................................219
12.4.1 Maskable interrupt request acknowledgment operation.............................................................219
12.4.2 Multiple interrupt servicing.........................................................................................................222
12.4.3 Interrupt request pending...........................................................................................................223
CHAPTER 13 STANDBY FUNCTION..................................................................................................224
13.1 Standby Function and Configuration.....................................................................................224
13.1.1 Standby function........................................................................................................................224
13.1.2 Registers used during standby..................................................................................................226
13.2 Standby Function Operation...................................................................................................227
13.2.1 HALT mode ...............................................................................................................................227
13.2.2 STOP mode...............................................................................................................................230
CHAPTER 14 RESET FUNCTION .......................................................................................................234
14.1 Register for Confirming Reset Source...................................................................................241
CHAPTER 15 POWER-ON-CLEAR CIRCUIT .....................................................................................242
15.1 Functions of Power-on-Clear Circuit .....................................................................................242
15.2 Configuration of Power-on-Clear Circuit...............................................................................243
15.3 Operation of Power-on-Clear Circuit......................................................................................243
15.4 Cautions for Power-on-Clear Circuit......................................................................................244
CHAPTER 16 LOW-VOLTAGE DETECTOR.......................................................................................246
16.1 Functions of Low-Voltage Detector .......................................................................................246
16.2 Configuration of Low-Voltage Detector.................................................................................246
16.3 Registers Controlling Low-Voltage Detector ........................................................................247
16.4 Operation of Low-Voltage Detector........................................................................................249
16.5 Cautions for Low-Voltage Detector........................................................................................252
CHAPTER 17 OPTION BYTE................................................................................................................255
CHAPTER 18 FLASH MEMORY..........................................................................................................258
18.1 Features ....................................................................................................................................258
18.2 Memory Configuration.............................................................................................................259
18.3 Functional Outline....................................................................................................................260
18.4 Writing with Flash Programmer..............................................................................................261
18.5 Programming Environment.....................................................................................................262
18.6 Pin Connection on Board........................................................................................................264
18.6.1 X1 and X2 pins..........................................................................................................................264
18.6.2 RESET pin.................................................................................................................................265
18.6.3 Port pins ....................................................................................................................................266
18.6.4 Power supply.............................................................................................................................266
18.7 On-Board and Off-Board Flash Memory Programming .......................................................267
18.7.1 Controlling flash memory...........................................................................................................267
18.7.2 Flash memory programming mode............................................................................................268
Preliminary User’s Manual U16898EJ2V0UD 13
18.7.3 Communication commands.......................................................................................................268
18.7.4 Security settings........................................................................................................................269
18.8 Flash Memory Programming by Self Writing........................................................................270
18.8.1 Outline of self programming ......................................................................................................270
18.8.2 Cautions on self programming function.....................................................................................273
18.8.3 Registers used for self programming function...........................................................................273
18.8.4 Example of shifting normal mode to self programming mode....................................................281
18.8.5 Example of shifting self programming mode to normal mode....................................................284
18.8.6 Example of block erase operation in self programming mode...................................................287
18.8.7 Example of block blank check operation in self programming mode.........................................290
18.8.8 Example of byte write operation in self programming mode......................................................293
18.8.9 Example of internal verify operation in self programming mode................................................296
18.8.10 Examples of operation when command execution time should
be minimized in self programming mode..................................................................................299
18.8.11 Examples of operation when interrupt-disabled time should
be minimized in self programming mode...................................................................................306
CHAPTER 19 INSTRUCTION SET OVERVIEW.................................................................................317
19.1 Operation..................................................................................................................................317
19.1.1 Operand identifiers and description methods............................................................................317
19.1.2 Description of “Operation” column.............................................................................................318
19.1.3 Description of “Flag” column......................................................................................................318
19.2 Operation List...........................................................................................................................319
19.3 Instructions Listed by Addressing Type...............................................................................324
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES).............................................327
CHAPTER 21 PACKAGE DRAWING..................................................................................................339
APPENDIX A DEVELOPMENT TOOLS ..............................................................................................340
A.1 Software Package....................................................................................................................343
A.2 Language Processing Software.............................................................................................343
A.3 Control Software......................................................................................................................344
A.4 Flash Memory Writing Tools...................................................................................................344
A.5 Debugging Tools (Hardware)..................................................................................................345
A.5.1 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A..............................................345
A.5.2 When using in-circuit emulator QB-78K0SKX1MINI..................................................................345
A.6 Debugging Tools (Software)...................................................................................................346
APPENDIX B NOTES ON TARGET SYSTEM DESIGN...................................................................347
APPENDIX C REGISTER INDEX.........................................................................................................349
C.1 Register Index (Register Name) .............................................................................................349
C.2 Register Index (Symbol)..........................................................................................................351
APPENDIX D REVISION HISTORY.....................................................................................................353
D.1 Major Revisions in This Edition .............................................................................................353
Preliminary User’s Manual U16898EJ2V0UD
14
CHAPTER 1 OVERVIEW
1.1 Features
O Minimum instruction execution time selectable from high speed (0.2
µ
s) and low speed (3.2
µ
s) (with CPU clock
of 10 MHz)
O General-purpose registers: 8 bits × 8 registers
O ROM and RAM capacities
Item
Part number Program Memory (Flash Memory) Memory (Internal High-Speed RAM)
µ
PD78F9221 2 KB 128 bytes
µ
PD78F9222 4 KB 256 bytes
O On-chip power-on clear (POC) circuit and low voltage detector (LVI)
O On-chip watchdog timer (operable on internal low-speed Ring-OSC clock)
O I/O ports: 17
O Timer: 4 channels
• 16-bit timer/event counter: 1 channel
• 8-bit timer: 2 channels
• Watchdog timer: 1 channel
O Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel
O 10-bit resolution A/D converter: 4 channels
O Supply voltage: VDD = 2.0 to 5.5 VNote
O Operating temperature range: TA = −40 to +85°C
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on
clear (POC) circuit is 2.1 V ±0.1 V.
1.2 Application Fields
O Automotive electronics
• System control of body instrumentation system (such as power windows and keyless entry reception)
• Sub-microcontroller of control system
O Household appliances
• Electric toothbrushes
• Electric shavers
O Toys
O Industrial equipment
• Sensor and switch control
• Power tools
CHAPTER 1 OVERVIEW
Preliminary User’s Manual U16898EJ2V0UD 15
1.3 Ordering Information
Part Number Package Internal ROM
µ
PD78F9221MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD78F9222MC-5A4 20-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD78F9221MC-5A4-A 20-pin plastic SSOP (7.62 mm (300)) Flash memory
µ
PD78F9222MC-5A4-A 20-pin plastic SSOP (7.62 mm (300)) Flash memory
Remark The
µ
PD78F9221MC-5A4-A and 78F9222MC-5A4-A are lead-free products.
1.4 Pin Configuration (Top View)
20-pin plastic SSOP (7.62 mm (300))
µ
PD78F9221MC-5A4
µ
PD78F9222MC-5A4
µ
PD78F9221MC-5A4-A
µ
PD78F9222MC-5A4-A
V
SSNote
P121/X1
P122/X2
P123
V
DD
RESET/P34
P31/TI010/TO00/INTP2
P30/TI000/INTP0
P41/INTP3
18
17
16
20
19
15
14
13
12
11
AV
REF
P20/ANI0
P21/ANI1
P22/ANI2
P23/ANI3
P130
P45
P44/RxD6
P43/TxD6/INTP1
P42/TOH1
1
2
3
4
5
6
7
8
9
10
P40
Note In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
ANI0 to ANI3: Analog input RESET: Reset
AVREF: Analog reference voltage RxD6: Receive data
INTP0 to INTP3: External interrupt input TI000, TI010: Timer input
P20 to P23: Port 2 TO00, TOH1: Timer output
P30, P31, P34: Port 3 TxD6: Transmit data
P40 to P45: Port 4 VDD: Power supply
P121 to P123: Port 12 VSS: Ground
P130: Port 13 X1, X2: Crystal oscillator (X1 input clock)
CHAPTER 1 OVERVIEW
Preliminary User’s Manual U16898EJ2V0UD
16
1.5 78K0S/Kx1+ Product Lineup
The following table shows the product lineup of the 78K0S/Kx1+.
Part Number
Item
78K0S/KU1+ 78K0S/KY1+ 78K0S/KA1+ 78K0S/KB1+
Number of pins 8 pins 16 pins 20 pins 30 pins
Flash memory 1 KB, 2 KB, 4 KB 1 KB, 2 KB, 4 KB 2 KB 4 KB 4 KB, 8 KB Internal
memory RAM 128 bytes 128 bytes 128 bytes 256
bytes 256 bytes
Supply voltage VDD = 2.0 to 5.5 VNote
Minimum instruction
execution time 0.20
µ
s (10 MHz, VDD = 4.0 to 5.5 V)
0.33
µ
s (6 MHz, VDD = 3.0 to 5.5 V)
0.40
µ
s (5 MHz, VDD = 2.7 to 5.5 V)
1.0
µ
s (2 MHz, VDD = 2.0 to 5.5 V)
System clock
(oscillation frequency) Internal high-speed Ring-OSC oscillation (8 MHz (TYP.))
Crystal/ceramic oscillation (1 to 10 MHz)
External clock input oscillation (1 to 10 MHz)
Clock for TMH1 and WDT
(oscillation frequency) Internal low-speed Ring-OSC oscillation (240 kHz (TYP.))
CMOS I/O 5 13 15 22
CMOS input 1 1 1 1
Port
CMOS output − − 1 1
16-bit (TM0) 1 ch
8-bit (TMH) 1 ch
8-bit (TM8) − 1 ch
Timer
WDT 1 ch
Serial interface − LIN-Bus-supporting UART: 1 ch
A/D converter 10 bits: 4 ch (2.7 to 5.5V)
Multiplier (8 bits ⋅ 8 bits) − Provided
External 2 4 Interrupts
Internal 5 9
RESET pin Provided
POC 2.1 V ±0.1 V
LVI Provided (selectable by software)
Reset
WDT Provided
Operating temperature range −40 to +85°C
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V POC) of the power-on-clear
(POC) circuit is 2.1 V ±0.1 V.
CHAPTER 1 OVERVIEW
Preliminary User’s Manual U16898EJ2V0UD 17
1.6 Block Diagram
78K0S
CPU
core
Internal
high-speed
RAM
Flash
memory
V
SSNote
V
DD
TOH1/P42
Port 2 P20 to P23
4
Port 4 P40 to P45
6
Port 13 P130
Power on clear/
low voltage
indicator
POC/LVI
control
Reset control
Port 3 P30, P31
2P34
P121 to P123
3
Port 12
System control
High-speed
Ring-OSC
RESET/P34
X1/P121
X2/P122
Low-speed
Ring-OSC
INTP0/P30
INTP1/P43
INTP2/P31
INTP3/P41
ANI0/P20 to
ANI3/P23 4A/D converter
AV
REF
8-bit timer
80
Watchdog timer
8-bit timer
H1
16-bit timer/event
counter
00
TO00/TI010/P31
TI000/P30
RxD6/P44
TxD6/P43
Serial interface
UART6
Interrupt control
Note In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
CHAPTER 1 OVERVIEW
Preliminary User’s Manual U16898EJ2V0UD
18
1.7 Functional Outline
Item
µ
PD78F9221
µ
PD78F9222
Flash memory 2 KB 4 KB Internal
memory High-speed RAM 128 bytes 256 bytes
Memory space 64 KB
X1 input clock (oscillation frequency) Crystal/ceramic/external clock input:
10 MHz (VDD = 2.0 to 5.5 V)
High speed (oscillation
frequency) Internal Ring oscillation: 8 MHz (TYP.) Ring-OSC
clock
Low speed (for TMH1
and WDT) Internal Ring oscillation: 240 kHz (TYP.)
General-purpose registers 8 bits × 8 registers
Minimum instruction execution time 0.2
µ
s/0.4
µ
s/0.8
µ
s/1.6
µ
s/3.2
µ
s (X1 input clock: fX = 10 MHz)
Instruction set • 16-bit operation
• Bit manipulation (set, reset, test), etc.
I/O port Total: 17 pins
CMOS I/O: 15 pins
CMOS input: 1 pin
CMOS output: 1 pin
Timer • 16-bit timer/event counter: 1 channel
• 8-bit timer (timer H1): 1 channel
• 8-bit timer (timer 80): 1 channel
• Watchdog timer: 1 channel
Timer output 2 pins (PWM: 1 pin)
A/D converter 10-bit resolution × 4 channels
Serial interface LIN-bus-supporting UART mode: 1 channel
External 4 Vectored
interrupt sources Internal 9
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on clear
• Internal reset by low-voltage detector
Supply voltage VDD = 2.0 to 5.5 VNote
Operating temperature range TA = −40 to +85°C
Package 20-pin plastic SSOP (7.62 mm (300))
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
Preliminary User’s Manual U16898EJ2V0UD 19
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Function List
(1) Port pins
Pin Name I/O Function After Reset Alternate-
Function Pin
P20 to P23 I/O Port 2.
4-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting software.
Input ANI0 to ANI3
P30 TI000/INTP0
P31
I/O Can be set to input or output mode in 1-
bit units.
An on-chip pull-up resistor can be
connected by setting software.
Input
TI010/TO00/
INTP2
P34 Input
Port 3
Input only Input RESET
P40 −
P41 INTP3
P42 TOH1
P43 TxD6/INTP1
P44 RxD6
P45
I/O Port 4.
6-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected by setting software.
Input
−
P121 X1
P122 X2
P123
I/O Port 12.
3-bit I/O port.
Can be set to input or output mode in 1-bit units.
An on-chip pull-up resistor can be connected only to P123 by
setting software.
Input
−
P130 Output Port 13.
1-bit output-only port Output −
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD
20
(2) Non-port pins
Pin Name I/O Function After Reset Alternate-
Function Pin
INTP0 P30/TI000
INTP1 P43/TxD6
INTP2 P31/TI010/TO00
INTP3
Input External interrupt input for which the valid edge (rising edge,
falling edge, or both rising and falling edges) can be specified Input
P41
RxD6 Input Serial data input for asynchronous serial interface Input P44
TxD6 Output Serial data output for asynchronous serial interface Input P43/INTP1
TI000 External count clock input to 16-bit timer/event counter 00.
Capture trigger input to capture registers (CR000 and CR010) of
16-bit timer/event counter 00
P30/INTP0
TI010
Input
Capture trigger input to capture register (CR000) of 16-bit
timer/event counter 00
Input
P31/TO00/INTP2
TO00 Output 16-bit timer/event counter 00 output Input P31/TI010/INTP2
TOH1 Output 8-bit timer H1 output Input P42
ANI0 to ANI3 Input Analog input of A/D converter Input P20 to P23
AVREF − Reference voltage of A/D converter − −
RESET Input System reset input − −
X1 Input Connection of crystal/ceramic resonator for system clock
oscillation.
External clock input
− P121
X2 − Connection of crystal/ceramic resonator for system clock
oscillation.
− P122
VDD − Positive power supply − −
VSS − Ground potential − −
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 21
2.2 Pin Functions
2.2.1 P20 to P23 (Port 2)
P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input
analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units.
(1) Port mode
P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using
port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pull-
up resistor option register 2 (PU2).
(2) Control mode
P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter. When using these pins as
analog input pins, refer to 10.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23.
2.2.2 P30, P31, and P34 (Port 3)
P30 and P31 constitute a 2-bit I/O port, port 3. In addition to I/O port pins, these pins also have functions to
input/output a timer signal, and input an external interrupt request signal.
P34 is a 1-bit input-only port. This pin is also used as a RESET pin.
P30 and P31 can be set to the following operation modes in 1-bit units.
(1) Port mode
P30 and P31 function as a 2-bit I/O port. Each bit of this port can be set to the input or output mode by using
port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pull-
up resistor option register 3 (PU3).
P34 functions as a 1-bit input-only port.
(2) Control mode
P30 and P31 function to input/output signals to/from internal timers, and to input an external interrupt request
signal.
(a) INTP0 and INTP2
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TI000
This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the
capture registers (CR000 and CR010) of 16-bit timer/event counter 00.
(c) TI010
This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.
(d) TO00
This pin outputs a signal from 16-bit timer/event counter 00.
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD
22
2.2.3 P40 to P45 (Port 4)
P40 to P45 constitute a 6-bit I/O port, port 4. In addition to I/O port pins, these pins also have functions to output a
timer signal, input external interrupt request signals, and input/output the data of the serial interface.
These pins can be set to the following operation modes in 1-bit units.
(1) Port mode
P40 to P45 function as a 6-bit I/O port. Each bit of this port can be set to the input or output mode by using
port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull-
up resistor option register 4 (PU4).
(2) Control mode
P40 to 45 function to output a signal from an internal timer, input external interrupt request signals, and
input/output data of the serial interface.
(a) INTP1 and INTP3
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both
rising and falling edges) can be specified.
(b) TOH1
This is the output pin of 8-bit timer H1.
(c) TxD6
This pin outputs serial data from the asynchronous serial interface.
(d) RxD6
This pin inputs serial data to the asynchronous serial interface.
2.2.4 P121 to P123 (Port 12)
P121 to P123 constitute a 3-bit I/O port, port 12.
Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). An on-chip pull-
up resistor can be connected to P123 by using pull-up resistor option register 12 (PU12).
P121 and P122 also function as the X1 and X2 pins, respectively.
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
2.2.5 P130 (Port 13)
This is a 1-bit output-only port.
2.2.6 RESET
This pin inputs an active-low system reset signal.
2.2.7 X1 and X2
These pins connect an oscillator to oscillate the X1 input clock.
Supply an external clock to X1.
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 23
2.2.8 AVREF
This pin inputs a reference voltage to the internal A/D converter. When the A/D converter is not used, connect this
pin to VDD.
2.2.9 VDD
This is the positive power supply pin.
2.2.10 VSS
This is the ground pin.
In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS
to a stabilized GND (= 0 V).
2.3 Pin I/O Circuits and Connection of Unused Pins
Table 2-1 shows I/O circuit type of each pin and the connections of unused pins.
For the configuration of the I/O circuit of each type, refer to Figure 2-1.
Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pin
P20/ANI0 to P23/ANI3 11 Input: Independently connect to AVREF or VSS via a resistor.
Output: Leave open.
P30/TI000/INTP0
P31/TI010/TO00/INTP2
8-A
I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P34/RESET 2 Input Connect to VDD via a resistor.
P40
P41/INTP3
P42/TOH1
P43/TxD6/INTP1
P44/RxD6
P45
8-A Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P121/X1
P122/X2
16-B Input: Independently connect to VSS via a resistor.
Output: Leave open.
P123 8-A
I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P130 3-C Output Leave open.
AVREF − Input Directly connect to VDD.
CHAPTER 2 PIN FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD
24
Figure 2-1. Pin I/O Circuits
IN
V
DD
P-ch
N-ch
Data OUT
Data
Output
disable
AV
REF
P-ch
N-ch
IN/OUT
AV
REF
(Threshold voltage)
V
SS
P-ch
N-ch
+
Input
enable
-
Pull up
enable
V
DD
P-ch
Pull up
enable
Data
Output
disable
V
DD
P-ch
V
DD
P-ch
IN/OUT
N-ch
P-ch
Feedback
cut-off
X1,
IN/OUT X2,
IN/OUT
OSC
enable
Data
Output
disable
V
DD
P-ch
N-ch
Data
Output
Disable
P-ch
N-ch
Type 2
Type 3-C
Type 8-A
Type 16-B
Type 11
Schmitt-triggered input with hysteresis characteristics Comparator
Preliminary User’s Manual U16898EJ2V0UD 25
CHAPTER 3 CPU ARCHITECTURE
3.1 Memory Space
The 78K0S/KA1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps.
Figure 3-1. Memory Map (
µ
PD78F9221)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
128 × 8 bits
Flash memory
2,048 × 8 bits
Use prohibited
Program memory
space
Data memory
space
Program area
Option byte area
Program area
CALLT table area
Vector table area
FFFFH
07FFH
0080H
007FH
0082H
0081H
0040H
003FH
0022H
0021H
0000H
FF00H
FEFFH
FE80H
FE7FH
0800H
F7FFH
0000H
Protect byte area
Remark The option byte and protect byte are 1 byte each.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD
26
Figure 3-2. Memory Map (
µ
PD78F9222)
Special function registers
(SFR)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Flash memory
4,096 × 8 bits
Program memory
space
Data memory
space
Program area
Option byte area
Program area
CALLT table area
Vector table area
Use prohibited
FFFFH
0FFFH
0000H
0080H
007FH
0082H
0081H
0040H
003FH
0022H
0021H
FF00H
FEFFH
FE00H
FDFFH
1000H
0FFFH
0000H
Protect byte area
Remark The option byte and protect byte are 1 byte each.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 27
3.1.1 Internal program memory space
The internal program memory space stores programs and table data. This space is usually addressed by the
program counter (PC).
The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities.
Table 3-1. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
µ
PD78F9221 2,048 × 8 bits
µ
PD78F9222
Flash memory
4,096 × 8 bits
The following areas are allocated to the internal program memory space.
(1) Vector table area
The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program
start addresses to be used when branching by RESET input or interrupt request generation. Of a
16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd
address.
Table 3-2. Vector Table
Vector Table Address Interrupt Request Vector Table Address Interrupt Request
0000H Reset input 0012H INTAD
0006H INTLVI 0016H INTP2
0008H INTP0 0018H INTP3
000AH INP1 001AH INTTM80
000CH INTTMH1 001CH INTSRE6
000EH INTTM000 001EH INTSR6
0010H INTTM010 0020H INTST6
Caution No interrupt sources correspond to the vector table address 0014H.
(2) CALLT instruction table area
The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of
addresses 0040H to 007FH.
(3) Option byte area
The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 17 OPTION
BYTE.
(4) Protect byte area
The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 18 FLASH
MEMORY.
3.1.2 Internal data memory space
128-byte internal high-speed RAM is provided in the
µ
PD78F9221 and 256-byte in the
µ
PD78F9222.
The internal high-speed RAM can also be used as a stack memory.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD
28
3.1.3 Special function register (SFR) area
Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see
Table 3-3).
3.1.4 Data memory addressing
The 78K0S/KA1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as
possible. The area (FE80H to FEFFH or FE00H to FEFFH) which contains a data memory and the special function
register area (SFR) can be accessed using a unique addressing mode in accordance with eac h function. Figures 3-3
and 3-4 illustrate the data memory addressing.
Figure 3-3. Data Memory Addressing (
µ
PD78F9221)
Special function registers (SFR)
256 × 8 bits
Internal high-speed RAM
128 × 8 bits
Flash memory
2,048 × 8 bits
Use prohibted
Direct addressing
Register indirect addressing
Based addressing
SFR addressing
Short direct addressing
FFFFH
FF00H
FEFFH
FF20H
FE1FH
FE80H
FE7FH
0800H
07FFH
0000H
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 29
Figure 3-4. Data Memory Addressing (
µ
PD78F9222)
Special function registers (SFR)
256 × 8 bits
Internal high-speed RAM
256 × 8 bits
Flash memory
4,096 × 8 bits
Use prohibited
Direct addressing
Register indirect addressing
Based addressing
SFR addressing
Short direct addressing
FFFFH
FF00H
FEFFH
FF20H
FE1FH
FE00H
FDFFH
FE20H
FE1FH
1000H
0FFFH
0000H
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD
30
3.2 Processor Registers
The 78K0S/KA1+ provides the following on-chip processor registers.
3.2.1 Control registers
The control registers have special functions to control the program sequence statuses and stack memory. The
control registers include a program counter, a program status word, and a stack pointer.
(1) Program counter (PC)
The program counter is a 16-bit register which holds the address information of the next program to be
executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to
be fetched. When a branch instruction is executed, immediate data or register contents are set.
RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.
Figure 3-5. Program Counter Configuration
015
PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
(2) Program status word (PSW)
The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW
instruction execution and are automatically restored upon execution of the RETI and POP PSW instructions.
RESET input sets PSW to 02H.
Figure 3-6. Program Status Word Configuration
70
IE Z 0 AC 0 0 1 CY
PSW
(a) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests except non-maskable interrupt
are disabled.
When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with
an interrupt mask flag for various interrupt sources.
This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI
instruction execution.
(b) Zero flag (Z)
When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.
(c) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all
other cases.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 31
(d) Carry flag (CY)
This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It
stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit
operation instruction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM
area can be set as the stack area.
Figure 3-7. Stack Pointer Configuration
015
SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented before writing (saving) to the stack memory and is incremented after reading
(restoring) from the stack memory.
Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.
Caution Since reset input makes the SP contents undefined, be sure to initialize the SP before using
the stack memory.
Figure 3-8. Data to Be Saved to Stack Memory
Interrupt
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower half
register pairs
SP SP _ 2
SP _ 2
CALL, CALLT
instructions
PUSH rp
instruction
SP _ 1
SP
SP SP _ 2
SP _ 2
SP _ 1
SP
PC7 to PC0
SP _ 3
SP _ 2
SP _ 1
SP
SP SP _ 3
Upper half
register pairs
Figure 3-9. Data to Be Restored from Stack Memory
RETI instruction
PSW
PC15 to PC8
PC15 to PC8
PC7 to PC0
Lower half
register pairs
RET instructionPOP rp
instruction
SP PC7 to PC0
Upper half
register pairs
SP + 1
SP SP + 2
SP
SP + 1
SP SP + 2
SP
SP + 1
SP + 2
SP SP + 3
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD
32
3.2.2 General-purpose registers
A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register
(AX, BC, DE, and HL).
Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Figure 3-10. General-Purpose Register Configuration
(a) Absolute names
R0
15 0 7 0
16-bit processing 8-bit processing
RP3
RP2
RP1
RP0 R1
R2
R3
R4
R5
R6
R7
(b) Function names
X
15 0 7 0
16-bit processing 8-bit processing
HL
DE
BC
AX A
C
B
E
D
L
H
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 33
3.2.3 Special function registers (SFRs)
Unlike the general-purpose registers, each special function register has a special function.
The special function registers are allocated to the 256-byte area FF00H to FFFFH.
The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and
bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register
type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
• 8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
• 16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying
an address, describe an even address.
Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:
• Symbol
Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the
RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these
symbols can be used as instruction operands if an assembler or integrated debugger is used.
• R/W
Indicates whether the special function register can be read or written.
R/W: Read/write
R: Read only
W: Write only
• Number of bits manipulated simultaneously
Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.
• After reset
Indicates the status of the special function register when a reset is input.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD
34
Table 3-3. Special Function Registers (1/2)
Number of Bits Manipulated
Simultaneously
Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF02H Port register 2 P2 √ √ −
FF03H Port register 3 P3 √ √ −
FF04H Port register 4 P4 √ √ −
FF0CH Port register 12 P12 √ √ −
FF0DH Port register 13 P13
R/W
Note 1
√ √ −
FF0EH 8-bit timer H compare register 01 CMP01 − √ −
FF0FH 8-bit timer H compare register 11 CMP11
R/W
− √ −
00H
FF12H
FF13H
16-bit timer counter 00 TM00 R − − √Note 2 0000H
FF14H
FF15H
16-bit timer capture/compare register 000 CR000 − − √Note 2 0000H
FF16H
FF17H
16-bit timer capture/compare register 010 CR010
R/W
− − √Note 2 0000H
FF18H
FF19H
10-bit A/D conversion result register ADCR − − √Note 2
FF1AH 8-bit A/D conversion result register ADCRH
R
− √ −
Undefined
FF22H Port mode register 2 PM2 √ √ −
FF23H Port mode register 3 PM3 √ √ −
FF24H Port mode register 4 PM4 √ √ −
FF2CH Port mode register 12 PM12 √ √ −
FFH
FF32H Pull-up resistance option register 2 PU2 √ √ −
FF33H Pull-up resistance option register 3 PU3 √ √ −
FF34H Pull-up resistance option register 4 PU4 √ √ −
FF3CH Pull-up resistance option register 12 PU12 √ √ −
00H
FF48H Watchdog timer mode register WDTM − √ − 67H
FF49H Watchdog timer enable register WDTE − √ − 9AH
FF50H Low voltage detect register LVIM √ √ −
FF51H Low voltage detection level select register LVIS
R/W
− √ −
00HNote 3
FF54H Reset control flag register RESF R − √ − 00HNote 4
FF58H Low-speed Ring-OSC mode register LSRCM √ √ −
FF5AH High-speed Ring-OSC mode register HSRCM √ √ −
FF60H 16-bit timer mode control register 00 TMC00 √ √ −
FF61H Prescaler mode register 00 PRM00 √ √ −
FF62H Capture/compare control register 00 CRC00 √ √ −
FF63H 16-bit timer output control register 00 TOC00 √ √ −
FF70H 8-bit timer H mode register 1 TMHMD1
R/W
√ √ −
00H
Notes 1. Only P34 is an input-only port.
2. A 16-bit access is possible only by the short direct addressing.
3. Retained only after a reset by LVI.
4. Varies depending on the reset cause.
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 35
Table 3-3. Special Function Registers (2/2)
Number of Bits Manipulated
Simultaneously
Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After Reset
FF80H A/D converter mode register ADM √ √ −
FF81H Analog input channel specify register ADS √ √ −
FF84H Port mode control register 2 PMC2 √ √ −
FF8CH Input switching control register ISC √ √ −
00H
FF90H Asynchronous serial interface operation mode
register 6 ASIM6
R/W
√ √ − 01H
FF92H Reception buffer register 6 RXB6 − √ − FFH
FF93H Asynchronous serial interface reception error
status register 6 ASIS6
R
− √ − 00H
FF94H Transmission buffer register 6 TXB6 R/W − √ − FFH
FF95H Asynchronous serial interface transmission status
register 6 ASIF6 R − √ −
FF96H Clock selection register 6 CKSR6 − √ −
00H
FF97H Baud rate generator control register 6 BRGC6 − √ − FFH
FF98H Asynchronous serial interface control register 6 ASICL6
R/W
√ √ − 16H
FFA0H Flash protect command register PFCMD W − √ − Undefined
FFA1H Flash status register PFS √ √ − 00H
FFA2H Flash programming mode control register FLPMC − √ − Undefined
FFA3H Flash programming command register FLCMD √ √ − 00H
FFA4H Flash address pointer L FLAPL √ √ −
FFA5H Flash address pointer H FLAPH √ √ −
Undefined
FFA6H Flash address pointer H compare register FLAPHC √ √ −
FFA7H Flash address pointer L compare register FLAPLC √ √ −
FFA8H Flash write buffer register FLW − √ −
FFCCH 8-bit timer mode control register 80 TMC80
R/W
√ √ −
00H
FFCDH 8-bit compare register 80 CR80 W − √ − Undefined
FFCEH 8-bit timer counter 80 TM80 R − √ −
FFE0H Interrupt request flag register 0 IF0 √ √ −
FFE1H Interrupt request flag register 1 IF1 √ √ −
00H
FFE4H Interrupt mask flag register 0 MK0 √ √ −
FFE5H Interrupt mask flag register 1 MK1 √ √ −
FFH
FFECH External interrupt mode register 0 INTM0 − √ −
FFEDH External interrupt mode register 1 INTM1 − √ −
00H
FFF3H Preprocessor clock control register PPCC √ √ − 02H
FFF4H Oscillation stabilization time selection register OSTS − √ − Undefined
Note
FFFBH Processor clock control register PCC
R/W
√ √ − 02H
Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For
details, refer to CHAPTER 17 OPTION BYTE.
CHAPTER 3 CPU ARCHITECTURE
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36
3.3 Instruction Address Addressing
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each
time another instruction is executed. When a branch instruction is executed, the branch destination address
information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S
Series Instructions User’s Manual (U11047E)).
3.3.1 Relative addressing
[Function]
The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start
address of the following instruction is transferred to the program counter (PC) to branch. The displacement
value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,
the range of branch in relative addressing is between –128 and +127 of the start address of the following
instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15 0
PC
15 0
S
15 0
PC
+
876
α
jdisp8
When S = 0, α indicates that all bits are “0”.
... PC is the start address of
the next instruction of
a BR instruction.
When S = 1, α indicates that all bits are “1”.
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Preliminary User’s Manual U16898EJ2V0UD 37
3.3.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) to branch.
This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.
CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.
[Illustration]
In case of CALL !addr16 and BR !addr16 instructions
15 0
PC
87
70
CALL or BR
Low addr.
High addr.
3.3.3 Table indirect addressing
[Function]
The table contents (branch destination address) of the particular location to be addressed by the immediate data
of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch.
Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be
used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.
[Illustration]
15 1
15 0
PC
70
Low addr.
High addr.
Memory (Table)
Effective address + 1
Effective address 01
00000000
87
87
65 0
0
001
765 10
ta4–0
Instruction code
CHAPTER 3 CPU ARCHITECTURE
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38
3.3.4 Register addressing
[Function]
The register pair (AX) contents to be specified with an instruction word are transferred to the program counter
(PC) to branch.
This function is carried out when the BR AX instruction is executed.
[Illustration]
70
rp
07
AX
15 0
PC
87
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 39
3.4 Operand Address Addressing
The following methods (addressing) are available to specify the register and memory to undergo manipulation
during instruction execution.
3.4.1 Direct addressing
[Function]
The memory indicated by immediate data in an instruction word is directly addressed.
[Operand format]
Identifier Description
addr16 Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code 0 0 1 0 1 0 0 1 Opcode
0 0 0 0 0 0 0 000H
1 1 1 1 1 1 1 0FEH
[Illustration]
70
Opcode
addr16 (low)
addr16 (high)
Memory
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3.4.2 Short direct addressing
[Function]
The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.
The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH. An internal high-
speed RAM is mapped at FE20H to FEFFH and the special function registers (SFR) are mapped at FF00H to
FF1FH.
The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this
area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,
and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to
1FH, bit 8 is set to 1. See [Illustration] below.
[Operand format]
Identifier Description
saddr Label or FE20H to FF1FH immediate data
saddrp Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE90H, #50H; When setting saddr to FE90H and the immediate data to 50H
Instruction code 1 1 1 1 0 1 0 1 Opcode
1 0 0 1 0 0 0 0 90H (saddr-offset)
0 1 0 1 0 0 0 0 50H (immediate data)
[Illustration]
15 0Short direct memory
Effective
address 1111111
8
07
Opcode
saddr-offset
α
When 8-bit immediate data is 20H to FFH, = 0.
When 8-bit immediate data is 00H to 1FH, = 1.
α
α
CHAPTER 3 CPU ARCHITECTURE
Preliminary User’s Manual U16898EJ2V0UD 41
3.4.3 Special function register (SFR) addressing
[Function]
A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction
word.
This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to
FF1FH are accessed with short direct addressing.
[Operand format]
Identifier Description
sfr Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code 1 1 1 0 0 1 1 1
0 0 1 0 0 0 0 0
[Illustration]
15 0SFR
Effective
address 1111111
87
07
Opcode
sfr-offset
1
CHAPTER 3 CPU ARCHITECTURE
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42
3.4.4 Register addressing
[Function]
A general-purpose register is accessed as an operand.
The general-purpose register to be accessed is specified with the register specify code and functional name in
the instruction code.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,
B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code 0 0 0 0 1 0 1 0
0 0 1 0 0 1 0 1
Register specify code
INCW DE; When selecting the DE register pair for rp
Instruction code 1 0 0 0 1 0 0 0
Register specify code
CHAPTER 3 CPU ARCHITECTURE
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3.4.5 Register indirect addressing
[Function]
The memory is addressed with the contents of the register pair specified as an operand. The register pair to be
accessed is specified with the register pair specify code in the instruction code. This addressing can be carried
out for all the memory spaces.
[Operand format]
Identifier Description
− [DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code 0 0 1 0 1 0 1 1
[Illustration]
15 08
D
7
E
07
7 0
A
DE
The contents of addressed
memory are transferred
Memory address specified
by register pair DE
CHAPTER 3 CPU ARCHITECTURE
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44
3.4.6 Based addressing
[Function]
8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is
used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.
A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.
[Operand format]
Identifier Description
− [HL+byte]
[Description example]
MOV A, [HL+10H]; When setting byte to 10H
Instruction code 0 0 1 0 1 1 0 1
0 0 0 1 0 0 0 0
3.4.7 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions
are executed or the register is saved/restored upon interrupt request generation.
Stack addressing can be used to access the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code 1 0 1 0 1 0 1 0
Preliminary User’s Manual U16898EJ2V0UD 45
CHAPTER 4 PORT FUNCTIONS
4.1 Functions of Ports
The 78K0S/KA1+ has the ports shown in Figure 4-1, whic h can be used for various c ontrol operations. Table 4-1
shows the functions of each port.
In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to
CHAPTER 2 PIN FUNCTIONS.
Figure 4-1. Port Functions
P45
Port 4
P20
Port 2
P23
P30
P31 Port 3
P40
Port 13 P130
P34
P121
P123
Port 12
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Table 4-1. Port Functions
Pin Name I/O Function After Reset Alternate-
Function Pin
P20 to P23 I/O Port 2.
4-bit I/O port.
Can be set to input or output mode in 1-bit units.
On-chip pull-up resistor can be connected by setting software.
Input ANI0 to ANI3
P30 TI000/INTP0
P31
I/O Can be set to input or output mode in 1-
bit units.
On-chip pull-up resistor can be
connected by setting software.
Input
TI010/TO00/
INTP2
P34 Input
Port 3
Input only Input RESET
P40 −
P41 INTP3
P42 TOH1
P43 TxD6/INTP1
P44 RxD6
P45
I/O Port 4.
6-bit I/O port.
Can be set to input or output mode in 1-bit units.
On-chip pull-up resistor can be connected setting software.
Input
−
P121 X1
P122 X2
P123
I/O Port 12.
3-bit I/O port.
Can be set to input or output mode in 1-bit units.
On-chip pull-up resistor can be connected only to P123 by
setting software.
Input
−
P130 Output Port 13.
1-bit output-only port. Output −
Caution The P121/X1 and P122/X2 pins are pulled down during reset.
Remarks 1. P121 and P122 can be allocated when the high-speed Ring-OSC is selected as the system clock.
2. P122 can be allocated when a n external clock is selected as the system clock.
4.2 Port Configuration
Ports consist of the following hardware units.
Table 4-2. Configuration of Ports
Item Configuration
Control registers Port mode registers (PM2, PM3, PM4, PM12)
Port registers (P2, P3, P4, P12, P13)
Port mode control register 2 (PMC2)
Pull-up resistor option registers (PU2, PU3, PU4, PU12)
Ports Total: 17 (CMOS I/O: 15, CMOS input: 1, CMOS output: 1)
Pull-up resistor Total: 13
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Preliminary User’s Manual U16898EJ2V0UD 47
4.2.1 Port 2
Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using
port mode register 2 (PM 2). When the P20 to P23 pins ar e used as an input port, an on-chip pull-up resistor can be
connected in 1-bit units by using pull-up resistor option register 2 (PU2).
This port is also used as the analog input pins of the internal A/D converter.
Reset input sets port 2 to the input mode.
Figure 4-2 shows the block diagram of port 2 .
Figure 4-2. Block Diagram of P20 to P23
P20/ANI0 to P23/ANI3
WRPU
RD
PU20 to PU23
WRPM
PM20 to PM23
VDD
P-ch
PU2
PMC2
PM2
WRPORT
Output latch
(P20 to P23)
PMC20 to PMC23
A/D converter
Internal bus
Selector
PU2: Pull-up resistor option register 2
PM2: Port mode register 2
PMC2: Port mode control register 2
RD: Read signal
WR××: Write signal
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4.2.2 Port 3
Pins P30 and P31 constitute a 2-bit I/O port with an output latch. Each bit of this port can be set to the input or
output mode by using port mode register 3 (PM3). When the P30 to P31 pins are used as an input port, an on-chip
pull-up resistor can be conne cted in 1-bit units by using pul l-up resistor option regist er 3 (PU3). This port is also used
for both timer I/O and external interrupt request input pin functions.
The P34 pin is a 1-bit input-only port and functions alternately as the RESET pin.
Reset input sets port 3 to the input mode.
Figures 4-3 to 4-5 show the block diagrams of port 3.
Figure 4-3. Block Diagram of P30
P30/TI000/INTP0
WRPU
RD
WRPORT
WRPM
PU30
Output latch
(P30)
PM30
VDD
P-ch
PU3
PM3
Internal bus
Selector
Alternate
function
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
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Preliminary User’s Manual U16898EJ2V0UD 49
Figure 4-4. Block Diagram of P31
P31/TI010/TO00/INTP2
WRPU
RD
WRPORT
WRPM
PU31
Output latch
(P31)
PM31
Alternate
function
VDD
P-ch
PU3
PM3
Internal bus
Selector
Alternate
function
PU3: Pull-up resistor option register 3
PM3: Port mode register 3
RD: Read signal
WR××: Write signal
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Figure 4-5. Block Diagram of P34
RD
P34/RESET
Option
byte
Reset
Internal bus
RD: Read signal
Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the
function to input an external reset signal to the RESET pin cannot be used. The function of the
port is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
If a low level is input to the RESET pin before the option byte is referenced again after reset is
released by the POC circuit, the 78K0S/KA1+ is reset and is held in the reset state until a high
level is input to the RESET pin.
4.2.3 Port 4
Port 4 is a 6-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using
port mode register 4 (PM 4). When the P40 to P45 pins ar e used as an input port, an on-chip pull-up resistor can be
connected in 1-bit units by using pull-up resistor option register 4 (PU4).
Alternate functions include external interrupt request input, serial interface data I/O, and timer output.
Reset input sets port 4 to the input mode.
Figures 4-6 to 4-9 show the block diagrams of port 4.
CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 51
Figure 4-6. Block Diagram of P40 and P45
P40, P45
WR
PU
RD
WR
PORT
WR
PM
PU40, PU45
Output latch
(P40, P45)
PM40, PM45
V
DD
P-ch
PU4
PM4
Internal bus
Selector
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-7. Block Diagram of P41 and P44
P41/INTP3,
P44/RxD6
WR
PU
RD
WR
PORT
WR
PM
PU41, PU44
Alternate
function
Output latch
(P41, P44)
PM41, PM44
V
DD
P-ch
PU4
PM4
Internal bus
Selector
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-8. Block Diagram of P42
P42/TOH1
WR
PU
RD
WR
PORT
WR
PM
PU42
Output latch
(P42)
PM42
Alternate
function
V
DD
P-ch
PM4
PU4
Internal bus
Selector
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Figure 4-9. Block Diagram of P43
P43/TxD6/INTP1
WRPU
RD
WRPORT
WRPM
PU43
Output latch
(P43)
PM43
Alternate
function
VDD
P-ch
PU4
PM4
Internal bus
Selector
Alternate
function
PU4: Pull-up resistor option register 4
PM4: Port mode register 4
RD: Read signal
WR××: Write signal
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Preliminary User’s Manual U16898EJ2V0UD 55
4.2.4 Port 12
Port 12 is a 3-bit I/O port with an output latch. Each bit of t his port can be set to the input or output mode by using
port mode register 12 (PM12). When the P123 pin is used as an input port, an on-chip pull-up resistor can be
connected by using pull- up resistor option register 12 (PU12).
The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the
P121 and P122 pins d iffer, therefore, depending on the selected system clock os cillator. The following three system
clock oscillators can be used.
(1) High-speed Ring-OSC oscillator
The P121 and P122 pins can be used as I/O port pins.
(2) Crystal/ceramic oscillator
The P121 and P122 pins cannot be used as I/O port pins because they are used as the X1 and X2 pins.
(3) External clock input
The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin.
The P122 pin can be used as an I/O port pin.
The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
Reset input sets port 12 to the input mode.
Figures 4-10 and 4-11 show the block diagrams of port 12.
Figure 4-10. Block Diagram of P121 and P122
P121/X1,
P122/X2
RD
WR
PORT
WR
PM
Output latch
(P121, P122)
PM121, PM122
PM12
Clock input
Internal bus
Selector
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
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56
Figure 4-11. Block Diagram of P123
P123
WRPU
RD
WRPORT
WRPM
PU123
Output latch
(P123)
PM123
VDD
P-ch
PM12
PU12
Internal bus
Selector
PU12: Pull-up resistor option register 12
PM12: Port mode register 12
RD: Read signal
WR××: Write signal
CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 57
4.2.5 Port 13
This is a 1-bit output-only port.
Figure 4-12 shows the block diagr am of port 13.
Figure 4-12. Block Diagram of P130
RD
Output latch
(P130)
WR
PORT
P130
Internal bus
RD: Read signal
WR××: Write signal
Remark When a reset is input, P130 outputs a low level. If P130 outputs a high level immediately after
reset is released, the output signal of P130 c an be used as a dummy CPU reset signal.
4.3 Registers Controlling Port Functions
The ports are controlled by the following four types of registers.
• Port mode registers (PM2, PM3, PM4, PM12)
• Port registers (P2, P3, P4, P12, P13)
• Port mode control register 2 (PMC2)
• Pull-up resistor option registers (PU2, PU3, PU4, PU12)
(1) Port mode registers (PM2, PM3, PM4, PM12)
These registers are used to set the corresponding port to th e input or output mode in 1-bit units.
Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets these registers to FFH.
When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in
Table 4-3.
Caution Because P30, P31, and P43 are also used as external interrupt pins, the corresponding
interrupt request flag is set if each of these pins is set to the output mode and its output level
is changed. To use the port pin in the output mode, therefore, set the corresponding
interrupt mask flag to 1 in advance.
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Figure 4-13. Format of Port Mode Register
Address: FF22H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM2 1 1 1 1 PM23 PM22 PM21 PM20
Address: FF23H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM3 1 1 1 1 1 1 PM31 PM30
Address: FF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40
Address: FF2CH After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM12 1 1 1 1 PM123 PM122 PM121 1
PMmn Selection of I/O mode of Pmn pin (m = 2, 3, 4, or 12; n = 0 to 7)
0 Output mode (ou tput buffer ON)
1 Input mode (output buffer OFF)
(2) Port registers (P2, P3, P4, P12, P13)
These registers are used to write data to be output from the corresponding port pin to an external device
connected to the chip.
When a port register is read, the pin level is read in the input mode, and the value of the output latch of the
port is read in the output mode.
P20 to P23, P30, P31, P34, P40 to P45, P121 to P123, and P130 are set by using a 1-bit or 8-bit memory
manipulation instruction.
Reset input sets these registers to 00H.
CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 59
Figure 4-14. Format of Port Register
Address: FF02H After reset: 00H (Output latch) R/W
Symbol 7 6 5 4 3 2 1 0
P2 0 0 0 0 P23 P22 P21 P20
Address: FF03H After reset: 00HNote (Output latch) R/WNote
Symbol 7 6 5 4 3 2 1 0
P3 0 0 0 P34 0 0 P31 P30
Address: FF04H After reset: 00H (Output latch) R/W
Symbol 7 6 5 4 3 2 1 0
P4 0 0 P45 P44 P43 P42 P41 P40
Address: FF0CH After reset: 00H (Output latch) R/W
Symbol 7 6 5 4 3 2 1 0
P12 0 0 0 0 P123 P122 P121 0
Address: FF0DH After reset: 00H (Output latch) R/W
Symbol 7 6 5 4 3 2 1 0
P13 0 0 0 0 0 0 0 P130
m = 2, 3, 4, 12, or 13; n = 0-7 Pmn
Controls of output data (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Note Because P34 is read-only, its reset value is undefined.
(3) Port mode control register 2 (PMC2)
This register specifies the port mode or A/D converter mode.
Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units.
PMC2 is set by using a 1-bit or 8-bit memory manipul ation instruction.
Reset input sets PMC2 to 00H.
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Figure 4-15. Format of Port Mode Control Register 2
Address: FF84H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20
PMC2n Specification of operation mode (n = 0 to 3)
0 Port mode
1 A/D converter mode
Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register
When Alternate Function Is Used
Alternate-Function Pin
Pin Name
Name I/O
PM×× P×× PMC2n
(n = 0 to 3)
P20 to P23 ANI0 to ANI3 Input 1 × 1
TI000 Input 1
× −
P30
INTP0 Input 1
× −
TO00 Output 0 0
−
TI010 Input 1
× −
P31
INTP2 Input 1
× −
P41 INTP3 Input 1 × −
P42 TOH1 Output 0 0 −
TxD6 Output 0 1
−
P43
INTP1 Input 1
× −
P44 RxD6 Input 1 × −
Remark ×: don’t care
PM××: Port mode register, P××: Port register (output latch of port)
PMC2×: Port mode control register
CHAPTER 4 PORT FUNCTIONS
Preliminary User’s Manual U16898EJ2V0UD 61
(4) Pull-up resistor option registers (PU2, PU3, PU4, PU12)
These registers are used to s pecify whether an on-chi p pull-up resistor is connected to P20 to P23, P30, P31,
P40 to P45, and P123. By setting PU2, PU3, PU4, or PU12, an on-chip pull-up resistor can be connected to
the port pin corresponding to the bit of PU2, PU3, PU4, or PU12.
PU2, PU3, PU4, and PU12 are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input set these registers to 00H.
Figure 4-16. Format of Pull-up Resistor Option Register
Address: FF32H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PU2 0 0 0 0 PU23 PU22 PU21 PU20
Address: FF33H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PU3 0 0 0 0 0 0 PU31 PU30
Address: FF34H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PU4 0 0 PU45 PU44 PU43 PU42 PU41 PU40
Address: FF3CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PU12 0 0 0 0 PU123 0 0 0
PUmn Selection of connection of on-chip pull-up resistor of Pmn (m = 2, 3, 4, or 12; n = 0 to 7)
0 Does not connect on-chip pull-up resistor
1 Connects on-chip pull-up resistor
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4.4 Operation of Port Function
The operation of a port differs, as follows, depending on the setting of the I/O mode.
Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit
units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not
subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and
outputs.
4.4.1 Writing to I/O port
(1) In output mode
A value can be written to the output latch by a transfer instruction. In addition, the conte nt s of the output latch are
output from the pin. Once data is written to the output latch, it is retained until new data is written to the output
latch.
Reset input cleans the data in the output latch.
(2) In input mode
A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the
pin status remains unchanged.
Once data is written to the output latch, it is retained until new data is written to the output latch.
4.4.2 Reading from I/O port
(1) In output mode
The contents of the output latch can be read by a transfer instruction. The contents of the output latch remain
unchanged.
(2) In input mode
The pin status can be read by a transfer instruction. The contents of the output latch remain unchanged.
4.4.3 Operations on I/O port
(1) In output mode
An operation is performed on the contents of the output latch and the result is written to the output latch. The
contents of the output latch are output from the pin.
Once data is written to the output latch, it is retained until new data is written to the output latch.
Reset input clears the data in the output latch.
(2) In input mode
The pin level is read and an operation is performed o n its contents. The operation result is written to t he output
latch. However, the pin status remains unchanged because the output buffer is off.
Preliminary User’s Manual U16898EJ2V0UD 63
CHAPTER 5 CLOCK GENERATO RS
5.1 Functions of Clock Generators
The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and
peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the
watchdog timer and 8-bit timer H1 (TMH1).
5.1.1 System clock oscillators
The following three types of system clock oscillators are used.
• High-speed Ring-OSC oscil lator
This circuit internally oscillat es a c lock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP
instruction.
If the high-speed Ring-OSC oscillator is selected to supply the system clock, the X1 and X2 pins can be used as
I/O port pins.
• Crystal/ceramic oscillator
This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can
oscillate a clock of 1 to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction.
• External clock input circuit
This circuit s upplies a clock from an extern al IC to the X1 pin. A clock of 1 to 10 MHz can be supplied. Interna l
clock supply can be stopped by execution of the STOP instruction.
If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin.
The system clock source is selected by using the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details.
5.1.2 Clock oscillator for interval time generation
The following circuit is used as a clock oscill ator for interval time generation.
• Low-speed Ring-OSC oscillator
This circuit oscillates a c lock o f 240 k Hz (TYP .). Its oscillati on can be stopp ed by usi ng t he low-s peed R ing-OSC
mode register (LSRCM) when it is specified b y the option byte that its oscillation can be stopped by software.
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Preliminary User’s Manual U16898EJ2V0UD
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5.2 Configuration of Clock Generators
The clock generators consist of the following hardware.
Table 5-1. Configuration of Clock Generators
Item Configuration
Control registers Processor clock control register (PCC)
Preprocessor clock control register (PPCC)
Low-speed Ring-OSC mode register (LSRCM)
Oscillation stabilization time select register (OSTS)
Oscillators Crystal/ceramic oscillator
High-speed Ring-OSC oscillator
External clock input circuit
Low-speed Ring-OSC oscillator
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 65
Figure 5-1. Block Diagram of Clock Generators
X1/P121
X2/P122 f
X
f
X
2
PCC1
C
P
U
STOP
PPCC1 PPCC0OSTS1 OSTS0
f
XP
2
2
f
XP
f
X
2
2
f
RL
LSRSTOP
Controller
Selector
CPU clock
(f
CPU
)
Internal bus
Internal bus
Oscillation stabilization
time select register (OSTS) Preprocessor clock
control register (PPCC) Processor clock
control register (PCC)
System clock oscillation
stabilization time counter
Selector
Prescaler
Clock to peripheral
hardware (f
XP
)
8-bit timer H1,
watchdog timer
Option byte
1: Cannot be stopped.
0: Can be stopped.
Low-speed Ring-OSC
mode register (LSRCM)
Low-speed
Ring-OSC
oscillator
Prescaler
System clock
oscillator
Note
External clock
input
Crystal/ceramic
oscillation
High-speed
Ring-OSC
oscillation
Watchdog timer
Note Select the high-speed Ring-OSC oscillator, crystal/ceramic oscillator, or external clock input as the system
clock source by using the option byte.
CHAPTER 5 CLOCK GENERATORS
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5.3 Registers Controlling Clock Generators
The clock generators are controlled by the following four registers.
• Processor clock control register (PCC)
• Preprocessor clock control register (PPCC)
• Low-speed Ring-OSC mode register (LSRCM)
• Oscillation stabilization time select register (OSTS)
(1) Processor clock control register (PCC) and preprocessor clock control register (PPCC)
These registers are used to specify the division ratio of the system clock.
PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets PCC and PPCC to 02H.
Figure 5-2. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 02H R/W
Symbol 7 6 5 4 3 2 1 0
PCC 0 0 0 0 0 0 PCC1 0
Figure 5-3. Format of Preprocessor Clock Control Register (PPCC)
Address: FFF3H After reset: 02H R/W
Symbol 7 6 5 4 3 2 1 0
PPCC 0 0 0 0 0 0 PPCC1 PPCC0
PPCC1 PPCC0 PCC1 Selection of CPU clock (fCPU)
0 0 0 fX
0 1 0 fX/2 Note 1
0 0 1 fX/22
1 0 0 fX/22 Note 2
0 1 1 fX/23 Note 1
1 0 1 fX/24 Note 2
Other than above Setting prohibited
Notes 1. If PPCC = 01H, the clock (fXP) supplied to the periphera l hardware is fX/2.
2. If PPCC = 02H, the clock (fXP) supplied to the peripheral hardware is fX/22.
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 67
The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the
CPU clock (fCPU) and the minimum instruction execution time is as shown in Table 5-2.
Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time
Minimum Instruction Execution Time: 2/fCPU CPU Clock (fCPU) Note
High-speed Ring-OSC clock
(at 8.0 MHz (TYP.)) Crystal/ceramic oscillation clock
or external clock input (at 10.0 MHz)
fX 0.25
µ
s 0.2
µ
s
fX/2 0.5
µ
s 0.4
µ
s
fX/22 1.0
µ
s 0.8
µ
s
fX/23 2.0
µ
s 1.6
µ
s
fX/24 4.0
µ
s 3.2
µ
s
Note The CPU clock (high-speed Ring-OSC clock, crystal/ceramic oscillation clock, or external clock input) is
selected by the option byte.
(2) Low-speed Ring-OSC mode register (LSRCM)
This register is used to select the operation mode of the low-speed Ring-OSC oscillator (240 kHz (TYP.)).
This register is valid when it is specified by the option byte that the low-speed Ring-OSC oscillator can be
stopped by software. If it is specified by the option byte that the low-speed Ring-OSC oscillator cannot be
stopped by software, setting of this register is invalid, and the low-speed Ring-OSC oscillator continues
oscillating. In addition, the source cl ock of WDT is fixed to the low-speed Ring-OSC oscillator. For de tails, refer
to CHAPTER 9 WATCHDOG TIMER.
LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input sets LSRCM to 00H.
Figure 5-4. Format of Low-Speed Ring-OSC Mode Register (LSRCM)
Address: FF58H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
LSRCM 0 0 0 0 0 0 0 LSRSTOP
LSRSTOP Oscillation/stop of low-speed Ring-OSC
0 Low-speed Ring-OSC oscillates
1 Low-speed Ring-OSC stops
CHAPTER 5 CLOCK GENERATORS
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(3) Oscillation stabilization time select register (OSTS)
This register is used to select oscillation stabi lization time of the clock su ppl ied from the os cillator w hen the STOP
mode is released. Th e wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected
as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or external
clock input is selected as the system clock source, no wait time elapses.
The system clock oscillator and the oscillation stabiliz ation time that elapses after power appl ication or release of
reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
OSTS is set by using an 8-bit memory manipulation instruction.
Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFF4H After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 0 OSTS1 OSTS0
OSTS1 OSTS0 Selection of oscillation stabilization time
0 0 210/fX (102.4
µ
s)
0 1 212/fX (409.6
µ
s)
1 0 215/fX (3.27 ms)
1 1 217/fX (13.1 ms)
Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set by
OSTS
2. The wait time after the STOP mode is released does not include the time from the release of
the STOP mode to the start of clock oscillation (“a” in the figure below), regardless of
whether STOP mode was released by reset input or interrupt generation.
STOP mode is released
Voltage
waveform
of X1 pin a
Caution 3. The oscillation stabilization time that elapses on power application or after release of reset is
selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
Remarks 1. ( ): fX = 10 MHz
2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the
resonator to be used.
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 69
5.4 System Clock Oscillators
The following three types of system clock oscillators are available.
• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).
• Crystal/ceramic oscillator: Oscillates a clock of 1 to 10 MHz.
• External clock input circuit: Supplies a clock of 1 to 10 MHz to the X1 pin.
5.4.1 High-speed Ring-OSC oscillator
The 78K0S/KA1+ includes a high-speed Rin g-OSC oscillator (8 MHz (TYP.)).
If the high-speed Ring-OSC is selected by the option byte as the clock source, the X1 and X2 pins can be used as
I/O port pins.
For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
5.4.2 Crystal/ceramic oscillator
The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2
pins.
If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are
used as crystal or ceramic resonator connect ion pins.
For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
Figure 5-6 shows the external circuit of the crystal/ceramic o scillator.
Figure 5-6. External Circuit of Crystal/Ceramic Oscillator
V
SS
X1
X2
Crystal resonator
or ceramic resonator
Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken
lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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Figure 5-7 shows examples of incorrect resonator connection.
Figure 5-7. Examples of Incorrect Resonator Connection (1/2)
(a) Too long wiring of connected circuit (b) Crossed signal lines
VSS X1 X2
VSS X1 X2
PORT
(c) Wiring near high fluctuating current (d) Current flowing through ground line of oscillator
(Potential at po ints A, B, and C fluctuates.)
V
SS
X1 X2
High current
V
SS
X1 X2
PORT
V
DD
AB C
High current
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 71
Figure 5-7. Examples of Incorrect Resonator Connection (2/2)
(e) Signals are fetched
V
SS
X1 X2
5.4.3 External clock input circuit
This circuit supplies a clock from an external IC to the X1 pin.
If external clock input is selected by the option byte as the system clock source, the X2 pin ca n be used as an I/O
port pin.
For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4
PORT FUNCTIONS.
5.4.4 Prescaler
The prescaler divides the clock (fX) output by the system clock oscillator to generate a clock (fXP) to be supplied to
the peripheral hardware. It al so divides th e clock to perip heral h ardware ( fXP) to generate a clock to be supplied to the
CPU.
Remark The clock output by the oscillator selected by the option byte (high-speed Ring-OSC oscillator,
crystal/ceramic oscillator, or external clock in put circuit) is divided. For d etails of the option byte, refer to
CHAPTER 17 OPTION BYTE.
CHAPTER 5 CLOCK GENERATORS
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5.5 Operation of CPU Clock Generator
A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of
oscillators.
• High-speed Ring-OSC oscillator: Internally oscillates a clock of 8 MHz (TYP.).
• Crystal/ceramic oscillator: Oscillates a clock of 1 to 10 MHz.
• External clock input circuit: Supplies a clock of 1 to 10 MHz to X1 pin.
The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 17
OPTION BYTE.
(1) High-speed Ring-OSC oscillator
When the high-speed Ring-OSC oscillator is selected by the option byte, the following is possible.
• Shortening of start time
If the high-speed Ring-OSC oscillator is selected as the oscillator, the CPU can be started without having to
wait for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened.
• Improvement of expandability
If the high-speed Ring-OSC oscillator is selected as the o scillator, the X1 and X2 pins can be used as I/O port
pins. For details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed
Ring-OSC oscillator.
Remark When the high-speed Ring-OSC oscillator is used, the clock accuracy is ±5%.
Figure 5-8. Timing Chart of Default Start by High-Speed Ring-OSC Oscillator
V
DD
High-speed Ring-OSC clock
PCC = 02H, PPCC = 02H
(a)
(b)
H
RESET
Internal reset
System clock
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note
)
Note Operatio n stop time is 277
µ
s (MIN.), 544
µ
s (TYP.), and 1.075 ms (MAX.).
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 73
(a) The internal reset signal is generated by the power-on clear function on po wer application, the option byt e is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the high-speed Ring-OSC clock
operates as the system clock.
Figure 5-9. Status Transition of Default Start by High-Speed Ring-OSC
HALT
instruction STOP
instruction
VDD > 2.1 V ±0.1 V
Start with PCC = 02H,
PPCC = 02H
HALT STOP
Interrupt
Reset signal
Interrupt
Power
application
Reset by
power-on clear
High-speed Ring-OSC
selected by option byte
Clock division ratio
variable during
CPU operation
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
(2) Crystal/ceramic oscillator
If crystal/ceramic oscillation is selected by the optio n byte, a clock frequency of 1 to 10 M Hz can be selected and
the accuracy of processing is improved because the frequency deviation is small, as compared with high-speed
Ring-OSC oscillation (8 MHz (TYP.)).
Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic
oscillator.
CHAPTER 5 CLOCK GENERATORS
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74
Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator
VDD
Crystal/ceramic
oscillator clock
PCC = 02H, PPCC = 02H
(a)
(b)
(c)
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stops
Note 1
)
Clock oscillation
stabilization
timeNote 2
Notes 1. Operation stop time is 276
µ
s (MIN.), 544
µ
s (TYP.), and 1.074 ms (MAX.).
2. The clock oscillation stabilization time for default st art is selected by the option byte. For detai ls, refer
to CHAPTER 17 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode
is released is selected by the oscillation stabilization time select register (OSTS).
(a) The internal reset signal is generated by the power- on clear function on power ap plication, the option byte is
referenced after reset, and the system clock is selected.
(b) After high-speed Ring-OSC clock is generated, the option byte is referenced and the system clock is
selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.
(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock
oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 17
OPTION BYTE.
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 75
Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation
HALT STOP
HALT
instruction STOP
instruction
V
DD
> 2.1 V ±0.1 V
Start with PCC = 02H,
PPCC = 02H
Interrupt
Reset signal
Interrupt
Power
application
Clock division ratio
variable during
CPU operation
Wait for clock
oscillation stabilization
Crystal/ceramic
oscillation selected
by option byte
Reset by
power-on clear
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
(3) External clock input circuit
If external clock input is selected by the option byte, the followin g is possible.
• High-speed operation
The accuracy of processing is improved as compared with high-speed Ring-OSC oscillation (8 MHz (TYP.))
because an oscillation freque ncy of 1 to 10 MHz can be selected a nd an external clock with a small frequency
deviation can be supplied.
• Improvement of expandability
If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For
details, refer to CHAPTER 4 PORT FUNCTIONS.
Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD
76
Figure 5-12. Timing of Default Start by External Clock Input
V
DD
(a)
(b)
External clock input
PCC = 02H, PPCC = 02H
H
RESET
System clock
Internal reset
CPU clock
Option byte is read.
System clock is selected.
(Operation stopsNote)
Note Operatio n stop time is 277
µ
s (MIN.), 544
µ
s (TYP.), and 1.075 ms (MAX.).
(a) The internal reset signal is generated by the power-on clear function on power ap plication, the option byte is
referenced after reset, and the system clock is selected.
(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the
system clock.
Figure 5-13. Status Transition of Default Start by External Clock Input
HALT STOP
HALT
instruction STOP
instruction
V
DD
> 2.1 V ±0.1 V
Start with PCC = 02H,
PPCC = 02H
Interrupt
Reset signal
Interrupt
Power
application
Reset by
power-on clear
External clock input
selected by option byte
Clock division ratio
variable during
CPU operation
Remark PCC: Processor clock control register
PPCC: Preprocessor clock control register
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD 77
5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware
The following two types of clocks are supplied to the peripheral hardware.
• Clock to peripheral hardware (fXP)
• Low-speed Ring-OSC clock (fRL)
(1) Clock to peripheral hardware
The clock to the peripheral hardware is supplied by dividing the system clock (fX). The division ratio is selected
by the pre-processor clock control register (PPCC).
Three types of frequencies are selectable: “fX”, “fX/2”, and “fX/22”. Table 5-3 lists the clocks supplied to the
peripheral hardware.
Table 5-3. Clocks to Peripheral Hardware
PPCC1 PPCC0 Selection of clock to peripheral hardware (fXP)
0 0 fX
0 1 fX/2
1 0 fX/22
1 1 Setting prohibited
(2) Low-speed Ring-OSC clock
The low-speed Ring-OSC oscillator of the clock oscillator for interval time generation is always started after
release of reset, and oscillates at 240 kHz (TYP.).
It can be specified by the option byte whether the low-speed Ring-OSC oscillator can or cannot be stopped by
software. If it is specified that the low-speed Ring-OSC osc illator can be stopped by software, oscillation can be
started or stopped by using the low-speed Ring-OSC mode register (LSRCM). If it is specified that it cannot be
stopped by software, the clock source of WDT is fixed to the low-speed Ring-OSC clock (fRL).
The low-speed Ring-OSC oscillator is independent of the CPU clock. If it is used as the source clock of WDT,
therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed Ring-OSC oscillator is
used as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status.
Table 5-4 shows the operation status of the low-speed Ring-OSC oscillator when it is selected as the source
clock of WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed
Ring-OSC oscillator.
Table 5-4. Operation Status of Low-Speed Ring-OSC Oscillator
Option Byte Setting CPU Status WDT Status TMH1 Status
LSRSTOP = 1 Stopped Stopped
LSRSTOP = 0
Operation mode
Operates Operates
LSRSTOP = 1 Stopped Stopped
Can be stopped by
software
LSRSTOP = 0
Standby
Stopped Operates
Operation mode Cannot be stopped
Standby
Operates
CHAPTER 5 CLOCK GENERATORS
Preliminary User’s Manual U16898EJ2V0UD
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Figure 5-14. Status Transition of Low-Speed Ring-OSC Oscillator
LSRSTOP = 0
Cannot be stopped
Can be stopped
Clock source of
WDT is selected
by software
Note
Clock source of
WDT is fixed to f
RL
Low-speed Ring-OSC
oscillator can be stopped Low-speed Ring-OSC
oscillator cannot be stopped
Low-speed Ring-OSC
oscillator stops
LSRSTOP = 1
V
DD
> 2.1 V ±0.1 V
Reset signal
Power
application
Reset by
power-on clear
Select by option byte
if low-speed Ring-OSC
can be stopped or not
Note The clock source of the watc hdog timer (WDT) is selected from fX or fRL, or it may be stopped. For details,
refer to CHAPTER 9 WATCHDOG TIMER.
Preliminary User’s Manual U16898EJ2V0UD 79
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
6.1 Functions of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 has the following functions.
(1) Interval timer
16-bit timer/event counter 00 generates interrupt requests at the preset time interval.
• Number of counts: 2 to 65536
(2) External event counter
16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of a signal input
externally.
• Valid level pulse width: 16/fXP or more
(3) Pulse width measurement
16-bit timer/event counter 00 can measure the pulse width of an externally input signal.
• Valid level pulse width: 2/fXP or more
(4) Square-wave output
16-bit timer/event counter 00 can output a square wave with any selected frequency.
• Cycle: (2 × 2 to 65536 × 2) × count clock cycle
(5) PPG output
16-bit timer/event counter 00 can output a square wave th at have arbitrary cycle and pulse width.
• 1 < Pulse width < Cycle ≤ (FFFF + 1) H
(6) One-shot pulse output
16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any
desired value.
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6.2 Configuration of 16-Bit Timer/Event Counter 00
16-bit timer/event counter 00 consists of the following hardware.
Table 6-1. Configuration of 16-Bit Timer/Event Counter 00
Item Configuration
Timer counter 16-bit timer counter 00 (TM00)
Register 16-bit timer capture/compare registers 000, 010 (CR000, CR010)
Timer input TI000, TI010
Timer output TO00, output controller
Control registers 16-bit timer mode control register 00 (TMC00)
Capture/compare control register 00 (CRC00)
16-bit timer output control register 00 (TOC00)
Prescaler mode register 00 (PRM00)
Port mode register 3 (PM3)
Port register 3 (P3)
Figures 6-1 shows a block diagram of these counters.
Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00
Internal bus
Capture/compare control
register 00 (CRC00)
TI010/TO00/
INTP2/P31
f
XP
f
XP
/2
2
f
XP
/2
8
f
X
TI000/INTP0/P30
Prescaler mode
register 00 (PRM00)
2
PRM001 PRM000
CRC002
16-bit timer capture/compare
register 010 (CR010)
Match
Match
16-bit timer counter 00
(TM00) Clear
Noise
elimi-
nator
CRC002CRC001 CRC000
INTTM000
TO00/TI010/
INTP2/P31
INTTM010
16-bit timer output
control register 00
(TOC00)
16-bit timer mode
control register 00
(TMC00)
Internal bus
TMC003 TMC002
TMC001
OVF00
TOC004
LVS00 LVR00
TOC001
TOE00
Selector
16-bit timer capture/compare
register 000 (CR000)
Selector
Selector
Selector
Noise
elimi-
nator
Noise
elimi-
nator
Output
controller
OSPE00
OSPT00
Output latch
(P31)
PM31
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 81
(1) 16-bit timer counter 00 (TM00)
TM00 is a 16-bit read-only register that counts count pulses.
The counter is incremented in synchroni zation with the risi ng edg e of the count clock. If the count val ue is read
during operation, input of the count clock is t emporarily stopped, and the count value at that point is read.
Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)
TM00
Symbol FF13H FF12H
Address: FF12H, FF13H After reset: 0000H R
The count value is reset to 0000H in the following cases.
<1> At reset input
<2> If TMC003 and TMC002 are cleared
<3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000
<4> If TM00 and CR000 match in the cle ar & start mode entered on a match between TM00 and CR000
<5> If OSPT00 is set to 1 in the one-shot pulse output mode
Cautions 1. Even if TM00 is read, the value is not captured by CR010.
2. During TM00 is read, the count clock is stopped.
(2) 16-bit timer capture/compare register 000 (CR000)
CR000 is a 16-bit register whi ch has the functions of both a captur e register and a compare reg ister. Whether
it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control
register 00 (CRC00).
CR000 is set by 16-bit memory manipulation instruction.
A reset clears CR000 to 0000H.
Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)
CR000
Symbol FF15H FF14H
Address: FF14H, FF15H After reset: 0000H R/W
• When CR000 is used as a compare register
The value set in CR000 is constantly comp ared with th e 16 -bit timer/count er 00 (TM00) c ount val ue, a nd an
interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the
interval time then TM00 is set to interval timer operation.
• When CR000 is used as a capture register
It is possible to select the va lid edge of the TI000 pin or the TI010 pi n as the capture trigger. Setting of the
TI000 or TI010 valid edge is performed by means of prescaler mode regist er 00 (PRM00) (refer to Table 6-
2).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD
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Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger TI000 Pin Valid Edge
ES010 ES000
Falling edge Rising edge 0 1
Rising edge Falling edge 0 0
No capture operation Both rising and falling edges 1 1
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger TI010 Pin Valid Edge
ES110 ES100
Falling edge Falling edge 0 0
Rising edge Rising edge 0 1
Both rising and falling edges Both rising and falling edges 1 1
Remarks 1. Setting ES010, ES000 = 1, 0 and ES1 10, ES100 = 1, 0 is prohibited.
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
ES110, ES100: Bits 7 and 6 of prescaler mode register 00 (PRM00)
CRC001, CRC000: Bits 1 and 0 of capture/compar e control register 00 (CRC00)
Cautions 1. Set CR000 to other than 0000H in the clear & st art mode entered on match between TM00
and CR000. This means a 1-pulse count operation cannot be performed when this
register is used as an external event counter. However, in the free-running mode and in
the clear & start mode using the valid edge of TI000 pin, if CR000 is set to 0000H, an
interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H
following overflow (FFFFH).
2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR000 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR000 is changed.
3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR000 set in compare mode even if a
capture trigger is input.
5. When P31 is used as the input pin for the valid edge of TI010, it cannot be used as a timer
output (TO00). Moreover, when P31 is used as TO00, it cannot be used as the input pin
for the valid edge of TI010.
6. If the register read period and the input of the capture trigger conflict when CR000 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the count stop of the timer and the input of the capture trigger
conflict, the capture trigger is undefined.
7. Changing the CR000 setting may cause a malfunction. To change the setting, refer to 6.5
Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare register
during timer operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 83
(3) 16-bit capture/compare register 010 (CR010)
CR010 is a 16-bit register whi ch has the functions of both a captur e register and a compare register. W hether
it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control
register 00 (CRC00).
CR010 is set by 16-bit memory manipulation instruction.
Reset input clears CR010 to 0000H.
Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)
CR010
Symbol FF17H FF16H
Address: FF16H, FF17H After reset: 0000H R/W
• When CR010 is used as a compare register
The value set in CR010 is constantly compa red with the 16-bit timer counter 00 (TM00) count value, and an
interrupt request (INTTM010) is generated if they match.
• When CR010 is used as a capture register
It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid e dge is set by
means of prescaler mode register 00 (PRM00) (refer to Table 6-3).
Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)
CR010 Capture Trigger TI000 Pin Valid Edge
ES010 ES000
Falling edge Falling edge 0 0
Rising edge Rising edge 0 1
Both rising and falling edges Both rising and falling edges 1 1
Remarks 1. Setting ES010, ES000 = 1, 0 is prohi bited.
2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)
CRC002: Bit 2 of capture/ compare control register 00 (CRC00)
Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000
pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010
changes from 0000H to 0001H following overflow (FFFFH).
2. If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), TM00
continues counting, overflows, and then starts counting from 0 again. If the new value of
CR010 is less than the old value, therefore, the timer must be reset to be restarted after
the value of CR010 is changed.
3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.
4. The capture operation may not be performed for CR010 set in compare mode even if a
capture trigger is input.
5. If the register read period and the input of the capture trigger conflict when CR010 is
used as a capture register, the capture trigger input takes precedence and the read data
is undefined. Also, if the timer count stop and the input of the capture trigger conflict,
the capture data is undefined.
6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change
the setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing
compare register during timer operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD
84
6.3 Registers to Control 16-Bit Timer/Event Counter 00
The following six types of registers are used to control 16-bit timer/event counter 00.
• 16-bit timer mode control register 00 (TMC00)
• Capture/compare control register 00 (CRC 00)
• 16-bit timer output control register 00 (TOC00)
• Prescaler mode register 00 (PRM00)
• Port mode register 3 (PM3)
• Port register 3 (P3)
(1) 16-bit timer mode control register 00 (TMC00)
This register sets the 16-bit timer operating mode, the 1 6-bit timer counter 00 (TM00) clear mode, and output
timing, and detects an overflow.
TMC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of TMC00 to 00H.
Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003
(operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and
TMC003 to 0, 0 to stop the operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 85
Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
7
0
6
0
5
0
4
0
3
TMC003
2
TMC002
1
TMC001
<0>
OVF00
Symbol
TMC00
Address: FF60H After reset: 00H R/W
OVF00 Overflow detection of 16-bit timer counter 00 (TM00)
0 Overflow not detected
1 Overflow detected
Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.
2. Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins
TI000/TI010 are not acknowledged.
3. Except when TI000 pin valid edge is selected as the count clock, stop the timer operation
before setting STOP mode or system clock stop mode; otherwise the timer may malfunction
when the system clock starts.
4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00)
after stopping the timer operation.
5. If the clear & start mode entered on a match between TM00 and CR000, clear & st art mode at
the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000
is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.
6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00
becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and
clear is disabled.
7. The capture operation is performed at the fall of the count clock. An interrupt request input
(INTTM0n0), however, occurs at the rise of the next count clock.
Remark TM00: 16-bit timer counter 00
CR000: 16-bit timer capture/compare register 000
CR010: 16-bit timer capture/compare register 010
TMC003 TMC002 TMC001 Operating mode and clear
mode selection TO00 inversion timing selection Interrupt request generation
0 0 0
0 0 1
Operation stop
(TM00 cleared to 0) No change Not generated
0 1 0 Free-running mode Match between TM00 and
CR000 or match between
TM00 and CR010
0 1 1 Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
1 0 0
1 0 1
Clear & start occurs on valid
edge of TI000 pin
−
1 1 0 Clear & start occurs on match
between TM00 and CR000 Match between TM00 and
CR000 or match between
TM00 and CR010
1 1 1 Match between TM00 and
CR000, match between TM00
and CR010 or TI000 pin valid
edge
<When operating as compare
register>
Generated on match between
TM00 and CR000, or match
between TM00 and CR010
<When operating as capture
register>
Generated on CR000 capture
trigger
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD
86
(2) Capture/compare control register 00 (CRC00)
This register controls the operation of the 16-bit capture/compare re gisters (CR000, CR010).
CRC00 is set by a 1-bit or 8-bit memory manipulati on instruction.
Reset input sets the value of CRC00 to 00H.
Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)
Address: FF62H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRC00 0 0 0 0 0 CRC002 CRC001 CRC000
CRC002 CR010 operating mode selection
0 Operate as compare register
1 Operate as capture register
CRC001 CR000 capture trigger selection
0 Capture on valid edge of TI010 pin
1 Capture on valid edge of TI000 pin by reverse phaseNote
CRC000 CR000 operating mode selection
0 Operate as compare register
1 Operate as capture register
Note If both the rising and falling edges have been selected as the valid edges of the TI000 pin, capture is
not performed.
Cautions 1. The timer operation must be stopped before setting CRC00.
2. When the clear & start mode enter ed on a match betwe en TM00 and CR000 is sele cted by
16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a
capture register.
3. To ensure the reliability of the capture operation, the capture trigger requires a pulse
longer than two cycles of the count clock selected by prescaler mode register 00
(PRM00) (refer to Figure 6-17).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 87
(3) 16-bit timer output control register 00 (TOC00)
This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F
set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot
pulse output operation enable/disable, and output trigger of one-shot pulse by software.
TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of TOC00 to 00H.
Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)
Address: FF63H After reset: 00H R/W
Symbol 7 <6> <5> 4 <3> <2> 1 <0>
TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00
OSPT00 One-shot pulse output trigger control via software
0 No one-shot pulse output trigger
1 One-shot pulse output trigger
OSPE00 One-shot pulse output operation control
0 Successive pulse output mode
1 One-shot pulse output mode Note
TOC004 Timer output F/F control using match of CR010 and TM00
0 Disables inversion operation
1 Enables inversion operation
LVS00 LVR00 Timer output F/F status setting
0 0 No change
0 1 Timer output F/F reset (0)
1 0 Timer output F/F set (1)
1 1 Setting prohibited
TOC001 Timer output F/F control using match of CR000 and TM00
0 Disables inversion operation
1 Enables inversion operation
TOE00 Timer output control
0 Disables output (output fixed to level 0)
1 Enables output
Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match
between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.
Cautions 1. Timer operation must be stopped before setting other than OSPT00.
2. If LVS00 and LVR00 are read, 0 is read.
3. OSPT00 is automatically cleared after data is set, so 0 is read.
4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.
5. A write interval of two cycles or more of the count clock selected by prescaler mode register
00 (PRM00) is required to write to OSPT00 successively.
6. When the TOE00 is 0, set the TOE00, LVS00, and LVR00 at the same time with the 8-bit
memory manipulation instruction. When the TOE00 is 1, the LVS00 and LVR00 can be set
with the 1-bit memory manipulation instruction.
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(4) Prescaler mode register 00 (PRM00)
This register is used to set the 16- bit timer counter 00 (TM00) co unt clock and the TI000, TI010 pi n input valid
edges.
PRM00 is set by a 1-bit or 8-bit memory manipulation i nstruction.
Reset input sets the value of PRM00 to 00H.
Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)
Address: FF61H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PRM00 ES110 ES100 ES010 ES000 0 0 PRM001 PRM000
ES110 ES100 TI010 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES010 ES000 TI000 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
PRM001 PRM000 Count clock selection
0 0 fXP (10 MHz)
0 1 fXP/22 (2.5 MHz)
1 0 fXP/28 (39.06 kHz)
1 1 TI000 pin valid edgeNote
Remarks 1. f
XP: Oscillation frequency of clock supplied to perip heral hardware
2. ( ): fXP = 10 MHz
Note The external cl ock requires a pulse longer than two cycles of the internal count clock (fXP).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 89
Cautions 1. Always set data to PRM00 after stopping the timer operation.
2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start
mode and the capture trigger at the valid edge of the TI000 pin.
3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.
<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the
operation of the 16-bit timer counter 00 (TM00) is enabled
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is
then enabled after a low level is input to the TI0n0 pin
→ If the falling edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is
enabled.
<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is
then enabled after a high level is input to the TI0n0 pin
→ If the rising edge or both rising and falling edges are specified as the valid edge
of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is
enabled.
4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the
count clock and when it is used as a capture trigger. In the former case, the count clock
is fXP, and in the latter case the count clock is selected by prescaler mode register 00
(PRM00). The capture operation is not performed until the valid edge is sampled and the
valid level is detected twice, thus eliminating noise with a short pulse width.
5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer
output (TO00). When using P31 as the timer output pin (TO00), it cannot be used as the
input pin (TI010) of the valid edge.
Remark n = 0, 1
(5) Port mode register 3 (PM3)
This register sets port 3 input/output in 1-bit units.
When using the P31/TO00/TI010/INTP2 pin for timer out put, set PM31 and the output latch of P31 to 0.
When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1.
At this time, the output latches of P30 and P31 can be either 0 or 1.
PM3 is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets the value of PM3 to FFH.
Figure 6-9. Format of Port Mode Register 3 (PM3)
7
1
6
1
5
1
4
1
3
1
2
1
1
PM31
0
PM30
Symbol
PM3
Address: FF23H After reset: FFH R/W
PM3n
0
1
P3n pin I/O mode selection (n = 0 or 1)
Output mode (output buffer on)
Input mode (output buffer off)
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6.4 Operation of 16-Bit Timer/Event Counter 00
6.4.1 Interval timer operation
Setting 16-bit timer mode control reg ister 00 (TMC00) and capture/com pare control register 00 (C RC00) as shown
in Figure 6-10 allows operatio n as an interval timer.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see F i gure 6-10 for the set value).
<2> Set any value to the CR000 register.
<3> Set the count clock by using the PRM00 register.
<4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remark For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.
Interrupt requests are generated rep eatedly using the count value set in 16-bit timer capture/compare register 000
(CR000) beforehand as the interval.
When the count value of 16-bit timer counter 00 (TM00) matches the v alue set to CR000, counting continues with
the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.
The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of
prescaler mode register 00 (PRM00).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
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Figure 6-10. Control Register Settings for Interval Timer Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0/1
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the
description of the respective control registers for details.
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Figure 6-11. Interval Timer Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
(TM00) OVF00
Clear
circuit
INTTM000
f
XP
f
XP
/2
2
f
XP
/2
8
TI000/INTP0/P30
Selector
Noise
eliminator
f
XP
Note
Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
Figure 6-12. Timing of Interval Timer Operation
Count clock
t
TM00 count value
CR000
INTTM000
0000H
0001H
N
0000H 0001H
N
0000H 0001H
N
NNNN
Timer operation enabled Clear Clear
Interrupt acknowledged Interrupt acknowledged
Remark Interval time = (N + 1) × t
N = 0001H to FFFFH (settable range)
When the compare register is cha nged duri ng timer count o peration, if the value after 16- bit timer captur e/compare
register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,
overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)
before the change, it is necessary to restart the timer after changing CR000.
Figure 6-13. Timing After Change of Compare Register During Timer Count Operation (N → M: N > M)
CR000
NM
Count clock
TM00 count value
X – 1 X FFFFH 0000H 0001H 0002H
Remark N > X > M
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6.4.2 External event counter operation
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see F i gure 6-14 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set any value to the CR000 register (0000H cannot be set).
<4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value).
Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to ena ble the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.
The external event counter counts the num ber of external clock puls es to be inp ut to the TI000 pin with using 16-b it
timer counter 00 (TM00).
TM00 is incremented each time the valid ed ge specified by prescaler mode register 00 (PRM00) is input.
When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is
cleared to 0 and the interrupt request signal (INTTM000) is generated.
Input a value other than 0000H to CR00 0. (A count oper ation with a pulse cannot be carried out.)
The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of
prescaler mode register 00 (PRM00).
Because an operation is carri ed out only when the valid e dge of the TI000 pin is detec ted twice after sampling with
the internal clock (fXP), noise with a short pulse width can be removed.
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Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0/1
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
(c) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0
ES000
1
3
0
2
0
PRM001
1
PRM000
1PRM00
Selects external clock.
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.
See the description of the respective control registers for details.
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Figure 6-15. External Event Counter Configuration Diagram
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00 (TM00)
Internal bus
Match
Clear
OVF00Note
INTTM000
Noise eliminator
f
XP
Valid edge of TI000
Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH.
Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified)
TI000 pin input
TM00 count value
CR000
INTTM000
0000H 0001H 0002H 0003H 0004H 0005H
N–1 N
0000H 0001H 0002H 0003H
N
Caution When reading the external event counter count value, TM00 should be read.
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6.4.3 Pulse width measurement operations
It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer
counter 00 (TM00).
There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by
restarting the timer in synchronization with the edge of the signal input to the TI000 pin.
When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate
the necessary pulse width. Clear the overflow flag after che cking it.
The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by
prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 6-17. CR010 Capture Operation with Rising Edge Specified
Count clock
TM00
TI000
Rising edge detection
CR010
INTTM010
N − 3N − 2N − 1 N N + 1
N
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see F igures 6-18, 6-21, 6-23, and 6-25 for the set value).
<2> Set the count clock by using the PRM00 register.
<3> Set the TMC00 register to start the operation (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value).
Caution To use two capture registers, set the TI000 and TI010 pins.
Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 12 INTERRUPT
FUNCTIONS.
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(1) Pulse width measurement with free-running counter and one capture register
When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler
mode register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer
capture/compare register 010 (CR010) and an external interrupt request signal (INTTM010) is set.
Specify both the rising and falling e dges by using bits 4 and 5 (ES000 and ES010) of PRM00.
Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed
when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.
Figure 6-18. Control Register Settings for Pulse Width Measurement with Free-Running Counter
and One Capture Register (When TI000 and CR010 Are Used)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES101
0/1
ES100
0/1
ES010
1
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter
f
XP
f
XP
/2
2
f
XP
/2
6
TI000/INTP0/P30
16-bit timer/counter 00
(TM00) OVF00
16-bit timer capture/compare
register 010 (CR010)
Internal bus
INTTM010
Selector
Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0
(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t
D1 D2 D3
D2 D3
D0 + 1
D1
D1 + 1
Note
Count clock
TM00 count value
TI000 pin input
CR010 capture value
INTTM010
OVF00
Note OVF00 must be cleared by software.
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(2) Measurement of two pulse widths with free-running counter
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously
measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin.
When the edge spec ified by bits 4 and 5 (ES000 and ES010) of prescaler mode registe r 00 (PRM00) is input
to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an
interrupt request signal (INTTM010) is set.
Also, when the edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the
value of TM00 is taken into 16-bit timer capture/compar e register 000 (CR000) and an interrupt request signal
(INTTM000) is set.
Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5
(ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00.
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus
eliminating noise with a short pulse width.
Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
0
CRC000
1CRC00
CR000 used as capture register
Captures valid edge of TI010 pin to CR000.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110
1
ES100
1
ES010
1
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies both edges for pulse width detection.
Specifies both edges for pulse width detection.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter
(with Both Edges Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0
(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t
(10000H − D1 + (D2 + 1)) × t
D1
D2 + 1D1
D2
D2 D3
D0 + 1
D1
D1 + 1 D2 + 1 D2 + 2
Note
TI010 pin input
CR000 capture value
INTTM010
INTTM000
OVF00
Count clock
TM00 count value
TI000 pin input
CR010 capture value
Note OVF00 must be cleared by software.
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(3) Pulse width measurement with free-running counter and two capture registers
When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse
width of the signal input to the TI000 pin.
When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00
(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010
(CR010) and an interrupt request signal (INTTM010) is set.
Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken
into 16-bit timer capture/compare regist er 000 (CR000).
Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a
capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating
noise with a short pulse width.
Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and
Two Capture Registers (with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
0
TMC002
1
TMC001
0/1
OVF00
0TMC00
Free-running mode
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
1
CRC000
1CRC00
CR000 used as capture register
Captures to CR000 at inverse edge
to valid edge of TI000
Note
.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Note If the valid edge of TI000 pin is specified to be both the rising and falling edges, 16-bit timer
capture/compare register 000 (CR00 0) can not perform the capture operation.
Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.
See the description of the respective control registers for details.
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Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter
and Two Capture Registers (with Rising Edge Specified)
t
0000H 0000H
FFFFH
0001H
D0
D0 D2
D1 D3
D2 D3D1
D0 + 1 D2 + 1D1 + 1
INTTM010
OVF00
CR000 capture value
Count clock
TM00 count value
TI000 pin input
CR010 capture value
(D1 − D0) × t (D3 − D2) × t(10000H − D1 + D2) × t
Note
Note OVF00 must be cleared by software.
(4) Pulse width measurement by means of restart
When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is
taken into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to
the TI000 pin is measured by clearing TM00 and restarting the count.
The edge specification can be selected from two types, rising or falling edges, by bits 4 and 5 (ES000 and
ES010) of prescaler mode register 00 (PRM00)
Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation
is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short
pulse width.
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Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
0
TMC001
0/1
OVF00
0TMC00
Clears and starts at valid edge of TI000 pin.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
1
CRC001
1
CRC000
1CRC00
CR000 used as capture register
Captures to CR000 at inverse edge to valid edge of TI000
Note
.
CR010 used as capture register
(c) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0
ES000
1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock (setting “11” is prohibited).
Specifies rising edge for pulse width detection.
Setting invalid (setting “10” is prohibited.)
Note If the valid edge of TI000 pin is specified to be both the rising and falling edges, 16-bit timer
capture/compare register 000 (CR00 0) can not perform the capture operation.
Figure 6-26. Timing of Pulse Width Measurement Operation by Means of Restart
(with Rising Edge Specified)
t
0000H 0001H0000H0001H 0000H 0001H
D0
D0
INTTM010
D1 × t
D2 × t
D2
D1
D2D1
CR000 capture value
Count clock
TM00 count value
TI000 pin input
CR010 capture value
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6.4.4 Square-wave output operation
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see F i gure 6-27 for the set value).
<3> Set the TOC00 register (see Figure 6-27 for the set value).
<4> Set any value to the CR000 register (0000H cannot be set).
<5> Set the TMC00 register to start the operation (see Figure 6-27 for the set value).
Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to ena ble the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.
A square wave with any sel ected frequency can be o utput at intervals determined by th e count value preset to 16-
bit timer capture/compare register 000 (CR000).
The TO00 pin output status is reversed at intervals determined by the c ount value preset to CR000 + 1 by setting
bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a squar e wav e
with any selected frequency to be output.
Figure 6-27. Control Register Settings in Square-Wave Output Mode (1/2)
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0/1
CRC001
0/1
CRC000
0CRC00
CR000 used as compare register
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Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2)
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00
0
OSPE00
0
TOC004
0
LVS00
0/1
LVR00
0/1
TOC001
1
TOE00
1TOC00
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting “11” is prohibited).
Does not invert output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Remark 0/1: Setting 0 or 1 allows another function to be used simultane ously with square-wave output. See th e
description of the respective control registers for details.
Figure 6-28. Square-Wave Output Operation Timing
Count clock
TM00 count value
CR000
INTTM000
TO00 pin output
0000H 0001H 0002H
N − 1N
0000H 0001H 0002H
N − 1N
0000H
N
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6.4.5 PPG output operations
Setting 16-bit timer mode control reg ister 00 (TMC00) and capture/com pare control register 00 (C RC00) as shown
in Figure 6-29 allows operatio n as PPG (Programmable Pulse Generator) output.
Setting
The basic operation setting procedure is as follows.
<1> Set the CRC00 register (see F i gure 6-29 for the set value).
<2> Set any value to the CR000 register as the cycle.
<3> Set any value to the CR010 register as the d uty factor.
<4> Set the TOC00 register (see Figure 6-29 for the set value).
<5> Set the count clock by using the PRM00 register.
<6> Set the TMC00 register to start the operation (see Figure 6-29 for the set value).
Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the
setting, refer to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00 (17) Changing compare
register during timer operation.
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to enable the INTTM000 interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS.
3. n = 0 or 1
In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle
that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer
capture/compare register 000 (CR00 0), resp ectively.
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Figure 6-29. Control Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
7
0
6
0
5
0
4
0
TMC003
1
TMC002
1
TMC001
0
OVF00
0TMC00
Clears and starts on match between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
7
0
6
0
5
0
4
0
3
0
CRC002
0
CRC001
×
CRC000
0CRC00
CR000 used as compare register
CR010 used as compare register
(c) 16-bit timer output control register 00 (TOC00)
7
0
OSPT00
0
OSPE00
0
TOC004
1
LVS00
0/1
LVR00
0/1
TOC001
1
TOE00
1TOC00
Enables TO00 output.
Inverts output on match between TM00 and CR000.
Specifies initial value of TO00 output F/F (setting "11" is prohibited).
Inverts output on match between TM00 and CR010.
Disables one-shot pulse output.
(d) Prescaler mode register 00 (PRM00)
ES110
0/1
ES100
0/1
ES010
0/1
ES000
0/1
3
0
2
0
PRM001
0/1
PRM000
0/1PRM00
Selects count clock.
Setting invalid (setting “10” is prohibited.)
Setting invalid (setting “10” is prohibited.)
Cautions 1. Values in the following range should be set in CR000 and CR010.
0000H < CR010 < CR000 ≤ FFFFH
2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of
(CR010 setting value + 1)/(CR000 setting value + 1).
Remark ×: Don’t care
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Figure 6-30. Configuration Diagram of PPG Output
16-bit timer capture/compare
register 000 (CR000)
16-bit timer counter 00
(TM00) Clear
circuit
Noise
eliminator
f
XP
f
XP
f
XP
/2
2
f
XP
/2
8
TI000/INTP0/P30
16-bit timer capture/compare
register 010 (CR010)
TO00/TI010/
INTP2/P31
Selector
Output controller
Figure 6-31. PPG Output Operation Timing
t
0000H 0000H
0001H
0001H
M − 1
Count clock
TM00 count value
TO00
Pulse width: (M + 1) × t
1 cycle: (N + 1) × t
N
CR000 capture value
CR010 capture value M
M
N − 1
NN
ClearClear
Remark 0000H < M < N ≤ FFFFH
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 109
6.4.6 One-shot pulse output operation
16-bit timer/event counter 00 can o utput a one-shot pulse in synchroniz ation with a software trigger or an external
trigger (TI000 pin input).
Setting
The basic operation setting procedure is as follows.
<1> Set the count clock by using the PRM00 register.
<2> Set the CRC00 register (see F igures 6-32 and 6-34 for the set value).
<3> Set the TOC00 register (see Figures 6-32 and 6-34 for the set value).
<4> Set any value to the CR000 and CR010 registers (0000H cannot be set).
<5> Set the TMC00 register to start the operation (see Figures 6-32 and 6-34 for the set value).
Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).
2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 12
INTERRUPT FUNCTIONS.
(1) One-shot pulse output with software trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control regis ter 00 (CRC00 ), and 16-bit timer output con trol register 00 (TOC00) as s hown in
Figure 6-32, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.
By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes
active at the count value (N) set in advance to 16-bit tim er capture/compare register 010 (CR 010). After that,
the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000
(CR000)Note.
Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00
register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 regist er. Do not set N to M.
Cautions 1. By setting the OSPT00 bit to 1 while the one-shot pulse is being output, 16-bit timer counter
00 (TM00) is cleared. To output the one-shot pulse again, wait until the current one-shot
pulse output is completed.
2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software
trigger, do not change the level of the TI000 pin or its alternate-function port pin.
Becau se the external trigger is valid even in this case, the timer is cleared and started even
at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a
pulse at an undesired timing.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD
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Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger
(a) 16-bit timer mode control register 00 (TMC00)
0000
7654
0
TMC003
TMC00
TMC002 TMC001 OVF00
Free-running mode
100
(b) Capture/compare control register 00 (CRC00)
00000
76543
CRC00
CRC002 CRC001 CRC000
CR000 as compare register
CR010 as compare register
0 0/1 0
(c) 16-bit timer output control register 00 (TOC00)
0
7
0 1 1 0/1
TOC00
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
Set to 1 for output.
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
0/1 0/1 0/1 0/1 0
PRM00
PRM001 PRM010
Selects count clock.
Setting invalid
(setting “10” is prohibited.)
0 0/1 0/1
ES110 ES100 ES010 ES000
Setting invalid
(setting “10” is prohibited.)
32
Caution Do not set 0000H to the CR000 and CR010 registers.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 111
Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger
0000H N
NN N N
MM M M
NMN + 1 N − 1M − 1
0001H
M + 1 M + 2
0000H
Count clock
TM00 count
CR010 set value
CR000 set value
OSPT00
INTTM010
INTTM000
TO00 pin output
Set TMC00 to 04H
(TM00 count starts)
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop
mode) is set to the TMC003 and TMC002 bits.
Remark N < M
(2) One-shot pulse output with external trigger
A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),
capture/compare control regis ter 00 (CRC00 ), and 16-bit timer output con trol register 00 (TOC00) as s hown in
Figure 6-34, and by using the valid edge of the TI000 pin as an external trigger.
The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00
(PRM00). The rising, falling, or both the rising and falling edges can be specified.
When the valid edge of th e TI000 pin is d etected, the 1 6-bit timer/event counter is c lear e d and started, and th e
output becomes active at the count value set in advance to 16-bit timer capture/compare register 010
(CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer
capture/compare register 000 (CR000)Note.
Note The case where N < M is described here. When N > M, the output becomes active with the CR000
register and inactive with the CR010 regist er. Do not set N to M.
Caution If the external trigger is generated again while the one-shot pulse is output, 16-bit timer
counter 00 (TM00) is cleared.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
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Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger
(with Rising Edge Specified)
(a) 16-bit timer mode control register 00 (TMC00)
0000
7654
1
TMC003
TMC00
TMC002 TMC001 OVF00
Clears and starts at
valid edge of TI000 pin.
000
(b) Capture/compare control register 00 (CRC00)
00000
76543
CRC00
CRC002 CRC001 CRC000
CR000 used as compare register
CR010 used as compare register
0 0/1 0
(c) 16-bit timer output control register 00 (TOC00)
0
7
011 0/1
TOC00
LVR00 TOC001 TOE00OSPE00OSPT00 TOC004 LVS00
Enables TO00 output.
Inverts output upon match
between TM00 and CR000.
Specifies initial value of
TO00 output F/F (setting “11” is prohibited.)
Inverts output upon match
between TM00 and CR010.
Sets one-shot pulse output mode.
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
0/1 0/1 0 1
PRM00
PRM001 PRM000
Selects count clock
(setting “11” is prohibited).
Specifies the rising edge
for pulse width detection.
0/1 0/1
ES110 ES100 ES010 ES000
Setting invalid
(setting “10” is prohibited.)
00
32
Caution Do not set the CR000 and CR010 registers to 0000H.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 113
Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)
0000H N
NN N N
MM M M
MN + 1 N + 2 M + 1 M + 2M − 2M − 1
0001H
0000H
Count clock
TM00 count value
CR010 set value
CR000 set value
TI000 pin input
INTTM010
INTTM000
TO00 pin output
When TMC00 is set to 08H
(TM00 count starts)
t
Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop mode) is
set to the TMC002 and TMC003 bits.
Remark N < M
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
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6.5 Cautions Related to 16-Bit Timer/Event Counter 00
(1) Timer start errors
An error of up to one clock may occur in the time requir ed for a match signal to be generated after timer start.
This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.
Figure 6-36. Start Timing of 16-Bit Timer Counter 00 (TM00)
TM00 count value
0000H 0001H 0002H 0004H
Count clock
Timer start
0003H
(2) 16-bit timer counter 00 (TM00) operation
<1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop
mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the
operation.
<2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010).
<3> During TM00 is read, the count clock is stopped.
<4> Regardless of the CPU’s operation mode, when the timer stops, the signals input to pins TI000/TI010
are not acknowledged.
(3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010)
<1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode
entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be
performed when this register is used as an ex ternal event counter.
<2> W hen the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 sh ould
not be specified as a capture register.
<3> In the free-running mode and in the clear & start mode using the valid ed ge of the TI000 pin, if CR0n0 is
set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to
0001H following overflow (FFFFH).
<4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overfl ows, and then
starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer
must be reset to be restarted after the value of CR0n0 is changed.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 115
(4) Capture register data retention
The values of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has
stopped are not guaranteed.
Remark n = 0, 1
(5) Setting of 16-bit timer mode control register 00 (TMC00)
The timer operation must be stopped before writing to bits other than the OVF flag.
(6) Setting of capture/compare control register 00 (CRC00)
The timer operation must be stopped before setting CRC00.
(7) Setting of 16-bit timer output control register 00 (TOC00)
<1> Timer operation must be stopped before setting other than OSPT00.
<2> If LVS00 and LVR00 are read, 0 is read.
<3> OSPT00 is automatically cleared after data is set, so 0 is read.
<4> Do not set OSPT00 to 1 other than in one-shot pulse output mode.
<5> A write interval of two cycles or more of the count clock selected by pr esc aler mode re gi ster 00 (PRM00)
is required to write to OSPT00 successively.
(8) Setting of prescaler mode register 00 (PRM00)
Always set data to PRM00 after stopping the timer operation.
(9) Valid edge setting
Set the valid edge of the TI000 pin with bits 4 and 5 (ES000 and ES010) of prescaler mode register 00
(PRM00) after stopping the timer operation.
(10) One-shot pulse output
One-shot pulse output norma lly oper ates o nly in the free-ru nning mode or in the cl ear & start mode at the vali d
edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between
TM00 and CR000, one-shot pulse output is n ot possible.
(11) One-shot pulse output by software
<1> By setting the OSPT00 bit to 1 while the one-shot pulse is being output, 16-bit timer counter 00 (TM00)
is cleared. To output the one-shot pulse again, wait until the current one-shot pulse output is completed.
<2> When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not
change the level of the TI000 pin or its alternate function port pin. Because the externa l trigger is valid
even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate
function port pin, resulting in the output of a pulse at an undesired timing.
<3> Do not set the 16-bit timer capture/compare registers 0 00 and 010 (CR000 and CR010) to 0000H.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
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(12) One-shot pulse output with external trigger
<1> If the external trigger is generated again while the one-shot pulse is output, 16-bit timer counter 00
(TM00) is cleared.
<2> Do not set the 16-bit timer capture/compare registers 0 00 and 010 (CR000 and CR010) to 0000H.
(13) Operation of OVF00 flag
<1> The OVF00 flag is also set to 1 in the following case.
Either of the clear & start mo de entered o n a match betw een TM00 a nd CR000, cle ar & start at the val id
edge of the TI000 pin, or free-running mode is selected.
↓
CR000 is set to FFFFH.
↓
When TM00 is counted up from FFFFH to 0000H.
Figure 6-37. Operation Timing of OVF00 Flag
Count clock
CR000
TM00
OVF00
INTTM000
FFFFH
FFFEH FFFFH 0000H 0001H
<2> Even if the OVF00 flag is cleared before the next count cloc k is counted (before TM00 b ecomes 0001H)
after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 117
(14) Conflicting operations
If the register read period and the input of the capture trig ger conflict whe n CR00 0/CR01 0 is used as a capture
register, the capture trigger input takes precedence an d the read data is undefined. Also, if the count stop of
the timer and the input of the capture trigger conflict, the captured data is undefined.
Figure 6-38. Capture Register Data Retention Timing
N N + 1 N + 2 M M + 1 M + 2
X N + 2 M + 1
Count clock
TM00 count value
Edge input
INTTM010
Capture read signal
CR010 capture value
Capture, but
read value is
not guaranteed
Capture
(15) Capture operation
<1> If the TI000 pin is specified as the valid edge of the count clock, a capture operation by the capture
register specified as the trigger for the TI000 pin is not possible.
<2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not
performed.
<3> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two
cycles of the count clock selected by prescaler mode register 00 (PRM00).
<4> The capture operation is performed at the fall of the count clock. A interrupt request input (INTTM0n0),
however, occurs at the rise of the next count clock.
<5> To use two capture registers, set the TI000 and TI010 pins.
(16) Compare operation
The capture operation may not be performed for CR0n 0 set in compare mode even if a capture trigger is input.
Remark n = 0, 1
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
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(17) Changing compare register during timer operation
<1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare regist er, when changing
CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer
capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the
timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer
counting, follow the procedure below using an INTTM000 interrupt.
<Changing cycle (CR000)>
1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0).
2. Disable the INTTM000 interrupt (TMMK000 = 1).
3. Rewrite CR000.
4. Wait for 1 cycle of the TM00 count clock.
5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1).
6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).
7. Enable the INTTM000 interrupt (TMMK000 = 0).
<Changing duty (CR010)>
1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0).
2. Disable the INTTM000 interrupt (TMMK000 = 1).
3. Rewrite CR010.
4. Wait for 1 cycle of the TM00 count clock.
5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1).
6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).
7. Enable the INTTM000 interrupt (TMMK000 = 0).
While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If
the value to be set in CR0n0 is small, the val ue of TM00 may exceed CR 0n0. Therefore, set the value,
considering the time lapse of the timer clock and CPU clock after an INTTM000 interrupt has been
generated.
Remark n = 0, 1
<2> If CR010 is changed during timer counting without performing processing <1> above, the value in
CR010 may be rewritten twice or more, causing an in version of the output level of the TO00 pin at each
rewrite.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Preliminary User’s Manual U16898EJ2V0UD 119
(18) Edge detection
<1> In the following cases, note with caution that the vali d edge of the TI0n0 pin is detected.
(a) Immediately after a system reset, if a high level is input to t he TI0n0 pin, the operati on of the 16-bit
timer counter 00 (TM00) is enabled
→ If the rising edge or b oth rising a nd falling edges are specif ied as the v alid edge of th e TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
(b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled
after a low level is input to the TI0n0 pin
→ If the falling edge or both ris ing and fal lin g edges are sp ecifi ed as the vali d edg e of the TI0n0 pi n,
a falling edge is detected imm ediately after the TM00 operation is enabled.
(c) When the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then
enabled after a high level is in put to the TI0n0 pin
→ If the rising ed ge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,
a rising edge is detected immediately after the TM00 operation is enabled.
Remark n = 0, 1
<2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and
when it is used as a capture trigger. In the former case, th e count clock is fXP, and in the latter case the
count clock is selected by prescaler m ode register 00 (PRM00). The capture operati on is not performed
until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short
pulse width.
(19) External event counter
When reading the external event count er count value, TM00 should be read.
(20) PPG output
<1> Values in the following range should be set in CR000 and CR010:
0000H < CR010 < CR000 ≤ FFFFH (setting CR000 to 0000H is prohibited)
<2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010
setting value + 1)/(CR000 setting value + 1).
(21) STOP mode or system clock stop mode setting
Except when TI000 pin valid edge is selected as the count cl ock, stop the timer operation before setting STOP
mode or system clock stop mode; otherwise the timer may malfunction when the system clock starts.
(22) P31/TI010/TO00 pin
When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).
When using P31 as the timer output pin (TO00), it cannot be used as the input pi n (TI010) of the valid edge.
Preliminary User’s Manual U16898EJ2V0UD
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CHAPTER 7 8-BIT TIMER 80
7.1 Function of 8-Bit Timer 80
8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance.
Table 7-1. Interval Time of 8-Bit Timer 80
Minimum Interval Time Maximum Interval Time Resolution
26/fXP (8
µ
s) 214/fXP (2.05 ms) 26/fXP (8
µ
s)
28/fXP (32
µ
s) 216/fXP (8.19 ms) 28/fXP (32
µ
s)
210/fXP (128
µ
s) 218/fXP (32.7 ms) 210/fXP (128
µ
s)
fXP = 8.0 MHz
216/fXP (8.19 ms) 224/fXP (2.01 s) 216/fXP (8.19 ms)
26/fXP (6.4
µ
s) 214/fXP (1.64 ms) 26/fXP (6.4
µ
s)
28/fXP (25.6
µ
s) 216/fXP (6.55 ms) 28/fXP (25.6
µ
s)
210/fXP (102
µ
s) 218/fXP (26.2 ms) 210/fXP (102
µ
s)
fXP = 10.0 MHz
216/fXP (6.55 ms) 224/fXP (1.68 s) 216/fXP (6.55 ms)
Remark fXP: Oscillation frequency of clock to peripheral hardware
CHAPTER 7 8-BIT TIMER 80
Preliminary User’s Manual U16898EJ2V0UD 121
7.2 Configuration of 8-Bit Timer 80
8-bit timer 80 consists of the following hardware.
Table 7-2. Configuration of 8-Bit Timer 80
Item Configuration
Timer counter 8-bit timer counter 80 (TM80)
Register 8-bit compare register 80 (CR80)
Control register 8-bit timer mode control register 80 (TMC80)
Figure 7-1. Block Diagram of 8-Bit Timer 80
Internal bus
Internal bus
8-bit compare register 80
(CR80)
Match
8-bit timer/counter 80
(TM80)
Clear
INTTM80
fXP/2
6
fXP/2
16
TCE80
TCL801 TCL800
8-bit timer mode control
register 80 (TMC80)
fXP/2
8
fXP/2
10
Selector
Remark f
XP: Oscillation frequency of clock to peripheral hardware
CHAPTER 7 8-BIT TIMER 80
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(1) 8-bit compare register 80 (CR80)
This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It
generates an interrupt request signal (INTTM80) if the two values match.
CR80 is set by using an 8-bit memory manipulation instruction. A value of 00H to FFH can be set to this
register.
Reset input makes the contents of this register undefined.
Figure 7-2. Format of 8-Bit Compare Register 80 (CR80)
Symbol
CR80
Address: FFCDH After reset: Undefined W
76543210
Caution When changing the value of CR80, be sure to stop the timer operation. If the value of CR80
is changed with the timer operation enabled, a match interrupt request signal may be
generated immediately.
(2) 8-bit timer/counter 80 (TM80)
This 8-bit register counts the count pulses.
The value of TM80 can be read by using an 8-bit memory manipulation instruction.
Reset input clears TM80 to 00H.
Figure 7-3. Format of 8-Bit Timer Counter 80 (TM80)
Symbol
TM80
Address: FFCEH After reset: 00H R
76543210
CHAPTER 7 8-BIT TIMER 80
Preliminary User’s Manual U16898EJ2V0UD 123
7.3 Register Controlling 8-Bit Timer 80
8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80).
(1) 8-bit timer mode control register 80 (TMC80)
This register is used to enable or stop the operation of 8-bit timer/counter 80 (TM80), and to set the count
clock of TM80.
This register is set by using a 1-bit or 8-bit memory manipulation instruction.
Reset input clears TMC80 to 00H.
Figure 7-4. Format of 8-Bit Timer Mode Control Register 80 (TMC80)
Address: FFCCH After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
TMC80 TCE80 0 0 0 0 TCL801 TCL800 0
TCE80 Control of operation of TM80
0 Stop operation (clear TM80 to 00H).
1 Enable operation.
Selection of count clock of 8-bit timer 80 TCL801 TCL800
f
XP = 8.0 MHz fXP = 10.0 MHz
0 0 fXP/26 125 kHz 156.3 kHz
0 1 fXP/28 31.25 kHz 39.06 kHz
1 0 fXP/210 7.81 kHz 9.77 kHz
1 1 fXP/216 0.12 kHz 0.15 kHz
Cautions 1. Be sure to set TMC80 after stopping the timer operation.
2. Be sure to clear bits 0 and 6 to 0.
Remark f
XP: Oscillation frequency of clock to peripheral hardware
CHAPTER 7 8-BIT TIMER 80
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7.4 Operation of 8-Bit Timer 80
7.4.1 Operation as interval timer
When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by
the count value set in advance to 8-bit compare register 80 (CR80).
To use 8-bit timer 80 as an interval timer, make the following setting.
<1> Disable the operation of 8-bit timer counter 80 (clear TCE80 (bit 7 of 8-bit timer mode control register 80
(TMC80)) to 0).
<2> Set the count clock of 8-bit timer 80 (refer to Tables 7-3 and 7-4).
<3> Set the count value to CR80.
<4> Enable the operation of TM80 (set TCE80 to 1).
When the count value of 8-bit timer counter 80 (TM80) matches the set value of CR80, the value of TM80 is
cleared to 00H and counting is continued. At the same time, an interrupt request signal (INTTM80) is generated.
Tables 7-3 and 7-4 show the interval time, and Figure 7-5 shows the timing of the interval timer operation.
Cautions 1. When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is
changed with the timer operation enabled, a match interrupt request signal may be generated
immediately.
2. If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by
using an 8-bit memory manipulation instruction, the error of one cycle after the timer is
started may be 1 clock or more. Therefore, be sure to follow the above sequence when using
TM80 as an interval timer.
Table 7-3. Interval Time of 8-Bit Timer 80 (fXP = 8.0 MHz)
TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution
0 0 26/fXP (8
µ
s) 214/fXP (2.05 ms) 26/fXP (8
µ
s)
0 1 28/fXP (32
µ
s) 216/fXP (8.19 ms) 28/fXP (32
µ
s)
1 0 210/fXP (128
µ
s) 218/fXP (32.7 ms) 210/fXP (128
µ
s)
1 1 216/fXP (8.19 ms) 224/fXP (2.01 s) 216/fXP (8.19 ms)
Remark fXP: Oscillation frequency of clock to peripheral hardware
Table 7-4. Interval Time of 8-Bit Timer 80 (fXP = 10.0 MHz)
TCL801 TCL800 Minimum Interval Time Maximum Interval Time Resolution
0 0 26/fXP (6.4
µ
s) 214/fXP (1.64 ms) 26/fXP (6.4
µ
s)
0 1 28/fXP (25.6
µ
s) 216/fXP (6.55 ms) 28/fXP (25.6
µ
s)
1 0 210/fXP (102
µ
s) 218/fXP (26.2 ms) 210/fXP (102
µ
s)
1 1 216/fXP (6.55 ms) 224/fXP (1.68 s) 216/fXP (6.55 ms)
Remark fXP: Oscillation frequency of clock to peripheral hardware
CHAPTER 7 8-BIT TIMER 80
Preliminary User’s Manual U16898EJ2V0UD 125
Figure 7-5. Timing of Interval Timer Operation
Clear Clear
Interrupt acknowledged Interrupt acknowledged
Count start
Interval time Interval time Interval time
Count clock
TM80 count value
CR80
TCE80
INTTM80
TO80
N01H00HN01H00HN00H 01H
NN NN
t
Remark Interval time = (N + 1) × t: N = 00H to FFH
CHAPTER 7 8-BIT TIMER 80
Preliminary User’s Manual U16898EJ2V0UD
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7.5 Notes on 8-Bit Timer 80
(1) Error when timer starts
The time from starting the timer to generation of the match signal inc ludes an error of up to 1.5 clocks. This is
because, if the timer is started while the count clock is high, the rising edge may be immediately detected and
the counter may be incremented (refer to Figure 7-6).
Figure 7-6. Case Where Error of 1.5 Clocks (Max.) Occurs
8-bit timer counter 80
(TM80)
Count pulse
Clear signal
Selected clock
TCE80
Delay A
Delay B
Selected clock
TCE80
Clear signal
Count pulse
TM80 count value 00H 01H 02H 03H ...
Delay A
Delay B
If the timer is started when the selected clock is high
and if delay A > delay B, an error of up to 1.5 clocks occurs.
(2) Setting of 8-bit compare register 80
8-bit compare register 80 (CR80) can be set to 00H.
(3) Note on setting STOP mode
Before executing the STOP instruction, be sure to stop the timer operation (TCE80 = 0).
Preliminary User’s Manual U16898EJ2V0UD 127
CHAPTER 8 8-BIT TIMER H1
8.1 Functions of 8-Bit Timer H1
8-bit timer H1 has the following functions.
• Interval timer
• PWM output mode
• Square-wave output
8.2 Configuration of 8-Bit Timer H1
8-bit timer H1 consists of the following hardware.
Table 8-1. Configuration of 8-Bit Timer H1
Item Configuration
Timer register 8-bit timer counter H1
Registers 8-bit timer H compare register 01 (CMP01)
8-bit timer H compare register 11 (CMP11)
Timer output TOH1
Control registers 8-bit timer H mode register 1 (TMHMD1)
Port mode register 4 (PM4)
Port register 4 (P4)
Figure 8-1 shows a block diagram.
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD
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Figure 8-1. Block Diagram of 8-Bit Timer H1
Match
Selector
Internal bus
TMHE1
CKS12
CKS11
CKS10
TMMD11 TMMD10
TOLEV1
TOEN1
8-bit timer H mode register 1
(TMHMD1)
8-bit timer H
compare register
11 (CMP11)
Decoder TOH1/P42
INTTMH1
Selector
f
XP
f
XP
/2
2
f
XP
/2
4
f
XP
/2
6
f
XP
/2
12
f
RL
/2
7
Interrupt
generator Output
controller
Level
inversion
1
0
F/F
R
8-bit timer
counter H1
PWM mode signal
Timer H enable signal
Clear
32
8-bit timer H
compare register
01 (CMP01)
Output latch
(P42) PM42
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 129
(1) 8-bit timer H compare register 01 (CMP01)
This register can be read or written by an 8-bit memory manip ulation instruction.
Reset input clears this register to 00H.
Figure 8-2. Format of 8-Bit Timer H Compare Register 01 (CMP01)
Symbol
CMP01
Address: FF0EH After reset: 00H R/W
76543210
Caution CMP01 cannot be rewritten during timer count operation.
(2) 8-bit timer H compare register 11 (CMP11)
This register can be read or written by an 8-bit memory manip ulation instruction.
Reset input clears this register to 00H.
Figure 8-3. Format of 8-Bit Timer H Compare Register 11 (CMP11)
Symbol
CMP11
Address: FF0FH After reset: 00H R/W
76543210
CMP11 can be rewritten during timer count operation.
If the CMP11 value is rewritten during timer operation, transferring is performed at the timing at which the count
value and CMP11 value match. If the transfer timing and writing from CPU to CMP11 conflict, transfer is not
performed.
Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1
= 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting
the same value to CMP11).
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Preliminary User’s Manual U16898EJ2V0UD
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8.3 Registers Controlling 8-Bit Timer H1
The following three registers are used to control 8-Bit Time r H1.
• 8-bit timer H mode register 1 (TMHMD1)
• Port mode register 4 (PM4)
• Port register 4 (P4)
(1) 8-bit timer H mode register 1 (TMHMD1)
This register controls the mode of timer H.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 131
Figure 8-4. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
TMHE1
Stop timer count operation (counter is cleared to 0)
Enable timer count operation (count operation started by inputting clock)
TMHE1
0
1
Timer operation enable
TMHMD1
Symbol CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
Address: FF70H After reset: 00H R/W
f
XP
f
XP
/2
2
f
XP
/2
4
f
XP
/2
6
f
XP
/2
12
f
RL
/2
7
CKS12
0
0
0
0
1
1
CKS11
0
0
1
1
0
0
CKS10
0
1
0
1
0
1
(10 MHz)
(2.5 MHz)
(625 kHz)
(156.25 kHz)
(2.44 kHz)
(1.88 kHz (TYP.))
Count clock (f
CNT
) selection
Setting prohibitedOther than above
Interval timer mode
PWM output mode
Setting prohibited
TMMD11
0
1
TMMD10
0
0
Timer operation mode
Low level
High level
TOLEV1
0
1
Timer output level control (in default mode)
Disable output
Enable output
TOEN1
0
1
Timer output control
Other than above
<7> 6543 2 <1> <0>
Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.
2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when
starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped
(TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register).
Remarks 1. f
XP: Oscillation frequency of clock to peripheral hardware
2. f
RL: Low-speed Ring-OSC clock oscillation frequency
3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.).
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD
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(2) Port mode register 4 (PM4)
This register sets port 4 input/output in 1-bit units.
When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0.
PM4 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to FFH.
Figure 8-5. Format of Port Mode Register 4 (PM4)
Address: FF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40
PM4n P4n pin I/O mode selection (n = 0 to 5)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 133
8.4 Operation of 8-Bit Timer H1
8.4.1 Operation as interval timer/square-wave output
When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is
generated and 8-bit timer counter H1 is cleared to 00H.
Compare register 11 (CMP11) is not used in interval timer mode. Sinc e a match of 8-bit timer cou nter H1 and the
CMP11 register is not detected even if the CMP11 register is set, timer output is not affected.
By setting bit 0 (TOEN1) of timer H m ode register 1 (TMH MD1) to 1, a s quare w ave of any fre quency (duty = 50%)
is output from TOH1.
(1) Usage
Generates the INTTMH1 signal repeatedly at the same interval.
<1> Set each register.
Figure 8-6. Register Setting During Interval Timer/Square-Wave Output Operation
(i) Setting timer H mode register 1 (TMHMD1)
0 0/1 0/1 0/1 0 0 0/1 0/1
TMMD10 TOLEV1 TOEN1CKS11CKS12TMHE1
TMHMD1
CKS10 TMMD11
Timer output setting
Timer output level inversion setting
Interval timer mode setting
Count clock (f
CNT
) selection
Count operation stopped
(ii) CMP01 register setting
• Compar e value (N)
<2> Count operation starts when TMHE1 = 1.
<3> When the values of 8-bit timer counter H1 and the CMP01 register m atch, the INTTMH1 signal is generated
and 8-bit timer counter H1 is cleared to 00H.
Interval time = (N +1)/fCNT
<4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear
TMHE1 to 0.
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD
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(2) Timing chart
The timing of the interval timer/square-wave output operation is shown below.
Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2)
(a) Basic operation
00H
Count clock Count start
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
01H N
Clear
Interval time
Clear
N
00H 01H N 00H 01H 00H
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter H1 clear
<2>
Level inversion,
match interrupt occurrence,
8-bit timer counter H1 clear
<3><1>
<1> The count operation is enabled by setting the TMHE1 bi t to 1. The count clock starts counting no more than
1 clock after the operation is enabled.
<2> When the values of 8-bit timer cou nter H1 and th e CMP01 register match, the v alue of 8- bit timer cou nter H 1
is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output.
<3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1
operation. If these are inactive from the first, the level is retained.
Remark N = 01H to FEH
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 135
Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2)
(b) Operation when CMP01 = FFH
00H
Count clock Count start
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
01H FEH
Clear
Clear
FFH 00H FEH FFH 00H
FFH
Interval time
(c) Operation when CMP01 = 00H
Count clock Count start
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
00H
00H
Interval time
CHAPTER 8 8-BIT TIMER H1
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8.4.2 Operation as PWM output mode
In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.
8-bit timer compare regist er 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register
during timer operation is prohibited.
8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register
during timer operation is possible.
The operation in PWM output mode is as follows.
TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the
CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1
and the CMP11 register match.
(1) Usage
In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.
<1> Set each register.
Figure 8-8. Register Setting in PWM Output Mode
(i) Setting timer H mode register 1 (TMHMD1)
0 0/1 0/1 0/1 1 0 0/1 1
TMMD10 TOLEV1 TOEN1CKS11CKS12TMHE1
TMHMD1
CKS10 TMMD11
Timer output enabled
Timer output level inversion setting
PWM output mode selection
Count clock (fCNT) selection
Count operation stopped
(ii) Setting CMP01 register
• Compare value (N): Cycle setting
(iii) Setting CMP11 register
• Compare value (M): Duty setting
Remark 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
<2> The count operation starts when TMHE1 = 1.
<3> The CMP01 register is the compare register that is to be compared first after count operation is enabled.
When the values of 8- bit timer counter H1 and the CMP01 register m atch, 8-bit timer cou nter H1 is clear ed,
an interrupt request signal (I NTTMH1) is generated, and TOH1 output becomes active. At the s ame time,
the compare register to be c o mpared with 8- bit timer c ount er H1 is chan ged from th e C MP01 register to the
CMP11 register.
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 137
<4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the
compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the
CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not
generated.
<5> By performing procedures <3 > and <4> repeatedly, a pulse with an arbitrary duty can be obtain ed.
<6> To stop the count operation, set TMHE1 = 0.
If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock
frequency is fCNT, the PWM pulse output cycle and duty are as follows.
PWM pulse output cycle = (N+1)/fCNT
Duty = Active width : Total width of PWM = (M + 1) : (N + 1)
Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKS12 to CKS10
bits of the TMHMD1 register) are required to transfer the CMP11 register value after
rewriting the register.
2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after
the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the
same value to the CMP11 register).
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD
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(2) Timing chart
The operation timing in PWM output mode is shown below.
Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are
within the following range.
00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH
Figure 8-9. Operation Timing in PWM Output Mode (1/4)
(a) Basic operation
Count clock
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
TOH1
(TOLEV1 = 1)
00H 01H A5H 00H 01H 02H A5H 00H A5H 00H01H 02H
CMP11
A5H
01H
<1> <2> <3> <4>
<1> The count operation is enabled by s etting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one
count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0).
<2> When the values of 8-bit timer cou nter H1 and the CMP01 register match, the TOH1 output level is inverted,
the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output.
<3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is
returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output.
<4> Clearing the TMHE1 bit to 0 durin g timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 139
Figure 8-9. Operation Timing in PWM Output Mode (2/4)
(b) Operation when CMP01 = FFH, CMP11 = 00H
Count clock
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
00H 01H FFH 00H 01H 02H FFH 00H FFH 00H01H 02H
CMP11
FFH
00H
(c) Operation when CMP01 = FFH, CMP11 = FEH
Count clock
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
00H 01H FEH FFH 00H 01H FEH FFH 00H 01H FEH FFH 00H
CMP11
FFH
FEH
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Preliminary User’s Manual U16898EJ2V0UD
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Figure 8-9. Operation Timing in PWM Output Mode (3/4)
(d) Operation when CMP01 = 01H, CMP11 = 00H
Count clock
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
01H
00H 01H 00H 01H 00H 00H 01H 00H 01H
CMP11 00H
CHAPTER 8 8-BIT TIMER H1
Preliminary User’s Manual U16898EJ2V0UD 141
Figure 8-9. Operation Timing in PWM Output Mode (4/4)
(e) Operation by changing CMP11 (CMP11 = 01H → 03H, CMP01 = A5H)
Count clock
8-bit timer counter H1
CMP01
TMHE1
INTTMH1
TOH1
(TOLEV1 = 0)
00H 01H 02H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H
CMP11 01H
A5H
03H01H (03H)
<1> <3> <4>
<2> <2>'
<5> <6>
<1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count
clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0).
<2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous
to the count clock.
<3> When the values of 8-bit timer cou nter H1 and th e CMP01 register match, the v alue of 8- bit timer cou nter H 1
is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output.
<4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the
values of 8-bit timer counter H1 and the CMP11 regist er before the change match, the value is transferred to
the CMP11 register and the CMP11 register value is changed (<2>’).
Howev er, three count clocks or more are required from when the CMP11 register value is changed to when
the value is transferred to the register. If a m atch signal is generated withi n three count clocks, the ch anged
value cannot be transferred to the register.
<5> When the values of 8-bit timer counter H1 and the CM P11 register after the change match, the TOH1 outpu t
becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.
<6> Clearing the TMHE1 bit to 0 durin g timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.
Preliminary User’s Manual U16898EJ2V0UD
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CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer is used to detect an ina dvertent program loop. If a program loo p is detected, an internal res et
signal is generated.
When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.
For details of RESF, see CHAPTER 14 RESET FUNCTION.
Table 9-1. Loop Detection Time of Watchdog Timer
Loop Detection Time
During Low-Speed Ring-OSC Clock Operation During System Clock Operation
211/fRL (4.27 ms) 213/fX (819.2
µ
s)
212/fRL (8.53 ms) 214/fX (1.64 ms)
213/fRL (17.07 ms) 215/fX (3.28 ms)
214/fRL (34.13 ms) 216/fX (6.55 ms)
215/fRL (68.27 ms) 217/fX (13.11 ms)
216/fRL (136.53 ms) 218/fX (26.21 ms)
217/fRL (273.07 ms) 219/fX (52.43 ms)
218/fRL (546.13 ms) 220/fX (104.86 ms)
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. f
X: Oscillation frequency of system clock
3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip
low-speed Ring-OSC oscillator as shown in Table 9-2.
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Preliminary User’s Manual U16898EJ2V0UD 143
Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode
Option Byte Setting
Low-Speed Ring-OSC Cannot Be Stopped Low-Speed Ring-OSC Can Be Stopped by Software
Watchdog timer clock
source Fixed to fRLNote 1. • Selectable by software (fX, fRL or stopped)
• When reset is released: fRL
Operation after reset Operation starts with the maximum interval (218/fRL). Operation starts with the maximum interval
(218/fRL).
Operation mode
selection The interval can be changed only once. The clock selection/interval can be changed only
once.
Features The watchdog timer cannot be stopped. The watchdog timer can be stoppedNote 2.
Notes 1. As long as po wer is being supplied, low-speed Ring-OSC oscillati on cannot be stopped (except in the
reset period).
2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the
clock source of the watchdog timer.
<1> If the clock source is fX, clock supply to the watchdog timer is stopped under the following
conditions.
• When fX is stopped
• In HALT/STOP mode
• During oscillation stabilizati on time
<2> If the clock source is fRL, clock supply to the watchdog timer is stopped under the following
conditions.
• If the CPU clock is fX and if fRL is stopped by software before execution of the STOP instruction
• In HALT/STOP mode
Remarks 1. f
RL: Low-speed Ring-OSC clock oscillation frequency
2. f
X: Oscillation frequency of system clock
CHAPTER 9 WATCHDOG TIMER
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9.2 Configuration of Watchdog Timer
The watchdog timer consists of the following hardw are.
Table 9-3. Configuration of Watchdog Timer
Item Configuration
Control registers Watchdog timer mode register (WDTM)
Watchdog timer enable register (WDTE)
Figure 9-1. Block Diagram of Watchdog Timer
f
RL
/2
2
Clock
input
controller
Output
controller Internal reset signal
WDCS2
Internal bus
WDCS1 WDCS0
f
X
/2
4
WDCS3WDCS4
011
Selector
16-bit
counter or
2
13
/f
X
to
2
20
/f
X
2
11
/f
RL
to
2
18
/f
RL
Watchdog timer enable
register (WDTE) Watchdog timer mode
register (WDTM)
3
2
Clear
Option byte
(to set “low-speed
Ring-OSC cannot be
stopped” or “low-speed
Ring-OSC can be
stopped by software”)
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD 145
9.3 Registers Controlling Watchdog Timer
The watchdog timer is controlled by the follo wing two registers.
• Watchdog timer mode register (WDTM)
• Watchdog timer enable register (WDTE)
(1) Watchdog timer mode register (WDTM)
This register sets the overflow time and operation clock of the watchdog timer.
This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be
written only once after reset is released.
Reset input sets this register to 67H.
Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)
0
WDCS0
1
WDCS1
2
WDCS2
3
WDCS3
4
WDCS4
5
1
6
1
7
0
Symbol
WDTM
Address: FF48H After reset: 67H R/W
WDCS4Note 1 WDCS3Note 1 Operation clock selection
0 0 Low-speed Ring-OSC clock (fRL)
0 1 System Clock (fX)
1 × Watchdog timer operation stopped
Overflow time setting WDCS2Note 2 WDCS1Note 2 WDCS0Note 2
During low-speed Ring-OSC
clock operation During system clock operation
0 0 0 211/fRL (4.27 ms) 213/fX (819.2
µ
s)
0 0 1 212/fRL (8.53 ms) 214/fX (1.64 ms)
0 1 0 213/fRL (17.07 ms) 215/fX (3.28 ms)
0 1 1 214/fRL (34.13 ms) 216/fX (6.55 ms)
1 0 0 215/fRL (68.27 ms) 217/fX (13.11 ms)
1 0 1 216/fRL (136.53 ms) 218/fX (26.21 ms)
1 1 0 217/fRL (273.07 ms) 219/fX (52.43 ms)
1 1 1 218/fRL (546.13 ms) 220/fX (104.86 ms)
Notes 1. If “low-speed Ring-OSC cann ot be stoppe d” is specif i ed by the opti on byt e , this cannot be set.
The low-speed Ring-OSC clock will be selected no matter what value is written.
2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).
CHAPTER 9 WATCHDOG TIMER
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Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “low-speed Ring-OSC cannot be
stopped” is selected by the option byte, other values are ignored).
2. After reset is released, WDTM can be written only once by an 8-bit memory
manipulation instruction. If writing is attempted a second time, an internal reset
signal is generated.
3. WDTM cannot be set by a 1-bit memory manipulation instruction.
4. When using the flash memory self programming by self writing, set the overflow time
for the watchdog timer so that enough everflow time is secured (Example 1-byte
writing: 200
µ
s MIN., 1-block deletion: 10 ms MIN.).
Remarks 1. fRL: Low-speed Ring-OSC clock oscillation frequency
2. fX: System clock oscillation frequency
3. ×: Don’t care
4. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.
(2) Watchdog timer enable register (WDTE)
Writing ACH to WDTE clears the watchdog timer counter a nd starts counting again.
This register can be set by an 8-bit memory manipulation instruction.
Reset input sets this register to 9AH.
Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)
01234567
Symbol
WDTE
Address: FF49H After reset: 9AH R/W
Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.
2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset
signal is generated.
3. The value read from WDTE is 9AH (this differs from the written value (ACH)).
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD 147
9.4 Operation of Watchdog Timer
9.4.1 Watchdog timer operation when “low-speed Ring-OSC cannot be stopped” is selected by option byte
The operation clock of watchdog timer is fix ed to low-speed Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Low-speed Ring-OSC clock
• Cycle: 218/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.))
• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2.
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. The operation clock (low-speed Ring-OSC clock) cannot be changed. If any value is written to bits 3
and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
execution. For 8-bit timer H1 (TMH1), a division of the low-speed Ring-OSC clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
A status transition diagram is shown below
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD
148
Figure 9-4. Status Transition Diagram When “Low-Speed Ring-OSC Cannot Be Stopped”
Is Selected by Option Byte
Reset
WDT clock: f
RL
Overflow time: 546.13 ms (MAX.)
STOP
WDT count continues.
HALT
WDT count continues.
STOP instruction
HALT instruction
WDT clock is fixed to f
RL
.
Select overflow time (settable only once).
WDT clock: f
RL
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
Interrupt
Interrupt
WDTE = “ACH”
Clear WDT counter .
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD 149
9.4.2 Watchdog timer operation when “low-speed Ring-OSC can be stopped by software” is selected by
option byte
The operation clock of t he watchdog timer can be selecte d as either the low-speed Ring-OSC clock or the system
clock.
After reset is released, operation is started at the maximum cycle of the low-speed Ring-OSC clock (bits 2, 1, and 0
(WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Low-speed Ring-OSC clock
• Cycle: 218/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.))
• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instructionNotes 1, 2, 3.
• Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and W DCS4).
Low-speed Ring-OSC clock (fRL)
System clock (fX)
Watchdog timer operation stopped
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.
2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.
3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal
reset signal is not generated even if the following pr ocessing is performed.
• WDTM is written a second time.
• A 1-bit memory manipulation instruction is executed to WDTE.
• A value other than ACH is written to WDTE.
Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.
After HALT/STOP mode is released, counting is started again using the operation clock of the
watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter
is not cleared to 0 but holds its value.
For the watchdog timer operation d uring STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer
operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.
A status transition diagram is shown below.
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD
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Figure 9-5. Status Transition Diagram When “Low-Speed Ring-OSC Can Be Stopped by Software”
Is Selected by Option Byte
Reset
WDT clock: f
RL
Overflow time: 546.13 ms (MAX.)
WDT clock = f
RL
Select overflow time
(settable only once).
WDT clock: f
RL
Overflow time: 4.27 ms to 546.13 ms (MAX.)
WDT count continues.
STOP
WDT count stops.
HALT
WDT count stops.
STOP
instruction
HALT instruction
Interrupt
Interrupt
WDTE = “ACH”
Clear WDT counter .
WDT operation stops.
WDCS4 = 1
WDT clock: f
X
Overflow time: 2
13
/f
X
to 2
20
/f
X
WDT count continues.
WDT clock = f
X
Select overflow time
(settable only once).
WDT clock: f
RL
WDT count stops.
WDTE = “ACH”
Clear WDT counter .
LSRSTOP = 1
LSRSTOP = 0
STOP
WDT count stops.
HALT
WDT count stops.
STOP
instruction
HALT
instruction
InterruptInterrupt
STOP
instruction
Interrupt
Interrupt
HALT
instruction
WDTE = “ACH”
Clear WDT counter .
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Preliminary User’s Manual U16898EJ2V0UD 151
9.4.3 Watchdog timer operation in STOP mode (when “low-speed Ring-OSC can be stopped by software” is
selected by option byte)
The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or
low-speed Ring-OSC clock is bein g used.
(1) When the watchdog timer operation clock is the clock to peripheral hardware (fX) when the STOP
instruction is executed
When STOP instruction is executed, o peration of the watchdog timer is stopped. After STOP mode is released,
operation stops for 34
µ
s (TYP.) (after waiting for the oscillation stabilization time set by the oscillation
stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then
counting is started again usin g the operation clock before the op eration was stopped. At this time, the counter is
not cleared to 0 but holds its value.
Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
<1> CPU clock: Crystal/ceramic oscillation clock
Operation stopped Operating
Oscillation stabilization time Normal operation
STOP
Oscillation stabilization time
(set by OSTS register)
Oscillation stopped
Watchdog timer Operating
fCPU
CPU operation Normal
operation Operation
stoppedNote
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Operation stopped Operating
Normal operation
Oscillation stopped
Watchdog timer
f
CPU
CPU operation STOP
Operating
Normal
operation Operation
stopped
Note
Note The operation stop time is 17
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
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Preliminary User’s Manual U16898EJ2V0UD
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(2) When the watchdog timer operation clock is the low-speed Ring-OSC clock (fRL) when the STOP
instruction is executed
When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is
released, operation stops for 34
µ
s (TYP.) and then counting is started again usi ng the oper ation clock before the
operation was stopped. At this time, the counter is not cleared to 0 but holds its value.
Figure 9-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Ring-OSC Clock)
<1> CPU clock: Crystal/ceramic oscillation clock
Operating
Oscillation stabilization time Normal operation
Oscillation stabilization time
(set by OSTS register)
Watchdog timer Operation stoppedOperating
fRL
fCPU
CPU operation Normal
operation STOP
Oscillation stopped
Operation
stoppedNote
<2> CPU clock: High-speed Ring-OSC clock or external clock input
Operating
Normal operation
Watchdog timer Operation stoppedOperating
fRL
fCPU
CPU operation Normal
operation STOP
Oscillation stopped
Operation
stoppedNote
Note The operation stop time is 17
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
CHAPTER 9 WATCHDOG TIMER
Preliminary User’s Manual U16898EJ2V0UD 153
9.4.4 Watchdog timer operation in HALT mode (when “low-speed Ring-OSC can be stopped by software” is
selected by option byte)
The watchdog timer stops co unting during HALT instruction execution regar dless of whether the operation c lock of
the watchdog timer is the system clock (fX) or low-speed Ring-OSC clock (fRL). After HALT mode is released, counting
is started again using the oper ation clock bef ore the operati on was stoppe d. At this time, the counter is not cleared to
0 but holds its value.
Figure 9-8. Operation in HALT Mode
Watchdog timer Operating
fX or fRL
fCPU
CPU operation Normal operation
Operating
HALT
Operation stopped
Normal operation
Preliminary User’s Manual U16898EJ2V0UD
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CHAPTER 10 A/D CONVERTER
10.1 Functions of A/D Converter
The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to
ANI3) with a resolution of 10 bits.
The A/D converter has the following function.
• 10-bit resolution A/D conversion
10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to
ANI3. Each time an A/D conversion operation en ds, an interrupt request (INTAD) is generated.
Figure 10-1 shows the timing of sampling and A/D conversion, and Table 10-1 shows the sampling time and A/D
conversion time.
Figure 10-1. Timing of A/D Converter Sampling and A/D Conversion
ADCS
Conversion time Conversion time
Sampling
time
Sampling
timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
time
Note
Note 2 or 3 clocks are required from the ADCS rising to sampling start.
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Preliminary User’s Manual U16898EJ2V0UD 155
Table 10-1. Sampling Time and A/D Conversion Time
fXP = 8 MHz fXP = 10 MHz FR2 FR1 FR0 Reference
Voltage
RangeNote 1
Sampling
TimeNote 2 Conversion
TimeNote 3 Sampling
TimeNote 2 Conversion
TimeNote 3 Sampling
TimeNote 2 Conversion
TimeNote 3
0 0 0 AVREF ≥ 4.5 V 12/fXP 36/fXP 1.5
µ
s 4.5
µ
s 1.2
µ
s 3.6
µ
s
0 0 1 AVREF ≥ 2.85 V 24/fXP 48/fXP 3.0
µ
s 6.0
µ
s
Setting prohibited
(2.4
µ
s)
Setting prohibited
(4.8
µ
s)
0 1 0 AVREF ≥ 2.7 V 48/fXP 72/fXP
Setting prohibited
(6.0
µ
s)
Setting prohibited
(9.0
µ
s)
Setting prohibited
(4.8
µ
s)
Setting prohibited
(7.2
µ
s)
0 1 1 AVREF ≥ 2.7 V 88/fXP 112/fXP 11.0
µ
s 14.0
µ
s
Setting prohibited
(8.8
µ
s)
Setting prohibited
(11.2
µ
s)
1 0 0 AVREF ≥ 4.5 V 24/fXP 72/fXP 3.0
µ
s 9.0
µ
s 2.4
µ
s 7.2
µ
s
1 0 1 AVREF ≥ 2.85 V 48/fXP 96/fXP 6.0
µ
s 12.0
µ
s 4.8
µ
s 9.6
µ
s
1 1 0 AVREF ≥ 2.7 V 96/fXP 144/fXP 12.0
µ
s 18.0
µ
s
Setting prohibited
(9.6
µ
s)
Setting prohibited
(14.4
µ
s)
1 1 1 AVREF ≥ 2.7 V 176/fXP 224/fXP 22.0
µ
s 28.0
µ
s 17.2
µ
s 22.4
µ
s
Notes 1. Be sure to set the FR2, FR1, and FR0 i n accordance with the reference voltage range and satisfy Notes 2
and 3 below.
Example When AVREF ≥ 2.7 V
• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
• The sampling time is 11.0
µ
s or more and the A/D conversion time is 14.0
µ
s or more and 100
µ
s or
less.
2. Set the sampling time as follows.
• AVREF ≥ 4.5 V: 1.0
µ
s or more
• AVREF ≥ 4.0 V: 2.4
µ
s or more
• AVREF ≥ 2.85 V: 3.0
µ
s or more
• AVREF ≥ 2.7 V: 11.0
µ
s or more
3. Set the A/D conversion time as follows.
• AVREF ≥ 4.5 V: 3.0
µ
s or more and less than 100
µ
s
• AVREF ≥ 4.0 V: 4.8
µ
s or more and less than 100
µ
s
• AVREF ≥ 2.85 V: 6.0
µ
s or more and less than 100
µ
s
• AVREF ≥ 2.7 V: 14.0
µ
s or more and less than 100
µ
s
Caution The above sampling time and conversion time do not include the clock frequency error. Select the
conversion time taking the clock frequency error into consideration.
Remarks 1. fXP: Oscillation frequency of cl ock to peripheral hardware
2. The conversion time refers to the total of the sampling time and the time from successively comparing
with the sampling value until the conversion result is output.
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Preliminary User’s Manual U16898EJ2V0UD
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Figure 10-2 shows the block diagram of A/D converter.
Figure 10-2. Block Diagram of A/D Converter
AV
REF
V
SS
INTAD
2
ADS1 ADS0
V
SS
ANI0/P20
ANI1/P21
ANI2/P22
ANI3/P23
ADCS FR2 FR1 ADCEFR0
3
Sample & hold circuit
Voltage comparator
Controller
A/D conversion result register
(ADCR, ADCRH)
Analog input
channel specification
register (ADS) A/D converter mode
register (ADM)
Internal bus
Successive
approximation
register (SAR)
Selector
D/A converter
Caution In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be
sure to connect VSS to a stabilized GND (= 0 V).
CHAPTER 10 A/D CONVERTER
Preliminary User’s Manual U16898EJ2V0UD 157
10.2 Configuration of A/D Converter
The A/D converter consists of the following hardware.
Table 10-2. Registers of A/D Converter Used on Software
Item Configuration
Registers 10-bit A/D conversion result register (ADCR)
8-bit A/D conversion result register (ADCRH)
A/D converter mode register (ADM)
Analog input channel specification register (ADS)
Port mode control register 2 (PMC2)
Port mode register 2 (PM2)
(1) ANI0 to ANI3 pins
These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into
digital signals. Pins other than the one selected as t he analog input pin by the analog input c hannel s pecification
register (ADS) can be used as input port pi ns.
(2) Sample & hold circuit
The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D
conversion is started, and holds the sampled analog input voltage value during A/D conversion.
(3) D/A converter
The D/A converter is connected between AVREF and VSS, and generates a voltage to be compared with the
analog input signal.
(4) Voltage comparator
The voltage comparator compares the samp led analog input voltage and the output voltage of the D/A converter.
(5) Successive approximation register (SAR)
This register compares the sampled an alog voltage and th e voltage of the D/A converter, and conv erts the result,
starting from the most significant bit (MSB).
When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D
conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR) .
(6) 10-bit A/D conversion result register (ADCR)
The result of A/D conversion is loaded from the successive approximation register to this register each time A/D
conversion is completed, an d the ADCR regi ster holds the result of A/D conversio n in its lower 10 bits (t he higher
6 bits are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)
The result of A/D conversion is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits.
(8) Controller
When A/D conversion has been completed, INTAD is generated.
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Preliminary User’s Manual U16898EJ2V0UD
158
(9) AVREF pin
This pin inputs an analog power/reference voltage to the A/D converter. When the A/D converter is not used,
connect this pin to VDD.
The signal input to ANI0 to AN I3 is converted into a digit al signal, based on the voltag e applie d across A VREF and
VSS.
(10) VSS pin
This is the ground potential pin.
In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to connect
VSS to a stabilized GND (= 0 V).
(11) A/D converter mode register (ADM)
This register is used to set the conversio n time of the anal og input sign al to be conver ted, and to start or stop the
conversion operation.
(12) Analog input channel specification register (ADS)
This register is used to specify the port that inputs the analog voltag e to be converted into a digital signal.
(13) Port mode control register 2 (PMC2)
This register is used when the P20/ANI0 to P23/ANI3 pins are used as the analog input pins of the A/D converter.
10.3 Registers Used by A/D Converter
The A/D converter uses the following six registers.
• A/D converter mode register (ADM)
• Analog input channel specification register (ADS)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
• Port mode cont rol register 2 (PMC2)
• Port mode regi ster 2 (PM2)
(1) A/D converter mode register (ADM)
This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.
ADM can be set by a 1-bit or 8-bit memory manipulation in struction.
Reset input clears this register to 00H.
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Preliminary User’s Manual U16898EJ2V0UD 159
Figure 10-3. Format of A/D Converter Mode Register (ADM)
Address: FF80H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 <0>
ADM ADCS 0 FR2 FR1 FR0 0 0 ADCE
ADCS A/D conversion operation control
0 Stops conversion operation
1Note 1 Starts conversion operation
fXP = 8 MHz fXP = 10 MHz FR2 FR1 FR0 Reference
Voltage
RangeNote 2
Sampling
TimeNote 3 Conversion
TimeNote 4 Sampling
TimeNote 3 Conversion
TimeNote 4 Sampling
TimeNote 3 Conversion
TimeNote 4
0 0 0 AVREF ≥
4.5 V 12/fXP 36/fXP 1.5
µ
s 4.5
µ
s 1.2
µ
s 3.6
µ
s
0 0 1 AVREF ≥
2.85 V 24/fXP 48/fXP 3.0
µ
s 6.0
µ
s
Setting
prohibited
(2.4
µ
s)
Setting
prohibited
(4.8
µ
s)
0 1 0 AVREF ≥
2.7 V 48/fXP 72/fXP
Setting
prohibited
(6.0
µ
s)
Setting
prohibited
(9.0
µ
s)
Setting
prohibited
(4.8
µ
s)
Setting
prohibited
(7.2
µ
s)
0 1 1 AVREF ≥
2.7 V 88/fXP 112/fXP 11.0
µ
s 14.0
µ
s
Setting
prohibited
(8.8
µ
s)
Setting
prohibited
(11.2
µ
s)
1 0 0 AVREF ≥
4.5 V 24/fXP 72/fXP 3.0
µ
s 9.0
µ
s 2.4
µ
s 7.2
µ
s
1 0 1 AVREF ≥
2.85 V 48/fXP 96/fXP 6.0
µ
s 12.0
µ
s 4.8
µ
s 9.6
µ
s
1 1 0 AVREF ≥
2.7 V 96/fXP 144/fXP 12.0
µ
s 18.0
µ
s
Setting
prohibited
(9.6
µ
s)
Setting
prohibited
(14.4
µ
s)
1 1 1 AVREF ≥
2.7 V 176/fXP 224/fXP 22.0
µ
s 28.0
µ
s 17.2
µ
s 22.4
µ
s
ADCE Comparator operation controlNote 5
0Note 1 Stops operation of comparator
1 Enables operation of comparator
Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware
2. The conversion time refers to the total of the sampling time and the time from successively
comparing with the sampling value until the conversion res ult is output.
Notes 1. Even when the ADCE = 0 (comparator operation sto pped), the A/D co nversion oper ation starts if
the ADCS is set to 1. However, the data of the first conversion is out of the guaranteed-value
range, so ignore it.
2. Be sure to set the FR2, FR1, and FR0 in accordance with the reference voltage range and
satisfy Notes 3 and 4 below.
Example When AVREF ≥ 2.7 V
• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.
• The sampling time is 11.0
µ
s or more and the A/D conversion time is 14.0
µ
s or
more and 100
µ
s or less.
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Notes 3. Set the sampling time as follows.
• AVREF ≥ 4.5 V: 1.0
µ
s or more
• AVREF ≥ 4.0 V: 2.4
µ
s or more
• AVREF ≥ 2.85 V: 3.0
µ
s or more
• AVREF ≥ 2.7 V: 11.0
µ
s or more
4. Set the A/D conversion time as follows.
• AVREF ≥ 4.5 V: 3.0
µ
s or more and less than 100
µ
s
• AVREF ≥ 4.0 V: 4.8
µ
s or more and less than 100
µ
s
• AVREF ≥ 2.85 V: 6.0
µ
s or more and less than 100
µ
s
• AVREF ≥ 2.7 V: 14.0
µ
s or more and less than 100
µ
s
5. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1
µ
s from
operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1
µ
s or more
has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over
the first conversion result. If the ADCS is set to 1 without waiting for 1
µ
s or longer, ignore the
data of the first conversion.
Table 10-3. Settings of ADCS and ADCE
ADCS ADCE A/D Conversion Operation
0 0 Stop status (DC power consumption path does not exist)
0 1 Conversion waiting mode (only comparator consumes power)
1 × Conversion mode
Figure 10-4. Timing Chart When Comparator Is Used
ADCE
Comparator
ADCS
Conversion
operation Conversion
operation Conversion stopped
Conversion
waiting
Comparator operating
Note
Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1
µ
s or longer to stabilize the
internal circuit.
Cautions 1. The above sampling time and conversion time do not include the clock frequency error.
Select the conversion time taking the clock frequency error into consideration.
2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
4. Be sure to clear bits 6, 2, and 1 to 0.
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Preliminary User’s Manual U16898EJ2V0UD 161
(2) Analog input channel specification register (ADS)
This register specifies the input port of the analog voltage to be A/D conv erted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 10-5. Format of Analog Input Channel Specification Register (ADS)
ADS0ADS1000000
Analog input channel specification
ANI0
ANI1
ANI2
ANI3
ADS0
0
1
0
1
ADS1
0
0
1
1
01234567
ADS
Address: FF81H After reset: 00H R/W
Symbol
Caution Be sure to clear bits 2 to 7 of ADS to 0.
(3) 10-bit A/D conversion result register (ADCR)
This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each
time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is
stored in ADCR in or der starting from bit 1 of FF19H. FF1 9H indicates the higher 2 bits of the conversi on result,
and FF18H indicates the lower 8 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset input makes ADCR undefined.
Figure 10-6. Format of 10-Bit A/D Conversion Result Register (ADCR)
Symbol
Address: FF18H, FF19H After reset: Undefined R
FF19H FF18H
000000
ADCR
Caution When writing to the A/D converter mode register (ADM) and analog input channel specification
register (ADS), the contents of ADCR may become undefined. Read the conversion result
following conversion completion before writing to ADM and ADS. Using timing other than the
above may cause an incorrect conversion result to be read.
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(4) 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit
resolution result.
ADCRH can be read by an 8-bit memory manipu lation instruction.
Reset input makes ADCRH undefined.
Figure 10-7. Format of 8-Bit A/D Conversion Result Register (ADCRH)
Symbol
ADCRH 76543210
Address: FF1AH After reset: Undefined R
(5) Port mode control register 2 (PMC2) and port mode register 2 (PM2)
When using the P20/ANI0 to P23/ANI3 pins for analog input, set PMC20 to PMC23 and PM20 to PM23 to 1. At
this time, the output latches of P20 to P23 may be 0 or 1.
PMC2 and PM2 are set by a 1-bit or 8-bit memory manipulation instructio n.
Reset input clears PMC2 to 00H and sets PM2 to FFH.
Figure 10-8. Format of Port Mode Control Register 2 (PMC2)
Address: FF84H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PMC2 0 0 0 0 PMC23 PMC22 PMC21 PMC20
PMC2n Operation mode specification (n = 0 to 3)
0 Port mode
1 A/D converter mode
Figure 10-9. Format of Port Mode Register 2 (PM2)
Address: FF22H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM2 1 1 1 1 PM23 PM22 PM21 PM20
PM2n Pmn pin I/O mode selection (n = 0 to 3)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Caution When PMC20 to PMC23 are set to 1, the P20/ANI 0 to P23/ANI3 pins cannot be used as port
pins.
CHAPTER 10 A/D CONVERTER
Preliminary User’s Manual U16898EJ2V0UD 163
10.4 A/D Converter Operations
10.4.1 Basic operations of A/D converter
<1> Select one channel for A/D conversion using the analog input channel specification register (ADS).
<2> Set ADCE to 1 and wait for 1
µ
s or longer.
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set ADCS to 1 and start the conversion oper ation.
(<5> to <11> are operations p erformed by hardware.)
<5> The voltage input to the selec ted analog input channel is sampled by the sample & hold circuit.
<6> When sampling has been done for a certain time, the sample & hol d circ uit is place d in the hol d state and the
input analog voltage is held until the A/D conversion operation has ended.
<7> Bit 9 of the successive approx imation register (SAR) is set. The D/A c onverter voltage tap is set to (1/2) VDD
by the tap selector.
<8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage
comparator. If the analog i nput is greater than (1/2) AVDD, the MSB of SAR remains set to 1. If the analog
input is smaller than (1/2) VDD, the MSB is reset to 0.
<9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A
converter voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVDD
• Bit 9 = 0: (1/4) AVDD
The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.
• Analog input voltage ≥ Voltage tap: Bit 8 = 1
• Analog input voltage < Voltage tap: Bit 8 = 0
<10> Comparison is contin ued in this way up to bit 0 of SAR.
<11> Upon completi on of the comparison of 10 bits, an effective digita l result value r emains in SAR, and the r esult
value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.
<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.
To stop the A/D converter, clear ADCS to 0.
To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the
status of ADCE = 0, however, start from <2>.
Remark The following two types of A/D conversion result registers can be used.
<1> ADCR (16 bits): Stores a 10-bit A/D conversion value.
<2> ADCRH (8 bits): Stores an 8-bit A/D conversion value.
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Figure 10-10. Basic Operation of A/D Converter
Conversion time
Sampling time
Sampling A/D conversion
Undefined Conversion
result
A/D converter
operation
SAR
ADCR,
ADCRH
INTAD
Conversion
result
A/D conversion operatio ns are performed continuously until bit 7 (ADCS) of the A/D conve r ter mode register (ADM)
is reset (0) by software.
If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D
conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again
from the beginning.
Reset input makes the A/D conversion result register (ADCR, ADCRH) undefined.
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10.4.2 Input voltage and conversion results
The relationship between th e analog inp ut voltage input to the analo g input pins (ANI0 to ANI3) and th e theoretical
A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following
expression.
SAR = INT ( × 1024 + 0.5)
or
(ADCR − 0.5) × ≤ VAIN < (ADCR + 0.5) ×
where, INT( ): Function which returns integer part of value i n parentheses
V
AIN: Analog in put voltage
AVREF: AVREF pin voltage
ADCR: 10-bit A/D conversion res ult register (ADCR) value
SAR: Successive approximation register
Figure 10-11 shows the relationship between the analog input voltage and the A/D conv ersion result.
Figure 10-11. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
3
2
1
0
03FFH
03FEH
03FDH
0003H
0002H
0001H
0000H
A/D conversion result
(ADCR)
SAR ADCR
1
2048 1
1024 3
2048 2
1024 5
2048
Input voltage/AV
REF
3
1024 2043
2048 1022
1024 2045
2048 1023
1024 2047
2048
1
VAIN
AVREF
AVREF
1024 AVREF
1024
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10.4.3 A/D converter operation mode
The operation mode of the A/ D conv erter is t he s elect m ode. One c hanne l of a nal og in put is sel ected fro m ANI0 to
ANI3 by the analog input channel specificati on register (ADS) and A/D conversion is executed.
(1) A/D conversion operation
By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the
voltage, which is applied to the analog input pin specified by the analog input channel specification register
(ADS), is started.
When A/D conversion has been comp leted, the result of the A/D c onversion is stored in the A/D conver sion res ult
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has
started and when one A/D conversion has been completed, the next A/D conversion operation is immediately
started. The A/D conversion operations are repeated until new data is written to ADS.
If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and
restarted from the beginning.
If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the
conversion result is undefined.
Figure 10-12. A/D Conversion Operation
ANIn
Rewriting ADM
ADCS = 1 Rewriting ADS ADCS = 0
ANIn
ANIn ANIn ANIm
ANIn ANIm ANIm
Stopped
A/D conversion
ADCR,
ADCRH
INTAD
Conversion is stopped
Conversion result is not retained
Remarks 1. n = 0 to 3
2. m = 0 to 3
CHAPTER 10 A/D CONVERTER
Preliminary User’s Manual U16898EJ2V0UD 167
The setting method is described below.
<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.
<2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel
specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.
<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.
<4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.
<5> An interrupt request signal (INTAD) is generated.
<6> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Change the channel>
<7> Chan ge the channel using bits 1 and 0 (ADS1, ADS0) of ADS.
<8> An interrupt request signal (INTAD) is generated.
<9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).
<Complete A/D conversion>
<10> Clear ADCS to 0.
<11> Clear ADCE to 0.
Cautions 1. Make sure the period of <1> to <4> is 1
µ
s or more.
2. It is no problem if the order of <1> and <2> is reversed.
3. <1> can be omitted. However, ignore the data resulting from the first conversion after
<4> in this case.
4. The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to
FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0.
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10.5 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input
voltage per bit of digital output is called 1LSB (Least Signifi cant Bit). The percentage of 1LSB with respect to the
full scale is expressed by %FSR (Full Scale Range).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but i s determined by overall error.
(2) Overall error
This shows the maximum error value between the actual m easured value and the theoretical value.
Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of
these express the overall error.
Note that the quantization error is not includ ed in the overall error in the characteristics table.
(3) Quantization error
When analog values are converted to digital values, a ±1/2LSB error naturally occurs. In an A/D converter, an
analog input v oltage in a range of ±1/2LSB is converted to the sam e digital code, so a quantization err or cannot
be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral
linearity error, and differential linearity error in the characteristics table.
Figure 10-13. Overall Error Figure 10-14. Quantization Error
Ideal line
0……0
1……1
Digital output
Overall
error
Analog input AV
REF
0
0……0
1……1
Digital output
Quantization error
1/2LSB
1/2LSB
Analog input
0AVREF
(4) Zero-scale error
This shows the difference between the actual measuremen t value of the analog input voltage an d the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the d ifference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output
changes from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measuremen t value of the analog input voltage an d the theoretical
value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It
expresses the maximum valu e of the differe nce betwe en th e actu al m eas urement v alu e a nd the i deal str aight li ne
when the zero-scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1 LSB, this indicates the difference b etween the actual measurem ent value
and the ideal value.
Figure 10-15. Zero-Scale Error Figure 10-16. Full-Scale Error
111
011
010
001 Zero-scale error
Ideal line
000012 3 AV
REF
Digital output (Lower 3 bits)
Analog input (LSB)
111
110
101
0000
AVREF−3
Full-scale error
Ideal line
Analog input (LSB)
Digital output (Lower 3 bits)
AVREF−2AVREF−1
AV
REF
Figure 10-17. Integral Linearity Error Figure 10-18. Differential Linearity Error
0
AV
REF
Digital output
Analog input
Integral linearity
error
Ideal line
1……1
0……0
0
AV
REF
Digital output
Analog input
Differential
linearity error
1……1
0……0
Ideal 1LSB width
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversion time in the characteristics table.
(9) Sampling time
This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling
time Conversion time
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10.6 Cautions fo r A/D Converter
(1) Operating current in STOP mode
The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by
clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode regist er (ADM) to 0.
(2) Input range of ANI0 to ANI3
Observe the rated range of the ANI0 to ANI3 input vo ltage. If a voltage of AVREF or hig her and VSS or lo wer (even
in the range of absolute maximum ratings) i s input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
(3) Conflicting operations
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by
instruction upon the end of conversion
ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,
ADCRH.
<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has pr iority. ADCR, ADCRH write is not performed, nor is the conversion end i nterrupt
signal (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attention must be paid to noise input to the AVREF pin and pins ANI0 to ANI3.
Because the effect increases in proportion to the output impedance of the analog input source, it is recommended
that a capacitor be connected externally, as shown in Figure 10-20, to reduce noise.
Figure 10-19. Analog Input Pin Connection
Reference
voltage
input
C = 0.01 to 0.1 F
If there is a possibility that noise equal to or higher than AV
REF
or
equal to or lower than V
SS
may enter, clamp with a diode with a
small V
F
value (0.3 V or lower).
AV
REF
V
SS
ANI0 to ANI3
µ
CHAPTER 10 A/D CONVERTER
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(5) ANI0/P20 to ANI3/P23
<1> The analog input pins (ANI0 to ANI3) are als o used as input port pins (P20 to P23).
When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while
conversion is in progress; otherwise the conversion resolution may be degraded.
<2> If a digital puls e is applied to the pins adjac ent to the pins currently used for A/D conver sion, the expected
value of the A/D conversion may not be obtaine d due to coupling noise. Therefore, do not apply a pulse to
the pins adjacent to the pin undergoing A/D conversion.
(6) Input impedance of ANI0 to ANI3 pins
In this A/D converter, the internal sampling c apacitor is charged and sampling is performed for approx. one sixth
of the conversion time.
Since only the leakage current flows other than during sampling and the current for charging the capacitor also
flows during sampling, the input impedance fluctuates and has no meaning.
If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended
to make the output impedanc e of the analog input source 1 kΩ or lower, or attach a cap acitor of around 0.01
µ
F
to 0.1
µ
F to the ANI0 to ANI3 pins (see Figure 10-19).
(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the
pre-change analog input may be set just bef ore the ADS re write. Cauti on is therefore re quired sinc e, at this time,
when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-
change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.
Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR,
ADCRH
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion) ADIF is set but ANIm conversion
has not ended.
Remarks 1. n = 0 to 3
2. m = 0 to 3
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(8) Conversion results just after A/D conversion start
The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the
ADCS bit is set to 1 within 1
µ
s after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =
0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to the A/D converter mode register (ADM) and analog input channel
specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion
result following conversion completio n before writing to ADM and ADS. Using a timing other than the ab ove may
cause an incorrect conversion result to be read.
(10) Internal equivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 10-21. Internal Equivalent Circuit of ANIn Pin
ANIn
C
OUT
C
IN
R
IN
LSI internal
R
OUT
Table 10-4. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit
AVREF ROUT RIN COUT CIN
4.5 V ≤ AVREF ≤ 5.5 V 1 kΩ 3 kΩ 8 pF 15 pF
2.7 V ≤ AVREF < 4.5 V 1 kΩ 60 kΩ 8 pF 15 pF
Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values.
2. n = 0 to 3
3. R
OUT: Allowable signal source impedance
R
IN: Analog input equivalent resistance
CIN: Analog input equivalent capacitance
C
OUT: Internal pin capacitance
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CHAPTER 11 SERIAL INTERFACE UA RT6
11.1 Functions of Serial Interface UART6
Serial interface UART6 has the following two modes.
(1) Operation stop mode
This mode is used when serial communication is not executed and can enable a reduction in the power
consumption.
For details, see 11.4.1 Operation stop mode.
(2) Asynchronous serial interface (UART) mode
This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.
For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate
generator.
• Two-pin configuration TXD6: Transmit data output pin
R
XD6: Receive data input pin
• Data length of communication data can be selected from 7 or 8 bits.
• Dedicated internal 8-bit baud rate generator allowing any baud rate to be set
• Transmission a nd reception can be performed independently.
• Twelve operating clock inputs selectable
• MSB- or LSB-first communicat ion selectable
• Inverted trans mission operation
• Synchronous b r eak field transmission from 13 to 20 bits
• More than 11 b its can be identified for synchronous break field reception (SBF reception flag provided).
Cautions 1. The TXD6 output inversion function inverts only the transmission side and not the reception
side. To use this function, the reception side must be ready for reception of inverted data.
2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal
operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP
mode), each register stops operating, and holds the value immediately before clock supply
was stopped. The TXD6 pin also holds the value immediately before clock supply was
stopped and outputs it. However, the operation is not guaranteed after clock supply is
resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.
3. If data is continuously transmitted, the communication timing from the stop bit to the next
start bit is extended two operating clocks of the macro. However, this does not affect the
result of communication because the reception side initializes the timing when it has
detected a start bit. Do not use the continuous transmission function if the interface is
incorporated in LIN.
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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication
protocol intended to aid the cost reduction of an automotive network.
LIN communication is single-master communication, and up to 15 slaves can be connected to one
master.
The LIN slaves are used to control the switches, actuator s, and sensors, and thes e are conn ected to the
LIN master via the LIN network.
Normally, the LIN master is connected to a network such as CAN (Controller Area Network).
In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that
complies with ISO9141.
In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and
corrects the baud rate error. Therefore, c omm unication is possibl e w hen t he bau d rat e er ror in the slav e
is ±15% or less.
Figures 11-1 and 11-2 outline the transmission and reception operations of LIN.
Figure 11-1. LIN Transmission Operation
Sleep
bus
Wakeup
signal frame
8 bits
Note 1
55H
transmission Data
transmission Data
transmission Data
transmission Data
transmission
13-bit
Note 2
SBF
transmission
Note 3
Synchronous
break field Synchronous
field Identifier
field Data field Data field Checksum
field
TX6
INTST6
Notes 1. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.
2. The synchronous break field is output by hardware. The output width is equal to the bit length set by
bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 11.4.2
(2) (h) SBF transmission).
3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.
Remark The interval between each field is controlled by software.
CHAPTER 11 SERIAL INTERFACE UART6
Preliminary User’s Manual U16898EJ2V0UD 175
Figure 11-2. LIN Reception Operation
Sleep
bus
13 bitsNote 2 SF
reception ID
reception Data
reception Data
reception Data
receptionNote 5
Note 3
Note 1
Note 4
Wakeup
signal frame Synchronous
break field Synchronous
field Identifier
field Data field Data field Checksum
field
RX6
SBF
reception
Reception interrupt
(INTSR6)
Edge detection
(INTP0)
Capture timer Disable Enable
Disable Enable
Notes 1. The wakeup s ignal is det ected at the edge of the pin, an d enables UART6 an d sets the SBF recepti on
mode.
2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or
more has been detected, it is assumed that SBF reception has been completed correctly, and an
interrupt request signal is output. If an SBF with low-leve l data of less than 11 bits has bee n detected,
it is assumed that an SBF r eception error has occurre d. The interrupt request signal is not output and
the SBF reception mode is restored.
3. If SBF reception has been completed correctly, an interrupt request signal is output. This SBF
reception completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is
suppressed, and error detection processing of UART communication and data transfer of the shift
register and RXB6 is not performed. The shift register holds the reset value FFH.
4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF
reception, and then re-set baud rate generator control register 6 (BRGC6).
5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6
after reception of the checksum field and to set the SBF reception mode again.
To perform a LIN receive operation, use a configuration like the one show n in Figure 11-3.
The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt
(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external
event capture operation of 16- bit timer/event counter 00, and the baud rate error can be calculated.
The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit
timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.
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Figure 11-3. Port Configuration for LIN Reception Operation
RXD6 input
INTP0 input
TI000 input
P44/RXD6
P30/INTP0/TI000
Port input
selection control
(ISC0)
<ISC0>
0: Selects INTP0 (P30).
1: Selects RxD6 (P44).
Selector
Port mode
(PM44)
Output latch
(P44)
Port mode
(PM30)
Output latch
(P30)
Port input
selection control
(ISC1)
<ISC1>
0: Selects TI000 (P30).
1: Selects RxD6 (P44).
Selector Selector
Selector
Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11)
The peripheral functions us ed in the LIN communication operation are shown below.
<Peripheral functions used>
• External interrupt (INTP0); wakeup signal detection
Use: Detects the wa keup signal edges and detects start of communication.
• 16-bit timer/event counter 00 (TI000); baud rate error detection
Use: Detects the ba ud rate error (measures the TI000 in put edge i nterval in th e captur e mod e) by detectin g the
synchronous field (SF) length and divides it by the number of bits.
• Serial i nterface UART6
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Preliminary User’s Manual U16898EJ2V0UD 177
11.2 Configuration of Serial Interface UART6
Serial interface UART6 consists of the following hardware.
Table 11-1. Configuration of Serial Interface UART6
Item Configuration
Registers Receive buffer register 6 (RXB6)
Receive shift register 6 (RXS6)
Transmit buffer register 6 (TXB6)
Transmit shift register 6 (TXS6)
Control registers Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
Port mode register 4 (PM4)
Port register 4 (P4)
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Figure 11-4. Block Diagram of Serial Interface UART6
Internal bus
Asynchronous serial interface
control register 6 (ASICL6)
Transmit buffer register 6
(TXB6)
Transmit shift register 6
(TXS6)
TXD6/
INTP1/P43
INTST6
Baud rate
generator
Asynchronous serial interface
control register 6 (ASICL6)
Reception control Receive shift register 6
(RXS6)
Receive buffer register 6
(RXB6)
RXD6/
P44
TI000, INTP0
Note
INTSR6
Baud rate
generator
Filter
INTSRE6
Asynchronous serial
interface reception error
status register 6 (ASIS6)
Asynchronous serial
interface operation mode
register 6 (ASIM6)
Asynchronous serial
interface transmission
status register 6 (ASIF6)
Transmission control
Registers
f
XP
f
XP
/2
f
XP
/2
2
f
XP
/2
3
f
XP
/2
4
f
XP
/2
5
f
XP
/2
6
f
XP
/2
7
f
XP
/2
8
f
XP
/2
9
f
XP
/2
10
f
XP
/2
11
8
Reception unit
Transmission unit
Clock selection
register 6 (CKSR6)
Baud rate generator
control register 6
(BRGC6)
Output latch
(P43)
PM43
8
Selector
Note Selectable with input switch control register (ISC).
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Preliminary User’s Manual U16898EJ2V0UD 179
(1) Receive buffer register 6 (RXB6)
This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).
Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift
register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.
• In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
• In MSB-first reception, the receive data is transferred to bits 7 to 1 of RXB6 and the LSB of RXB6 is always 0.
If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.
RXB6 can be read by an 8-bit memory manipulati on instruction. No data can be written to this register.
Reset input sets this register to FFH.
(2) Receive shift register 6 (RXS6)
This register converts the serial data input to the RXD6 pin into para llel data.
RXS6 cannot be directly manipulat ed by a program.
(3) Transmit buffer register 6 (TXB6)
This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.
If the data length is set to 7 bits:
• In LSB-fast transmission, data is transferred to bits 0 to 6 of TXB6, and the MSB of TXB6 is not transmitted.
• In MSB-fast transmission, data is transferred to bits 7 to 1 of TXB6, and the LSB of TXB6 is not transmitted.
This register can be read or written by an 8-bit memory manip ul ation instruction.
Reset input sets this register to FFH.
Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface tran smission
status register 6 (ASIF6) is 1.
2. Do not refresh (write the same value to) TXB6 by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation
mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).
(4) Transmit shift register 6 (TXS6)
This register transmits the data transferred from TXB6 from the TXD6 pin as serial dat a. Data is transferred from
TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one
frame was transmitted for continuous transmission. Da ta is transferred fro m TXB6 and tr ansmitted from the T XD6
pin at the falling edge of the base clock.
TXS6 cannot be directly manipulated by a program.
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11.3 Registers Controlling Serial Interface UART6
Serial interface UART6 is controlled by the following nine registers.
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchronous serial interface reception error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode regi ster 4 (PM4)
• Port register 4 (P4)
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instructio n.
Reset input sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
Address: FF90H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enabling/disabling operation of internal operation clock
0
Note 1 Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuitNote 2.
1
Note 3 Enable operation of the internal operation clock
TXE6 Enabling/disabling transmission
0 Disable transmission (synchronously reset the transmission circuit).
1 Enable transmission
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when
POWER6 is cleared to 0 during a transmission 0.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the
POWER6 bit.
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Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)
RXE6 Enabling/disabling reception
0 Disable reception (synchronously reset the reception circuit).
1 Enable reception
PS61 PS60 Transmission operation Reception operation
0 0 Parity bit not output. Reception without parity
0 1 Output 0 parity. Reception as 0 parityNote
1 0 Output odd parity. Judge as odd parity.
1 1 Output even parity. Judge as even parity.
CL6 Specification of character length of transmit/receive data
0 Character length of data = 7 bits
1 Character length of data = 8 bits
SL6 Specification of number of stop bits of transmit data
0 Number of stop bits = 1
1 Number of stop bits = 2
ISRM6 Enabling/disabling occurrence of reception completion interrupt in case of error
0 “INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).
1 “INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).
Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial
interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.
Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0,
and then clear POWER6 to 0.
2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0,
and then clear POWER6 to 0.
3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If
POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.
4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.
5. Fix the PS61 and PS60 bits to 0 when mounting the device on LIN.
6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.
7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
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(2) Asynchronous serial interface reception error status register 6 (ASIS6)
This register indicates an error status on completion of reception by serial interface UART6. It includes three
error flag bits (PE6, FE6, OVE6).
This register is read-only by an 8-bit memory manipulation instruction.
Reset input clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read when this
register is read.
Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)
Address: FF93H After re set: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIS6 0 0 0 0 0 PE6 FE6 OVE6
PE6 Status flag indicating parity error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the parity of transmit data does not match the parity bit on completion of reception
FE6 Status flag indicating framing error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1 If the stop bit is not detected on completion of reception
OVE6 Status flag indicating overrun error
0 If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read
1
If receive data is set to the RXB register and the next reception operation is completed before the
data is read.
Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of
asynchronous serial interface operation mode register 6 (ASIM6).
2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop
bits.
3. If an overrun error occurs, the next receive data is not written to receive buffer register 6
(RXB6) but discarded.
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(3) Asynchronous serial interface transmission status register 6 (ASIF6)
This register indicates the status of transmission by serial interface UART6. It includes two status flag bits
(TXBF6 and TXSF6).
Transmission can be continue d without disruption even during an i nterrupt period, by writing the next data to the
TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
This register is read-only by an 8-bit memory manipulation instruction.
Reset input clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.
Figure 11-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)
Address: FF95H After re set: 00H R
Symbol 7 6 5 4 3 2 1 0
ASIF6 0 0 0 0 0 0 TXBF6 TXSF6
TXBF6 Transmit buffer data flag
0 If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)
1 If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)
TXSF6 Transmit shift register data flag
0
If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6
(TXB6) after completion of transfer
1 If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)
Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the T XBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
2. To initialize the transmission unit upon completion of continuous transmission, be sure to
check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,
and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the
transmit data cannot be guaranteed.
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(4) Clock selection register 6 (CKSR6)
This register selects the base clock of serial interface UA RT6.
CKSR6 can be set by an 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 11-8. Format of Clock Selection Register 6 (CKSR6)
Address: FF96H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60
TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection
0 0 0 0 fXP (10 MHz)
0 0 0 1 fXP/2 (5 MHz)
0 0 1 0 fXP/22 (2.5 MHz)
0 0 1 1 fXP/23 (1.25 MHz)
0 1 0 0 fXP/24 (625 kHz)
0 1 0 1 fXP/25 (312.5 kHz)
0 1 1 0 fXP/26 (156.25 kHz)
0 1 1 1 fXP/27 (78.13 kHz)
1 0 0 0 fXP/28 (39.06 kHz)
1 0 0 1 fXP/29 (19.53 kHz)
1 0 1 0 fXP/210 (9.77 kHz)
1 0 1 1 fXP/211 (4.89 kHz)
Other than above Setting prohibited
Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Remarks 1. Figures in parentheses are for operation with fXP = 10 MHz
2. f
XP: Oscillation frequency of clock to peripheral hardware
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(5) Baud rate generator control register 6 (BRGC6)
This register sets the division value of the 8-bit counter of serial interface UART6.
BRGC6 can be set by an 8-bit memory manipulation instruction.
Reset input sets this register to FFH.
Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
Figure 11-9. Format of Baud Rate Generator Control Register 6 (BRGC6)
Address: FF97H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC6 MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60
MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60 k Output clock selection of
8-bit counter
0 0 0 0 0 × × × × Setting prohibited
0 0 0 0 1 0 0 0 8 fXCLK6/8
0 0 0 0 1 0 0 1 9 fXCLK6/9
0 0 0 0 1 0 1 0 10 fXCLK6/10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1 1 1 0 0 252 fXCLK6/252
1 1 1 1 1 1 0 1 253 fXCLK6/253
1 1 1 1 1 1 1 0 254 fXCLK6/254
1 1 1 1 1 1 1 1 255 fXCLK6/255
Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the
MDL67 to MDL60 bits.
2. The baud rate is the output clock of the 8-bit counter divided by 2.
Remarks 1. f
XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register
2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)
3. ×: Don’t care
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(6) Asynchronous serial interface control register 6 (ASICL6)
This register controls the serial communication operatio ns of serial interface UART6.
ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 16H.
Caution ASICL6 can be refreshed (the same value is written) by software during a communication
operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5
(RXE6) of ASIM6 = 1). However, if the S BRT6 = 1 and SBTT = 1 are set in the refresh operation
during the SBF reception (SBRF6 = 1) or SBF transmission (between the SBTT6 setting (1) and
the INTST6 occurrence), it triggers the SBF reception and SBF transmission again, so do not
set.
Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)
Address: FF98H After re set: 16H R/WNote
Symbol <7> <6> 5 4 3 2 1 0
ASICL6 SBRF6 SBRT6 SBTT6 SBL62 SBL61 SBL60 DIR6 TXDLV6
SBRF6 SBF reception status flag
0 If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly
1 SBF reception in progress
SBRT6 SBF reception trigger
0 −
1 SBF reception trigger
SBTT6 SBF transmission trigger
0 −
1 SBF transmission trigger
Note Bit 7 is read-on ly.
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Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)
SBL62 SBL61 SBL60 SBF transmission output width control
1 0 1 SBF is output with 13-bit length.
1 1 0 SBF is output with 14-bit length.
1 1 1 SBF is output with 15-bit length.
0 0 0 SBF is output with 16-bit length.
0 0 1 SBF is output with 17-bit length.
0 1 0 SBF is output with 18-bit length.
0 1 1 SBF is output with 19-bit length.
1 0 0 SBF is output with 20-bit length.
DIR6 Specification of first bit
0 MSB
1 LSB
TXDLV6 Enabling/disabling inverting TXD6 output
0 Normal output of TXD6
1 Inverted output of T XD6
Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode again and
hold (1) the status of the SBRF6 flag.
2. Before setting the SBRT6 bit to 1, make sure that bit 7 ( POWER6) and bit 5 (RXE6) of ASIM6 =
1. Moreover, after setting the SBRT6 bit to 1, do not clear the SBRT6 bit to 0 before the SBF
reception ends (an interrupt request signal is generated).
3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF
reception has been correctly completed.
4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =
1. Moreover, after setting the SBTT6 bit to 1, do not clear the SBTT6 bit to 0 before the SBF
transmission ends (an interrupt request signal is generated).
5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of
SBF transmission.
6. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.
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(7) Input switch control register (ISC)
The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN
(Local Interconnect Network) reception. The input signal is switched by setting ISC.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 11-11. Format of Input Switch Control Register (ISC)
Address: FF8CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ISC 0 0 0 0 0 0 ISC1 ISC0
ISC1 TI000 input source selection
0 TI000 (P30)
1 RxD6 (P44)
ISC0 INTP0 input source selection
0 INTP0 (P30)
1 RxD6 (P44)
(8) Port mode register 4 (PM4)
This register sets port 4 input/output in 1-bit units.
When using the P43/TxD6/INTP1 pin for ser ial interface data output, clear PM43 to 0 and set the output latch of
P43 to 1.
When using the P44/Rx D6 pin for serial interface dat a input, set PM44 to 1. The output latch of P44 at this time
may be 0 or 1.
PM4 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to FFH.
Figure 11-12. Format of Port Mode Register 4 (PM4)
Address: FF24H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
PM4 1 1 PM45 PM44 PM43 PM42 PM41 PM40
PM4n P4n pin I/O mode selection (n = 0 to 5)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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11.4 Operation of Serial Interface UART6
Serial interface UART6 has the following two modes.
• Operation stop mode
• Asynchronous serial interface (UART) mode
11.4.1 Operation stop mode
In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In
addition, the pins can be used as ordinary port pins in this mode. To set t he oper ation stop mode, clear bits 7, 6, and
5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
(1) Register used
The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).
ASIM6 can be set by a 1-bit or 8-bit memory manipulation in struction.
Reset input sets this register to 01H.
Address: FF90H After reset: 01H R/W
Symbol <7> <6> <5> 4 3 2 1 0
ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6
POWER6 Enabling/disabling operation of internal operation clock
0
Note 1 Disable operation of the internal operation clock (fix the clock to low level) and asynchronously
reset the internal circuitNote 2.
TXE6 Enabling/disabling transmission
0 Disable transmission operation (synchronously reset the transmission circuit).
RXE6 Enabling/disabling reception
0 Disable reception (synchronously reset the reception circuit).
Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to high level when
POWER6 = 0 during a transmission.
2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.
To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.
Remark To use th e RxD6/P44 an d TxD6/INTP1/P43 pins as general-purpose port pins, see CHAPTER 4 PORT
FUNCTIONS.
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11.4.2 Asynchronous serial interface (UART) mode
In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be
performed.
A dedicated UART baud rate gener ator is incorporated, so that communic ation can be executed at a wi de range of
baud rates.
(1) Registers used
• Asynchronous serial interface operation mode register 6 (ASIM6)
• Asynchro nous serial interface recepti on error status register 6 (ASIS6)
• Asynchronous serial interface transmission status register 6 (ASIF6)
• Clock selection register 6 (CKSR6)
• Baud rate generator control register 6 (BRGC6)
• Asynchronous serial interface control register 6 (ASICL6)
• Input switch control register (ISC)
• Port mode register 4 (PM4)
• Port register 4 (P4)
The basic procedure of setting an operation in the UART mode is as follows.
<1> Set the CKSR6 register (see F igure 11-8).
<2> Set the BRGC6 register (see Figure 11-9).
<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 11-5).
<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 re gister (see Figure 11-10).
<5> Set bit 7 (POWER6) of the ASIM6 register to 1.
<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.
Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.
<7> Write data to transmit buffer register 6 (TXB6). → Data transmission is started.
Caution Take relationship with the other party of communication into consideration when setting the
port mode register and port register.
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The relationship between the register settings and pins is shown below.
Table 11-2. Relationship Between Register Settings and Pins
Pin Function POWER6 TXE6 RXE6 PM43 P43 PM44 P44 UART6
Operation TxD6/INTP1/P43 RxD6/P44
0 0 0 ×Note ×
Note ×
Note ×
Note Stop P43 P44
0 1 ×Note ×
Note 1 × Reception P43 RxD6
1 0 0 1 ×Note ×
Note Transmission TxD6 P44
1
1 1 0 1 1 ×
Transmission/
reception TxD6 RxD6
Note Can be set as port function.
Remark ×: don’t care
POWER6: Bit 7 of asynch ronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
PM4×: Port mode reg ister
P4×: Port output latch
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(2) Communication operation
(a) Format and waveform example of normal transmit/receive data
Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data.
Figure 11-13. Format of Normal UART Transmit/Receive Data
1. LSB-first transmission/reception
Start
bit Parity
bit
D0 D1 D2 D3 D4
1 data frame
Character bits
D5 D6 D7 Stop bit
2. MSB-first transmission/reception
Start
bit Parity
bit
D7 D6 D5 D4 D3
1 data frame
Character bits
D2 D1 D0 Stop bit
One data frame consists of the following bits.
• Start bit ... 1 bit
• Charact er bits ... 7 or 8 bits
• Parity bit ... Even parity, odd parity, 0 parity, or no parity
• Stop bit ... 1 or 2 bits
The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial
interface operation mode register 6 (ASIM6).
Whether data is communic ated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial
interface control register 6 (ASICL6).
Whether the TXD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.
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Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform
1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, TXD6 pin
inverted output
1 data frame
Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop
4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 Parity StopStop
5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H
1 data frame
Start D0 D1 D2 D3 D4 D5 D6 D7 Stop
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(b) Parity types and operation
The parity bit is used to d etect a bit error in communication data. Usua lly, the same type of parity bit is used
on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error
can be detected. With zero parity and no parity, an error cannot be detected.
Caution Fix the PS61 and PS60 bits to 0 when the device is incorporated in LIN.
(i) Even parity
• Transmission
Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
The value of the parity bit is as follows.
If transmit data has an odd number of bits that are “1”: 1
If transmit data has an even number of bits that are “1”: 0
• Reception
The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a
parity error occurs.
(ii) Odd parity
• Transmission
Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that
are “1” is odd.
If transmit data has an odd number of bits that are “1”: 0
If transmit data has an even number of bits that are “1”: 1
• Reception
The number of bits that are “1” in the receive data, incl uding the parity bit, is counted. If it is even, a
parity error occurs.
(iii) 0 parity
The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.
The parity bit is not detected when the data is received. Therefore, a parity error does not occur
regardless of whether the parity bit is “0” or “1”.
(iv) No parity
No parity bit is appended to the transmit data.
Reception is performed assuming that ther e is no parity bit whe n data is received. Because there is no
parity bit, a parity error does not occur.
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(c) Normal transmission
The TXD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode
register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.
Transmission can be started by writing transmit data to tr ansmit buffer register 6 (TXB6). The start bit, parity
bit, and stop bit are automatically appende d to the data.
When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,
the data is sequentially output from TXS6 to the TXD6 pin. When transmission is completed, the parity and
stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated.
Transmission is stopped until the data to be t r ansmitted next is written to TXB6.
Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt
occurs as soon as the last stop bit has been output.
Figure 11-15. Normal Transmission Completion Interrupt Request Timing
1. Stop bit length: 1
INTST6
D0Start D1 D2 D6 D7 Stop
TXD6 (output) Parity
2. Stop bit length: 2
TXD6 (output)
INTST6
D0Start D1 D2 D6 D7 Parity Stop
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(d) Continuous transmission
The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift regi ster 6
(TXS6) has started its shift operation. Cons equently, even while the INT ST6 interrupt is being serv iced after
transmission of one data frame, data can be continuously transmitted and an efficient communication rate
can be realized. In add ition, the TXB6 r egist er can be effici ently written tw ice (2 bytes) wi thout h aving to wait
for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface
transmission status register 6 (ASIF6) when the transmission completion in terrupt has occurred.
To transmit data continuously, be s ure to reference the ASIF6 register to check the transmission status and
whether the TXB6 register can be written, and then write the data.
Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register chan ge from “ 10” to “11”, and to “01”
during continuous transmission. To check the status, therefore, do not use a
combination of the TXBF6 and TXSF6 flags for judgment. Judge whether continuous
transmission is possible or not by reading only the TXBF flag.
2. When the device is incorporated in a LIN, the continuous transmission function cannot
be used. Make sure that asynchronous serial interface transmission status register 6
(ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6).
TXBF6 Writing to TXB6 Register
0 Writing enabled
1 Writing disabled
Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.
Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)
to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the
transmit data cannot be guaranteed.
The communication status can be checked us ing the TXSF6 flag.
TXSF6 Transmission Status
0 Transmission is completed.
1 Transmission is in progress.
Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure
to check that the TXSF6 flag is “0” after generation of the transmission completion
interrupt, and then execute initialization. If initialization is executed while the TXSF6
flag is “1”, the transmit data cannot be guaranteed.
2. During continuous transmission, an overrun error may occur, which means that the
next transmission was completed before execution of INTST6 interrupt servicing after
transmission of one data frame. An overrun error can be detected by developing a
program that can count the number of transmit data and by referencing the TXSF6 flag.
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Preliminary User’s Manual U16898EJ2V0UD 197
Figure 11-16 shows an example of the co ntinuous transmission processing flow.
Figure 11-16. Example of Continuous Transmission Processing Flow
Write TXB6.
Set registers.
Write TXB6.
Transfer
executed necessary
number of times? Yes
Read ASIF6
TXBF6 = 0? No
No
Yes
Transmission
completion interrupt
occurred?
Read ASIF6
TXSF6 = 0?
No
No
No
Yes
Yes
Yes
Yes
Completion of
transmission processing
Transfer
executed necessary
number of times?
Remark TXB6: Transmit buffer register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)
TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)
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Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of
ending continuous transmission.
Figure 11-17. Timing of Starting Continuous Transmission
T
X
D6 Start
INTST6
Data (1)
Data (1) Data (2) Data (3)
Data (2)Data (1) Data (3)
FF
FF
Parity Stop Data (2) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
Start Start
Note
Note W hen ASIF6 is read, there is a period in w hich T XBF6 and TXSF6 = 1, 1. Therefore, judge wh ether
writing is enabled using only the TXBF6 bit.
Remark T
XD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
CHAPTER 11 SERIAL INTERFACE UART6
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Figure 11-18. Timing of Ending Continuous Transmission
T
X
D6 Start
INTST6
Data (n − 1)
Data (n − 1) Data (n)
Data (n)Data (n − 1) FF
Parity
Stop Stop Data (n) Parity Stop
TXB6
TXS6
TXBF6
TXSF6
POWER6 or TXE6
Start
Remark TXD6: TXD6 pin (output)
INTST6: Interrupt request signal
TXB6: Transmit buffer register 6
TXS6: Transmit shift register 6
ASIF6: Asynchronous serial interface transmission status register 6
TXBF6: Bit 1 of ASIF6
TXSF6: Bit 0 of ASIF6
POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)
TXE6: Bit 6 of asynchronous serial interface operation mod e register (ASIM6)
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(e) Normal reception
Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial
interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is
detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the
RXD6 pin input is sampled again ( in Figure 11-19). If the RXD6 pin is low level at this time, it is recognized
as a start bit.
When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift
register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt
(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun
error (OVE6) occurs, however, the receive data is not written to RXB6.
Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception
position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception.
Figure 11-19. Reception Completion Interrupt Request Timing
RXD6 (input)
INTSR6
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity
RXB6
Stop
Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.
Otherwise, an overrun error will occur when the next data is received, and the reception
error status will persist.
2. Reception is always performed with the “number of stop bits = 1”. The second stop bit
is ignored.
3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)
before reading RXB6.
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Preliminary User’s Manual U16898EJ2V0UD 201
(f) Reception error
Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error
flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data
reception, a reception error interrupt request (INTSR6/INTSRE6) is ge nerated.
Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception
error interrupt servicing (INTSR6/INTSRE6) (see Figure 11-6).
The contents of ASIS6 are reset to 0 when ASIS6 is read.
Table 11-3. Cause of Reception Error
Reception Error Cause
Parity error The parity specified for transmission does not match the parity of the receive data.
Framing error Stop bit is not detected.
Overrun error Reception of the next data is completed before data is read from receive buffer
register 6 (RXB6).
The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt
(INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to
0.
Figure 11-20. Reception Error Interrupt
1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are
separated)
(a) No error during reception (b) Error during reception
INTSR6
INTSRE6
INTSR6
INTSRE6
2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)
(a) No error during reception (b) Error during reception
INTSRE6
INTSR6
INTSRE6
INTSR6
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(g) Noise filter of receive data
The RXD6 signal is sampled with the base clock output by the prescaler block.
If two sampled values are the same, the output of the match detector changes, and the data is sampled as
input data.
Because the circuit is configur ed as shown in Figure 1 1-21, the internal processing of the r eception o perat ion
is delayed by two clocks from the external signal status.
Figure 11-21. Noise Filter Circuit
Internal signal B
Internal signal A
Match detector
In
Base clock
R
X
D6/P44 QIn
LD_EN
Q
(h) SBF transmission
When the device is incor porated in LIN, the SBF (Synchronous Break Field) transmission co ntrol function is
used for transmission. For the transmission operation of LIN, see Figure 11-1 LIN Transmission
Operation.
When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TxD6 pin
outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the tran smission enabled status is entered,
and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6
(ASICL6) to 1.
Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following
the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and
SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.
Transmission is suspended u ntil the data to be transmitted next is written to transmit buffer register 6 (TXB6),
or until SBTT6 is set to 1.
Figure 11-22. SBF Transmission
TXD6
INTST6
1 2 3 4 5 6 7 8 9 10 11 12 13 Stop
SBTT6
Remark TXD6: TXD6 pin (output)
INTST6: Transmission completion interrupt request
SBTT6: Bit 5 of asynch ronous serial interface control register 6 (ASICL6)
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(i) SBF reception
When the device is incorporated in LIN, the SBF (Synchronous Break Field) reception control function is
used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception Operation .
Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6
(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SB RT6)
of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,
the RXD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable
status.
When the start bit has been detected, reception is started, and serial data is sequentially stored in the
receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of S BF is
11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At
this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of
errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status
register 6 (ASIS6)) is suppressed, and error detection processing of UART communicati on is not performed.
In addition, data transfer betw een receive shift register 6 (RXS6) and rec eive buffer register 6 (RXB6) is not
performed, and the reset valu e of FFH is r etained. If the wi dth of SBF is 10 bits or l ess, an interr upt doe s not
occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In
this case, the SBRF6 and SBRT6 bits are not cleared.
Figure 11-23. SBF Reception
1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)
RXD6
SBRT6
/SBRF6
INTSR6
1234567891011
2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)
R
X
D6
SBRT6
/SBRF6
INTSR6
12345678910
“0”
Remark RXD6: RXD6 pin (input)
SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)
SBRF6: Bit 7 of ASICL6
INTSR6: Reception completion interrupt request
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11.4.3 Dedicated baud rate generator
The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and
generates a serial clock for transmission/reception of UART 6.
Separate 8-bit counters are provided for transmission and reception.
(1) Configuration of baud rate generator
• Base clock
The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to
each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is
1. This clock is called the base clock and its frequency is called fXCLK6. The base clock is fixed to low level
when POWER6 = 0.
• Transmission counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when POWER6 = 1 and TXE6 = 1.
The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).
If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been
completely transmitted. If there is no d ata to be tra nsmitted next, the cou nter is not cleare d to 0 and continue s
counting until POWER6 or TXE6 is cleared to 0.
• Reception counter
This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial
interface operation mode register 6 (ASIM6) is 0.
It starts counting when the start bit has been detected.
The counter stops operation after one frame has been received, until the next start bit is detected.
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Figure 11-24. Configuration of Baud Rate Generator
Selector
POWER6
8-bit counter
Match detector Baud rate
Baud rate generator
BRGC6: MDL67 to MDL60
1/2
POWER6, TXE6 (or RXE6)
CKSR6: TPS63 to TPS60
f
XP
f
XP
/2
f
XP
/2
2
f
XP
/2
3
f
XP
/2
4
f
XP
/2
5
f
XP
/2
6
f
XP
/2
7
f
XP
/2
8
f
XP
/2
9
f
XP
/2
10
f
XP
/2
11
fXCLK6
Remark POWER6: Bit 7 of asynch ronous serial interface operation mode register 6 (ASIM6)
TXE6: Bit 6 of ASIM6
RXE6: Bit 5 of ASIM6
CKSR6: Clock selection register 6
BRGC6: Baud rate generator control register 6
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(2) Generation of serial clock
A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control
register 6 (BRGC6).
Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.
Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.
(a) Baud rate
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)
(b) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
Cautions 1. Keep the baud rate error during transmission to within the permissible error range at
the reception destination.
2. Make sure that the baud rate error during reception satisfies the range shown in (4)
Permissible baud rate range during reception.
Example: Frequency of base clock = 10 MHz = 10,000,000 Hz
Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)
Target baud rate = 153600 bps
Baud rate = 10 M/(2 × 33)
= 10000000/(2 × 33) = 151,515 [bps]
Error = (151515/153 600 − 1) × 100
= −1.357 [%]
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)
fXCLK6
2 × k
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(3) Example of setting baud rate
Table 11-4. Set Data of Baud Rate Generator
fXP = 10.0 MHz fXP = 8.38 MHz fXP = 4.19 MHz
Baud Rate
[bps] TPS63 to
TPS60 k Calculated
Value ERR[%] TPS63 to
TPS60 k Calculated
Value ERR[%] TPS63 to
TPS60 k Calculated
Value ERR[%]
600 6H 130 601 0.16 6H 109 601 0.11 5H 109 601 0.11
1200 5H 130 1202 0.16 5H 109 1201 0.11 4H 109 1201 0.11
2400 4H 130 2404 0.16 4H 109 2403 0.11 3H 109 2403 0.11
4800 3H 130 4808 0.16 3H 109 4805 0.11 2H 109 4805 0.11
9600 2H 130 9615 0.16 2H 109 9610 0.11 1H 109 9610 0.11
10400 2H 120 10417 0.16 2H 101 10371 0.28 1H 101 10475 −0.28
19200 1H 130 19231 0.16 1H 109 19220 0.11 0H 109 19220 0.11
31250 1H 80 31250 0.00 0H 134 31268 0.06 0H 67 31268 0.06
38400 0H 130 38462 0.16 0H 109 38440 0.11 0H 55 38090 −0.80
76800 0H 65 76923 0.16 0H 55 76182 −0.80 0H 27 77693 1.03
115200 0H 43 116279 0.94 0H 36 116389 1.03 0H 18 116389 1.03
153600 0H 33 151515 −1.36 0H 27 155185 1.03 0H 14 149643 −2.58
230400 0H 22 227272 −1.36 0H 18 232778 1.03 0H 9 232778 1.03
Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKS R6) (setting of base clock (fXCLK6))
k: Value set by MDL67 to MDL60 bits of baud rate generator control register 6
(BRGC6) (k = 8, 9, 10, ..., 255)
f
XP: Oscillation frequency of clock to peripheral hardware
ERR: Baud rate error
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(4) Permissible baud rate range during reception
The permissible error from the baud rate at the transmission destination during reception is shown below.
Caution Make sure that the baud rate error during reception is within the permissible error range, by
using the calculation expression shown below.
Figure 11-25. Permissible Baud Rate Range During Reception
FL 1 data frame (11 × FL)
FLmin
FLmax
Data frame length
of UART6 Start bit Bit 0 Bit 1 Bit 7 Parity bit
Minimum permissible
data frame length
Maximum permissible
data frame length
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit
Latch timing
Stop bit
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
As shown in Figure 11-25, the latch timing of the receive data is determined by the counter set by baud rate
generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this
latch timing, the data can be correctly received.
Assuming that 11-bit data is received, the theoretical values can be calculated as follows.
FL = (Brate)−1
Brate: Baud rate of UART6
k: Set value of BRGC6
FL: 1-bit data length
Margin of l atch timing: 2 clocks
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Minimum permissibl e data frame length: FLmin = 11 × FL − × FL = FL
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
BRmax = (FLmin/11)−1 = Brate
Similarly, the maximum permissible data fr ame length can be calculated as follows.
10 k + 2 21k − 2
11 2 × k 2 × k
FLmax = FL × 11
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
BRmin = (FLmax/11)−1 = Brate
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Table 11-5. Maximum/Minimum Permissible Baud Rate Error
Division Ratio (k) Maximum Permissible Baud Rate Error Minimum Permissible Baud Rate Error
8 +3.53% −3.61%
20 +4.26% −4.31%
50 +4.56% −4.58%
100 +4.66% −4.67%
255 +4.72% −4.73%
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
frequency, and division ratio ( k). The high er t he inp ut clock frequency an d the higher th e division
ratio (k), the higher the permissible error.
2. k: Set value of BRGC6
22k
21k + 2
× FLmax = 11 × FL − × FL = FL
21k – 2
20k
20k
21k − 2
k − 2
2k 21k + 2
2k
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(5) Data frame length during continuous transmission
When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by
two clocks of base clock from the normal value. However, the result of communication is not affected because
the timing is initialized on the reception side when the start bit is detected.
Figure 11-26. Data Frame Length During Continuous Transmission
Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit
FL
1 data frame
FL FL FL FL FLFLFLstp
Start bit of
second byte
Start bit Bit 0
Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following
expression is satisfied.
FLstp = FL + 2/fXCLK6
Therefore, the data frame length during continuous transmission is:
Data frame length = 11 × FL + 2/fXCLK6
Preliminary User’s Manual U16898EJ2V0UD 211
CHAPTER 12 INTERRUPT FUNCTIONS
12.1 Interrupt Function Types
All interrupts are controlled as maskable interrupts.
• Maskable interrupts
These interrupts undergo mask control. If two or more interrupt requests are simultaneously generated, each
interrupt has a predetermined priority as shown in Table 12-1.
A standby release signal is generated.
There are nine internal sources and four external sources of maskable interrupts.
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12.2 Interrupt Sources and Configuration
There are a total of 13 interrupt sources, and up to four reset sources (see Table 12-1).
Table 12-1. Interrupt Sources
Interrupt Source Interrupt Type PriorityNote 1
Name Trigger
Internal/
External Vector Table
Address Basic
Configuration
TypeNote 2
1 INTLVI Low-voltage detectionNote 3 Internal 0006H (A)
2 INTP0 0008H
3 INTP1
Pin input edge detection External
000AH
(B)
4 INTTMH1 Match between TMH1 and CMP01
(when compare register is specified) 000CH
5 INTTM000 Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection (when
capture register is specified)
000EH
6 INTTM010 Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection (when
capture register is specified)
0010H
7 INTAD End of A/D conversion
Internal
0012H
(A)
8 INTP2 0016H
9 INTP3
Pin input edge detection External
0018H
(B)
10 INTTM80 Match between TM80 and CR80 001AH
11 INTSRE6 UART6 reception error occurrence 001CH
12 INTSR6 End of UART6 reception 001EH
Maskable
13 INTST6 End of UART6 transmission
Internal
0020H
(A)
RESET Reset input
POC Power-on-clear
LVI Low-voltage detectionNote 4
Reset −
WDT WDT overflow
− 0000H −
Notes 1. Priority is the priority order when several maskable interrupt requests are generated at the same time. 1
is the highest and 13 is the lowest.
2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 12-1.
3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected.
4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected.
Caution No interrupt sources correspond to the vector table address 0014H.
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Figure 12-1. Basic Configuration of Interrupt Function
(A) Internal maskable interrupt
MK
IF
IE
Internal bus
Interrupt request
Vector table
address generator
Standby release signal
(B) External maskable interrupt
Internal bus
External interrupt mode
register (INTM0, INTM1) MK
IF
IE
Vector table
address generator
Standby
release signal
Edge
detector
Interrupt
request
IF: Interrupt request flag
IE: Interrupt enable flag
MK: Interrupt mask flag
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12.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following four types of registers.
• Interrupt request flag registers (IF0, IF1)
• Interrupt mask flag registers (MK0, MK1)
• External interrupt mode registers (INTM0, INTM1)
• Program status word (PSW)
Table 12-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Table 12-2. Interrupt Request Signals and Corresponding Flags
Interrupt Request Signal Interrupt Request Flag Interrupt Mask Flag
INTLVI
INTP0
INTP1
INTTMH1
INTTM000
INTTM010
INTAD
INTP2
INTP3
INTTM80
INTSRE6
INTSR6
INTST6
LVIIF
PIF0
PIF1
TMIFH1
TMIF000
TMIF010
ADIF
PIF2
PIF3
TMIF80
SREIF6
SRIF6
STIF6
LVIMK
PMK0
PMK1
TMMKH1
TMMK000
TMMK010
ADMK
PMK2
PMK3
TMMK80
SREMK6
SRMK6
STMK6
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(1) Interrupt request flag registers (IF0, IF1)
An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the
instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is
acknowledged or when a reset signal is input.
IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears IF0 and IF1 to 00H.
Figure 12-2. Format of Interrupt Request Flag Registers (IF0, IF1)
Address: FFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> 0
IF0 ADIF TMIF010 TMIF000 TMIFH1 PIF1 PIF0 LVIIF 0
Address: FFE1H After reset: 00H R/W
Symbol 7 <6> <5> <4> <3> <2> <1> 0
IF1 0 STIF6 SRIF6 SREIF6 TMIF80 PIF3 PIF2 0
××IF× Interrupt request flag
0 No interrupt request signal has been issued.
1 An interrupt request signal has been issued; an interrupt request status.
Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port function, an
interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before
using the output mode.
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(2) Interrupt mask flag registers (MK0, MK1)
The interrupt mask flag is used to enable and disable the corresponding maskable interrupts.
MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.
Reset input sets MK0 and MK1 to FFH.
Figure 12-3. Format of Interrupt Mask Flag Registers (MK0, MK1)
Address: FFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> 0
MK0 ADMK TMMK010 TMMK000 TMMKH1 PMK1 PMK0 LVIMK 1
Address: FFE5H After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> 0
MK1 1 STMK6 SRMK6 SREMK6 TMMK80 PMK3 PMK2 1
××MK× Interrupt servicing control
0 Enables interrupt servicing.
1 Disables interrupt servicing.
Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs,
when the output level is changed by specifying the output mode of the port function, an
interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before
using the output mode.
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(3) External interrupt mode register 0 (INTM0)
This register is used to set the valid edge of INTP0 to INTP2.
INTM0 is set with an 8-bit memory manipulation instruction.
Reset input clears INTM0 to 00H.
Figure 12-4. Format of External Interrupt Mode Register 0 (INTM0)
Address: FFECH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
INTM0 ES21 ES20 ES11 ES10 ES01 ES00 0 0
ES21 ES20 INTP2 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both rising and falling edges
ES11 ES10 INTP1 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both rising and falling edges
ES01 ES00 INTP0 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both rising and falling edges
Cautions 1. Be sure to clear bits 0 and 1 to 0.
2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag
(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt
request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will
enable interrupts.
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(4) External interrupt mode register 1 (INTM1)
INTM1 is used to specify the valid edge for INTP3.
INTM1 is set with an 8-bit memory manipulation instruction.
Reset input clears INTM1 to 00H.
Figure 12-5. Format of External Interrupt Mode Register 1 (INTM1)
Address: FFEDH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
INTM1 0 0 0 0 0 0 ES31 ES30
ES31 ES30 INTP3 valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both rising and falling edges
Cautions 1. Be sure to clear bits 2 to 7 to 0.
2. Before setting INTM1, set PMK3 to 1 to disable interrupts.
To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.
(5) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.
PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and
dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically
saved to a stack, and the IE flag is reset to 0.
Reset input sets PSW to 02H.
Figure 12-6. Program Status Word (PSW) Configuration
IE Z 0 AC 0 0 1 CYPSW
Symbol After reset
02H
76543210
IE
0
1
Disabled
Enabled
Whether to enable/disable interrupt acknowledgment
Used in the execution of ordinary instructions
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12.4 Interrupt Servicing Operation
12.4.1 Maskable interrupt request acknowledgment operation
A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the
corresponding interrupt mask flag is cleared to 0. A vectored interrupt request is acknowledged in the interrupt
enabled status (when the IE flag is set to 1).
The time required to start the interrupt servicing after a maskable interrupt request has been generated is shown in
Table 12-3.
See Figures 12-8 and 12-9 for the interrupt request acknowledgment timing.
Table 12-3. Time from Generation of Maskable Interrupt Request to Servicing
Minimum Time Maximum TimeNote
9 clocks 19 clocks
Note The wait time is maximum when an interrupt
request is generated immediately before BT and
BF instructions.
Remark 1 clock: (fCPU: CPU clock)
When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting
from the interrupt request assigned the highest priority.
A pending interrupt is acknowledged when a status in which it can be acknowledged is set.
Figure 12-7 shows the algorithm of interrupt request acknowledgment.
When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in
that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to
the PC, and execution branches.
To return from interrupt servicing, use the RETI instruction.
1
fCPU
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Figure 12-7. Interrupt Request Acknowledgment Processing Algorithm
Start
××IF = 1?
××MK = 0?
IE = 1?
Vectored interrupt
servicing
Yes (Interrupt request generated)
Yes
Yes
No
No
No
Interrupt request pending
Interrupt request pending
××IF: Interrupt request flag
××MK: Interrupt mask flag
IE: Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)
Figure 12-8. Interrupt Request Acknowledgment Timing (Example of MOV A, r)
Clock
CPU
Interrupt
MOV A, r
Saving PSW and PC, jump
to interrupt servicing
8 clocks
Interrupt servicing program
If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,
the interrupt is acknowledged after the instruction under execution is complete. Figure 12-8 shows an example of the
interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is
executed for 4 clocks, if an interrupt occurs for 3 clocks after the execution starts, the interrupt acknowledgment
processing is performed after the MOV A, r instruction is executed.
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Figure 12-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last
Clock During Instruction Execution)
Saving PSW and PC, jump
to interrupt servicing
8 clocks
Interrupt
servicing
program
Clock
CPU
Interrupt
NOP MOV A, r
If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing
starts after the next instruction is executed.
Figure 12-9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is
set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is
executed, and then the interrupt acknowledgment processing is performed.
Caution Interrupt requests will be held pending while the interrupt request flag registers (IF0, IF1) or
interrupt mask flag registers (MK0, MK1) are being accessed.
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12.4.2 Multiple interrupt servicing
Multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is being serviced can be
performed using a priority order system. When two or more interrupts are generated at once, interrupt servicing is
performed according to the priority assigned to each interrupt request in advance (see Table 12-1).
Figure 12-10. Example of Multiple Interrupts
Example 1. Multiple interrupts are acknowledged
INTyy
EI
Main processing
EI
INTyy servicingINTxx servicing
RETI
IE = 0
INTxx
RETI
IE = 0
During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.
The EI instruction is issued before each interrupt request acknowledgment, and the interrupt request acknowledgment
enable state is set.
Example 2. Multiple interrupts are not generated because interrupts are not enabled
INTyy
EI
Main processing
RETI
INTyy servicingINTxx servicing
IE = 0
INTxx
RETI
INTyy is held pending
IE = 0
Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request
INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and
acknowledged after the INTxx servicing is performed.
IE = 0: Interrupt request acknowledgment disabled
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12.4.3 Interrupt request pending
Some instructions may keep pending the acknowledgment of an instruction request until the completion of the
execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated
during the execution. The following shows such instructions (interrupt request pending instruction).
• Manipulation instruction for interrupt request flag registers (IF0, IF1)
• Manipulation instruction for interrupt mask flag registers (MK0, MK1)
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CHAPTER 13 STANDBY FUNCTION
13.1 Standby Function and Configuration
13.1.1 Standby function
Table 13-1. Relationship Between Operation Clocks in Each Operation Status
Low-Speed Ring-OSC Oscillator
Note 2
Status
Operation Mode
Note 1
LSRSTOP = 0 LSRSTOP = 1
System Clock Clock Supplied to
Peripheral
Hardware
Reset Stopped
STOP
Stopped Stopped
HALT
Oscillating OscillatingNote 3 Stopped
Oscillating Oscillating
Notes 1. When “Cannot be stopped” is selected for low-speed Ring-OSC by the option byte.
2. When it is selected that th e low-speed Ring- OSC oscillator “can be stoppe d by software”, oscillatio n of
the low-speed Ring-OSC osci llator can be stopped by LSRSTOP.
3. If the operating clock of the watchdog timer is the low-speed Ring-OSC clock, the watchdog timer is
stopped.
Caution The LSRSTOP setting is valid only when “Can be stopped by software” is set for the low-speed
Ring-OSC oscillator by the option byte.
Remark LSRSTOP: Bit 0 of the low-speed Ring-OSC mode register (LSRCM)
The standby function is designed to reduce the operating current of the system. The following two modes are
available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
Oscillation of the system clock oscillator continues. If the low-speed Ring-OSC oscillator is operating before
the HALT mode is set, oscillation of the clock of the low-speed Ring-OSC oscillator continues (refer to Table
13-1. Oscillation of the low-speed Ring-OSC clock (whether it cannot be stopped or can be stopped by
software) is set by the option byte). In this mode, the operating current is not decreased as much as in the
STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request
generation and carrying out in termittent operations.
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(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops,
stopping the whole system, thereby considerably reducing the CPU operating current.
Because this mode can be cleared by an interrupt request, it ena bles intermittent operations to be carried out.
However, select the HALT mode if processing must be immediately started by an interrupt request when the
operation stop timeNote is generated after the STOP mode is released (because an additional wait time for
stabilizing oscillation elapses when crystal/ceramic oscillation is used).
Note The operation stop time is 17
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
In either of these two modes, all the content s of registers, flags and data memory just before the standby mode is
set are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before
executing STOP instruction (except the peripheral hardware that operates on the low-speed
Ring-OSC clock).
2. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D
converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute
the HALT or STOP instruction.
3. If the low-speed Ring-OSC oscillator is operating before the STOP mode is set, oscillation of
the low-speed Ring-OSC clock cannot be stopped in the STOP mode (refer to Table 13-1).
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13.1.2 Registers used during standby
The oscillation stabiliz ation ti me after the st andby mode is release d is controlle d by the oscillation stabilizatio n time
select register (OSTS).
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS.
(1) Oscillation stabilization time select register (OSTS)
This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the
STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscill ation clock is
selected as the system clock and after the STOP mode is released. If the high-speed Ring-OSC oscillator or
external clock input is selected as the system clock source, no wait time elapses.
The system clock oscillator and the oscillation stabilization time that elaps es after power application or release
of reset are selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
OSTS is set by using the 8-bit memory manipulation instruction.
Figure 13-1. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFF4H After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 0 OSTS1 OSTS0
OSTS1 OSTS0 Selection of oscillation stabilization time
0 0 210/fX (102.4
µ
s)
0 1 212/fX (409.6
µ
s)
1 0 215/fX (3.27 ms)
1 1 217/fX (13.1 ms)
Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.
Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set
by OSTS
2. The wait time after the STOP mode is released does not include the time from the
release of the STOP mode to the start of clock oscillation (“a” in the figure below),
regardless of whether STOP mode was released by reset input or interrupt generation.
STOP mode is released
Voltage
waveform
of X1 pin a
3. The oscillation stabilization time that elapses on power application or after release of
reset is selected by the option byte. For details, refer to CHAPTER 17 OPTION BYTE.
Remarks 1. ( ): fX = 10 MHz
2. Determine the oscillation stabilization time of the resonator by checking the characteristics of
the resonator to be used.
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13.2 Standby Function Operation
13.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction.
The operating statuses in the HALT mode ar e shown below.
Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby
mode is immediately cleared if set.
Table 13-2. Operating Statuses in HALT Mode
Low-Speed Ring-OSC Can Be StoppedNote
Setting of HALT Mode
Item
Low-Speed Ring-OSC
Cannot Be StoppedNote When Low-Speed Ring-
OSC Oscillation Continues When Low-Speed Ring-
OSC Oscillation Stops
System clock Clock supply to CPU is stopped.
CPU Operation stops.
Port (latch) Holds status before HALT mode was set.
16-bit timer/event counter 00 Operable
8-bit timer 80 Operable
Sets count clock to fXP to fXP/212 Operable
8-bit timer
H1 Sets count clock to fRL/27 Operable Operable Operation stops.
System clock selected as
operating clock Setting prohibited Operation stops.
Watchdog
timer
“Low-speed Ring-OSC clock”
selected as operating clock Operable (Operation
continues.) Operation stops.
A/D converter Operable
Serial interface UART6 Operable
Power-on-clear circuit Always operates.
Low-voltage detector Operable
External interrupt Operable
Note “Cannot be stopped” or “Stopped by software” is selected for low-speed Ring-OSC by the option byte (for the
option byte, see CHAPTER 17 OPTION BYTE).
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(2) HALT mode release
The HALT mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt
acknowledgement is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgement is
disabled, the next address instruction is executed.
Figure 13-2. HALT Mode Release by Interrupt Request Generation
HALT
instruction Wait
Wait Operating modeHALT modeOperating mode
Oscillation
System clock
oscillation
Status of CPU
Standby
release signal
Interrupt
request
Remarks 1. The broken lines indicate the case when the interrupt request which has released the
standby mode is acknowledged.
2. The wait time is as follows:
• When vectored interrupt ser v icing is carried out: 11 to 13 clocks
• When vectored interrupt ser v icing is not carried out: 3 to 5 clocks
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(b) Release by reset input
When the reset signal is input, HALT mode is released, and then, as in the case with a normal reset
operation, the program is exe cuted after branching to the reset vector address.
Figure 13-3. HALT Mode Release by Reset Input
(1) When CPU clock is high-speed Ring-OSC clock or external input clock
HALT
instruction
Reset signal
System clock
oscillation
Operation
mode HALT mode Reset
period Operation mode
Oscillates Oscillation stops Oscillates
CPU status Operation
stopsNote
Note Operation is stopp ed (277
µ
s (MIN.), 544
µ
s (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) When CPU clock is crystal/ceramic oscillation clock
HALT
instruction
Reset signal
System clock
oscillation
Operation
mode HALT mode Reset
period Operation
stops
Note
Oscillation
stabilization waits
Oscillates Oscillation stops Oscillates
CPU status
Oscillation stabilization time
(2
10
/f
X
to 2
17
/f
X
)
Operation
mode
Note Operation is stopp ed (276
µ
s (MIN.), 544
µ
s (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark f
X: System clock oscillation frequency
Table 13-3. Operation in Response to Interrupt Request in HALT Mode
Release Source MK×× IE Operation
0 0 Next address instruction execution
0 1 Interrupt servicing execution
Maskable interrupt request
1 × HALT mode held
Reset input − × Reset processing
×: don’t care
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13.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction.
Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the standby
mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is
restored after the STOP instruction is executed and then the operation is stopped for 34
µ
s
(TYP.) (after an additional wait time for stabilizing the oscillation set by the oscillation
stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is
used).
The operating statuses in the STOP mode are shown below.
Table 13-4. Operating Statuses in STOP Mode
Low-Speed Ring-OSC Can Be StoppedNote
Setting of HALT Mode
Item
Low-Speed Ring-OSC
Cannot Be StoppedNote When Low-Speed Ring-
OSC Oscillation Continues When Low-Speed Ring-
OSC Oscillation Stops
System clock Oscillation stops.
CPU Operation stops.
Port (latch) Holds status before STOP mode is set.
16-bit timer/event counter 00 Operation stops.
8-bit timer 80 Operation stops.
Sets count clock to fXP to fXP/212 Operation stops.
8-bit timer
H1 Sets count clock to fRL/27 Operable Operable Operation stops.
“Clock to peripheral hardware”
selected as operating clock Setting prohibited Operation stops.
Watchdog
timer
“Low-speed Ring-OSC clock”
selected as operating clock Operable (Operation
continues.) Operation stops.
A/D converter Operation stops.
Serial interface UART6 Operation stops.
Power-on-clear circuit Always operates.
Low-voltage detector Operable
External interrupt Operation stops.
Note “Cannot be stopped” or “Stopped by software” is selected for low-speed Ring-OSC by the option byte (for the
option byte, see CHAPTER 17 OPTION BYTE).
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(2) STOP mode release
Figure 13-4. Operation Timing When STOP Mode Is Released
<1> If high-speed Ring-OSC clock or external input clock is selected as system clock to be supplied
System clock
oscillation
CPU clock
STOP mode
is released.
STOP mode
High-speedRing-OSC clock or external clock input
Operation
stops
Note
.
<2> If crystal/ceramic oscillation clock is selected as system clock to be supplied
System clock
oscillation
CPU clock
STOP mode
is released.
STOP mode
HALT status
(oscillation stabilization time set by OSTS)
Crystal/ceramic oscillation clock
Operation
stops
Note
.
Note The operation stop time is 17
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
The STOP mode can be released by the followin g two sources.
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(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is
carried out. If interrupt acknowledgment is disabled, the next address instruction is ex ecuted.
Figure 13-5. STOP Mode Release by Interrupt Request Generation
(1) If CPU clock is high-speed Ring-OSC clock or external input clock
Operation
mode Operation mode
Oscillation
STOP
instruction
STOP mode
Standby release
signal
System clock
oscillation
CPU status
Oscillation Oscillation stops.
Operation
stopsNote.
Interrupt
request
(2) If CPU clock is crystal/ceramic oscillation clock
Waiting for stabilization
of oscillation
Oscillation stabilization time
(set by OSTS)
(HALT mode status)
Operation
mode Operation
mode
Oscillation
STOP
instruction
STOP mode
Standby release
signal
System clock
CPU status
Oscillation Oscillation stops.
Operation
stopsNote.
Interrupt
request
Note The operation stop time is 17
µ
s (MIN.), 34
µ
s (TYP.), and 67
µ
s (MAX.).
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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(b) Release by reset input
When the reset signal is input, STOP mode is released and a reset operation is performed after the
oscillation stabilization time has elapsed.
Figure 13-6. STOP Mode Release by Reset Input
(1) If CPU clock is high-speed Ring-OSC clock or external input clock
STOP
instruction
Reset signal
System clock
oscillation
Operation
mode STOP mode Reset
period Operation mode
Oscillation Oscillation stops. Oscillation
CPU status Operation
stopsNote.
Note Operatio n is stopped (277
µ
s (MIN.), 544
µ
s (TYP.), 1.075 ms (MAX.)) because the option byte is
referenced.
(2) If CPU clock is crystal/ceramic oscillation clock
STOP
instruction
Reset signal
System clock
oscillation
Operation
mode STOP mode Reset
period Operation
stops
Note
.Operation
mode
Oscillation Oscillation stops. Oscillation
CPU status
Oscillation stabilization time
(2
10
/f
X
to 2
17
/f
X
)
Oscillation
stabilization waits
Note Operatio n is stopped (276
µ
s (MIN.), 544
µ
s (TYP.), 1.074 ms (MAX.)) because the option byte is
referenced.
Remark f
X: System clock oscillation frequency
Table 13-5. Operation in Response to Interrupt Request in STOP Mode
Release Source MK×× IE Operation
0 0 Next address instruction execution
0 1 Interrupt servicing execution
Maskable interrupt request
1 × STOP mode held
Reset input − × Reset processing
×: don’t care
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CHAPTER 14 RESET FUNCTION
The following four operations are ava ilable to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit
(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)
External and internal resets h ave no functional differences . In both cases, program execution starts at the addr ess
at 0000H and 0001H when the reset signal is input.
A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI
circuit voltage detection, and each item of hardware is set to the status shown in Table 14-1. Each pin is high
impedance during r eset input or during the oscillati on stabili zation time j ust after reset release, exc ept for P130, wh ich
is low-level output.
When a high level is input to the RESET pin, the reset is released and program execution starts using the CPU
clock after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization time
elapses if crystal/ceramic oscillation is selected). A reset generated by the watchdog timer source is automatically
released after the reset, and program ex ecution starts using the CPU cl ock after referencing the option byte (after the
option byte is referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected).
(see Figures 14-2 to 14-4). Reset by POC and LVI circuit power s upply detection is auto matically released when VDD
> VPOC or VDD > VLVI after the reset, and program execution starts using the CPU clock after referencing the option
byte (after the option byte is referenced a nd the clock oscillat ion stabilizati on time elapse s if crystal/ceramic oscillatio n
is selected) (see CHAPTER 15 POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR).
Cautions 1. For an external reset, input a low level for 2
µ
s or more to the RESET pin.
2. During reset input, the system clock and low-speed Ring-OSC clock stop oscillating.
3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KA1+ is reset if a low
level is input to the RESET pin after reset is released by the POC circuit and before the option
byte is referenced again. The reset status is retained until a high level is input to the RESET
pin.
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD 235
Figure 14-1. Block Diagram of Reset Function
RESET
LVIRFWDTRF
Reset control flag register (RESF)
Internal bus
Reset signal of
watchdog timer
Reset signal of
power-on-clear circuit
Reset signal of
low-voltage detector Reset signal
Reset signal to
LVIM/LVIS register
Clear
Set ClearSet
Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.
Remarks 1. LVIM: Low-voltage detect regi ster
2. LVIS: Low-voltage detection level select register
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD
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Figure 14-2. Timing of Reset by RESET Input
<1> With high-speed Ring-OSC clock or external clock input
Hi-Z
RESET
Port pin
(except P130)
Port pin
(P130) Note 2
Delay
Normal operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
High-speed Ring-OSC clock or
external clock input
Delay
Operation stops because option
byte is referenced
Note 1
.
Notes 1. The operation stop time is 277
µ
s (MIN.), 544
µ
s (TYP.), and 1.075 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
<2> With crystal/ceramic oscillation clock
Hi-Z
RESET
Port pin
(P130) Note 2
Port pin
(except P130)
Delay
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (2
10
/f
X
to 2
17
/f
X
)
Normal operation
(reset processing, CPU clock)
Internal reset signal
Crystal/ceramic
oscillation clock
Delay
Operation stops because option
byte is referenced
Note 1
.
Notes 1. The operation stop time is 276
µ
s (MIN.), 544
µ
s (TYP.), and 1.074 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
Remark f
X: System clock oscillation frequency
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD 237
Figure 14-3. Timing of Reset by Overflow of Watchdog Timer
<1> With high-speed Ring-OSC clock or external clock input
Hi-Z
Port pin
(except P130)
Port pin
(P130) Note 2
Normal operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
High-speed Ring-OSC clock or
external clock input
Operation stops because option
byte is referencedNote 1.
Watchdog overflow
Notes 1. The operation stop time is 277
µ
s (MIN.), 544
µ
s (TYP.), and 1.075 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
<2> With crystal/ceramic oscillation clock
Hi-Z
Port pin
(P130) Note 2
Port pin
(except P130)
Normal operation
in progress
Reset period
(oscillation stops)
Oscillation stabilization
time (210/fX to 217/fX)
Normal operation
(reset processing, CPU clock)
Internal reset signal
Crystal/ceramic
oscillation clock
Operation stops because option
byte is referenced
Note 1
.
CPU clock
Watchdog overflow
Notes 1. The operation stop time is 276
µ
s (MIN.), 544
µ
s (TYP.), and 1.074 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.
Remark f
X: System clock oscillati on frequency
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD
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Figure 14-4. Reset Timing by RESET Input in STOP Mode
<1> With high-speed Ring-OSC clock or external clock input
Hi-Z
RESET
Port pin
(except P130)
Port pin
(P130) Note 2
Delay
Normal
operation
in progress
CPU clock
Reset period
(oscillation stops)
Normal operation (reset processing, CPU clock)
Internal reset signal
High-speed Ring-OSC clock or
external clock input
Delay
Operation stops because option
byte is referenced
Note 1
.
Stop status
(oscillation stops)
STOP instruction is executed.
Notes 1. The operation stop time is 277
µ
s (MIN.), 544
µ
s (TYP.), and 1.075 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
<2> With crystal/ceramic oscillation clock
Hi-Z
RESET
Port pin
(except P130)
Port pin
(P130) Note 2
Delay
Normal
operation
in progress
CPU clock Normal operation
(reset processing, CPU clock)
Internal reset signal
High-speed Ring-OSC clock or
external clock input
Delay
Operation stops because option
byte is referenced
Note 1
.
Reset period
(oscillation stops)
Stop status
(oscillation stops)
STOP instruction is executed.
Oscillation stabilization
time (210/fX to 217/fX)
Notes 1. The operation stop time is 276
µ
s (MIN.), 544
µ
s (TYP.), and 1.074 ms (MAX.).
2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is
effected, the output signal of P130 can be dummy-output as the reset sign al to the CPU.
Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 15
POWER-ON-CLEAR CIRCUIT and CHAPTER 16 LOW-VOLTAGE DETECTOR.
2. fX: System clock oscillation frequency
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD 239
Table 14-1. Hardware Statuses After Reset Acknowledgment (1/2)
Hardware Status After Reset
Program counter (PC) Note 1 Contents of reset vector
table (0000H and
0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 02H
Data memory Undefined Note 2
RAM
General-purpose registers Undefined Note 2
Ports (P2 to P4, P12, P13) (output latches) 00H
Port mode registers (PM2 to PM4, PM12) FFH
Port mode control register (PMC2) 00H
Pull-up resistor option registers (PU2, PU3, PU4, PU12) 00H
Processor clock control register (PCC) 02H
Preprocessor clock control register (PPCC) 02H
Low-speed Ring-OSC mode register (LSRCM) 00H
Oscillation stabilization time select register (OSTS) Undefined
Timer counter 00 (TM00) 0000H
Capture/compare registers 000, 010 (CR000, CR010) 0000H
Mode control register 00 (TMC00) 00H
Prescaler mode register 00 (PRM00) 00H
Capture/compare control register 00 (CRC00) 00H
16-bit timer 00
Timer output control register 00 (TOC00) 00H
Timer counter 80 (TM80) 00H
Compare register (CR80) Undefined
8-bit timer 80
Mode control register 80 (TMC80) 00H
Compare registers (CMP01, CMP11) 00H 8-bit timer H1
Mode register 1 (TMHMD1) 00H
Mode register (WDTM) 67H Watchdog timer
Enable register (WDTE) 9AH
Conversion result registers (ADCR, ADCRH) Undefined
Mode register (ADM) 00H
A/D converter
Analog input channel specification register (ADS) 00H
Notes 1. Only the conte nts of PC are undefined w hile reset is being i nput and wh ile the oscillatio n stabiliz ation time
elapses. The statuses of the other hardware units remain unchanged.
2. The status after reset is held in the standby mode.
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD
240
Table 14-1. Hardware Statuses After Reset Acknowledgment (2/2)
Hardware Status After Reset
Receive buffer register 6 (RXB6) FFH
Transmit buffer register 6 (TXB6) FFH
Asynchronous serial interface operation mode register 6 (ASIM6) 01H
Asynchronous serial interface reception error status register 6
(ASIS6) 00H
Asynchronous serial interface transmission error status register 6
(ASIF6) 00H
Clock select register 6 (CKSR6) 00H
Baud rate generator control register 6 (BRGC6) FFH
Asynchronous serial interface control register 6 (ASICL6) 16H
Serial interface UART6
Input select control register (ISC) 00H
Reset function Reset control flag register (RESF) 00HNote
Low-voltage detection register (LVIM) 00HNote
Low-voltage detector
Low-voltage detection level select register (LVIS) 00HNote
Request flag registers (IF0, IF1) 00H
Mask flag registers (MK0, MK1) FFH
Interrupt
External interrupt mode registers (INTM0, INTM1) 00H
Flash protect command register (PFCMD) Undefined
Flash status register (PFS) 00H
Flash programming mode control register (FLPMC) Undefined
Flash programming command register (FLCMD) 00H
Flash address pointer L (FLAPL)
Flash address pointer H (FLAPH)
Undefined
Flash address pointer H compare register (FLAPHC) 00H
Flash address pointer L compare register (FLAPLC) 00H
Flash memory
Flash write buffer register (FLW) 00H
Note These values change as follows depending on the reset source.
Reset Source
Register
RESET Input Reset by POC Reset by WDT Reset by LVI
RESF See Table 14-2.
LVIM
LVIS
Cleared (00H) Cleared (00H) Cleared (00H) Held
CHAPTER 14 RESET FUNCTION
Preliminary User’s Manual U16898EJ2V0UD 241
14.1 Register for Confirming Reset Source
Many internal reset generatio n sources exist in the 78K0S/ KA1+. The reset control flag r egister (RESF) is used t o
store which source has generated the reset request.
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.
Figure 14-5. Format of Reset Control Flag Register (RESF)
Address: FF54H After re set: 00HNote R
Symbol 7 6 5 4 3 2 1 0
RESF 0 0 0 WDTRF 0 0 0 LVIRF
WDTRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset req uest is generated.
LVIRF Internal reset request by low-voltage detector (LVI)
0 Internal reset request is not generated, or RESF is cleared.
1 Internal reset req uest is generated.
Note The value after reset varies d epending on the reset source.
Caution Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 14-2.
Table 14-2. RESF Status When Reset Request Is Generated
Reset Source
Flag
RESET Input Reset by POC Reset by WDT Reset by LVI
WDTRF Set (1) Held
LVIRF
Cleared (0) Cleared (0)
Held Set (1)
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CHAPTER 15 POWER-ON-CLEAR CIRCUIT
15.1 Functions of Power-on-Clear Circuit
The power-on-clear circuit (POC) has the following functions.
• Generates inte rnal reset signal at power on.
• Compares supply voltage (VDD) and detection voltag e (VPOC = 2.1 V ±0.1 V), and gener ates internal reset signa l
when VDD < VPOC.
• Compares supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.1 V), and releases internal reset signal
when VDD ≥ VPOC.
Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register
(RESF) is cleared to 00H.
2. Because the detection voltage (VPOC) of the POC circuit is in a range of 2.1 V ±0.1 V, use a
voltage in the range of 2.2 to 5.5 V.
Remark This product incorporates multiple har dware functions that generate an internal reset signal. A flag that
indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.
For details of RESF, see CHAPTER 14 RESET FUNCTION.
CHAPTER 15 POWER-ON-CLEAR CIRCUIT
Preliminary User’s Manual U16898EJ2V0UD 243
15.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circ uit is shown in Figure 15-1.
Figure 15-1. Block Diagram of Power-on-Clear Circuit
−
+
Reference
voltage
source
Internal reset signal
V
DD
V
DD
15.3 Operation of Power-on-Clear Circuit
In the power-on-clear circuit, the supply voltage (VDD) and detection voltage (VPOC = 2.1 V ±0.1 V) are compared,
and an internal reset signal is generated when VDD < VPOC, and an internal reset is released when VDD ≥ VPOC.
Figure 15-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit
Time
Supply voltage (VDD)
POC detection voltage
(VPOC = 2.1 V ±0.1 V)
Internal reset signal
Remark The internal reset signal is active-low.
CHAPTER 15 POWER-ON-CLEAR CIRCUIT
Preliminary User’s Manual U16898EJ2V0UD
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15.4 Cautions for Power-on-Clear Circuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection
voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports.
Figure 15-3. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
Power-on clear
; The reset source (power-on clear, WDT, or LVI)
can be identified by the RESF register.
;TMIFH1 = 1: Interrupt request is generated.
;Initialization of ports, etc.
;8-bit timer H1 can operate on the low-speed Ring-OSC clock.
Source: f
RL
(480 kHz (MAX.))/2
7
× compare value 200 = 53 ms
(f
RL
: Low-speed Ring-OSC clock oscillation frequency)
No
Note 1
Reset
Check reset
source
Note 2
Yes
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Timer starts
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
CHAPTER 15 POWER-ON-CLEAR CIRCUIT
Preliminary User’s Manual U16898EJ2V0UD 245
Figure 15-3. Example of Software Processing After Release of Reset (2/2)
• Checking reset cause
Yes
No
Check reset source
Power-on clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by low-voltage
detector
No
WDTRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Yes
Preliminary User’s Manual U16898EJ2V0UD
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CHAPTER 16 LOW-VOLTAGE DETECTOR
16.1 Functions of Low-Voltage Detector
The low-voltage detector (LVI) has followin g functions.
• Compares supply voltage (VDD) and detection voltage (VLVI), and generates an internal interrupt signal or
internal reset signal when VDD < VLVI.
• Detection levels (ten levels) of supply voltage can be changed by software.
• Interrupt or reset function can be selected by software.
• Operable in STOP mode.
When the low-voltage d etector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if
reset occurs. For details of RESF, refer to CHAPTER 14 RESET FUNCTION.
16.2 Configuration of Low-Voltage Detector
The block diagram of the low-voltage detector is shown in Figure 16-1.
Figure 16-1. Block Diagram of Low-Voltage Detector
LVION
Reference
voltage source
V
DD
N-ch
Low-voltage detection
level select register (LVIS) Low-voltage detect
register (LVIM)
LVIS2 LVIMD LVIF
INTLVI
Internal reset signal
4
V
DD
LVIS1 LVIS0
LVIS3
Low-voltage detection level selector
Selector
Internal bus
+
−
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD 247
16.3 Registers Controlling Low-Voltage Detector
The low-voltage detector is controlled by the following registers.
• Low-voltage de tect register (LVIM)
• Low-voltage detection level select register (LVIS)
(1) Low-voltage detect register (LVIM)
This register sets low-voltage detection and the operation mode.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00HNote 1.
Figure 16-2. Format of Low-Voltage Detect Register (LVIM)
<0>
LVIF
<1>
LVIMD
2
0
3
0
4
0
5
0
6
0
<7>
LVION
Symbol
LVIM
Address: FF50H After reset: 00H
Note 1
R/W
Note 2
LVIONNote 3 Enabling low-voltage detection operation
0 Disable operation
1 Enable operation
LVIMD Low-voltage detection operation mode selection
0 Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI)
1 Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI)
LVIFNote 4 Low-voltage detection flag
0 Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is disabled
1 Supply voltage (VDD) < detection voltage (VLVI)
Notes 1. Retained only after a reset by LVI.
2. Bit 0 is a read-only bit.
3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use
software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until th e voltage is
confirmed at LVIF.
4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and
LVIMD = 0.
Cautions 1. To stop LVI, follow either of the procedures below.
• When using 8-bit manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
2. Be sure to set bits 2 to 6 to 0.
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD
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(2) Low-voltage detection level select register (LVIS)
This register selects the low-voltage detection level.
This register can be set by an 8-bit memory manipulation instruction.
Reset input clears this register to 00HNote.
Figure 16-3. Format of Low-Voltage Detection Level Select Register (LVIS)
Address: FF51H, After reset: 00HNote R/W
Symbol 7 6 5 4 3 2 1 0
LVIS 0 0 0 0 LVIS3 LVIS2 LVIS1 LVIS0
LVIS3 LVIS2 LVIS1 LVIS0 Detection level
0 0 0 0 VLVI0 (4.3 V ±0.2 V)
0 0 0 1 VLVI1 (4.1 V ±0.2 V)
0 0 1 0 VLVI2 (3.9 V ±0.2 V)
0 0 1 1 VLVI3 (3.7 V ±0.2 V)
0 1 0 0 VLVI4 (3.5 V ±0.2 V)
0 1 0 1 VLVI5 (3.3 V ±0.15 V)
0 1 1 0 VLVI6 (3.1 V ±0.15 V)
0 1 1 1 VLVI7 (2.85 V ±0.15 V)
1 0 0 0 VLVI8 (2.6 V ±0.15 V)
1 0 0 1 VLVI9 (2.35 V ±0.15 V)
Other than above Setting prohibited
Note Retained only after a reset by LVI.
Caution Bits 4 to 7 must be set to 0.
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD 249
16.4 Operation of Low-Voltage Detector
The low-voltage detector can be use d in the following two modes.
• Used as reset
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an internal reset signal when
VDD < VLVI, and releases internal reset when VDD ≥ VLVI.
• Used as interrupt
Compares the supply voltage (VDD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)
when VDD < VLVI.
The operation is set as follows.
(1) When used as reset
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
register (LVIS).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (VDD) < detection
voltage (VLVI)).
Figure 16-4 shows the timing of generating the inter nal reset signal of the low-voltage detector. Numbers < 1>
to <6> in this figure correspond to <1> to <6> above.
Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately
after the processing in <3>.
2. If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIM is set to 1, an internal reset
signal is not generated.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD
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Figure 16-4. Timing of Low-Voltage Detector Internal Reset Signal Generation
2.7 V
<2>
<1>
Note 1
Note 2
<3>
<5>
<6>
H
Supply voltage (V
DD
)
LVI detection voltage
(V
LVI
)
POC detection voltage
(V
POC
)
LVIF flag
LVIRF flag
Note 3
LVI reset signal
POC reset signal
Internal reset signal
LVIMK flag
(set by software)
LVION flag
(set by software)
LVIMD flag
(set by software)
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
Time
Clear
Clear
Clear
<4> 0.2 ms or longer
Notes 1. The LVIMK flag is set to “1” by reset input.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 14
RESET FUNCTION.
Remark <1> to <6> in Figure 16- 4 a bov e correspon d to <1> to <6> in the descri ption of “w hen star ting oper ation ”
in 16.4 (1) When used as reset.
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD 251
(2) When used as interrupt
• When starting operation
<1> Mask the LVI interrupt (LVIMK = 1).
<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select
register (LVIS).
<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
<4> Use software to instigate a wait of at least 0.2 ms.
<5> Wait until “supply voltage (VDD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.
<6> Clear the interrupt request flag of LVI (LVIIF) to 0.
<7> Release the interrupt mask flag of LVI (LVIMK).
<8> Execute the EI instruction (when vector interr upts are used).
Figure 16-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to
<7> in this figure correspond to <1> to <7> above.
• When stopping operation
Either of the following procedures must be executed.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
Figure 16-5. Timing of Low-Voltage Detector Interrupt Signal Generation
2.7 V
<2>
<1>
Note 1
<3>
<5>
Note 2
Note 2
Supply voltage (V
DD
)
LVI detection voltage
(V
LVI
)
POC detection voltage
(V
POC
)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
LVIMK flag
(set by software)
LVION flag
(set by software)
Time
<6>
Cleared by software
<7> Cleared by software
<4> 0.2 ms or longer
Notes 1. The LVIMK flag is set to “1” by reset input.
2. The LVIF and LVIIF flags may be set (1).
Remark <1> to <7> in Figure 16- 5 a bov e correspon d to <1> to <7> in the descri ption of “w hen star ting oper ation ”
in 16.4 (2) When used as interrupt.
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16.5 Cautions for Low-Voltage Detector
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection vo ltage
(VLVI), the operation is as follows depending on how the low-voltage detector is used.
<1> When used as reset
The system may be repeatedly reset and release d from the reset status.
In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily
set by taking action (1) below.
<2> When used as interrupt
Interrupt requests may be frequently generat ed. Take action (2) below.
In this system, take the following actions.
<Action>
(1) When used as reset
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
software counter that uses a timer, and then initialize the ports (see Figure 16-6).
(2) When used as interrupt
Perform the processingNote for low voltage detection. Check that “supply voltage (VDD) ≥ detection voltage (VLVI)”
in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM).
Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0 and enable interrupts (EI).
In a system where the supply voltag e fluctuation p eriod is long in t he vicinity of the LVI de tection voltage, wait for
the supply voltage fluctuation period, check that “supply voltage (VDD) ≥ detection voltage (VLVI)” using the LVIF
flag, and then enable interrupt s (EI).
Note For low voltage detection processing, the CPU clock speed is switched to slow speed and the A/D
converter is stopped, etc.
CHAPTER 16 LOW-VOLTAGE DETECTOR
Preliminary User’s Manual U16898EJ2V0UD 253
Figure 16-6. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Yes
LVI
No
;The reset source (power-on clear, WDT, or LVI)
can be identified by the RESF register.
;TMIFH1 = 1: Interrupt request is generated.
;Initialization of ports
;8-bit timer H1 can operate with the low-speed Ring-OSC clock.
Source: f
RL
(480 kHz (MAX.))/2
7
× compare value 200 = 53 ms
(f
RL
: low-speed Ring-OSC clock oscillation frequency)
Note 1
Reset
Check
reset source
Note 2
50 ms has passed?
(TMIFH1 = 1?)
Initialization
processing
Start timer
(set to 50 ms)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
CHAPTER 16 LOW-VOLTAGE DETECTOR
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Figure 16-6. Example of Software Processing After Release of Reset (2/2)
• Checking reset source
Yes
No
Yes
No
Check reset source
Power-on-clear/external
reset generated
Reset processing by
watchdog timer
Reset processing by
low-voltage detector
WDTRF of RESF
register = 1?
LVIRF of RESF
register = 1?
Preliminary User’s Manual U16898EJ2V0UD 255
CHAPTER 17 OPTION BYTE
The 78K0S/KA1+ has an area called an option byte at address 0080H of the flash memory. When using the
product, be sure to set the following functions by using the option byte.
1. Selection of system clock source
• High-speed Ring-OSC clock
• Crystal/ceramic oscillation clock
• External clock input
2. Low-speed Ring-OSC clock oscillation
• Cannot be stopped.
• Can be stopped by software.
3. Control of RESET pin
• Used as RESET pin
• RESET pin is used as an input port pin (P34).
4. Oscillation stabilization time on power application or after reset release
• 210/fX
• 212/fX
• 215/fX
• 217/fX
Figure 17-1. Positioning of Option Byte
Option byte
OSCSEL1
RMCE11
Flash memory
(2048/4096 × 8 bits)
07FFH/0FFFH
0000H
0080H
DEF
OSTS1
OSCSEL0
RINGOSC
DEF
OSTS0
CHAPTER 17 OPTION BYTE
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Figure 17-2. Format of Option Byte (1/2)
Address: 0080H
7 6 5 4 3 2 1 0
1 DEFOSTS1 DEFOSTS0 1 RMCE OSCSEL1 OSCSEL0 RINGOSC
RINGOSC Low-speed Ring-OSC clock oscillation
1 Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit)
0 Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit)
Cautions 1. If it is selected that low-speed Ring-OSC clock oscillation cannot be stopped, the count
clock to the watchdog timer (WDT) is fixed to low-speed Ring-OSC.
2. If it is selected that low-speed Ring-OSC can be stopped by software, supply of the count
clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of bit 0
(LSRSTOP) of the low-speed Ring-OSC mode register (LSRCM). Similarly, clock supply
is also stopped when a clock other than the low-speed Ring-OSC is selected as a count
clock to WDT. If low-speed Ring-OSC is selected as the count clock to 8-bit timer H1,
however, the count clock is supplied in the HALT/STOP mode while low-speed Ring-OSC
operates (LSRSTOP = 0).
OSCSEL1 OSCSEL0 Selection of system clock source
0 0 Crystal/ceramic oscillation clock
0 1 External clock input
1 × High-speed Ring-OSC clock
Caution Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under
which the X1 and X2 pins can be used differ depending on the selected system clock source.
(1) High-speed Ring-OSC clock
P121 and P122 can be used as I/O port pins.
(2) Crystal/ceramic oscillation clock
The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input
pins.
(3) External clock input
Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O
port pin.
Remark × : don’t care
RMCE Control of RESET pin
1 RESET pin is used as is.
0 RESET pin is used as input port pin (P34).
Caution If a low level is input to the RESET pin after reset is released by the power-on clear function
and before the option byte is referenced again, the 78K0S/KA1+ is reset, and the status is
held until a high level is input to the RESET pin.
CHAPTER 17 OPTION BYTE
Preliminary User’s Manual U16898EJ2V0UD 257
Figure 17-2. Format of Option Byte (2/2)
DEFOSTS1 DEFOSTS0 Oscillation stabilization time on power application or after reset release
0 0 210/fx (102.4
µ
s)
0 1 212/fx (409.6
µ
s)
1 0 215/fx (3.27 ms)
1 1 217/fx (13.1 ms)
Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected
as the system clock source. No wait time elapses if the high-speed Ring-OSC or external
clock input is selected as the system clock source.
Remarks 1. ( ): fX = 10 MHz
2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator
to be used.
Preliminary User’s Manual U16898EJ2V0UD
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CHAPTER 18 FLASH MEMORY
18.1 Features
The internal flash memory of the 78K0S/KA1+ has the following features.
{ Erase/write wit h a single power supply
{ Capacity: 2 KB/4 KB
• Erase unit: 1 block (256 bytes)
• Write unit: 1 byte
{ Rewriting method
• Rewriting by communication with dedicated flash programmer (on-board/off-board programming)
• Rewriting flash memor y by user program (self programming)
{ Flash memory write prohibit function support ed (security function)
CHAPTER 18 FLASH MEMORY
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18.2 Memory Configuration
The 2/4 KB internal flash memory area is divided into 8/16 blocks and can be programmed/erased in block units.
All the blocks can also be erased at once.
Figure 18-1. Flash Memory Mapping
Special function resister
(256 byte)
Internal high-speed RAM
(128/256 byte)
Use prohibited
Flash memory
(2/4 KB)
FFFFH
FF00H
FEFFH
0000H 0000H
0100H
00FFH
Block 0 (256 bytes)
Block 1 (256 bytes)
Block 2 (256 bytes)
Block 3 (256 bytes)
Block 4 (256 bytes)
Block 5 (256 bytes)
Block 6 (256 bytes)
Block 7 (256 bytes)
Block 0 (256 bytes)
Block 1 (256 bytes)
Block 2 (256 bytes)
Block 3 (256 bytes)
Block 4 (256 bytes)
Block 5 (256 bytes)
Block 6 (256 bytes)
Block 7 (256 bytes)
Block 8 (256 bytes)
Block 9 (256 bytes)
Block 10 (256 bytes)
Block 11 (256 bytes)
Block 12 (256 bytes)
Block 13 (256 bytes)
Block 14 (256 bytes)
Block 15 (256 bytes)
2 KB 4 KB
0200H
01FFH
0300H
02FFH
0400H
03FFH
0500H
04FFH
0600H
05FFH
0700H
06FFH
0800H
07FFH
0900H
08FFH
0A00H
09FFH
0B00H
0AFFH
0C00H
0BFFH
0D00H
0CFFH
0E00H
0DFFH
0F00H
0EFFH
0FFFH
Note
• PD78F9221
• PD78F2222
µ
µ
CHAPTER 18 FLASH MEMORY
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18.3 Functional Outline
The inter nal flash memor y of the 78K0S/KA1+ can be rewrit ten by using the rewr ite function of the dedic ated flash
programmer, regardless of whether the 78K0S/KA1+ has already been mounted on the target system or not (on-
board/off-board programming).
The function for rewriting a program with the user program (self programming), which is ideal for an application
when it is assumed that the program is changed after production/shipment of the target system, is provided.
In addition, a security functi on that prohibits rewriting the user program writ ten to the internal flas h memor y is also
supported, so that the program cannot be changed by an unauthorized person.
Refer to 18.7.4 Security settings for details on the security function.
Table 18-1. Rewrite Method
Rewrite Method Functional Outline Operation Mode
On-board programming Flash memory can be rewritten after the device is mounted on the
target system, by using a dedicated flash programmer.
Off-board programming Flash memory can be rewritten before the device is mounted on the
target system, by using a dedicated flash programmer and a dedicated
program adapter board (FA series).
Flash memory
programming mode
Self programming Flash memory can be rewritten by executing a user program that has
been written to the flash memory in advance by means of on-board/off-
board programming.
Self programming mode
Remarks 1. The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.
2. Refer to the following sections for details on the flash memory writing control function.
• 18.7 On-Board and Off-Board Flash Memory Programming
• 18.8 Flash Memory Programming by Self Writing
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Preliminary User’s Manual U16898EJ2V0UD 261
18.4 Writing with Flash Programmer
The following two types of dedicated flash programmers can be used for writing data to the internal flash memor y
of the 78K0S/KA1+.
• FlashPro4 (PG-FP4, FL-PR4)
• PG-FPL2
Data can be written to the flash memory on- board or off-board, by using a dedicated flash programmer.
(1) On-board programming
The contents of the flash memory can be rewritten after the 78K0S/KA1+ has been mounted on the target
system. The connectors that connect the dedicated flash programmer and the test pad must be mounted on
the target system. The test pad is required only when writing data with the crystal/ceramic resonator mounted
(refer to Figure 18-5 for mounting of the test pad).
(2) Off-board programming
Data can be written to the flash memory with a dedicated pr ogram adapter (FA series) before the 78K0S/KA1 +
is mounted on the target system.
Remark The FL-PR4 and FA series are products of Naito Densei Machida Mfg. Co., Ltd.
CHAPTER 18 FLASH MEMORY
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18.5 Programming Environment
The environment required for writing a program to the flash memory is illustrated below.
Figure 18-2. Environment for Writing Program to Flash Memory
RS-232C
USB
Host machine
Dedicated flash programmer
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
78K0S/KA1+
V
DD
V
SS
RESET
DGDATA
Note
DGCLK
Note
Power Status
MODE
Target 3V
Target
PG-FPL2
USB
FlashPro4
PG-FPL2
Note DGCLK and DGDATA are single-wire bidirectional communication interfaces. They use UART as the
communication mode.
A host machine that controls the dedicated flash programmer is necessary. When using the PG-FP4 or FL-PR4,
data can be written with just the dedicated flash programmer after downloading the program from the host machine.
UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash
programmer and the 78K0S/KA1+. To write the flash memory off-board, a dedicated program adapter (FA series) is
necessary.
Download the latest programmer firmware, GUI, and parameter file from the download site for development tools
(http://www.necel.com/micro/ods/jpn/index.html).
Table 18-2. Wiring Between 78K0S/KA1+ and FlashPro4
FlashPro4 Connection Pin 78K0S/KA1+ Connection Pin
Pin Name I/O Pin Function Pin Name Pin No.
CLKNote Output Clock to 78K0S/KA1+
FLMD0Note Output On-board mode signal
X1/P121 2
SI/RxDNote Input Receive signal
SO/TxDNote Output Receive signal/on-board mode signal
X2/P122 3
/RESET Output Reset signal RESET/P34 6
VDD – VDD voltage generation/voltage monitor VDD 5
GND – Ground VSS 1
Note In the 78K0S/KA1+, the CLK and FLMD0 signals are con nected to the X1 pin and the SI/RxD and SO/TxD
signals to the X2 signal; therefore, these signals need to be directly connected.
CHAPTER 18 FLASH MEMORY
Preliminary User’s Manual U16898EJ2V0UD 263
Figure 18-3. Communication with FlashPro4
78K0S/KA1+
CLK
FLMD0
SO/TxD
/RESET
V
DD
GND
FlashPro4
signal name
SI/RxD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Table 18-3. Wiring Between 78K0S/KA1+ and PG-FPL2
PG-FPL2 Connection Pin 78K0S/KA1+ Co nnection Pin
Pin Name I/O Pin Function Pin Name Pin No.
CLK Output Clock to 78K0S/KA1+ X1/P121 2
DGDATA I/O Transmit/receive signal, on-board mode signal X2/P122 3
/RESET Output Reset signal RESET/P34 6
VDD I/O VDD voltage generation VDD 5
GND – Ground VSS 1
Figure 18-4. Communication with PG-FPL2
78K0S/KA1+
DGCLK
DGDATA
/RESET
VDD
GND
PG-FPL2
signal name 1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CHAPTER 18 FLASH MEMORY
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18.6 Pin Connection on Board
To write the flash memory on-board, connectors that con nect the dedicate d flash progr ammer must be provided o n
the target system. First provide a function that selects the normal operation mode or flash memory programming
mode on the board.
When the flash memory programming mo de is set, all the pins not used for programming the flash memory are i n
the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately
after reset, the pins must be processed as described bel ow.
The state of the pins in the self programming mode is the same as that in the HALT mode.
18.6.1 X1 and X2 pins
The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2
pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the
connection with the external device.
Perform the following processing (1) and (2) when on-board writing is performed with t he resonator mounted, when
it is difficult to isolate the resonator, while a crystal or ceramic resonator is selected as the system clock.
(1) Mount the minimum-possible test pads between the device and the resonator, and connect the flash
programmer via the test pad. Keep the wiring as short as possible (refer to Figure 18-5 and Table 18-4).
(2) Set the oscillation frequency of the communication clock for writing using the GUI software of the dedicated
flash programmer. Researc h the series/parallel resonant and antiresonant frequencies of the resonator used,
and set the oscillation freque ncy so that it is outside the range of the reso nant frequency ±10% (re fer to Figure
18-6 and Table 18-5).
Figure 18-5. Example of Mounting Test Pads
X2X1VSS
Test pad
Table 18-4. Clock to Be Used and Mounting of Test Pads
Clock to Be Used Mounting of Test Pads
High-speed Ring-OSC clock
External clock
Before resonator is mounted
Not required
Crystal/ceramic oscillation
clock After resonator is mounted Required
CHAPTER 18 FLASH MEMORY
Preliminary User’s Manual U16898EJ2V0UD 265
Set oscillation fre
q
uenc
y
Click
Figure 18-6. PG-FP4 GUI Software Setting Example
Table 18-5. Oscillation Frequency and PG-FP4 GUI Software Setting Value Example
Oscillation Frequency PG-FP4 GUI Software Setting Value Example
(Communication Frequency)
1 MHz ≤ fX < 4 MHz 8 MHz
4 MHz ≤ fX < 8 MHz 9 MHz
8 MHz ≤ fX < 9 MHz 10 MHz
9 MHz ≤ fX ≤ 10 MHz 8 MHz
Caution The above setting values are under development, so they may be changed in the future.
18.6.2 RESET pin
If the reset signal of the dedicated flash programmer is co nnected to the RESET pin that is connected to the reset
signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the
reset signal generator.
If the reset signal is input from the user system while the flash memory programming mode is set, the flash
memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash
programmer.
(Main window) (Standard tab in Device setup window)
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Figure 18-7. Signal Collision (RESET Pin)
RESET
Dedicated flash programmer
connection signal
Reset signal generator
Signal collision
Output pin
In the flash memory programming mode, the signal output by the reset
signal generator collides with the signal output by the dedicated flash
programmer. Therefore, isolate the signal of the reset signal generator.
78K0S/KA1+
18.6.3 Por t pins
When the flash memory programming mode is set, all the pins not used for flash memory programming enter the
same status as that immediately after reset. If external devices connected to the ports do not recognize the port
status immediately after reset, the port pin must be connected to VDD or VSS via a resistor.
The state of the pins in the self programming mode is the same as that in the HALT mode.
18.6.4 Power supply
Connect the VDD pin to VDD of the flash programmer, and the VSS pin to VSS of the flash programmer.
Supply AVREF with the same power supply as that in the normal operation mode.
CHAPTER 18 FLASH MEMORY
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18.7 On-Board and Off-Board Flash Memory Programming
18.7.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash memory.
Figure 18-8. Flash Memory Manipulation Procedure
Start
Manipulate flash memory
End?
Yes
No
End
Flash memory programming
mode is set
CHAPTER 18 FLASH MEMORY
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18.7.2 Flash memory programming mode
To rewrite the contents of the flash memory by usin g the dedicated flash programmer, set the 78K 0S/KA1+ in the
flash memory programming mode. When the 78K0S/KA1+ is connected to the flash programmer and a
communication command is transmitted to the microcontroller, the microcontroller is set in the flash memory
programming mode.
Change the mode by using a jumper when writing the flash memory on-board.
18.7.3 Communication commands
The 78K0S/KA1+ communica tes with the dedicated flash p rogrammer by using commands. The signals sent from
the flash programmer to the 78K0S/KA1+ ar e cal led commands, and the commands sent from the 78K 0S/KA1+ to the
dedicated flash programmer are called response commands.
Figure 18-9. Communication Commands
Command
Response command
78K0S/KA1+
PG-FP4
(Flash Pro4)
Cxxxxxx
Bxxxxx
Axxxx
XXX YYY
XXXXX XXXXXX
XXXX
XXXX YYYY
STATVE
FlashPro4
Dedicated flash programmer
Power Status
MODE
Target 3V
Target
PG-FPL2
PG-FPL2
The flash memory control commands of the 78K0S/KA1+ are listed in the table below. All these commands are
issued from the programmer and the 78K0S/ KA1+ perform pr ocessing corresponding to the respective commands.
Table 18-6. Flash Memory Control Commands
Classification Command Name Function
Batch erase (chip erase) command Erases the contents of the entire memory Erase
Block erase command Erases the contents of the memory of the specified block
Write Write command Writes to the specified address range and executes a verify
check of the contents.
Checksum Checksum command Reads the checksum of the specified address range and
compares with the written data.
Blank check Blank check command Confirms the erasure status of the entire memory.
Security Security setting command Prohibits batch erase (chip erase) command, block erase
command, and write command to prevent operation by third
parties.
The 78K0S/KA1+ returns a response comma nd for the command issued by the ded icated flash programmer. The
response commands sent from the 78K0S/KA1+ are listed below.
Table 18-7. Response Commands
Command Name Function
ACK Acknowledges command/data.
NAK Acknowledges illegal command/data.
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18.7.4 Security settings
The operations shown belo w can be prohibited using the security setting command.
Caution The security setting is valid when the programming mode is set next time. Therefore, when the
security setting command is executed, exit from the programming mode, then set the
programming mode again.
• Batch erase (chip erase)
Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is
prohibited. Once execution of the batch e rase (chip erase) command is prohibited, all the prohibition settings can
no longer be cancelled.
Caution After the secu rity setting of the batch erase is set, erasure cannot be performed for the device .
In addition, even if a write command is executed, data different from that which has already
been written to the flash memory cannot be written because the erase command is disabled.
• Block erase
Execution of the block erase command for a specific block in the flash memory is prohibited. This prohibition
setting can be cancelled usin g the batch erase (chip erase) command.
• Write
Execution of the write and block erase commands for entire blocks in the flash memory is prohibited. This
prohibition setting can be cancelled using the batch erase (chip erase) command.
The batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash
memory is shipped. The above security settings are possible only for on-board/off-board programm ing. Each security
setting can be used in combination.
Table 18-8 shows the relationship betwee n the eras e and write comman ds when the 7 8K 0S/KA1+ security functi on
is enabled.
Table 18-8. Relationship Between Commands When Security Function Is Enabled
Command
Security
Batch Erase (Chip
Erase) Command Block Erase
Command Write Command
When batch erase (chip erase) security
operation is enabled Disabled EnabledNote
When block erase security operation is
enabled Enabled
When write security operation is enabled
Enabled
Disabled
Disabled
Note Since the erase command is disabled, data different from that which has already been written to the
flash memory cannot be written.
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Table 18-9 shows the relationship betwee n the security setting and the operation in each programming mode.
Table 18-9. Relationship Between Security Setting and Operation In Each Programming Mode
On-Board/Off-Board Programming Self Programming Programming Mode
Security Setting Security Setting Security Operation Security Setting Security Operation
Batch erase (chip erase)
Block erase
Write
Possible ValidNote 1 Impossible InvalidNote 2
Notes 1. Execution of each comma nd is prohibited by the security setting.
2. Execution of self programming command is possible regar dless of the security setting.
18.8 Flash Memory Programming by Self Writing
The 78K0S/KA1+ supports a self programming function that can be used to rewrite the flash memory via a user
program, making it possible to upgr ade programs in the field.
Caution Self programming processing must be included in the program before performing self writing.
Remark To use the inter nal flash memor y of the 78K0S/KA1+ as the external EEPROM for stor ing data, refer to
“78K0S/Kx1+ EEPROM Emulation AN” (release schedule is undefined).
18.8.1 Outline of self programming
To execute self programming, shift the mode from the normal operation of the user pr ogram (normal mode) to the
self programming mode. Write/erase proces sing for the flash memory, wh ich has been s et to the register in advance ,
is performed by executing the HALT instruction during self programming mode. The HALT state is automatically
released when processing is completed.
To shift to the self programming mode, execute a specific sequence for a specific register. Refer to 18.8.4
Example of shifting normal mode to self programming for details.
Remark Data written by self programming can be referenced with the MOV instruction.
Table 18-10. Self Programming Mode
Mode User Program Execution Execution of Write/erase for Flash
Memory with HALT Instruction
Normal mode Enabled −
Self programming mode EnabledNote Enabled
Note Maskable interrupt servicing is disabled during self programming mode.
Figure 18-10 shows a block diagram for self programming, Figure 18-11 shows the self programming state
transition diagram, Table 18-11 lists the commands for controlling self programming.
CHAPTER 18 FLASH MEMORY
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Flash programming mode
control register (FLPMC) Flash protect command
register (PFCMD)
Self programming mode setting register
Self programming mode
setting sequencer
HALT signal
Self programming command execution
Flash memory controller
Verify
circuit
Write
circuit
Erase
circuit
WEPERR
VCERR
FPRERR
HALT release signal
FLCMD2 FLCMD1 FLCMD0
Internal bus
Flash programming command
register (FLCMD)
Increment
circuit
Flash memory
Protect byte
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0
5
Flash address
pointer H (FLAPH)
Flash address
pointer L (FLAPL)
Flash address pointer H
compare register
(FLAPHC)
Match
Match
Flash address pointer L
compare register
(FLAPLC) Flash write buffer register
(FLW)
Unmatch
Internal bus
Flash status register (PFS)
3
Figure 18-10. Block Diagram of Self Programming
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Figure 18-11. Self Programming State Transition Diagram
Register for
self programming
Self programming mode
Self programming
command under execution
Normal mode
User program
Operation
setting
Operation reference
Flash memory
Flash memory
control block (hardware)
Specific sequence
Self programming
command completion/error Self programming command
execution by HALT instruction
Operation setting
Table 18-11. Self Programming Controlling Commands
Command Name Function Time Taken from HALT Instruction Execution
to Command Execution End
Internal verify This command is used to check if data has been
correctly written to the flash memory. After data has
been written to the memory, specify the block number,
the start address, and the end address, then execute
this command.
Internal verify for 1 block (internal verify
command executed once): 6.8 ms
Internal verify for 1 byte: 27
µ
s
Block erasure This command is used to erase a specified block.
Specify the block number before execution. 8.5 ms
Block blank check This command is used to check if data in a specified
block has been erased. Specify the block number,
then execute this command.
480
µ
s
Byte write This command is used to write 1-byte data to the
specified address in the flash memory. Specify the
write address and write data, then execute this
command.
150
µ
s
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18.8.2 Cautions on self programming function
• If an interrupt occurs during self programming, the interrupt request flag is set (1), and interrupt servicing is
performed after the self programming mode is released. To avoid this operation, disable interrupt servicing (by
setting MK0 and MK1 to FFH, and executing the DI instruction) during self programming or before a mode is
shifted from the nor mal mode to the self programming mode with a specific sequence.
• No instructions can be executed while a self programming command is being executed. Therefore, clear and
restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self
programming. Refer to Table 18-11 for the time taken for the execution of self programming.
• RAM is not used while a self programming command is being executed.
• If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,
writing/erasing is not guaranteed.
• The value of the blank data set during block erasure is FFH.
• When the oscillator or the exter nal clock is selected as the main clock, a wait time of 16
µ
s is required star ting
from the setting of the self programming mode to the execution of the HALT instruction.
• The state of the pins in self programming mode is the same as that in HALT mode.
• Since the security function set via on-board/off-board programming is disabled in self programming mode, the
self programming command can be executed regardless of the security function setting. To disa ble write or erase
processing during self programming, set the protect byte.
18.8.3 Registers used for self programming function
The following registers are used for the self programming function.
• Flash programming mode control register (FLPMC)
• Flash protect command register (PFCMD)
• Flash status register (PFS)
• Flash programming command register (FLCMD)
• Flash address pointers H and L (FLAPH and FLAPL)
• Flash address pointer H compare register and flash address pointer L compare re gister (FLAPHC and FLAPLC)
• Flash write buffer register (FLW)
The 78K0S/KA1+ has an area called a protect byte at address 0081H of the flash memory.
(1) Flash programming mode control register (FLPMC)
This register is used to set the operation mode when data is written to the flash memory in the self
programming mode, and to read the set val ue of the protect byte.
Data can be written to FLPMC only in a specific sequence (refer to 18.8.3 (2) Flash protect command
register (PFCMD)) so that the application system does not stop by accident because of malfunctions due to
noise or program hang-ups.
This register is set with an 8-bit memory manipulation instruction.
Reset input makes the contents of this register undefined.
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Figure 18-12. Format of Flash Programming Mode Control Register (FLPMC)
Address: FFA2H After reset: UndefinedNote 1 R/WNote 2
Symbol 7 6 5 4 3 2 1 0
FLPMC 0 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 0 FLSPM
FLSPM Selection of operation mode during self programming mode
0
Normal mode
Flash memory instructions can be fetched from all addresses.
1
Self programming mode
Before executing the HALT instruction, set the command, address offset, write
data, and set FLSPM to 1. After setting these items, execute the HALT
instruction; the flash memory mo de is then shifted from the norm al mode to the
flash memory programming mode.
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 The set value of the protect byte
is read to these bits.
Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect
byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released.
2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only.
Cautions 1. Note the following when setting the self programming mode.
• If an interrupt occurs during self programming, the interrupt request flag
is set (1), and interrupt servicing is performed after the self programming
mode is released. To avoid this operation, disable interrupt servicing (by
setting MK0 and MK1 to FFH, and executing the DI instruct ion) during self
programming or before a mode is shifted from the normal mode to the self
programming mode with a specific sequence.
• No instructions can be executed while a self programming command is
being executed. Therefore, clear and restart the watchdog timer counter in
advance so that the watchdog timer does not overflow during self
programming. Refer to Table 18-11 for the time taken for the execution of
self programming.
• If the supply voltage drops or the reset signal is input while the flash
memory is being written or erased, writing/erasing is not guaranteed.
2. When the oscillator or the external clock is selected as the main clock, a wait
time of 16
µ
s is required from setting FLSPM to 1 to execution of the HALT
instruction.
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(2) Flash protect command register (PFCMD)
If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an
operation to write the flash programming mode control register (FLPMC) may have a serious effect on the
system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop
inadvertently.
Writing FLPMC is enabled only when a write operation is performed in the f ollowing specific sequence.
<1> Write a specific value to PFCMD (A5H)
<2> Write the value to be set to FLPMC (writing in this step is invalid)
<3> Write the inverted value of the value to be set to FLPMC (writing in this step is invalid)
<4> Write the value to be set to FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal store operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set with an 8-bit memory manipulation instruction.
Reset input makes PFCMD undefined.
Figure 18-13. Format of Flash Protect Command Register (PFCMD)
Address: FFA0H After reset: Undefined W
Symbol 7 6 5 4 3 2 1 0
PFCMD REG7 REG6 REG5 REG4 REG3 REG2 REG1 REG0
Caution Disable interrupt servicing (by setting MK0 and MK1 to FFH and executing the
DI instruction) while the specific sequence is under execution.
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(3) Flash status register (PFS)
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writ ing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears PFS to 00H.
Figure 18-14. Format of Flash Status Register (PFS)
Address: FFA1H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PFS 0 0 0 0 0
WEPRERR VCERR FPRERR
1. Operating conditions of FPRERR flag
<Setting conditions>
• If PFCMD is written when the store instruction operatio n recently performed on a peripheral reg ister is not to
write a specific value (A5H) to PFCMD
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction
after <2>
• If the first store instruction operation after <3> is on a peripheral register other than FLPMC
• If a value other than the value to be set to FL PMC (value wri tten in <2>) is written by t he fi rst store instructio n
after <3>
Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command
register (PFCMD).
<Reset conditions>
• If 0 is written to the FPRERR flag
• If the reset signal is input
2. Operating conditions of VCERR flag
<Setting conditions>
• Erasure verification error
• Internal writing verification error
If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the
memory again in the specified procedure.
Remark The VCERR flag may also be set if an erase or write protect error occurs.
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<Reset conditions>
• When 0 is written to the VCERR flag
• When the reset signal is input
3. Operating conditions of WEPRERR flag
<Setting conditions>
• If the area specified by the protect byte to be protected from erasing or writing is specified by the flash
address pointer H (FLAPH) and a command is executed to this area
<Reset conditions>
• When 0 is written to the WEPRERR flag
• When the reset signal is input
(4) Flash programming command register (FLCMD)
This register is used to specify whether the fl ash mem ory is erase d, written, or verified in t he se lf progr ammin g
mode.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears this register to 00H.
Figure 18-15. Format of Flash Programming Command Register (FLCMD)
Address: FFA3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
FLCMD 0 0 0 0 0 FLCMD2 FLCMD1 FLCMD0
FLCMD2 FLCMD1 FLCMD0 Command Name Function
0 0 1 Internal verify This command is used to check if
data has been correctly written to the
flash memory. After data has been
written to the memory, execute this
command by specifying a block
number, start address, and end
address. If an error occurs, bit 1
(VCERR) or bit 2 (WEPRERR) of the
flash status register (PFS) is set to 1.
0 1 1 Block erase This command is used to erase
specified block. It is used both in the
on-board mode and self
programming mode.
1 0 0 Block blank check This command is used to check if the
specified block has been erased.
1 0 1 Byte write This command is used to write 1-byte
data to the specified address in the
flash memory. Specify the write
address and write data, then execute
this command.
Other than aboveNote Setting prohibited
Note If a value other than the above is set and the self programming mode is set, the self programming
mode is canceled immediately and no execution occurs. At this time, the flag of the PFS register is
not set.
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(5) Flash address pointers H and L (FLAPH and FLAPL)
These registers are used to specify the start address of the flash memory when the mem ory is erased, written,
or verified in the self programming mode.
FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of
FLAPHC and FLAPLC when the programming command is not executed. When the programming command
is executed, therefore, set the value again.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset input makes these registers undefined.
Figure 18-16. Format of Flash Address Pointer H/L (FLAPH/FLAPL)
Address: FFA4H, FFA5H After reset: Undefined R/W
FLAPH (FFA5H) FLAPL (FFA4H)
0 0 0 0 FLA
P11
FLA
P10
FLA
P9
FLA
P8
FLA
P7
FLA
P6
FLA
P5
FLA
P4
FLA
P3
FLA
P2
FLA
P1
FLA
P0
Caution Be sure to clear bits 4 to 7 of FLAPH to 0.
(6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and
FLAPLC)
These registers are used to specify the address range in which the inter n al sequ enc er operates when the fl a s h
memory is verified in the self programming mode.
Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to
be executed to FLAPLC.
These registers are set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears these registers to 00H.
Figure 18-17. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)
Address: FFA6H, FFA7H After reset: 00H R/W
FLAPHC (FFA7H) FLAPLC (FFA6H)
0 0 0 0 FLAP
C11
FLAP
C10
FLAP
C9
FLAP
C8
FLAP
C7
FLAP
C6
FLAP
C5
FLAP
C4
FLAP
C3
FLAP
C2
FLAP
C1
FLAP
C0
Cautions 1. Be sure to clear bits 4 to 7 of FLAPHC to 0.
2. Set the number of the block subject to a block erase, write, verify, or blank check
(same value as FLAPH) to FLAPHC.
3. Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is
performed.
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(7) Flash write buffer register (FLW)
This register is used to store the data to be written to the flash memory.
This register is set with a 1-bit or 8-bit memory manipulation instruction.
Reset input clears these registers to 00H.
Figure 18-18. Format of Flash Write Buffer Register (FLW)
Address: FFA8H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
FLW FLW7 FLW6 FLW5 FLW4 FLW3 FLW2 FLW1 FLW0
(8) Protect byte
This protect byte is used to specify the area that is to be protected from wr iting or erasing. The specified area
is valid only in the self programming mode. Because self programming of the protected a rea is invalid, the data
written to the protected are a is guaranteed.
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Figure 18-19. Format of Protect Byte
Address: 0081H
7 6 5 4 3 2 1 0
1 PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 1 1
•
µ
PD78F9221
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status
0 1 1 0 0 Blocks 7 to 0 are protected.
0 1 1 0 1
Blocks 5 to 0 are protected.
Blocks 6 and 7 can be written or erased.
0 1 1 1 0
Blocks 3 to 0 are protected.
Blocks 4 to 7 can be written or erased.
0 1 1 1 1
Blocks 1 and 0 are protected.
Blocks 2 to 7 can be written or erased.
1 1 1 1 1 All blocks can be written or erased.
Other than above Setting prohibited
•
µ
PD78F9222
PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0 Status
0 1 0 0 0 Blocks 15 to 0 are protected.
0 1 0 0 1
Blocks 13 to 0 are protected.
Blocks 14 and 15 can be written or erased.
0 1 0 1 0
Blocks 11 to 0 are protected.
Blocks 12 to 15 can be written or erased.
0 1 0 1 1
Blocks 9 to 0 are protected.
Blocks 10 to 15 can be written or erased.
0 1 1 0 0
Blocks 7 to 0 are protected.
Blocks 8 to 15 can be written or erased.
0 1 1 0 1
Blocks 5 to 0 are protected.
Blocks 6 to 15 can be written or erased.
0 1 1 1 0
Blocks 3 to 0 are protected.
Blocks 4 to 15 can be written or erased.
0 1 1 1 1
Blocks 1 and 0 are protected.
Blocks 2 to 15 can be written or erased.
1 1 1 1 1 All blocks can be written or erased.
Other than above Setting prohibited
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18.8.4 Example of shifting normal mode to self programming mode
The operating mode must be shifted from normal mode to self programming mode before performing self
programming.
An example of shifting to self programming mode is explained below.
<1> Disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (MK0, MK1) to
FFH and executing the DI instruction).
<2> Clear the flash status register (PFS).
<3> Set self programming mode using a specific sequence.
• Write a specific value (A5H) to PFCMD.
• Write 01H to FLPMC (writing in this step is invalid).
• Write 0FEH (inverted value of 01H) to FLPMC (writing in this step is invalid).
• Write 01H to FLPMC (writing in this step is valid).
<4> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS.
Abnormal → <2>, normal → <5>
<5> Mode shift is completed.
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
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Figure 18-20. Example of Shifting to Self Programming Mode
Shift to self programming mode
<1> Disable interrupts (by setting MK0
and MK1 to FFH and executing
DI instruction)
PFCMD = A5H
<4> Check execution result
(FPRERR flag)
Abnormal
Normal
; When interrupt function is used
<2> Clear PFS
<5> Termination
FLPMC = 01H (set value)
FLPMC = 0FEH (inverted set value)
FLPMC = 01H (set value)
; Set value is invalid
; Set value is valid
<3>
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written。
Remark <1> to <5> in Figure 18-20 correspond to <1> to <5> in 18.8.4 (previous page).
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An example of the program list that shifts the mode to self programming mode is sho wn below.
;----------------------------
;START
;----------------------------
MOV MK0,#11111111B ; Masks all interrupts
MOV MK1,#11111111B
DI
ModeOnLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#01H ; FLPMC register control (sets value)
MOV FLPMC,#0FEH ; FLPMC register control (inverts set value)
MOV FLPMC,#01H ; Sets self programming mode with FLPMC register
; control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOnLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs.
;----------------------------
;END
;----------------------------
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18.8.5 Example of shifting self programming mode to normal mode
The operating mode must be returned from self programming mode to normal mode after performing self
programming.
An example of shifting to normal mode is ex plained below.
<1> Clear the flash status register (PFS).
<2> Set normal mode using a specific sequence.
• Write the specific value (A5H) to PFCMD.
• Write 00H to FLPMC (writing in this step is invalid)
• Write 0FFH (inverted value of 00H) to FLPMC (writing in this step is invalid)
• Write 00H to FLPMC (writing in this step is valid)
<3> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS.
Abnormal → <1>, normal → <4>
<4> Enable interrupt servicing (by executing the EI instr uction and chan ging MK0 and MK1) to restore the or iginal
state.
<5> Mode shift is completed
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
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Figure 18-21. Example of Shifting to Normal Mode
Shift to normal mode
PFCMD = A5H
<3> Check execution result
(FPRERR flag)
Abnormal
Normal
<1> Clear PFS
<5> Termination
FLPMC = 00H (set value)
FLPMC = 0FFH (inverted set value)
FLPMC = 00H (set value)
; Set value is invalid
; Set value is valid
<4> Enable interrupts (by executing
EI instruction and changing
MK0, MK1) ; When interrupt function is used
<2>
Caution Be sure to perform the series of operations described above using the user program at an
address where data is not erased nor written.
Remark <1> to <5> in Figure 18-21 correspo nd to <1> to <5> in 18.8.5 (previous page).
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An example of a program list that shifts the mode to normal mode is shown below.
;----------------------------
;START
;----------------------------
ModeOffLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#00H ; FLPMC register control (sets value)
MOV FLPMC,#0FFH ; FLPMC register control (inverts set value)
MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOffLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
;----------------------------
;END
;----------------------------
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18.8.6 Example of block erase operation in self programming mode
An example of the block erase operation in self programming mode is explained below.
<1> Set 03H (block erase) to the flash program command register (FLCMD).
<2> Set the block number to be erased, to flash address pointer H (FLAPH).
<3> Set flash address pointer L (FLAPL) to 00H.
<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the flash address pointer L compare register (FLAPLC) to 00H.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 ( VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Nor mal → <11>
<10> Block erase processing is abnormally term inated.
<11> Block erase processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
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Figure 18-22. Example of Block Erase Operation in Self Programming Mode
<11> Normal termination
<7> Clear & restart WDT counter
(WDTE = ACH)Note
<9> Check execution result
(VCERR and WEPRERR flags)
<8> Execute HALT instruction
Normal
<6> Clear PFS
<1> Set erase command
(FLCMD = 03H)
<2> Set no. of block to be erased
to FLAPH
Block erasure
<4> Set the same value as
that of FLAPH to FLAPHC
<10> Abnormal termination
Abnormal
<3> Set FLAPL to 00H
<5> Set FLAPLC to 00H
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11> in Figure 18-22 correspond to < 1> to <11> in 18.8.6 (previous page).
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An example of a program list that performs a block erase in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashBlockErase:
MOV FLCMD,#03H ; Sets flash control command (block erase)
MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH)
MOV FLAPLC,#00H ; Fixes FLAPLC to “00H”
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
MOV CmdStatus,A ; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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18.8.7 Example of block blank check operation in self programming mode
An example of the block blank check operation in self programming mode is explained below.
<1> Set 04H (block blank check) to the flash program command register (FLCMD).
<2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH).
<3> Set flash address pointer L (FLAPL) to 00H.
<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Set the flash address pointer L compare register (FLAPLC) to FFH.
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 ( VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Nor mal → <11>
<10> Block blank check is abnormally terminated.
<11> Block blank check is normally terminated.
Note This setting is not requ ired w hen the watchdog timer is not used.
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Figure 18-23. Example of Block Blank Check Operation in Self Programming Mode
<11> Normal termination
<7> Clear & restart WDT counter
(WDTE = ACH)
Note
<9> Check execution result
(VCERR and WEPRERR flags)
<8> Execute HALT instruction
Normal
Abnormal
<6> Clear PFS
<1> Set
block blank check
command (FLCMD = 04H)
<2> Set no. of block for
blank check to FLAPH
Block blank check
<10> Abnormal termination
<5> Set FLAPLC to 00H
<4> Set the same value as
that of FLAPH to FLAPHC
<3> Set FLAPL to 00H
Note This setting is not requ ired w hen the watchdog timer is not used.
Remark <1> to <11>in Figure 18-23 c orrespond to <1> to <11> in 18.8.7 (previous page).
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An example of a program list that performs a block blank check in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashBlockBlankCheck:
MOV FLCMD,#04H ; Sets flash control command (block blank check)
MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified
; here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of
; FLAPH)
MOV FLAPLC,#0FFH ; Fixes FLAPLC to “FFH”
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
MOV CmdStatus,A ; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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18.8.8 Example of byte write operation in self programming mode
An example of the byte write operation in self programming mode is explained below.
<1> Set 05H (byte write) to the flash program command register (FLCMD).
<2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH).
<3> Set the address at which data is to be written, to flash address pointer L (FLAPL).
<4> Set the data to be written, to the flash write buffer register (FLW ).
<5> Clear the flash status register (PFS).
<6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note.
<7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<8> Check if a self programming error has occurred using bit 1 ( VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <9>
Nor mal → <10>
<9> Byte write processing is abnormally terminated.
<10> Byte write processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
Caution If a write results in failure, erase the block once and write to it again.
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Figure 18-24. Example of Byte Write Operation in Self Programming Mode
<10> Normal termination
<6> Clear & restart WDT counter
(WDTE = ACH)
Note
<8> Check execution result
(VCERR and WEPRERR flags)
<7> Execute HALT instruction
Normal
Abnormal
<5> Clear PFS
<1> Set byte write command
(FLCMD = 05H)
Byte write
<9> Abnormal termination
<4> Set data to be written to FLW
<2> Set no. of block to be
written, to FLAPH
<3> Set address at which data
is to be written, to FLAPL
Note This setting is not requ ired w hen the watchdog timer is not used.
Remark <1> to <10> in Figure 18-24 correspond to <1> to <10> in 18.8.8 (previous page).
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An example of a program list that performs a byte write in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashWrite:
MOV FLCMD,#05H ; Sets flash control command (byte write)
MOV FLAPH,#07H ; Sets address to which data is to be written, with
; FLAPH (block 7 is specified here)
MOV FLAPL,#20H ; Sets address to which data is to be written, with
; FLAPL (address 20H is specified here)
MOV FLW,#10H ; Sets data to be written (10H is specified here)
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
MOV CmdStatus,A ; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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18.8.9 Example of internal verify operation in self programming mode
An example of the internal verify operation in self programming mode is explained below.
<1> Set 01H (internal verify) to the flash program command register (FLCMD).
<2> Set the number of block for which internal verify is performed, to flash address pointer H (FLAPH).
<3> Sets the verify start address to flash address pointer L (FLAPL).
<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).
<5> Sets the verify end address to the flash address pointer L compare register (FLAPLC).
<6> Clear the flash status register (PFS).
<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)Note.
<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the
HALT instruction if self programming has been executed.)
<9> Check if a self programming error has occurred using bit 1 ( VCERR) and bit 2 (WEPRERR) of PFS.
Abnormal → <10>
Nor mal → <11>
<10> Internal verify processing is abnormally terminated.
<11> Internal verify processing is normally terminated.
Note This setting is not required when the watchdog timer is not used.
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Figure 18-25. Example of Internal Verify Operation in Self Programming Mode
<11> Normal termination
<7> Clear & restart WDT counter
(WDTE = ACH)Note
<9> Check execution result
(VCERR and WEPRERR flags)
<8> Execute HALT instruction
Normal
Abnormal
<6> Clear PFS
<1> Set internal verify
command (FLCMD = 01H)
Internal verify
<10> Abnormal termination
<2> Set no. of block for
internal verify, to FLAPH
<4> Set the same value as
that of FLAPH to FLAPHC
<5>
Set end address to
FLAPLC
<3> Set start address to FLAPL
Note This setting is not required when the watchdog timer is not used.
Remark <1> to <11> in Figure 18-25 correspond to < 1> to <11> in 18.8.9 (previous page).
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An example of a program list that performs an internal verify in self programming mode is shown below.
;----------------------------
;START
;----------------------------
FlashVerify:
MOV FLCMD,#01H ; Sets flash control command (internal verify)
MOV FLAPH,#07H ; Sets verify start address with FLAPH (block 7 is specified
; here)
MOV FLAPL,#00H ; Sets verify start address with FLAPL (Address 00H is
; specified here)
MOV FLAPHC,#07H
MOV FLAPLC,#20H ; Sets verify end address
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
MOV CmdStatus,A ; Execution result is stored in variable
; (CmdStatus = 0: normal termination, other than 0: abnormal
; termination)
;----------------------------
;END
;----------------------------
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18.8.10 Examples of operation when command execution time should be minimized in self programming
mode
Examples of operation when the command execution time should be minimized in self programming mode are
explained below.
(1) Erasure to blank check
<1> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<2> Execution of block erase → Error check (<1> to <11> in 18.8.6)
<3> Execution of block blank check → Error check (<1> to <11> in 18.8.7)
<4> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
Figure 18-26. Example of Operation When Command Execution Time Should Be Minimized
(from Erasure to Blank Check)
<4> Shift to normal mode
Abnormal
<1> Shift to self programming
mode
Erasure to blank check
Abnormal termination
Note
<2> Execute block erase
<3> Execute block blank check
<2> Check execution result
(VCERR and WEPRERR flags)
<3> Check execution result
(VCERR and WEPRERR flags)
Normal termination
Normal
Abnormal
Normal
Figure 18-22
<1> to <11>
Figure 18-23
<1> to <11>
Figure 18-20
<1> to <5>
Figure 18-21
<1> to <5>
Note Perform processing to shift to normal mode i n order to return to normal processing.
Remark <1> to <4> in Figure 18-26 correspond to <1> to <4> in 18.8.10 (1) above.
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An example of a program list when the command execution time (from erasure to black check) should be
minimized in self programmin g mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
MOV MK0,#11111111B ; Masks all interrupts
MOV MK1,#11111111B
DI
ModeOnLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#01H ; FLPMC register control (sets value)
MOV FLPMC,#0FEH ; FLPMC register control (inverts set value)
MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control (sets
; value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOnLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
FlashBlockErase:
MOV FLCMD,#03H ; Sets flash control command (block erase)
MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified
; here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of
; FLAPH)
MOV FLAPLC,#00H ; Fixes FLAPLC to “00H”
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks erase error
; Performs abnormal termination processing when an error
; occurs.
FlashBlockBlankCheck:
MOV FLCMD,#04H ; Sets flash control command (block blank check)
MOV FLAPH,#07H ; Sets number of block for blank check (block 7 is specified
; here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
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MOV FLAPHC,#07H ; Sets blank check block compare number (same value as of
; FLAPH)
MOV FLAPLC,#0FFH ; Fixes FLAPLC to “FFH”
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks blank check error
; Performs abnormal termination processing when an error
; occurs.
ModeOffLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#00H ; FLPMC register control (sets value)
MOV FLPMC,#0FFH ; FLPMC register control (inverts set value)
MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOffLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
BR StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
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(2) Write to internal verify
<1> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<2> Specification of source data for write
<3> Execution of byte write → Error check (<1> to <10> in 18.8.8)
<4> <3> is repeated until all data are written.
<5> Execution of internal verify → Error check (<1> to <11> in 18.8.9)
<6> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
Figure 18-27. Example of Operation When Command Execution Time Should Be Minimized
(from Write to Internal V erify)
<6> Shift to normal mode
Abnormal
<1> Shift to self programming
mode
Write to internal verify
<3> Execute byte write command
<5> Execute internal verify command
<3> Check execution result
(VCERR and WEPRERR flags)
<5> Check execution result
(VCERR and WEPRERR flags)
Normal termination
Normal
Abnormal
Normal
Figure 18-
24
<1> to <10>
Figure 18-
25
<1> to <11>
Figure 18-21
<1> to <5>
<2> Set source data for write
<4> All data written? Yes
No
Figure 18-20
<1> to <5>
Abnormal termination
Note
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <6> in Figure 18-27 correspo nd to <1> to <6> in 18.8.10 (2) above.
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An example of a program l ist when the com mand execution ti me (from write to interna l verify) should be minim ized
in self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
MOV MK0,#11111111B ; Masks all interrupts
MOV MK1,#11111111B
DI
ModeOnLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#01H ; FLPMC register control (sets value)
MOV FLPMC,#0FEH ; FLPMC register control (inverts set value)
MOV FLPMC,#01H ; Sets self programming mode with FLPMC register control
; (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOnLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
FlashWrite:
MOVW HL,#DataAdrTop ; Sets address at which data to be written is located
MOVW DE,#WriteAdr ; Sets address at which data is to be written
FlashWriteLoop:
MOV FLCMD,#05H ; Sets flash control command (byte write)
MOV A,D
MOV FLAPH,A ; Sets address at which data is to be written
MOV A,E
MOV FLAPL,A ; Sets address at which data is to be written
MOV A,[HL]
MOV FLW,A ; Sets data to be written
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks write error
; Performs abnormal termination processing when an error
; occurs.
INCW HL ; address at which data to be written is located + 1
MOVW AX,HL
CMPW AX,#DataAdrBtm ; Performs internal verify processing
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BNC $FlashVerify ; if write of all data is completed
INCW DE ; Address at which data is to be written + 1
BR FlashWriteLoop
FlashVerify:
MOVW HL,#WriteAdr ; Sets verify address
MOV FLCMD,#01H ; Sets flash control command (internal verify)
MOV A,H
MOV FLAPH,A ; Sets verify start address
MOV A,L
MOV FLAPL,A ; Sets verify start address
MOV A,D
MOV FLAPHC,A ; Sets verify end address
MOV A,E
MOV FLAPLC,A ; Sets verify end address
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks internal verify error
; Performs abnormal termination processing when an error
; occurs.
ModeOffLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#00H ; FLPMC register control (sets value)
MOV FLPMC,#0FFH ; FLPMC register control (inverts set value)
MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOffLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
BR StatusNormal
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;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
; Data to be written
;---------------------------------------------------------------------
DataAdrTop:
DB XXH
DB XXH
DB XXH
DB XXH
：
：
DB XXH
DataAdrBtm:
;---------------------------------------------------------------------
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18.8.11 Examples of operation when interrupt-disab led time should be minimized in self programming mode
Examples of operation when the interrupt-disabled time should be minimized in self programming mode are
explained below.
(1) Erasure to blank check
<1> Specification of block erase command (<1> to <5> in 18.8.6)
<2> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<3> Execution of block erase command → Error check (<6> to <11> in 18.8.6)
<4> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
<5> Specification of block blank check command (<1> to <5> in 18.8.7)
<6> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<7> Execution of block blank check command → Error check (<6> to <11> in 18.8.7)
<8> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
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Figure 18-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized
(from Erasure to Blank Check)
Abnormal
Erasure to blank check
Abnormal termination
Note
<1> Specify block erase command
<3> Check execution result
(VCERR and WEPRERR flags)
Normal termination
Normal
Abnormal
Figure 18-22
<1> to <5>
<2> Shift to self programming
mode
Figure 18-20
<1> to <5>
<3> Execute block erase command
Figure 18-22
<6> to <11>
<4> Shift to normal mode
Figure 18-21
<1> to <5>
<5> Specify block blank
check command
<7> Check execution result
(VCERR and WEPRERR flags)
Figure 18-23
<1> to <5>
<6> Shift to self programming
mode
Figure 18-20
<1> to <5>
<7> Execute block blank
check command
Figure 18-23
<6> to <11>
<8> Shift to normal mode
Figure 18-21
<1> to <5>
Normal
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <8> in Figure 18-28 correspond to <1> to <8> in 18.8.11 (1) (previous page).
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An example of a program list when the interrupt-disabled time (from erasure to blank check) should be minimize d
in self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
FlashBlockErase:
; Sets erase command
MOV FLCMD,#03H ; Sets flash control command (block erase)
MOV FLAPH,#07H ; Sets number of block to be erased (block 7 is specified here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
MOV FLAPHC,#07H ; Sets erase block compare number (same value as that of FLAPH)
MOV FLAPLC,#00H ; Fixes FLAPLC to “00H”
CALL !ModeOn ; Shift to self programming mode
; Execution of erase command
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks erase error
; Performs abnormal termination processing when an error
; occurs.
CALL !ModeOff ; Shift to normal mode
; Sets blank check command
MOV FLCMD,#04H ; Sets flash control command (block blank check)
MOV FLAPH,#07H ; Sets block number for blank check (block 7 is specified here)
MOV FLAPL,#00H ; Fixes FLAPL to “00H”
MOV FLAPHC,#07H ; Sets blank check block compare number (same value as that of
; FLAPH)
MOV FLAPLC,#0FFH ; Fixes FLAPLC to “FFH”
CALL !ModeOn ; Shift to self programming mode
; Execution of blank check command
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks blank check error
; Performs abnormal termination processing when an error occurs
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CALL !ModeOff ; Shift to normal mode
BR StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
;Processing to shift to self programming mode
;---------------------------------------------------------------------
ModeOn:
MOV MK0,#11111111B ; Masks all interrupts
MOV MK1,#11111111B
DI
ModeOnLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#01H ; FLPMC register control (sets value)
MOV FLPMC,#0FEH ; FLPMC register control (inverts set value)
MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets
; value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOnLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
RET
;---------------------------------------------------------------------
; Processing to shift to normal mode
;---------------------------------------------------------------------
ModeOff:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#00H ; FLPMC register control (sets value)
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MOV FLPMC,#0FFH ; FLPMC register control (inverts set value)
MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOff ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs。
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
RET
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(2) Write to internal verify
<1> Specification of source data for write
<2> Specification of byte write command (< 1> to <4> in 18.8.8)
<3> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<4> Execution of byte write command → Error check (<5> to <10> in 18.8.8)
<5> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
<6> <2> to <5> is repeated until al l data are written.
<7> The inter nal verify command is specified (<1> to <5> in 18.8.9)
<8> Mode is shifted from normal mode to self programming mode (<1> to <5> in 18.8.4)
<9> Execution of internal verify command → Error check (<6> to <11> in 18.8.9)
<10> Mode is shifted from self programming mode to normal mode (<1> to <5> in 18.8.5)
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Figure 18-29. Example of Operation When Interrupt-Disabled Time Should Be Minimized
(from Write to Internal V erify)
Abnormal
Abnormal termination
Note
<2> Specify byte write command
<4> Check execution result
(VCERR and WEPRERR flags)
Normal termination
Normal
Abnormal
Figure 18-24
<1> to <4>
<3> Shift to self programming
mode
Figure 18-20
<1> to <5>
<4> Execute byte write command
Figure 18-24
<5> to <10>
<5> Shift to normal mode
Figure 18-21
<1> to <5>
<7> Specify internal verify command
<9> Check execution result
(VCERR and WEPRERR flags)
Figure 18-25
<1> to <5>
<8> Shift to self programming
mode
Figure 18-20
<1> to <5>
<9> Execute internal verify command
Figure 18-25
<6> to <10>
<10> Shift to normal mode
Figure 18-21
<1> to <5>
Normal
<1> Set source data for write
Write to internal verify
<6> All data written? Yes
No
Note Perform processing to shift to normal mode in order to return to normal processing.
Remark <1> to <10> in Figure 18-29 correspond to <1> to <10> in 18.8.11 (2) (previous page).
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An example of a program list when the interrupt-dis abled time (from write to internal verify) should be minimized i n
self programming mode is shown below.
;---------------------------------------------------------------------
;START
;---------------------------------------------------------------------
; Sets write command
FlashWrite:
MOVW HL,#DataAdrTop ; Sets address at which data to be written is located
MOVW DE,#WriteAdr ; Sets address at which data is to be written
FlashWriteLoop:
MOV FLCMD,#05H ; Sets flash control command (byte write)
MOV A,D
MOV FLAPH,A ; Sets address at which data is to be written
MOV A,E
MOV FLAPL,A ; Sets address at which data is to be written
MOV A,[HL]
MOV FLW,A ; Sets data to be written
CALL !ModeOn ; Shift to self programming mode
; Execution of write command
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks write error
; Performs abnormal termination processing when an error
; occurs.
CALL !ModeOff ; Shift to normal mode
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
; Judgment of writing all data
INCW HL ; Address at which data to be written is located + 1
MOVW AX,HL
CMPW AX,#DataAdrBtm ; Performs internal verify processing
BNC $FlashVerify ; if write of all data is completed
INCW DE ; Address at which data is to be written + 1
BR FlashWriteLoop
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; Setting internal verify command
FlashVerify:
MOVW HL,#WriteAdr ; Sets verify address
MOV FLCMD,#01H ; Sets flash control command (internal verify)
MOV A,H
MOV FLAPH,A ; Sets verify start address
MOV A,L
MOV FLAPL,A ; Sets verify start address
MOV A,D
MOV FLAPHC,A ; Sets verify end address
MOV A,E
MOV FLAPLC,A ; Sets verify end address
CALL !ModeOn ; Shift to self programming mode
; Execution of internal verify command
MOV PFS,#00H ; Clears flash status register
MOV WDTE,#0ACH ; Clears & restarts WDT
HALT ; Self programming is started
MOV A,PFS
CMP A,#00H
BNZ $StatusError ; Checks internal verify error
; Performs abnormal termination processing when an error occurs
CALL !ModeOff ; Shift to normal mode
BR StatusNormal
;---------------------------------------------------------------------
;END (abnormal termination processing); Perform processing to shift to
normal mode in order to return to normal processing
;---------------------------------------------------------------------
StatusError:
;---------------------------------------------------------------------
;END (normal termination processing)
;---------------------------------------------------------------------
StatusNormal:
;---------------------------------------------------------------------
;Processing to shift to self programming mode
;---------------------------------------------------------------------
ModeOn:
MOV MK0,#11111111B ; Masks all interrupts
MOV MK1,#11111111B
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DI
ModeOnLoop:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#01H ; FLPMC register control (sets value)
MOV FLPMC,#0FEH ; FLPMC register control (inverts set value)
MOV FLPMC,#01H ; Sets self programming mode via FLPMC register control (sets
; value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOnLoop ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs
RET
;---------------------------------------------------------------------
; Processing to shift to normal mode
;---------------------------------------------------------------------
ModeOff:
MOV PFS,#00H
MOV PFCMD,#0A5H ; PFCMD register control
MOV FLPMC,#00H ; FLPMC register control (sets value)
MOV FLPMC,#0FFH ; FLPMC register control (inverts set value)
MOV FLPMC,#00H ; Sets normal mode via FLPMC register control (sets value)
MOV A,PFS
CMP A,#00H
BNZ $ModeOff ; Checks completion of write to specific registers
; Repeats the same processing when an error occurs。
MOV MK0,#INT_MK0 ; Restores interrupt mask flag
MOV MK1,#INT_MK1
EI
RET
;---------------------------------------------------------------------
;Data to be written
;---------------------------------------------------------------------
DataAdrTop:
DB XXH
DB XXH
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DB XXH
DB XXH
:
:
DB XXH
DataAdrBtm:
;---------------------------------------------------------------------
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CHAPTER 19 INSTRUCTION SET OVERVIEW
This chapter lists the instruction set of the 78K0S/KA1+. For details of the operation and machine language
(instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E).
19.1 Operation
19.1.1 Operand identifiers and description methods
Operands are described in “Operand” column of each i nstruction in acco rdance with the description method of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more
description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are
described as they are. Each symbol has the following meaning.
• #: Immediate data specific ation
• !: Absolute address specification
• $: Relative address specification
• [ ]: Indirect address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, $ and [ ] symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in the table below, R0, R1, R2, etc.) can be used for descri ption.
Table 19-1. Operand Identifiers and Description Methods
Identifier Description Method
r
rp
sfr
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
saddr
saddrp FE20H to FF1FH Immediate data or labels
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5 0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark For symbols of special function registers, see Table 4-3 Special Function Registers.
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19.1.2 Description of “Operation” column
A: A register; 8-bit accumulator
X: X register
B: B register
C: C register
D: D register
E: E register
H: H register
L: L register
AX: AX register pair; 16-bit accumulator
BC: BC register pair
DE: DE register pair
HL: HL register pair
PC: Program counter
SP: Stack pointer
PSW: Program status word
CY: Carry flag
AC: Auxiliary carr y flag
Z: Zero flag
IE: Interrupt request enable flag
( ): Memory contents indicated by address or register contents in parentheses
×H, ×L: Higher 8 bits and lower 8 bits of 16-bit register
∧: Logical product (AND)
∨: Logical sum (OR)
∨: Exclusive logical sum (exclusive OR)
: Inverted data
addr16: 16-bit immediate data or label
jdisp8: Sign ed 8-bit data (displacement value)
19.1.3 Description of “Flag” column
(Blank): Unchanged
0: Cleared to 0
1: Set to 1
×: Set/cleared according to the result
R: Previously saved value is stored
CHAPTER 19 INSTRUCTION SET OVERVIEW
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19.2 Operation List
Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
r, #byte 3 6 r ← byte
saddr, #byte 3 6 (saddr) ← byte
sfr, #byte 3 6 sfr ← byte
A, r Note 1 2 4 A ← r
r, A Note 1 2 4 r ← A
A, saddr 2 4 A ← (saddr)
saddr, A 2 4 (saddr) ← A
A, sfr 2 4 A ← sfr
sfr, A 2 4 sfr ← A
A, !addr16 3 8 A ← (addr16)
!addr16, A 3 8 (addr16) ← A
PSW, #byte 3 6 PSW ← byte × × ×
A, PSW 2 4 A ← PSW
PSW, A 2 4 PSW ← A × × ×
A, [DE] 1 6 A ← (DE)
[DE], A 1 6 (DE) ← A
A, [HL] 1 6 A ← (HL)
[HL], A 1 6 (HL) ← A
A, [HL + byte] 2 6 A ← (HL + byte)
MOV
[HL + byte], A 2 6 (HL + byte) ← A
A, X 1 4 A ↔ X
A, r Note 2 2 6 A ↔ r
A, saddr 2 6 A ↔ (saddr)
A, sfr 2 6 A ↔ sfr
A, [DE] 1 8 A ↔ (DE)
A, [HL] 1 8 A ↔ (HL)
XCH
A, [HL, byte] 2 8 A ↔ (HL + byte)
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
rp, #word 3 6 rp ← word
AX, saddrp 2 6 AX ← (saddrp)
saddrp, AX 2 8 (saddrp) ← AX
AX, rp Note 1 4 AX ← rp
MOVW
rp, AX Note 1 4 rp ← AX
XCHW AX, rp Note 1 8 AX ↔ rp
A, #byte 2 4 A, CY ← A + byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte × × ×
A, r 2 4 A, CY ← A + r × × ×
A, saddr 2 4 A, CY ← A + (saddr) × × ×
A, !addr16 3 8 A, CY ← A + (addr16) × × ×
A, [HL] 1 6 A, CY ← A + (HL) × × ×
ADD
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) × × ×
A, #byte 2 4 A, CY ← A + byte + CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) + byte + CY × × ×
A, r 2 4 A, CY ← A + r + CY × × ×
A, saddr 2 4 A, CY ← A + (saddr) + CY × × ×
A, !addr16 3 8 A, CY ← A + (addr16) + CY × × ×
A, [HL] 1 6 A, CY ← A + (HL) + CY × × ×
ADDC
A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY × × ×
A, #byte 2 4 A, CY ← A − byte × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte × × ×
A, r 2 4 A, CY ← A − r × × ×
A, saddr 2 4 A, CY ← A − (saddr) × × ×
A, !addr16 3 8 A, CY ← A − (addr16) × × ×
A, [HL] 1 6 A, CY ← A − (HL) × × ×
SUB
A, [HL + byte] 2 6 A, CY ← A − (HL + byte) × × ×
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A, CY ← A − byte − CY × × ×
saddr, #byte 3 6 (saddr), CY ← (saddr) − byte − CY × × ×
A, r 2 4 A, CY ← A − r − CY × × ×
A, saddr 2 4 A, CY ← A − (saddr) − CY × × ×
A, !addr16 3 8 A, CY ← A − (addr16) − CY × × ×
A, [HL] 1 6 A, CY ← A − (HL) − CY × × ×
SUBC
A, [HL + byte] 2 6 A, CY ← A − (HL + byte) − CY × × ×
A, #byte 2 4 A ← A ∧ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∧ byte ×
A, r 2 4 A ← A ∧ r ×
A, saddr 2 4 A ← A ∧ (saddr) ×
A, !addr16 3 8 A ← A ∧ (addr16) ×
A, [HL] 1 6 A ← A ∧ (HL) ×
AND
A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×
A, #byte 2 4 A ← A ∨ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r ×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
OR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×
A, #byte 2 4 A ← A ∨ byte ×
saddr, #byte 3 6 (saddr) ← (saddr) ∨ byte ×
A, r 2 4 A ← A ∨ r ×
A, saddr 2 4 A ← A ∨ (saddr) ×
A, !addr16 3 8 A ← A ∨ (addr16) ×
A, [HL] 1 6 A ← A ∨ (HL) ×
XOR
A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
A, #byte 2 4 A − byte × × ×
saddr, #byte 3 6 (saddr) − byte × × ×
A, r 2 4 A − r × × ×
A, saddr 2 4 A − (saddr) × × ×
A, !addr16 3 8 A − (addr16) × × ×
A, [HL] 1 6 A − (HL) × × ×
CMP
A, [HL + byte] 2 6 A − (HL + byte) × × ×
ADDW AX, #word 3 6 AX, CY ← AX + word × × ×
SUBW AX, #word 3 6 AX, CY ← AX − word × × ×
CMPW AX, #word 3 6 AX − word × × ×
r 2 4 r ← r + 1 × × INC
saddr 2 4 (saddr) ← (saddr) + 1 × ×
r 2 4 r ← r − 1 × × DEC
saddr 2 4 (saddr) ← (saddr) − 1 × ×
INCW rp 1 4 rp ← rp + 1
DECW rp 1 4 rp ← rp − 1
ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 ×
ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 ×
RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 ×
ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×
saddr.bit 3 6 (saddr.bit) ← 1
sfr.bit 3 6 sfr.bit ← 1
A.bit 2 4 A.bit ← 1
PSW.bit 3 6 PSW.bit ← 1 × × ×
SET1
[HL].bit 2 10 (HL).bit ← 1
saddr.bit 3 6 (saddr.bit) ← 0
sfr.bit 3 6 sfr.bit ← 0
A.bit 2 4 A.bit ← 0
PSW.bit 3 6 PSW.bit ← 0 × × ×
CLR1
[HL].bit 2 10 (HL).bit ← 0
SET1 CY 1 2 CY ← 1 1
CLR1 CY 1 2 CY ← 0 0
NOT1 CY 1 2 CY ← CY ×
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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Flag Mnemonic Operand Bytes Clocks Operation
Z AC CY
CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT [addr5] 1 8 (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP − 2
RET 1 6 PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI 1 8 PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2),
SP ← SP + 3 R R R
PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1 PUSH
rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL, SP ← SP − 2
PSW 1 4 PSW ← (SP), SP ← SP + 1 R R R POP
rp 1 6 rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP, AX 2 8 SP ← AX MOVW
AX, SP 2 6 AX ← SP
!addr16 3 6 PC ← addr16
$addr16 2 6 PC ← PC + 2 + jdisp8
BR
AX 1 6 PCH ← A, PCL ← X
BC $saddr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1
BNC $saddr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0
BZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1
BNZ $saddr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0
saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 1
BT
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1
saddr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
sfr.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr16 3 8 PC ← PC + 3 + jdisp8 if A.bit = 0
BF
PSW.bit, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 0
B, $addr16 2 6 B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16 2 6 C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
DBNZ
saddr, $addr16 3 8 (saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP 1 2 No Operation
EI 3 6 IE ← 1 (Enable Interrupt)
DI 3 6 IE ← 0 (Disable Interrupt)
HALT 1 2 Set HALT Mode
STOP 1 2 Set STOP Mode
Remark One instruction clock cycle is one CPU clock cycle (fCPU) selected by the processor clock control
register (PCC).
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19.3 Instructions Listed by Addressing Type
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd Operand
1st Operand
#byte A r sfr saddr !addr16 PSW [DE] [HL]
[HL + byte] $addr16 1 None
A ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOVNote
XCHNote
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV MOV
XCH
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV
XCH
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
ROR
ROL
RORC
ROLC
r MOV MOV INC
DEC
B, C DBNZ
sfr MOV MOV
saddr MOV
ADD
ADDC
SUB
SUBC
AND
OR
XOR
CMP
MOV DBNZ INC
DEC
!addr16 MOV
PSW MOV MOV PUSH
POP
[DE] MOV
[HL] MOV
[HL + byte] MOV
Note Except r = A.
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(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd Operand
1st Operand
#word AX rpNote saddrp SP None
AX ADDW SUBW
CMPW MOVW
XCHW MOVW MOVW
rp MOVW MOVWNote INCW
DECW
PUSH
POP
saddrp MOVW
sp MOVW
Note Only when rp = BC, DE, or HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd Operand
1st Operand
$addr16 None
A.bit BT
BF SET1
CLR1
sfr.bit BT
BF SET1
CLR1
saddr.bit BT
BF SET1
CLR1
PSW.bit BT
BF SET1
CLR1
[HL].bit SET1
CLR1
CY SET1
CLR1
NOT1
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(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ
2nd Operand
1st Operand
AX !addr16 [addr5] $addr16
Basic instructions BR CALL
BR CALLT BR
BC
BNC
BZ
BNZ
Compound instructions DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
These specifications are only target values, and may not be satisfied by mass-produced products.
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbol Conditions Ratings Unit
VDD −0.3 to +6.5 V
VSS −0.3 to +0.3 V
Supply voltage
AVREF −0.3 to VDD + 0.3Note V
VI1 P30, P31, P34, P40 to P45, P121 to P123 −0.3 to VDD + 0.3Note V Input voltage
VI2 P20 to 23 − 0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note V
Output voltage VO −0.3 to VDD + 0.3Note V
Analog input voltage VAN − 0.3 to AVREF + 0.3Note
and −0.3 to VDD + 0.3Note V
Per pin −10 mA Output current, high IOH
Total of pins other than P20 to P23 −44 mA
Per pin 20 mA Output current, low IOL
Total of all pins 44 mA
In normal operation mode
Operating ambient
temperature TA
During flash memory programming
−40 to +85 °C
Storage temperature Tstg −40 to +125 °C
Note Must be 6.5 V or lower
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
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X1 Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1)
Resonator Recommended Circuit Parameter Conditions MIN. TYP. MAX. Unit
Ceramic
resonator
X2X1VSS
C2C1
Oscillation
frequency (fX)Note 2 1 10.0 MHz
Crystal
resonator
X2X1V
SS
C2C1
Oscillation
frequency (fX)Note 2 1 10.0 MHz
2.7 V ≤ VDD ≤ 5.5 V 1 10.0
X1 input
frequency (fX)Note 2 2.0 V ≤ VDD < 2.7 V 1 5.0
MHz
2.7 V ≤ VDD ≤ 5.5 V 0.045 0.5
External
clock
X1
X1 input high-
/low-level width
(tXH, tXL) 2.0 V ≤ VDD < 2.7 V 0.09 0.5
µ
s
Notes 1. Use this produ ct in a voltage range of 2.2 to 5.5 V because the detecti on voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristic s for instruction execution time.
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation
themselves or apply to the resonator manufacturer for evaluation.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
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High-Speed Ring-OSC Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 7.60 8.00 8.40 MHz On-chip high-speed Ring-OSC Oscillation frequency (fX)Note 2
2.0 V ≤ VDD < 2.7 V T.B.D MHz
Notes 1. Use this produ ct in a voltage range of 2.2 to 5.5 V because the detecti on voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
2. Indicates only oscillator characteristics. Refer to AC Characteristic s for instruction execution time.
Low-Speed Ring-OSC Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote)
Resonator Parameter Conditions MIN. TYP. MAX. Unit
On-chip low-speed Ring-OSC Oscillation frequency (fRL) 120 240 480 kHz
Note Use this product in a voltage rang e of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-o n-clear
(POC) circuit is 2.1 V ±0.1 V.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
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DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 2.0 V ≤ VDD ≤ 5.5 V –5 mA
4.0 V ≤ VDD ≤ 5.5 V –25 mA
IOH1 Pins other than
P20 to P23 Total
2.0 V ≤ VDD < 4.0 V –15 mA
Per pin 2.0 V ≤ AVREF ≤ 5.5 V –5 mA
Output current, high
IOH2 P20 to P23
Total 2.0 V ≤ AVREF ≤ 5.5 V –15 mA
Per pin 2.0 V ≤ VDD ≤ 5.5 V 10 mA
4.0 V ≤ VDD ≤ 5.5 V 30 mA
Output current, low IOL
Total of all pins
2.0 V ≤ VDD < 4.0 V 15 mA
VIH1 P30, P31, P34, P40 to P45, P123 0.8VDD VDD V
VIH2 P20 to P23 0.7AVREF AVREF V
Input voltage, high
VIH3 P121, P122 0.8VDD VDD V
VIL1 P30, P31, P34, P40 to P45, P123 0 0.2VDD V
VIL2 P20 to P23 0 0.3AVREF V
Input voltage, low
VIL3 P121, P122 0 0.3VDD V
Total of pins other than
P20 to P23
IOH1 = –15 mA
4.0 V ≤ VDD ≤ 5.5 V
IOH1 = –5 mA VDD − 1.0 V VOH1
IOH1 = –100
µ
A 2.0 V ≤ VDD < 4.0 V VDD – 0.5 V
4.0 V ≤ AVREF ≤ 5.5 V
IOH2 = –5 mA AVREF – 1.0 V
Output voltage, high
VOH2 Total of pins P20 to P23
IOH2 = –10 mA
2.0 V ≤ AVREF < 4.0 V
IOH2 = –5 mA AVREF – 0.5 V
Total of pins
IOL = 30 mA 4.0 V ≤ VDD ≤ 5.5 V
IOL = 10 mA 1.3 V
Output voltage, low VOL
2.0 V ≤ VDD ≤ 4.0 V
IOL = 400
µ
A 0.4 V
Input leakage current, high ILIH1 VI = VDD Pins other than X1 3
µ
A
Input leakage current, low ILIL1 VI = 0 V Pins other than X1 –3
µ
A
Output leakage current, high ILOH VO = VDD Pins other than X2 3
µ
A
Output leakage current, low ILOL VO = 0 V Pins other than X2 –3
µ
A
Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V POC) of the power-on-clear
(POC) circuit is 2.1 V ±0.1 V.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
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DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Pull-up
resistance RPU VI = 0 V 10 30 100 kΩ
Pull-down
resistance RPD P121, P122, reset status 10 30 100 kΩ
When A/D converter is stopped 6.1 12.2
fX = 10 MHz
VDD = 5.0 V ±10%Note 4
When A/D converter is operating
Note 8 7.6 15.2
mA
When A/D converter is stopped 5.5 11.0
fX = 6 MHz
VDD = 5.0 V ±10%Note 4
When A/D converter is operating
Note 8 14.0
mA
When A/D converter is stopped 3.0 6.0
IDD1Note 3 Crystal/ceramic
oscillation, external
clock input
oscillation operating
modeNote 6
fX = 5 MHz
VDD = 3.0 V ±10%Note 5
When A/D converter is operating
Note 8 4.5 9.0
mA
When peripheral functions are stopped
1.7 3.8
fX = 10 MHz
VDD = 5.0 V ±10%Note 4
When peripheral functions are operating
6.7
mA
When peripheral functions are stopped
1.3 3.0
fX = 6 MHz
VDD = 5.0 V ±10%Note 4
When peripheral functions are operating
6.0
mA
When peripheral functions are stopped
0.48 1
IDD2 Crystal/ceramic
oscillation, external
clock input HALT
modeNote 6
fX = 5 MHz
VDD = 3.0 V ±10%Note 5
When peripheral functions are operating
2.1
mA
When A/D converter is stopped 5.5 11.0IDD3 High-speed Ring-OSC
operating modeNote 7 fX = 8 MHz
VDD = 5.0 V ±10%Note 4
When A/D converter is operating
Note 8 7.0 14.0
mA
When peripheral functions are stopped
1.4 3.2 IDD4 High-speed Ring-
OSC HALT modeNote 7 fX = 8 MHz
VDD = 5.0 V ±10%Note 4
When peripheral functions are operating
5.9
mA
When low-speed Ring-OSC is stopped
3.5 35.5VDD = 5.0 V ±10%
When low-speed Ring-OSC is operating
17.5 63.5
µ
A
When low-speed Ring-OSC is stopped
3.5 15.5
Supply
currentNote 2
IDD5 STOP mode
VDD = 3.0 V ±10%
When low-speed Ring-OSC is operating
11.0 30.5
µ
A
Notes 1. Use this produ ct in a voltage range of 2.2 to 5.5 V because the detecti on voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
2. Total current flowing through the internal power supply (VDD). Peripheral operation current is included
(however, the current that flows through the pull-up resistors of ports is not inclu ded).
3. I
DD1 includes peripheral operation current.
4. When the processor clock control register (PCC) is set to 00H.
5. When the processor clock control register (PCC) is set to 02H.
6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using
the option byte.
7. When the high-speed Ring-OSC is selected as the system clock source using the option byte.
8. The current that flows through the AVREF pin is included.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD
332
AC Characteristics
(1) Basic operati on (TA = −40 to +85°C, VDD = 2.0 to 5.5 VNote 1)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V 0.2 4
µ
s
3.0 V ≤ VDD < 4.0 V 0.33 4
µ
s
2.7 V ≤ VDD < 3.0 V 0.4 4
µ
s
Crystal/ceramic oscillation
clock, external clock input
2.0 V ≤ VDD < 2.7 V 1 4
µ
s
4.0 V ≤ VDD ≤ 5.5 V 0.23 4.22
µ
s
2.7 V ≤ VDD < 4.0 V 0.47 4.22
µ
s
Cycle time (minimum
instruction execution time) TCY
High-speed Ring-OSC
clock
2.0 V ≤ VDD < 2.7 V 0.95 4.22
µ
s
4.0 V ≤ VDD ≤ 5.5 V 2/fsam+
0.1Note 2
µ
s
TI000 input high-level width,
low-level width tTIH,
tTIL 2.0 V ≤ VDD < 4.0 V 2/fsam+
0.2Note 2
µ
s
Interrupt input high-level
width, low-level width tINTH,
tINTL
1
µ
s
RESET input low-level
width tRSL 2
µ
s
Notes 1. Use this produ ct in a voltage range of 2.2 to 5.5 V because the detecti on voltage (VPOC) of the power-on-
clear (POC) circuit is 2.1 V ±0.1 V.
2. Selection of fsam = fXP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, fsam = fXP.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD 333
TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input)
Supply voltage V
DD
[V]
123456
0.1
0.4
1.0
10
60
Cycle time T
CY
[ s]
Guaranteed
operation range
0.33
2.7 5.5
µ
TCY vs. VDD (High-speed Ring-OSC Clock)
123456
0.1
1.0
10
60
2.7 5.5
0.23
4.22
0.47
0.95
Supply voltage VDD [V]
Cycle time TCY [ s]
Guaranteed
operation range
µ
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD
334
(2) Serial interface (TA = −40 to +85°C, VDD = 2.0 to 5.5 V)
UART mode (UART6, dedicated baud rate generator output)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 312.5 kbps
AC Timing Test Points (Excluding X1 Input)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
Clock Timing
1/f
X
t
XL
t
XH
X1 input
TI000 Timing
t
TIL0
t
TIH0
TI000
Interrupt Input Timing
INTP0 to INTP3
t
INTL
t
INTH
RESET Input Timing
RESET
t
RSL
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD 335
A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = 0 VNote 1)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution 10 10 10 bit
4.0 V ≤ AVREF ≤ 5.5 V ±0.2 ±0.4 %FSR Overall errorNotes 2, 3 AINL
2.7 V ≤ AVREF < 4.0 V ±0.3 ±0.6 %FSR
4.5 V ≤ AVREF ≤ 5.5 V 3.0 100
µ
s
4.0 V ≤ AVREF < 4.5 V 4.8 100
µ
s
2.85 V ≤ AVREF < 4.0 V 6.0 100
µ
s
Conversion time tCONV
2.7 V ≤ AVREF < 2.85 V 14.0 100
µ
s
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR Zero-scale errorNotes 2, 3 Ezs
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±0.4 %FSR Full-scale errorNotes 2, 3 Efs
2.7 V ≤ AVREF < 4.0 V ±0.6 %FSR
4.0 V ≤ AVREF ≤ 5.5 V ±2.5 LSB Integral non-linearity errorNote 2 ILE
2.7 V ≤ AVREF < 4.0 V ±4.5 LSB
4.0 V ≤ AVREF ≤ 5.5 V ±1.5 LSB Differential non-linearity errorNote 2 DLE
2.7 V ≤ AVREF < 4.0 V ±2.0 LSB
Analog input voltage VAIN VSSNote 1 AVREF V
Notes 1. In the 78K0S/KA1+, VSS functions alternately as the ground potential of the A/D converter. Be sure to
connect VSS to a stabilized GND (= 0 V).
2. Excludes qua ntization error (±1/2 LSB).
3. This value is indicated as a ratio (%FSR) to the full-scale value.
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD
336
POC Circuit Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Detection voltage VPOC 2.0 2.1 2.2 V
Power supply boot time tPTH VDD: 0 V → 2.1 V 1.5
µ
s
Response delay time 1Note 1 tPTHD When power supply rises, after reaching
detection voltage (MAX.) 3.0 ms
Response delay time 2Note 2 tPD When power supply falls 1.0 ms
Minimum pulse width tPW 0.2 ms
Notes 1. Time required from voltage detection to internal reset release.
2. Time required from voltage detection to internal reset signal generation.
POC Circuit Timing
Supply voltage
(V
DD
)
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
PTH
t
PTHD
t
PW
t
PD
Time
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD 337
LVI Circuit Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVI0 4.1 4.3 4.5 V
VLVI1 3.9 4.1 4.3 V
VLVI2 3.7 3.9 4.1 V
VLVI3 3.5 3.7 3.9 V
VLVI4 3.3 3.5 3.7 V
VLVI5 3.15 3.3 3.45 V
VLVI6 2.95 3.1 3.25 V
VLVI7 2.7 2.85 3.0 V
VLVI8 2.5 2.6 2.7 V
Detection voltage
VLVI9 2.25 2.35 2.45 V
Response timeNote 1 tLD 0.2 2.0 ms
Minimum pulse width tLW 0.2 ms
Operation stabilization wait timeNote 2 tLWAIT 0.1 0.2 ms
Notes 1. Time required from voltage detection to interrupt output or internal reset signal generation.
2. Time required from setting LVION to 1 to operation stabilization.
Remarks 1. V
LVI0 > VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9
2. V
POC < VLVIm (m = 0 to 9)
LVI Circuit Timing
Supply voltage
(V
DD
)
Detection voltage (MIN.)
Detection voltage (TYP.)
Detection voltage (MAX.)
t
LW
t
LD
t
LWAIT
LVION 1 Time
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 2.0 5.5 V
Release signal set time tSREL 0
µ
s
CHAPTER 20 ELECTRICAL SPECIFICATIONS (TARGET VALUES)
Preliminary User’s Manual U16898EJ2V0UD
338
Flash Memory Programming Characteristics (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Supply current IDD VDD = 5.5 V 7.0 mA
TA = −10 to +85°C 1000 Times
Erasure countNote
(per 1 block) NERASE
TA = −40 to +85°C T.B.D. Times
4.5 V ≤ VDD ≤ 5.5 V 0.90 s
3.5 V ≤ VDD < 4.5 V 1.00 s
TA = −10 to +85°C,
NERASE ≤ 100
2.7 V ≤ VDD < 3.5 V 1.20 s
4.5 V ≤ VDD ≤ 5.5 V 3.52 s
3.5 V ≤ VDD < 4.5 V 3.92 s
TA = −10 to +85°C,
NERASE ≤ 1000
2.7 V ≤ VDD < 3.5 V 4.69 s
4.5 V ≤ VDD ≤ 5.5 V T.B.D. s
3.5 V ≤ VDD < 4.5 V T.B.D. s
TA = −40 to +85°C,
NERASE ≤ 100
2.7 V ≤ VDD < 3.5 V T.B.D. s
4.5 V ≤ VDD ≤ 5.5 V T.B.D. s
3.5 V ≤ VDD < 4.5 V T.B.D. s
Chip erase time TCERASE
TA = −40 to +85°C,
NERASE ≤ 1000
2.7 V ≤ VDD < 3.5 V T.B.D. s
4.5 V ≤ VDD ≤ 5.5 V 0.48 s
3.5 V ≤ VDD < 4.5 V 0.53 s
TA = −10 to +85°C,
NERASE ≤ 100
2.7 V ≤ VDD < 3.5 V 0.63 s
4.5 V ≤ VDD ≤ 5.5 V 1.86 s
3.5 V ≤ VDD < 4.5 V 2.07 s
TA = −10 to +85°C,
NERASE ≤ 1000
2.7 V ≤ VDD < 3.5 V 2.48 s
4.5 V ≤ VDD ≤ 5.5 V T.B.D. s
3.5 V ≤ VDD < 4.5 V T.B.D. s
TA = −40 to +85°C,
NERASE ≤ 100
2.7 V ≤ VDD < 3.5 V T.B.D. s
4.5 V ≤ VDD ≤ 5.5 V T.B.D. s
3.5 V ≤ VDD < 4.5 V T.B.D. s
Block erase time TBERASE
TA = −40 to +85°C,
NERASE ≤ 1000
2.7 V ≤ VDD < 3.5 V T.B.D. s
TA = −10 to +85°C, NERASE ≤ 1000 150
µ
s Byte write time TWRITE
TA = −40 to +85°C, NERASE ≤ 1000 T.B.D.
µ
s
Per 1 block 6.8 ms Internal verify TVERIFY
Per 1 byte 27
µ
s
Blank check TBLKCHK Per 1 block 480
µ
s
TA = −10 to +85°C, NERASE ≤ 1000 10 Years Retention years
TA = −40 to +85°C, NERASE ≤ 1000 T.B.D. Years
Note Depending on the erasure co unt (NERASE), the erase time varies. Refer to the chip erase time and bloc k erase
time parameters.
Remark When a product is first written after shipment, “erase → write” and “write only” are both taken as one
rewrite.
Preliminary User’s Manual U16898EJ2V0UD 339
CHAPTER 21 PACKAG E DRAWING
NS
C
DM
M
PL
U
T
G
F
E
B
K
J
detail of lead end
S
20 11
110
A
H
I
ITEM
B
C
I
L
M
N
20-PIN PLASTIC SSOP (7.62 mm (300))
A
K
D
E
F
G
H
J
P
T
MILLIMETERS
0.65 (T.P.)
0.475 MAX.
0.13
0.5
6.1±0.2
0.10
6.65±0.15
0.17±0.03
0.1±0.05
0.24
1.3±0.1
8.1±0.2
1.2
+0.08
−0.07
1.0±0.2
3°+5°
−3°
0.25
0.6±0.15
U
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
S20MC-65-5A4-2
Preliminary User’s Manual U16898EJ2V0UD
340
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for development of systems using the 78K0S/KA1+. Figure A-1
shows development tools.
• Compatibility with PC98-NX series
Unless stated otherwise, products whic h are supported by IBM PC/ATTM and compati bles can also be used with
the PC98-NX series. When using the PC98-NX series, therefore, refer to the explanations for IBM PC/AT and
compatibles.
• WindowsTM
Unless stated otherwise, “Windows” refers to the following operating systems.
• Windows 98
• Windows NTTM Ver. 4.0
• Windows 2000
• Windows XP
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD 341
Figure A-1. Development Tools (1/2)
(1) When using the in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Debugging software
• Integrated debugger
• System simulator
Host machine
(PC or EWS)
Interface adapter
In-circuit emulator
Note 3
Emulation board
Note 4
Target cable or emulation probe
Pin header or
conversion socket
Target system
Flash programmer
Flash memory
writing adapter
Flash memory
Power supply unit
•Software package
Control software
•Project Manager
(Windows version only)
Note 2
Software package
Flash memory writing environment
Notes 1. The C library source file is not includ ed in the software package.
2. The Project Manager PM plus is include d in the assembler package.
PM plus is used only in the Windows environment.
3. All products other than the in-circuit emulators IE-78K0S-NS and IE-78K0S-NS-A are optional.
4. The in-circuit emulator IE-789234-NS-EM1 is provid ed with the target cable.
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD
342
Figure A-1. Development Tools (2/2)
(2) When using the in-circuit emulator QB-78K0SKX1MINI
Language processing software
• Assembler package
• C compiler package
• Device file
• C library source file
Note 1
Debugging software
• Integrated debugger
• System simulator
Host machine
(PC or EWS)
Interface adapter
Debug adapter
Target cable or emulation probe
Pin header
Target system
Flash programmer
Flash memory
writing adapter
Flash memory
Power supply unit
•Software package
Control software
•Project Manager
(Windows version only)
Note 2
Software package
Flash memory writing environment In-circuit emulator
Note 3
QB-78K0SMINI
Notes 1. The C library source file is not includ ed in the software package.
2. The Project Manager PM plus is include d in the assembler package.
PM plus is used only in the Windows environment.
3. The in-circuit emulator QB-78K0SKX1MINI is provided with the integrate d debugger ID78K0S-QB, the
flash memory programmer PG-FPL2, a power supply unit, and a target cable. Other products are
optional.
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD 343
A.1 Software Package
This is a package that bundles the software tools required for development of the 78K/0S Series.
The following tools are included.
RA78K0S, CC78K0S, ID78K0S-NS, etc.
SP78K0S
Software package
Part number:
µ
S××××SP78K0S
Remark ×××× in the part number differs depending on the operating system to be used.
µ
S××××SP78K0S
×××× Host Machine OS Supply Medium
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
and compatibles English Windows
CD-ROM
A.2 Language Processing Software
Program that converts program written in mnemonic into object code that can be executed by
microcontroller.
In addition, automatic functions to generate symbol table and optimize branch instructions are also
provided. Used in combination with device file (DF789234) (sold separately).
<Caution when used in PC environment>
The assembler package is a DOS-based application but may be used under the Windows
environment by using PM plus (included in the assembler package).
RA78K0S
Assembler package
Part number:
µ
S××××RA78K0S
Program that converts program written in C language into object codes that can be executed by
microcontroller.
Used in combination with assembler package (RA78K0S) and device file (DF789234) (both sold
separately).
<Caution when used in PC environment>
The C compiler package is a DOS-based application but may be used under the Windows
environment by using PM plus (inc luded in the assembler package).
CC78K0S
C library package
Part number:
µ
S××××CC78K0S
File containing the information inherent to the device.
Used in combination with other tools (RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB, or SM+ for
78K0S).
DF789234Note 1
Device file
Part number:
µ
S××××DF789234
Source file of functions constituting object library included in C compiler package.
Necessary for changing object library included in C compiler package according to customer’s
specifications.
Since this is the source file, its working environment does not depend on any particular operating
system.
CC78K0S-LNote 2
C library source file
Part number:
µ
S××××CC78K0S-L
Notes 1. DF789234 is a common file that can be used with RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB,
and SM+ for 78K0S.
2. CC78K0S-L is not included in the software package (SP78K0S).
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD
344
Remark ×××× in the part number differs depending on the host machine and operating system to be used.
µ
S××××RA78K0S
µ
S××××CC78K0S
µ
S××××CC78K0S-L
×××× Host Machine OS Supply Media
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
and compatibles English Windows
3P17 HP9000 series 700TM HP-UXTM (Rel. 10.10)
3K17 SPARCstationTM SunOSTM (Rel. 4.1.4),
SolarisTM (Rel. 2.5.1)
CD-ROM
µ
S××××DF789234
×××× Host Machine OS Supply Media
AB13 Japanese Windows
BB13
PC-9800 series, IBM PC/AT
and compatibles English Windows
3.5” 2HD FD
A.3 Control Software
PM plus
Project manager This is control software designed so that the user program can be efficiently developed
in the Windows environment. With this software, a series of user program
development operations, including starting the editor, build, and starting the debugger,
can be executed on PM plus.
<Caution>
PM plus is included in the assembler package (RA78K0S). It can be used only in the
Windows environment.
A.4 Flash Memory Writing Tools
Flashpro IV (FL-PR4, PG-FP4)
Flash memory programmer Flash programmer dedicated to the microcontrollers incorporating a flash memory
PG-FPL2
Flash memory programmer Flash programmer dedicated to the microcontrollers incorporating a flash memory
Provided with the in-circuit emulator QB-78K0SKX1MINI.
FA-20MC
Flash memory writing adapter Flash memory writing adapter. Used in connection with Flashpro IV.
Designed for use with a 20-pin plastic SSOP (MC-5A4 type).
Remark FL-PR4 and FA-20MC are products of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191)
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD 345
A.5 Debugging Tools (Hardware)
A.5.1 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A
IE-78K0S-NS
In-circuit emulator In-circuit emulator for debugging hardware and software of application system using 78K/0S
Series. Supports integrated debugger (ID78K0S-NS). Used in combination with AC adapter,
emulation probe, and interface adapter for connecting the host machine.
IE-78K0S-NS-A
In-circuit emulator This in-circuit emulator has a coverage function in addition to the functions of the IE-78K0S-
NS, and enhanced debugging functions such as an enhanced tracer function and timer
function.
IE-70000-MC-PS-B
AC adapter Adapter for supplying power from 100 to 240 VAC outlet.
IE-70000-CD-IF-A
PC card interface PC card and interface cable required when using a notebook type PC as the host machine
(PCMCIA socket supported).
IE-70000-PC-IF-C
Interface adapter Adapter required when using IBM PC/AT and compatibles as the host machine (ISA bus
supported).
IE-70000-PCI-IF-A
Interface adapter Adapter required when using a personal computer incorporating the PCI bus is used as the
host machine.
IE-789234-NS-EM1
Emulation board Emulation board for emulating the peripheral hardware inherent to the device.
Used in combination with in-circuit emulator. A target cable is provided.
NP-30MC
Emulation probe This probe is used to connect the in-circuit emulator to the target system and is designed for
use with a 30-pin plastic SSOP (MC-5A4 type).
NSPACK20BK
YSPACK30BK
Conversi on c on ne c t or
This conversion connector connects the NP-30MC to a target system board designed to mount
a 20-pin plastic SSOP (MC-5A4 type).
• NSPACK20BK: Connector for connecting target
• YSPACK30BK: Connector for connecting emulator
Specifications of pin header on
target system 0.635 mm × 0.635 mm (height: 6 mm)
Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.
For further information, contact: Naito Densei Machida Mfg . Co., Ltd. (TEL +81-45-475-4191)
2. NSPACK20BK and YSPACK30BK are products of TOKYO ELETECH CORPORATION.
For further information, contact Daimaru Kogyo Co., Ltd.
Tokyo Electronics Department (TEL: +81-3-3820-7112)
Osaka Electronics Department (TEL: +81-6-6244-6672)
A.5.2 When using in-circuit emulator QB-78K0SKX1MINI
QB-78K0SKX1MINI
In-circuit emulator In-circuit emulator for debugging hardware and software of application system using
78K0S/Kx1+ Series. Supports integrated debugger (ID78K0S-QB). Used in combination with
AC adapter, target cable, and USB interface cable for connecting the host machine.
Specifications of pin header on
target system 0.635 mm × 0.635 mm (height: 6 mm)
APPENDIX A DEVELOPMENT TOOLS
Preliminary User’s Manual U16898EJ2V0UD
346
A.6 Debugging Tools (Software)
This debugger supports the in-circuit emulators for the 78K/0S Series. ID78K0S-NS is Windows-
based software.
This debugger has enhanced debugging functions supporting C language. By using its window
integration function that associates the source program, disassemble display, and memory display
with trace results, the trace results can be displayed corresponding to the source program.
It is used with a device file (DF789234) (sold separately).
ID78K0S-NS
(supporting in-circuit
emulator IE-78K0S-NS/
IE-78K0S-NS-A)
Integrated debugger
Ordering number:
µ
S××××ID78K0S-NS
This debugger supports the in-circuit emulators for the 78K0S/Kx1+ Series. ID78K0S-QB is
Windows-based software.
Provided with the debug function supporting C language, source programming, disassemble
display, and memory display are possible. This is used with the device file (DF789234) (sold
separately).
It is provided with the in-circuit emulator QB-78K0SKX1MINI.
ID78K0S-QB
(supporting in-circuit
emulator
QB-78K0SKX1MINI)
Integrated debugger
Ordering number:
µ
S××××ID78K0S-QB (not for sale)
This is a system simulator for the 78K/0S series. SM+ for 78K0S is Windows-based software.
This simulator can execute C-source-level or assembler-level debugging while simulating the
operations of the target system on the host machine.
By using SM+ for 78K0S, the logic and performance of the application can be verified
independently of hardware development. Therefore, the development efficiency can be enhanced
and the software quality can be improved.
This simulator is used with a device file (DF789234) (sold separately).
SM+ for 78K0SNote 1
System simulator
Ordering number:
µ
S××××SM789234-B
This is a file that has device-specific information.
It is used with the RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-QB, and SM+ for 78K0S (all sold
separately).
DF789234Note 2
Device file
Ordering number
µ
S××××DF789234
Notes 1. Under development
2. DF789234 is a common file that can be used with the RA78K0S, CC78K0S, ID78K0S-NS, ID78K0S-
QB, and SM+ for 78K0S.
Remark ×××× in the part number differs depending on the operating system to be used and the supply medium.
µ
S××××ID78K0S-NS
µ
S××××ID78K0S-QB
µ
S××××SM789234-B
×××× Host Machine OS Supply Medium
BB13 English Windows 3.5” 2HD FD
AB17 Japanese Windows
BB17
PC-9800 series, IBM PC/AT
and compatibles
English Windows
CD-ROM
µ
S××××DF789234
×××× Host Machine OS Supply Medium
AB13 Japanese Windows
BB13
PC-9800 series, IBM PC/AT
and compatibles English Windows
3.5” 2HD FD
Preliminary User’s Manual U16898EJ2V0UD 347
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
The following show the conditions when connecting the emulation probe to the conversion connector and
conversion socket in the case using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A. Follow the configuration
below and consider the shape of parts to be mounted on the target system when designing a system.
Figure B-1. Distance Between In-Circuit Emulator IE-78K0S-NS/IE-78K0S-NS-A
and Conversion Connector NP-30MC
In-circuit emulator
IE-78K0S-NS, IE-78K0S-NS-A
Emulation board
IE-789234-NS-EM1
Target system
CN5
Emulation probe
NP-30MC Conversion connector
YSPACK20BK,
NSPACK30BK
NP-30MC tip board
150 mm
Remarks 1. The NP-30MC is a product made by Naito Densei Machida Mfg. Co., Ltd.
2. The YSPACK30BK and NSPACK20BK are products by Naito Densei Machida Mfg. Co., Ltd.
APPENDIX B NOTES ON TARGET SYSTEM DESIGN
Preliminary User’s Manual U16898EJ2V0UD
348
Figure B-2. Condition for Connecting Target System
(When Using In-Circuit Emulator IE-78K0S-NS, IE-78K0S-NS-A)
31 mm
37 mm
Target system
Emulation probe
NP-30MC
13 mm
Emulation board
IE-789234-NS-EM1
15 mm
20 mm
5 mm
NP-30MC tip board
Conversion connector
YSPACK30BK,
NSPACK20BK
Guide pin
YQ-Guide
Remarks 1. The NP-30MC is a product made by Naito Densei Machida Mfg. Co., Ltd.
2. The YSPACK30BK and NSPACK20BK are products by Naito Densei Machida Mfg. Co., Ltd.
Preliminary User’s Manual U16898EJ2V0UD 349
APPENDIX C REGISTER INDEX
C.1 Register Index (Register Name)
8-bit A/D conversion result register (ADCRH) … 162
8-bit compare register 80 (CR80) … 122
8-bit timer counter 80 (TM80) … 122
8-bit timer H compare register 01 (CMP01) … 129
8-bit timer H compare register 11 (CMP11) … 129
8-bit timer H mode register 1 (TMHMD1) … 130
8-bit timer mode control register 80 (TMC80) … 123
10-bit A/D conversion result register (ADCR) … 161
16-bit timer capture/compare register 000 (CR000) … 81
16-bit timer capture/compare register 010 (CR010) … 83
16-bit timer counter 00 (TM00) … 81
16-bit timer mode control register 00 (TMC00) … 84
16-bit timer output control register 00 (TOC00) … 87
[A]
A/D converter mode register (ADM) … 158
Analog input channel specify register (ADS) … 161
Asynchronous serial interface operation mode register 6 (ASIM6) … 180
Asynchronous serial interface reception error status register 6 (ASIS6) … 182
Asynchronous serial interface transmission status register 6 (ASIF6) … 183
Asynchronous serial interface control re gister 6 (ASICL6) … 186
[B]
Baud rate generator control register 6 (BRGC6) … 185
[C]
Capture/compare control register 00 (CRC00) … 86
Clock selection register 6 (CKSR6) … 184
[E]
External interrupt mode register 0 (INTM0) … 217
External interrupt mode register 1 (INTM1) … 218
[F]
Flash address pointer H (FLAPH) … 278
Flash address pointer L (FLAPL) … 278
Flash address pointer H compare register (FLAPHC) … 278
Flash address pointer L compare register (FLAPLC) … 278
Flash status register (PFS) … 276
Flash programming command register (FLCMD) … 275
Flash programming mode control register (FLPMC) … 273
Flash protect command register (PFCMD) … 277
Flash write buffer register (FLW) … 279
APPENDIX C REGISTER INDEX
Preliminary User’s Manual U16898EJ2V0UD
350
[I]
Input switching control register (ISC) … 188
Interrupt mask flag register 0 (MK0) … 216
Interrupt mask flag register 0 (MK0) … 216
Interrupt request flag register 0 (IF0) … 215
Interrupt request flag register 1 (IF1) … 215
[L]
Low voltage detect register (L VIM) … 247
Low voltage detection level select register (LVIS) … 248
Low-speed Ring-OSC mode register (LSRCM) … 67
[O]
Oscillation stabilization time selection register (OSTS) … 68, 226
[P]
Port mode control register 2 (PMC2) … 59, 162
Port mode register 2 (PM2) … 57, 162
Port mode register 3 (PM3) … 57, 89
Port mode register 4 (PM4) … 57, 132, 188
Port mode register 12 (PM12) … 57
Port register 2 (P2) … 58
Port register 3 (P3) … 58
Port register 4 (P4) … 58
Port register 12 (P12) … 58
Port register 13 (P13) … 58
Preprocessor clock control register (PPCC) … 66
Prescaler mode register 00 (PRM00) … 88
Processor clock control register (PCC) … 66
Pull-up resistance option register 2 (PU2) … 61
Pull-up resistance option register 3 (PU3) … 61
Pull-up resistance option register 4 (PU4) … 61
Pull-up resistance option register 12 (PU12) … 61
[R]
Receive buffer register 6 (RXB6) … 179
Reset control flag register (RESF) … 241
[T]
Transmit buffer register 6 (TXB6) … 179
[W]
Watchdog timer enable register (WDTE) … 146
Watchdog timer mode register (WDTM) … 145
APPENDIX C REGISTER INDEX
Preliminary User’s Manual U16898EJ2V0UD 351
C.2 Register Index (Symbol)
[A]
ADCR: 10-bit A/D conversion result register … 161
ADCRH: 8-bit A/D conversion result register … 162
ADM: A/D converter mode register … 158
ADS: Analog input channel specify register … 161
ASICL6: Asynchronous serial interface control register 6 … 186
ASIF6: Asynchronous serial interface transmission status register 6 … 183
ASIM6: Asynchronous serial interface operation mode register 6 … 180
ASIS6: Asynchronous serial interface reception error status register 6 … 182
[B]
BRGC6: Baud rate generator control register 6 … 185
[C]
CKSR6: Clock selection register 6 … 184
CMP01: 8-bit timer H compare register 01 … 129
CMP11: 8-bit timer H compare register 11 … 129
CR000: 16-bit timer ca pture/compare register 000 … 81
CR010: 16-bit timer ca pture/compare register 010 … 83
CR80: 8-bit compare register 80 … 122
CRC00: Capture/compare control register 00 … 86
[F]
FLAPH: Flash address pointer H … 278
FLAPHC: Flash address point er H compare register … 278
FLAPL: Flash address pointer L … 278
FLAPLC: Flash address point er L compare register … 278
FLCMD: Flash programming command register … 275
FLPMC: Flash programming mode control register … 273
FLW: Flash write buffer register … 279
[I]
IF0: Interrupt request flag register 0 … 215
IF1: Interrupt reque s t flag register 1 … 215
INTM0: External interrupt mode register 0 … 217
INTM1: External interrupt mode register 1 … 218
ISC: Input switching control register … 188
[L]
LSRCM: Low-sp ee d Ring-OSC mode register … 67
LVIM: Low voltage detect register … 247
LVIS: Low voltage detection level select register … 248
[M]
MK0: Interrupt mask flag register 0 … 216
MK0: Interrupt mask flag register 0 … 216
APPENDIX C REGISTER INDEX
Preliminary User’s Manual U16898EJ2V0UD
352
[O]
OSTS: Oscillation stabilization time selection register … 68, 226
[P]
P2: Port register 2 … 58
P3: Port register 3 … 58
P4: Port register 4 … 58
P12: Port register 1 2 … 58
P13: Port register 13 … 58
PCC: Processor clock control register … 65
PFCMD: Flash protect command register … 277
PFS: Flash status register … 276
PM2: Port mode register 2 … 57, 162
PM3: Port mode register 3 … 57, 89
PM4: Port mode register 4 … 57, 132, 188
PM12: Port mode register 12 … 57
PMC2: Port mode control register 2 … 59, 162
PPCC: Preprocessor clock control register … 66
PRM00: Prescaler mode register 0 0 … 88
PU2: Pull-up resistance option register 2 … 61
PU3: Pull-up resistance option register 3 … 61
PU4: Pull-up resistance option register 4 … 61
PU12: Pull-up resistance option register 12 … 61
[R]
RESF: Reset control flag register … 241
RXB6: Receive buffer register 6 … 179
[T]
TM00: 16-bit timer counter 00 … 81
TM80: 8-bit timer counter 80 … 122
TMC00: 16-bit timer mode control register 00 … 84
TMC80: 8-bit timer mode control register 80 … 123
TMHMD1: 8-bit timer H mode register 1 … 130
TOC00: 16-bit timer output control register 00 … 87
TXB6: Transmit buffer register 6 … 179
[W]
WDTE: Watchdog timer enable register … 146
WDTM: Watchdog timer mode register … 145
Preliminary User’s Manual U16898EJ2V0UD 353
APPENDIX D REVISION HISTORY
D.1 Major Revisions in This Edition (1/4)
Page Description
Addition of lead-free products
•
µ
PD78F9221MC-5A4-A
•
µ
PD78F9222MC-5A4-A
Modification of watchdog timer operation clock
• Low-voltage Ring-OSC clock (fRL) or clock to peripheral hardware (fXP)
→ Low-voltage Ring-OSC clock (fRL) or system clock (fX)
Deletion of high-speed Ring-OSC mode register (HSRCM)
Throughout
Deletion of INTFLC (interrupt request)
pp. 19, 20, 22 Addition of Caution to 2.1 Pin Function List, 2.2.4 P121 to P123 (Port 12), and 2.2.7 X1 and X2
p. 23 Modification of the following pin connections in Table 2-1 Types of Pin I/O Circuits and Connection of
Unused Pins
• P20/ANI0 to P23/ANI3
• P34/RESET
• P121/X1
• P122/X2
pp. 25, 26 Modification of Figure 3-1 Memory Map (
µ
PD78F9221) and Figure 3-2 Memory Map (
µ
PD78F9222)
p. 27 Addition of Caution to and modification of Table 3-2 Vector Table
p. 27 Addition of (4) Protect byte area to 3.1.1 Internal program memory space
p. 34 Addition of Note 3 to Table 3-3 Special Function Registers (1/2)
p. 35 Addition of registers to be used for the self programming function to Table 3-3 Special Function Registers
(2/2)
p. 46 Addition of Caution and modification of Remark 2 in Table 4-1 Port Functions
p. 49 Addition of Figure 4-4 Block Diagram of P31
p. 54 Modification of Figure 4-9 Block Diagram of P43
p. 65 Modification of Figure 5-1 Block Diagram of Clock Generators
pp. 72, 74, 76 Modification of operation stop time in the following figures.
• Figure 5-8 Timing Chart of Default Start by High-Speed Ring-OSC Oscillator
• Figure 5-10 Timing Chart of Default Start by Crystal/Ceramic Oscillator
• Figure 5-12 Timing of Default Start by External Clock Input
p. 78 Modification of Note in Figure 5-14 Status Transition of Low-Speed Ring-OSC Oscillator
pp. 81 to 83 Addition of Cautions to 6.2 Configuration of 16-Bit Timer/Event Counter 00 (1) 16-bit timer counter 00
(TM00), (2) 16-bit timer capture/compare register 000 (CR000), and (3) 16-bit capture/compare register
010 (CR010)
p. 85 Addition of Cautions in Figure 6-5 Format of 16-Bit Timer Mode Control Register 00 (TMC00)
p. 87 Addition of Caution 6 to Figure 6-7 Format of 16-Bit Timer Output Control Register 00 (TOC00)
p. 89 Modification of Caution 3 and addition of Caution 4 in Figure 6-8 Format of Prescaler Mode Register 00
(PRM00)
APPENDIX D REVISION HISTORY
Preliminary User’s Manual U16898EJ2V0UD
354
(2/4)
Page Description
pp. 96, 98, 100,
102, 103 Modification of output width of INTTM010 and INTTM000 in the following figures
• Figure 6-17 CR010 Capture Operation with Rising Edge Specified
• Figure 6-20 Timing of Pulse Width Measurement Operation by Free-Running Counter and One
Capture Register (with Both Edges Specified)
• Figure 6-22 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both
Edges Specified)
• Figure 6-24 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two
Capture Registers (with Rising Edge Specified)
• Figure 6-26 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge
Specified)
p. 107 Modification of Caution 1 in Figure 6-29 Control Register Settings for PPG Output Operation
p. 111 Modification of Figure 6-33 Timing of One-Shot Pulse Output Operation with Software Trigger
pp. 114 to 119 Modification and addition to 6.5 Cautions Related to 16-Bit Timer/Event Counter 00
p. 123 Addition of Caution 2 to Figure 7-4 Format of 8-Bit Timer Mode Control Register 80 (TMC80)
p. 142 Modification of Table 9-1 Loop Detection Time of Watchdog Timer
pp. 145, 146 Addition of Caution 4 and modification to Figure 9-2 Format of Watchdog Timer Mode Register (WDTM)
p. 148 Modification of Figure 9-4 Status Transition Diagram When “Low-Speed Ring-OSC Cannot Be Stopped”
Is Selected by Option Byte
p. 150 Modification of Figure 9-5 Status Transition Diagram When “Low-Speed Ring-OSC Can Be Stopped by
Software” Is Selected by Option Byte
pp. 151, 152 Modification of operation stop time in the following figures
• Figure 9-6 Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)
• Figure 9-7 Operation in STOP Mode (WDT Operation Clock: Low-Speed Ring-OSC Clock)
p. 154 Addition of Note to and modification of Figure 10-1 Timing of A/D Converter Sampling and A/D
Conversion
p. 155 Addition of Note 1, Caution, and Remark 2 to and modification of Table 10-1 Sampling Time and A/D
Conversion Time
p. 156 Modification of Figure 10-2 Block Diagram of A/D Converter
pp. 159, 160 Modification of Note 5, addition of Notes 1, 2, Cautions 1, 2, 4 and Remark 2 to, and modification of Figure
10-3 Format of A/D Converter Mode Register (ADM)
p. 160 Modification of Note in Figure 10-4 Timing Chart When Comparator Is Used
p. 163 Addition of explanation <3> to 10.4.1 Basic operations of A/D converter
p. 165 Modification of Figure 10-11 Relationship Between Analog Input Voltage and A/D Conversion Result
p. 167 Addition of explanation <3> to 10.4.3 A/D converter operation mode
pp 170, 171 Modification of 10.6 (1) Operating current in STOP mode and (6) Input impedance of ANI0 to ANI3 pins
p. 170 Modification of capacitor value in Figure 10-19 Analog Input Pin Connection
p. 172 Modification of Figure 10-21 Internal Equivalent Circuit of ANIn Pin and Table 10-4 Resistance and
Capacitance Values (Reference Values) of Equivalent Circuit
p. 179 Addition of description to 11.2 (3) Transmit buffer register 6 (TXB6)
p. 180 Modification of Note 1 in Figure 11-5 Format of Asynchronous Serial Interface Operation Mode Register
6 (ASIM6) (1/2)
p. 186 Modification of Caution in 11.3 (6) Asynchronous serial interface control register 6 (ASICL6)
p. 196 Modification of Caution 1 in 11.4.2 (2) (d) Continuous transmissio n
p. 202 Modification of 11.4.2 (2) (h) SBF transmission
p. 207 Modification of Table 11-4 Set Data of Baud Rate Generator
APPENDIX D REVISION HISTORY
Preliminary User’s Manual U16898EJ2V0UD 355
(3/4)
Page Description
p. 212 Addition of Caution to and modification of Table 12-1 Interrupt Sources
p. 225 Modification of description on operation stop time in 13.1.1 (2) STOP mode
p. 227 Modification of Table 13-2 Operating Statuses in HALT Mode
p. 228 Modification of Remark 2 in Figure 13-2 HALT Mode Release by Interrupt Request Generation
p. 229 Modification of Note in Figure 13-3 HALT Mode Release by Reset Input
p. 230 Modification of Caution in 13.2.2 (1) STOP mode setting and operating statuses
p. 230 Modification of Table 13-4 Operating Statuses in STOP Mode
pp. 231, 232 Modification of operation stop time in the following figures.
• Figure 13-4 Operation Timing When STOP Mode Is Released
• Figure 13-5 STOP Mode Release by Interrupt Request Generation
p. 233 Modification of Note in Figure 13-6 STOP Mode Release by Reset Input
pp. 235 to 238 Modification of the following figures
• Figure 14-1 Block Diagram of Reset Function
• Figure 14-2 Timing of Reset by RESET Input
• Figure 14-3 Timing of Reset by Overflow of Watchdog Timer
• Figure 14-4 Reset Timing by RESET Input in STOP Mode
p. 240 Addition of registers to be used for self programming function in Table 14-1 Hardware Statuses After Reset
Acknowledgment
p. 247 Addition of Note 1 to Figure 16-2 Format of Low-Voltage Detect Register (LVIM)
p. 248 Addition of Note to Figure 16-3 Format of Low-Voltage Detection Level Select Register (LVIS)
p. 250 Addition of Notes 1 and 2 to and modification of Figure 16-4 Timing of Low-Voltage Detector Internal
Reset Signal Generation
p. 251 Addition of Notes 1 and 2 to and modification of Figure 16-5 Timing of Low-Voltage Detector Interrupt
Signal Generation
p. 252 Addition of Note to 16.5 Cautions for Low-Voltage Detector <Action> (2) When used as interrupt
p. 258 Revision of CHAPTER 18 FLASH MEMORY
pp. 327 to 333,
336, 338 Modification or addition of values in the following characteristics in CHAPTER 20 ELECTRICAL
SPECIFICATIONS (TARGET VALUES)
• Absolute maximum ratings
Output current high, output current low, and operating ambient temperature
• X1 oscillator characteristics
• Low-speed Ring-OSC oscillator characteristics
• DC characteristics
• AC characteristics
(1) Basic operation cycle time (minimum instruction execution time), RESET input low-level width
• POC circuit characteristics
Condition for power supply boot time
• Flash memory programming characteristics
pp. 341, 342 Modification Figure A-1 Development Tools
pp. 343, 344 Modification of device file names and Remark in A.2 Language Processing Software
p. 344 Addition of project manager name to A.3 Control Software
p. 344 Addition of PG-FPL2 to A.4 Flash Memory Writing Tools
p. 345 Modification of emulation board name used when the IE-78K0S-NS or IE-78K0S-NS-A is used, and deletion of
NP-20GS and EV-9500GS-20, and addition of Specification of pin header on target system to A.5.1 When
using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A
p. 350 Addition of A.5.2 When using in-circuit emulator QB-78K0KX1MINI
APPENDIX D REVISION HISTORY
Preliminary User’s Manual U16898EJ2V0UD
356
(4/4)
Page Description
p. 346 Modification of system simulator name, device file name, and Remark in and addition of ID78K0S-QB to A.6
Debugging Tool s (Software)
pp. 347, 348 Modification of Figure B-1 Distance Between In-Circuit Emulator IE-78K0S-NS/IE-78K0S-NS-A and
Conversion Connector NP-30M C and Figure B-2 Condition for Con necti ng Tar get System (Wh en Using
In-Circuit Emulator IE-78K0S-NS, IE-78K0S-NS-A)
p. 353 Addition of APPENDIX D REVISION HISTORY
