SEN-12670 - SparkFun Electronics

Freescale Semiconductor Document Number: MAG3110

Data Sheet: Technical Data Rev. 9.2, 02/2013

An Energy Efficient Solution by Freescale

Xtrinsic MAG3110 Three-Axis, Digital

Magnetometer

Freescale’s MAG3110 is a small, low-power, digital 3-axis magnetometer.

The device can be used in conjunction with a 3-axis accelerometer to realize an

orientation independent electronic compass that can provide accurate heading

information. It features a standard I2C serial interface output and smart embedded

functions.

The MAG3110 is capable of measuring magnetic fields with an output data rate

(ODR) up to 80 Hz; these output data rates correspond to sample intervals from

12.5 ms to several seconds.

The MAG3110 is available in a plastic DFN package and it is guaranteed to

operate over the extended temperature range of -40°C to +85°C.

Features

• 1.95 V to 3.6 V supply voltage (VDD)

• 1.62 V to VDD IO volt age (VDDIO)

• Ultra small 2 mm x 2 mm x 0.85 mm, 0.4 mm pitch, 10-pin package

• Full-scale range ±1000 T

• Sensitivity of 0.10 T

• Noise down to 0.25 T rms

• Output Data Rates (ODR) up to 80 Hz

• 400 kHz Fast Mode compatible I2C interface

• Low-power, single-shot measurement mode

• RoHS compliant

Applications

• Electronic Compass (e-compass)

• Location-Ba se d Se rvi ces

Ruggedized Target markets

• Smartphones, personal navigation devices, robotics, UAVs , speed sensing, current sensing and wrist watches with

embedded electronic compasses (e-compass) function.

Table 1. Ordering information

Part number I2C Address Package description Shipping

MAG3110FCR1 0x0E DFN-10 Tape and Reel (1000)

FXMS3110CDR1 0x0F DFN-10 Tape and Reel (1000)

10-PIN DFN

2 mm x 2 mm x 0.85 mm

CASE 2154-02

MAG3110

Top and Bottom View

Top View

Pin Connections

Cap-A

VDD

Cap-R

GND

INT1

SDA

VDDIO

SCL

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Related Documentation

The MAG3110 device features and operations are described in a variety of reference manuals, user guides, and application

notes. To find the most-current versions of these documents:

1. Go to the Freescale homepage at: http://www.freescale.com/

2. In the Keyword search box at the top of the page, enter the device number MAG3110.

3. In the Refine Your Result pane on the left, click on the Documentation link.

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.1 Application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Operating and Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.1 Operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.4 I2C Interface characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.5 I2C pullup resistor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.1 Factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.2 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

5 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 Sensor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2 Device ID. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.3 User Offset Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

5.4 Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.5 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6 Geomagnetic Field Maps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 PCB Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.1 Overview of Soldering Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.2 Halogen Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

7.3 PCB Mounting Recommendations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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1 Block diagram and pin description

Figure 1. Block diagram

Figure 2. Pin connections and measurement coordinate system

Figure 3. Device mark ing diagram

Digital Signal

SDA

SCL

Processing and

Y-axis

Clock Oscillator Reference

INT1

X-axis

Z-axis

MUX ADC Control

Trim Logic +

Regulator VDD

VDDIO

(TOP VIEW)

Cap-A

VDD

Cap-R

GND

INT1

SDA

VDDIO

SCL

MAG

LYW

L = WAFER L OT

Y = LAST DIGIT OF YEAR

W = WOR K WEEK

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1.1 Application circuit

Device power is supplied through the VDD line. Power supply decoupling capacitors (100 nF ceramic) should be placed as near

as possible to pins 1 and 2 of the device. Additionally a 1F (or larger) capacitor sh ould be us ed for bu lk deco upling o f the VDD

supply rail as shown in Figure 4. VDDIO supplies powe r for the digital I/O pins SCL, SDA, and INT1.

The control signals SCL and SDA, are not tolerant of voltages more than VDDIO + 0.3 volts. If VDDIO is removed, the control

signals SCL and SDA will clamp any logic signals through their internal ESD protection diodes.

Figure 4. Electrical connectio n

Table 2. Pin descriptions

Pin Name Function

1 Cap-A Bypass cap for internal regulator

2 VDD Power supply, 1.95 V – 3.6 V

3 NC Do not connect

4 Cap-R Magnetic reset pulse circuit capacitor connection

5GNDGND

6SDAI

2C Serial Data

7SCLI

2C Serial Clock

8 VDDIO Digital interface supply, 1.65 V - VDD

9 INT1 Interrupt - active high output

10 GND GND

SDA

VDDIO

(Top view)

100 nF

1 F

VDD

100 nF 100 nF

SCL

INT1

4.7 K

100 nF 4.7 K

Cap-A

VDD

Cap-R

GND

INT1

SDA

VDDIO

SCL

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2 Operating and Electrical Specifications

2.1 Operating characteristics

Table 3. Operating chara cteristics @ VDD = 2.4 V, VDDIO = 1.8 V, T = 25°C unless otherwise note d.

Parameter Test Conditions Symbol Min Typ Max Unit

Full-scale range FS ±1000 µT

Output data range(1)

1. Output data range is the sum of ±10000 LSBs full-scale range, ±10000 LSBs user defined offset (provided that CTRL_REG2[RAW] = 0) and

±10000 zero-flux offset.

-30000 +30000 LSB

Sensitivity So 0.10 µT/LSB

Sensitivity change versus temperature Tcs ±0.1 %/°C

Zero-flux offset accuracy ±100 µT

Hysteresis(2)

2. Hysteresis is measured from 0 T to 1000 T to 0 T and from 0 T to -1000 T to 0 T.

0.25 1 %

Non linearity

Best fit straight line(3)

3. Best-fit straight line over the 0 to ±1000 T full-scale range.

NL -1 ±0.3 1 %FS

Magnetometer output noise OS = 00(4)

4. OS = Over Sampling Ratio.

Noise

0.4

µT rms

OS = 01 0.35

OS = 10 0.3

OS = 11 0.25

Sensor die-to-package misalignment error (yaw) D2PEyaw ±0.37 ±1.36 degrees

Operating temperature range Top -40 +85 °C

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2.2 Absolute maximum ratings

S t resses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device under these conditions is not implied. Exposure to ma ximum rating conditions for

extended periods may affect device reliability.

Table 4. Maximum ratings

Rating Symbol Value Unit

Supply voltage VDD -0.3 to +3.6 V

Input voltage on any control pin (SCL, SDA) Vin -0.3 to VDDIO + 0.3 V

Maximum applied magnetic/field BMAX 100,000 µT

Operating temperature range Top -40 to +85 °C

Storage temperature range TSTG -40 to +125 °C

Table 5. ESD and latchup protection characteristics

Rating Symbol Value Unit

Human Body Model HBM ±2000 V

Machine Model MM ±200 V

Charge Device Model CDM ±500 V

Latchup current at T = 85°C ILU ±100 mA

This device is sensitive to mechanical shock. Improper handling can cause permanent damage of the part or

cause the part to otherwise fail.

This device is sensitive to ESD, improper handling can cause permanent damage to the part.

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2.3 Electrical characteristics

Table 6. Electrical characteristics @ VDD = 2.4 V, VDDIO = 1.8 V, T = 25°C unless otherwise noted

Parameter Test Conditions Symbol Min Typ Max Unit

Supply voltage VDD 1.95 2.4 3.6 V

Interface supply voltage VDDIO 1.62 VDD V

Supply current in ACTIVE mode ODR(1)(2) 80 Hz, OS(1) = 00

1. ODR = Output Data Rate; OS = Over Sampling Ratio.

2. Please see Table 32 for all ODR and OSR setting combinations, as well as corresponding current consumption and noise levels.

Idd

900

µA

ODR 40 Hz, OS(3) = 00

3. By design.

550

ODR 20 Hz, OS(3) = 00 275

ODR 10 Hz, OS(3) = 00 137.5

ODR 5 Hz, OS(3) = 00 68.8

ODR 2.5 Hz, OS(3) = 00 34.4

ODR 1.25 Hz, OS(3) = 00 17.2

ODR 0.63 Hz, OS = 00 8.6

Supply current drain in STANDBY mode Measurement mode off IddStby 2 µA

Digital high level input voltage

SCL, SDA VIH 0.75*VDDIO V

Digital low level input voltage

SCL, SDA VIL 0.3* VDDIO V

High level output voltage

INT1 IO = 500 µA VOH 0.9*VDDIO V

Low level output voltage

INT1 IO = 500 µA VOL 0.1* VDDIO V

Low level output voltage

SDA IO = 500 µA VOLS 0.1* VDDIO V

Output Data Rate (ODR) ODR 0.8*ODR ODR 1.2 *ODR Hz

Signal bandwidth BW ODR/2 Hz

Boot time from power applied to boot complete BT 1.7 ms

Turn-on time(4)(5)

4. Time to obtain valid data from STANDBY mode to ACTIVE Mode.

5. In 80 Hz mode ODR.

CTRL_REG1[OS] = 2'b01 Ton 25 ms

Operating temperature range Top -40 +85 °C

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2.4 I2C Interface characteristics

Table 7. I2C slave timing values(1)

1. All values are referred to VIH (min) and VIL (max) levels.

Parameter Symbol I2C Fast Mode Unit

Min Max

SCL clock frequency

Pullup = 1 k Cb = 20 pF fSCL 0400kHz

Bus free time between STOP and START condition tBUF 1.3 s

Repeated START hold time tHD;STA 0.6 s

Repeated START setup time tSU;STA 0.6 s

STOP condition setup time tSU;STO 0.6 s

SDA data hold time(2)

2. tHD;DAT is the data hold time that is measured from the falling edge of SCL; the hold time applies to data in transmission and the acknowledge.

tHD;DAT 0.05(3)

3. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH (min) of the SCL signal) to bridge the

undefined region of the falling edge of SCL.

(4)

4. The maximum tHD;DAT could be must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This device may stretch the LOW

period (tLOW) of the SCL sign al.

s

SDA valid time(5)

5. tVD;DAT = time for Data signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;DAT 0.9(4) s

SDA valid acknowledge time(6)

6. tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA output (HIGH or LOW, depending on which one is worse).

tVD;ACK 0.9(4) s

SDA setup time tSU;DAT 100(7)

7. A Fast mode I2C device can be used in a Standard mode I2C system, but the requirement tSU;DAT 250 ns must then be met. This will

automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the

SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C

specification) before the SCL line is released. Also the acknowledge timing must meet this setup time.

SCL clock low time tLOW 1.3 s

SCL clock high time tHIGH 0.6 s

SDA and SCL rise time tr20 + 0.1Cb(8) 1000 ns

SDA and SCL fall time(3) (8) (9) (10)

8. Cb = total capacitance of one bus line in pF.

9. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns.

This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding

the maximum specified tf.

10.In Fast mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for

this when considering bus timing.

tf20 + 0.1Cb(8) 300 ns

Pulse width of spikes on SDA and SCL that must be suppressed by input filter tSP 50 ns

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Figure 5. I2C slave timing diagram

2.5 I2C pullup resistor selection

The SCL and SDA signals are driven by open-drain buffers and a pullup resistor is required to make the signals rise to the high

state. The value of the pullup resistors depends on the system I2C clock rate and the total capacitive load on the I2C bus.

Higher resistance pullups will conserve power, at the expense of a slower rise time on the SCL and SDA lines (due to the RC

time constant between the bus capacitance and the pullup resistor), and will limit the maximum I2C clock frequency that can be

achieved.

Lower resistance value pullup resistors consume more power, but enable higher I2C clock operating frequencies.

I2C bus capacitance consists of the sum of the parasitic device and trace capacitances present. In general, longer bus traces and

an increased number of devices lead to higher total bus capacitance and will require lower value pullup resistors to enable a given

frequency of operation.

For Standard mode operation, pullup resistor values between 5 k and 10 k are recommended as a starting point, but may

need to be lowered depending on the number of devices present on the bus and the total bus capacitance. For Fast mode

operation, pullup resistor value s of 1k (or lower) may be required.

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3 Modes of Operation

4 Functionality

MAG3110 is a small low-power, digital outp ut, 3-axis linear magnetometer packaged in a 10-pin DFN. The device contains a

magnetic transducer for sensing and an ASIC for control and digital I2C communications.

4.1 Factory calibration

MAG3110 is factory calibrated for sensitivity and temperature coefficient of sensitivity. All factory calibration coefficients are

automatically applied by the ASIC before a measurement is taken and the result written to registe rs 0x01 to 0x06 (Section 5,

“Register Descriptions,” on page 15).

The magnetic offset registers in addresses 0x09 to 0x0E are not a factory calibration offset but allow the user to define a hard-

iron offset which can be automatically subtracted from the magnetic field readings (see Section 4.2.4, “User offset corrections,”

on page 12).

4.2 Digital interface

There are two signa ls associated with the I2C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). External pullup

resistors (connected to VDDIO) are needed for SDA and SCL. When the bus is free, both lines are high. The I2C interface is

compliant with Fast mode (400 kHz), and Normal mode (100 kHz) I2C standards.

4.2.1 General I2C operation

There are two signa ls associated with the I2C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a

bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to VDDIO are

required for SDA and SCL. When the bus is free both the lines are high. The I2C interface is compliant with fast mode (400 kHz),

and normal mode (100 kHz) I2C standards. Operation at fre quencies higher than 400 kHz is possible, but depends on several

factors including th e pullup resistor values, and total bus capacitance (trace + device capacitance).

A transaction on the bus is started with a start condition (ST) signal, which is defined as a HIGH-to-LOW transition on the data

line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy. The

next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, indicates

whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in

the system compares the first seven bits after the ST condition with its own add ress. If they match, the device considers itself

addressed by the master . The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge

(ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it

remains stable low during the high period of the acknowledge clock period.

The number of bytes per transfer is unlimited. If a receiver can't receive another complete byte of data until it has performed some

other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the

receiver is ready for another byte and releases the data line. This delay action is called clock stretching. Not all receiver devices

support clock stretching. Not all master de vices recognize clock stretching. This part supports clock stretching.

Table 8. Modes of operation descripti on

Mode I2C Bus State Function Description

STANDBY I2C communication is possible. Only POR and Digital blocks are enabled, the Analog subsystem is disabled.

ACTIVE I2C communication is possible. All blocks are enabled (POR, Digital, Analog).

Table 9. Serial interface pin description

Pin name Pin description

VDDIO IO voltage

SCL I2C Serial Clock

SDA I2C Serial Data

INT Data ready interrupt pin

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A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (SP) signal. A write or burst write

is always terminated by the master issuing the SP signal. A master should properly terminate a read by not acknowledging a byte

at the appropriate time in the protocol. A master may also issue a repeated start signal (SR) during a transfer .

The 7-bit I2C slave address assigned to MAG3110 is 0x0E (standard); the address assigned to FXMS3110CD is 0x0F

(Windows™ 8).

4.2.2 I2C Read/Write operations

Single byte read

The master (or MCU) transmits a st art condition (ST) to the MAG3110, followed by the slave address, with the R/W bit set to “0”

for a write, and the MAG3110 sends an acknowl edgement. Then the master (or MCU) transmits the address o f the register to

read and the MAG31 10 sends an acknowledgement. The master (or MCU) transmits a repeated start condition (SR), followed by

the slave address with the R/W bit set to “1” for a read from the previously selected register. The MAG3110 then acknowledges

and transmits the dat a from the requested register. The master does not acknowledge (NAK) the transmitted data, but transmits

a stop condition to end the data transfer.

Multiple byte read

When performing a multi-byte or “burst” read, the MAG3110 automatically increment s the re gister address read pointer after a

read command is received. Therefore, after following the step s of a single byte read, multiple bytes of data can be read from

sequential registers after each MAG31 10 acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the master

followed by a stop condition (SP) signaling the end of transmission.

Single byte write

To start a write command, the master transmits a start condition (ST) to the MAG31 10, followed by the slave address with the R/W

bit set to “0” for a write, and the MAG3110 sends an acknowledgement. Then th e master (or MCU) transmits the address of the

register to write to, and the MAG31 10 sends an acknowledgement. Then the master (or MCU) transmits the 8-bit data to write to

the designated register and the MAG3110 sends an acknowledgement that it ha s recei ved the dat a. Sin c e th i s tran smi ssi o n is

complete, the master transmits a stop condition (SP) to end the dat a transfer. Th e dat a sent to the MAG 3110 is now stored i n the

approp riate register.

Multiple byte write

The MAG3110 automatically increments the register address write pointer after a write command is received. Therefore, after

following the steps of a single byte write, multiple bytes of data can be written to sequential registers after each MAG3110

acknowledgm en t (ACK) is re cei ved.

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Figure 6. I2C timing diagram

4.2.3 Fast Read mode

When the Fast Read (FR) bit is set (CTRL_REG1, 0x10 , bit 2), the MSB 8-bit data is read through the I2C bus. Auto-increment

is set to skip over the LSB data. When FR bit is cleared, the complete 16-bit data is read accessing all 6 bytes sequentially

(OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, OUT_Z_LSB).

4.2.4 User offset corrections

The 2’s complement user of fset correction register values are used to compensate for correcting the X, Y, and Z-axis after device

board mount. These values may be used to compensate for hard-iron interference and zero-flux offset of the sensor.

Depending on the setting of the CTRL_REG2[RAW] bit, the magnetic field sample data is corrected with the user offset values

(CTRL_REG2[RAW] = 0), or can be read out uncorrected for user offset values (CTRL_REG2[RAW] = 1).

The factory calibration for gain, offset and temperature compensation is always automatically applied irrespective of the setting

of the CTRL_REG2[RA W] bit which only controls whether the user offset correction values stored in the OFF_X/Y/Z registers are

applied to the output data. In order to not saturate the sensor output, user written offset values should be within the range of

±10,000 counts.

< Single Byte Read >

Master ST Device Address[6:0] WRegister Address[7:0] SR Device Address[6:0] R NAK SP

Slave AK AK AK Data[7:0]

< Multiple Byte Read >

Master ST Device Address[6:0] WRegister Address[7:0] SR Device Address[6:0] R AK

Slave AK AK AK Data[7:0]

Master AK AK NAK SP

Slave Data[7:0] Data[7:0] Data[7:0]

< Multiple Byte Write >

Master ST Device Address[6:0] WRegister Address[7:0] Data[7:0] Data[7:0] SP

Slave AK AK AK AK

< Single Byte Write >

Master ST Device Ad dress[6:0] WRegister Address[7:0] Data[7:0] SP

Slave AK AK AK

Legend

ST: Start Condition SP: Stop Condition NAK: No Acknowledge W: Write = 0

SR: Repeated Start Condition AK: Acknowledge R: Read = 1

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4.2.5 INT1

The DR_ST ATUS register (see section 5.1.1) contains the ZYXDR bit which denotes the presence of new measurement data on

one or more axes. Software polling can be used to detect the transition of the ZYXDR bit from 0 to 1 but, since the ZYXDR bit is

also logically connected to the INT1 pin, a more efficient approach is to use INT1 to trigger a software interrupt when new

measurement data is available as follows:

1. Enable automatic resets by setting AUTO_MRST_EN bit in CTRL_REG2 (CTRL_REG2 = 0b1XXXXXX).

2. Put MAG3110 in ACTIVE mode (CTRL_REG1 = 0bXXXXXX01).

3. Idle until INT1 goes HIGH and activates an interrupt service routine in the user software.

4. Read magnetometer data as required from registers 0x01 to 0x06. INT1 is cleared when register 0x01 OUT_X_MSB is

read.

5. Return to idle in step 3.

4.2.6 Triggered Measurements

Set the TM bit in CTRL_REG1 when you want the part to acquire only one sample on each axis. See table below for details.

The anti-aliasing filter in the A/D converter has a finite delay before the output “settles”. The output data for the first ODR period

after getting out of Standby mode is expected to be slightly off. This effect will be more pronounced for the lower over-sampling

settings since with higher settings the error of the first acquisition will be averaged over the total number of samples. Therefore,

it is not recommended to use TRIGGER MODE (CTRL_REG1[AC] =0, CTRL_REG1[TM] =1) measurements for applications that

require high accuracy, especially with low over-sampling settings.

Table 10.

AC TM Description

0 0 ASIC is in low power standby mode.

The ASIC will exit standby mode, perform one measurement cycle based on the

programmed ODR and OSR setting, update the I2C data registers and re- enter

standby mode.

The ASIC will perform continuous measurements based on the current OSR and

ODR settings.

The ASIC will continue the current measurement at the fastest applicable ODR

for the user programmed OSR. The ASIC will return back to the programmed

ODR after completing the triggered measurement.

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4.2.7 MAG3110 Setup Examples

Continuous measurements with ODR = 80 Hz, OSR = 1

1. Enable automatic magnetic sensor resets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80)

2. Put MAG3110 in active mode 80 Hz ODR with OSR = 1 by writing 0x01 to CTRL_REG1 (CTRL_REG1 = 0x01)

3. At this point it is possible to sync with MAG3110 utilizing INT1 pin or using polling of the DR_STATUS register as

explained in section 4.2.5.

Continuous measurements with ODR = 0.63 Hz, OSR = 2

1. Enable automatic magnetic sensor resets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80)

2. Put MAG3110 in active mode 0.63 Hz ODR with OSR = 2 by writing 0xC9 to CTRL_REG1 (CTRL_REG1 = 0xC9)

3. At this point, it is possible to sync with MAG3110 utilizing INT1 pin or using polling of the DR_STATUS re gister as

explained in section 4.2.5.

Triggered measurements with ODR = 10 Hz, OSR = 8

1. Enable automatic magnetic sensor resets by setting bit AUTO_MRST_EN in CTRL_REG2. (CTRL_REG2 = 0x80)

2. Initiate a triggered measurement with OSR = 128 by writing 0b00011010 to CTRL_REG1 (CTRL_REG1 =

0b00011010).

3. MAG3110 will acquire the triggered measurement and go back into STANDBY mode. It is possible at this point to sync

on INT1 or resort to polling of DR_STATUS register to read the acquired data out of MAG3110.

4. Go back to step 2 based on application needs.

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5 Register Descriptions

Table 11. Register Address Map

Name Type Register

Address Auto-Increment

Address (Fast Read)(1)

1. Fast Read mode for quickly reading the Most Significant Bytes (MSB) of the sampled data.

Default Value Comment

DR_STATUS(2)

2. Register contents are preserved when transitioning from “ACTIVE” to “STANDBY” mode.

R 0x00 0x01 0000 0000 Data ready status per axis

OUT_X_MSB(2) R 0x01 0x02 (0x03) data Bits [15:8] of X measurement

OUT_X_LSB(2) R 0x02 0x03 data Bits [7:0] of X measurement

OUT_Y_MSB(2) R 0x03 0x04 (0x05) data Bits [15:8] of Y measurement

OUT_Y_LSB(2) R 0x04 0x05 data Bits [7:0] of Y measurement

OUT_Z_MSB(2) R 0x05 0x06 (0x07) data Bits [15:8] of Z measurement

OUT_Z_LSB(2) R 0x06 0x07 data Bits [7:0] of Z measurement

WHO_AM_I(2) R 0x07 0x08 0xC4 Device ID Number

SYSMOD(2) R 0x08 0x09 data Current System Mode

OFF_X_MSB R/W 0x09 0x0A 0000 0000 Bits [14:7] of user X offset

OFF_X_LSB R/W 0x0A 0x0B 0000 0000 Bits [6:0] of user X offset

OFF_Y_MSB R/W 0x0B 0x0C 0000 0000 Bits [14:7] of user Y offset

OFF_Y_LSB R/W 0x0C 0x0D 0000 0000 Bits [6:0] of user Y offset

OFF_Z_MSB R/W 0x0D 0x0E 0000 0000 Bits [14:7] of user Z offset

OFF_Z_LSB R/W 0x0E 0x0F 0000 0000 Bits [6:0] of user Z offset

DIE_TEMP(2) R 0x0F 0x10 data Temperature, signed 8 bits in C

CTRL_REG1(3)

3. Modification of this register’s contents can only occur when device is “STANDBY” mode, except the TM and AC bit fields in CTRL_REG1

R/W 0x10 0x11 0000 0000 Operation modes

CTRL_REG2(3) R/W 0x11 0x12 0000 0000 Operation modes

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5.1 Sensor Status

5.1.1 DR_STATUS (0x00)

Data Ready Status

This read-only status register provides the acquisition status information on a per-sample basis, and reflects real-time updates

to the OUT_X, OUT_Y, and OUT_Z registers.

ZYXOW is set to 1 whenever new data is acquired before completing the retrieval of the previous set. This event occurs when

the content of at least one data register (i.e. OUT_X, OUT_Y, OUT_Z) has been overwritten. ZYXOW is cleared when the high-

bytes of the data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all active channels are read.

ZOW is set to 1 whenever new Z-axis acquisition is completed before the retrieval of the previous data. When this occurs the

previous data is overwritten. ZOW is cleared any time OUT_Z_MSB register is read.

YOW is set to 1 whenever new Y-axis acquisition is completed before the retrieval of the previous data. When this occurs the

previous data is overwritten. YOW is cleared any time OUT_Y_MSB register is read.

XOW is set to 1 whenever new X-axis acquisition is completed before the retrieval of the previous data. When this occurs the

previous data is overwritten. XOW is cleared any time OUT_X_MSB register is read.

ZYXDR signals that new acquisition for any of the enabled channels is available. ZYXDR is cleared when the high-bytes of the

data (OUT_X_MSB, OUT_Y_MSB, OUT_Z_MSB) of all the enabled channels are read.

ZDR is set to 1 whenever new Z-axis data acquisition is completed. ZDR is cleared any time OUT_Z_MSB register is read.

YDR is set to 1 whenever new Y-axis data acquisition is completed. YDR is cleared any time OUT_Y_MSB register is read.

XDR is set to 1 whenever new X-axis data acquisition is completed. XDR is cleared any time OUT_X_MSB register is read.

Table 12. DR_STATUS Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZYXOW ZOW YOW XOW ZYXDR ZDR YDR XDR

Table 13. DR_STATUS Descriptions

ZYXOW X, Y, Z-axis Data Overwrite. Default value: 0.

0: No data overwrite has occurred.

1: Previous X or Y or Z data was overwritten by new X or Y or Z data before it was completely read.

ZOW Z-axis Data Overwrite. Default value: 0.

0: No data overwrite has occurred.

1: Previous Z-axis data was overwritten by new Z-axis data before it was read.

YOW Y-axis Data Overwrite. Default value: 0.

0: No data overwrite has occurred.

1: Previous Y-axis data was overwritten by new Y-axis data before it was read.

XOW X-axis Data Overwrite. Default value: 0

0: No data overwrite has occurred.

1: Previous X-axis data was overwritten by new X-axis data before it was read.

ZYXDR X or Y or Z-axis new Data Ready. Default value: 0.

0: No new set of data ready.

1: New set of data is ready.

ZDR Z-axis new Data Available. Default value: 0.

0: No new Z-axis data is ready.

1: New Z-axis data is ready.

YDR Z-axis new Data Available. Default value: 0.

0: No new Y-axis data is ready.

1: New Y-axis data is ready.

XDR Z-axis new Data Available. Default value: 0.

0: No new X-axis data is ready.

1: New X-axis data is ready.

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5.1.2 OUT_X_MSB (0x01), OUT_X_LSB (0x02), OUT_Y_MSB (0x03), OUT_Y_LSB (0x04),

OUT_Z_MSB (0x05), OUT_Z_LSB (0x06)

X-axis, Y-axis, and Z-axis 16-bit output sample data of the magnetic field strength expressed as signed 2's complement numbers.

When RA W bit is set (CTRL_REG2[RA W] = 1), the output range is between -20,000 to 20,000 bit counts (the combination of the

1000 T full scale range and the zero-flux offset ranging up to 1000 T).

When RAW bit is clear (CTRL_REG2[RA W] = 0), the output range is between -30,000 to 30,000 bit counts when the user offset

ranging between -10,000 to 10,0 00 bit counts are included.

The DR_ST A TUS register, OUT_X_MSB, OUT_X_LSB, OUT_Y_MSB, OUT_Y_LSB, OUT_Z_MSB, and OUT_Z_LSB are stored

in the auto-incrementing address range of 0x00 to 0x06. Data acquisition is a sequential read of 6 bytes.

If the Fast Read (FR) bit is set in CTRL_REG1 (0x10), auto-increment will skip over LSB of the X, Y, Z sample registers. This will

shorten the data acquisition from 6 bytes to 3 bytes. If the LSB registers are directly addressed, the LSB information can still be

read regardless of FR bit setting.

The preferred method for reading data registers is the burst-read method where the user application acquires data sequentially

starting from register 0x01. If register 0x01 is not read first, the rest of the data registers (0x02 - 0x06) will not be updated with

the most recent acquisition. It is still possible to address individual data registers, however register 0x01 must be read prio r to

ensure that the latest acquisition data is being read.

Table 14. OUT_X_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XD15 XD14 XD13 XD12 XD11 XD10 XD9 XD8

Table 15. OUT_X_L SB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XD7 XD6 XD5 XD4 XD3 XD2 XD1 XD0

Table 16. OUT_Y_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

YD15 YD14 YD13 YD12 YD11 YD10 YD9 YD8

Table 17. OUT_Y_LSB Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

YD7 YD6 YD5 YD4 YD3 YD2 YD1 YD0

Table 18. OUT_Z_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZD15 ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8

Table 19. OUT_Z _LSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZD6ZD6ZD5ZD4ZD3ZD2ZD1ZD0

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5.2 Device ID

5.2.1 WHO_AM_I (0x07)

Device identification register . This read-only register contains the devi ce identifier which is set to 0xC4. This value is factory

programmed.

5.2.2 SYSMOD (0x08)

The read-only system mode register indicates the current device ope rating mode.

5.3 User Offset Correction

5.3.1 OFF_X_MSB (0x09), OFF_X_LSB (0x0A), OFF_Y_MSB (0x0B), OFF_Y_LSB (0x0C),

OFF_Z_MSB (0x0D), OFF_Z_LSB (0x0E)

These registers contain the X-axis, Y-axis, and Z-axis user defined offsets in 2's complement format which are used when

CTRL_REG2[RAW] = 0 (see section 5.5.2) to correct for the MAG3110 zero-flux offset and for hard-iron offsets on the PCB

caused by external components. The maximum range for the user offsets is in the range -10,000 to 10,000 bit counts comprising

the sum of the correction for the sensor zero-flux offset and the PCB hard-iron offset (range -1000 T to 1000 T or -10,000 to

10,000 bit counts).

The user offsets are automatically subtracted by the MAG3110 logic when CTRL_REG2[RAW] = 0 before the magnetic field

readings are written to the data measurement output registers OUT_X/Y/Z. The maximum range of the X, Y and Z data

measurement registers when CTRL_REG2[RAW] = 0 is therefore -30,000 to 30,000 bit counts and is computed without clipping.

The user offsets are not subtracted when CTRL_REG2[RA W] = 1. The least significant bit of the user defined X, Y and Z offsets

is forced to be zero irrespective of the value written by the user.

If the MAG3110 zero-flux offset and PCB hard-iron offset corrections are performed by an external microprocessor (the most

likely scenario) then the user offset registers can be ignored and the CTRL_REG2[RAW] bit should be set to 1.

The user offset registers should not be confused with the factory calibration corrections which are not user accessible and are

always applied to the measured magnetic data irrespective o the setting of CTRL_REG2[RA W].

Table 20. WHO_AM_I Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

11000100

Table 21. SYSMOD Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

000000SYSMOD1 SYSMOD0

Table 22. SYSMOD Description

SYSMOD

System Mode. Default value: 00.

00: STANDBY mode.

01: ACTIVE mode, RAW data.

10: ACTIVE mode, non-RAW user-corrected data.

Table 23. OFF_X_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XD14 XD13 XD12 XD11 XD10 XD9 XD8 XD7

Table 24. OFF_X_LSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

XD6 XD5 XD4 XD3 XD2 XD1 XD0 0

Table 25. OFF_Y_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

YD14 YD13 YD12 YD11 YD10 YD9 YD8 YD7

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5.4 Temperature

5.4.1 DIE_TEMP (0x0F)

The register contains the die temperature in °C expressed as an 8-bit 2's complement number. The sensitivity of the temperature

sensor is factory trimmed to 1°C/LSB. The temperature sensor offset is not factory trimmed and must be calibrated by the user

software if higher absolute accuracy is required. Note: The register allows for temperature measurements from -128°C to 127°C

but the output range is limited to -40°C to 125°C. The temperature data is updated on every measurement cycle.

5.5 Control Registers

5.5.1 CTRL_REG1 (0x10)

Note: Except for ST ANDBY mode selection (Bit 0, AC), the device must be in ST ANDBY mode to change any of the fields within

CTRL_REG1 (0x10).

Table 26. OFF_Y_LSB Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

YD6 YD5 YD4 YD3 YD2 YD1 YD0 0

Table 27. OFF_Z_MSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZD14 ZD13 ZD12 ZD11 ZD10 ZD9 ZD8 ZD7

Table 28. OFF_Z_LSB Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ZD6ZD5ZD4ZD3ZD2ZD1ZD0 0

Table 29. TEMP Register

Bit 7 B it 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T7 T6 T5 T4 T3 T2 T1 T0

Table 30. CTRL_REG1 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DR2 DR1 DR0 OS1 OS0 FR TM AC

Table 31. CTRL_REG1 Description

DR[2:0] Output data rate selection. Default value: 000.

See Table 32 for more information.

OS [1:0]

This register configures the over sampling ratio for the measurement. The selected number of samples is collected and

averaged before being placed in the output data registers. The oversampling setting made here applies to both the triggered

and active modes of operation.

Default value: 00.

See Table 32 for more information.

FR Fast Read selection. Default value: 0.

0: The full 16-bit values are read.

1: Fast Read, 8-bit values read from the MSB registers (Auto-increment skips over the LSB register in burst-read mode).

Trigger immediate measurement. Default value: 0

0: Normal operation based on AC condition.

1: Trigger measurement.

If part is in ACTIVE mode, any measurement in progress will continue with the highest ODR possible for the selected OSR.

In STANDBY mode triggered measurement will occur immediately and part will return to STANDBY mode as soon as the

measurement is complete.

Operating mode selection. Note: see section 4.2.6 for details. Default value: 0.

0: STANDBY mode.

1: ACTIVE mode.

ACTIVE mode will make periodic measurements based on values programmed in the Data Rate (DR) and Over Sampling

Ratio bits (OS).

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Table 32. Over-Sampling Ratio and Data Ra te Description

DR2 DR1 DR0 OS1 OS0 Output Rate

(Hz)

Over

Sample

Ratio

ADC Rate

(Hz) Current Typ

ANoise Typ

T rms

0000080.00161280 900.0 0.4

0000140.00321280 900.0 0.35

0001020.00641280 900.0 0.3

0001110.001281280 900.0 0.25

0010040.0016640550.00.4

0010120.0032640550.00.35

0011010.0064640550.00.3

001115.00128640550.00.25

0100020.0016320275.00.4

0100110.0032320275.00.35

010105.0064320275.00.3

010112.50128320275.00.25

0110010.0016160137.50.4

011015.0032160137.50.35

011102.5064160137.50.3

011111.25128160137.50.25

100005.00168068.80.4

100012.50328068.80.35

100101.25648068.80.3

100110.631288068.80.25

101002.50168034.40.4

101011.25328034.40.35

101100.63648034.40.3

101110.311288034.40.25

110001.25168017.20.4

110010.63328017.20.35

110100.31648017.20.3

110110.161288017.20.25

111000.6316808.60.4

111010.3132808.60.35

111100.1664808.60.3

111110.08128808.60.25

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5.5.2 CTRL_REG2 (0x11)

Table 33. CTRL_REG2 Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

AUTO_MRST_EN — RAW Mag_RST ————

Table 34. CTRL_REG2 Description

AUTO_MRST_EN

Automatic Magnetic Sensor Reset. Default value: 0.

0: Automatic magnetic sensor resets disabled.

1: Automatic magnetic sensor resets enabled.

Similar to Mag_RST, however, the resets occur automatically before each data acquisition.

This bit is recommended to be always explicitly enabled by the host application. This a WRITE ONLY bit and always reads

back as 0.

RAW

Data output correction. Default value: 0.

0: Normal mode: data values are corrected by the user offset register values.

1: Raw mode: data values are not corrected by the user offset register values.

Note: The factory calibration is always applied to the measured data stored in registers 0x01 to 0x06 irrespective of the

setting of the RAW bit.

Mag_RST

Magnetic Sensor Reset (One-Shot). Default value: 0.

0: Reset cycle not active.

1: Reset cycle initiate or Reset cycle busy/active.

When asserted, initiates a magnetic sensor reset cycle that will restore correct operation after exposure to an excessive

magnetic field which exceeds the Full Scale Range (see Table 3) but is less than the Maximum Applied Magnetic Field

(see Table 4).

When the cycle is finished, value returns to 0.

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6 Geomagnetic Field Maps

The magnitude of the geomagnetic field varies from 25 T in South America to about 60 T over Northern China. The horizontal

component of the field varies from zero at the magnetic poles to 40 T.

These web sites have further information:

http://wdc.kugi.kyoto-u.ac.jp/igrf/

http://geomag.usgs.gov/

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Geomagnetic Field

Sensitivity Full-Scale

Range

(0.1 T) (1000 T)

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7 PCB Guidelines

Surface mount Printed Circuit Board (PCB) layout is a critical portion of the total design. The footprint for the surfa c e mount

packages must be the correct size to ensure proper solder connection interface between the PCB and the package. With the

correct footprint, the packages will self-align when subjected to a solder reflow process. These guidelines are for soldering and

mounting the Dual Flat No-Lead (DFN) package inertial sensors to PCBs. The purpose is to minimize the stress on the package

after board mounting. The MAG3110 digital output magnetometers use the DFN package platform. This section describes

suggested methods of soldering these devices to the PCB for consumer applications.

Please see Freescale application note AN4247,”Layout Recommend ation for PCBs Using a magnetometer Sensor” for a

technical discussion on hard and soft-iron magnetic interference and general guidelines on layout and component selection

applicable to any PC B using a magnetometer sensor.

Freescale application note AN1902, “Quad Flat Pack No-Lead (QFN) Micro Dual Flat Pack No-Lead (DFN)” discusses the DFN

package used by the MAG3110, PCB design guidelines fo r using DFN packages and temperature profiles for reflow soldering.

7.1 Overview of Soldering Considerations

Information provid ed here is based on experiments executed on DFN devices. They do not represent exact conditions present

at a customer site. Hence, information herein should be used as guidance only and process and design optimizations are

recommended to develop an application specific solution. It should be noted that with the proper PCB footprint and solder stencil

designs, the package will self-align during the solder reflow process.

7.2 Halogen Content

This package is designed to be Halogen Free, exceeding most ind ustry and customer standards. Halogen Free means that no

homogeneous material within the assembly package shall contain chlorine (Cl) in excess of 700 ppm or 0.07% weight/weight or

bromine (Br) in excess of 900 ppm or 0.09% weight/weight.

7.3 PCB Mounting Recommendations

1. The PCB land should be designe d as Non Solder Mask Defined (NSMD) as shown in Figure 7.

2. No additional via pattern underneath package.

3. PCB land pad is 0.6 mm x 0.225 mm as shown in Figure 7.

4. Solder mask opening = PCB land pad edge + 0.125 mm larger all around = 0.725 mm x 1.950 mm

5. Stencil opening = PCB land pad -0.05 mm smaller all around = 0.55 mm x 0.175 mm.

6. Stencil thickness is 100 or 125 mm.

7. Do not place any components or vias at a distance less than 2 mm from the pa ckage land area. This may cause

additional package stress if it is too close to the package land area.

8. Signal traces connected to pads are as symmetric as possible. Put dummy traces on NC pads in order to have same

length of exposed trace for all pads.

9. Use a standard pick and place process and equipment. Do not use a hand solderin g process.

10. Assemble PCB when in an enclosure. Using caution, determi ne the position of screw down holes and any press fit. It is

important that the assembled PCB remain flat after assembly to keep electronic operation of the device optimal.

11. The PCB should be rated for the multiple lead-free reflow condition with max 260°C temperature.

12. No copper traces on top layer of PCB under the package. This will cause planarity issues with board mount. Freescale

DFN sensors are compliant with Restrictions on Hazardous Substances (RoHS), havi ng halide free molding compound

(green) and lead-free terminations. These terminations are compatible with tin-lead (Sn-Pb) as well as tin-silver-copper

(Sn-Ag-Cu) solder paste soldering processes. Reflow profiles applicable to those processes can be used successfully for

soldering the devices.

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Figure 7. Footpr ints and Soldering Masks (dimensions in mm)

0.400

0.200 0.225

0.600

0.200

0.550

0.175

1.950

0.725

Package Footprint PCB Cu Footprint

Stencil Opening Solder Mask Opening

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PACKAGE DIMENSIONS

CASE 2154-02

ISSUE A

10-PIN DFN

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PACKAGE DIMENSIONS

CASE 2154-02

ISSUE A

10-PIN DFN

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PACKAGE DIMENSIONS

CASE 2154-02

ISSUE A

10-PIN DFN

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Table 35. Revision history

Revision

number Revision

date Description of changes

8 05/2012

• Updated content on page 1.

• Updated pin descriptions in Table 1.

• Updated pin connection drawing and Figure 2 to reflect horizontal bar for pin 1.

• Added Figure 3, Device Marking Diagram

• Updated Output Data Range row in Table 2.

• Updated Figure 4 to include pin names.

• Updated Bit 7 in Table 31 and 32 for emphasis. Changed description as highlighted in Red and bold text.

9 09/2012

• Added FXMS3110CDR1, Windows 8 option to ordering information.

• Table 1: Updated Pin 6, SDA, description.

• Table 2: added Sensor die-to-package row.

• Updated Table 5, Boot time from power row Max value from deleted, Typ value added, 1.7.

• Deleted section 4.1. Updated I2C sections 4.3.1 and 4.3.2 (replaced Pullup section).

9.1 10/2012 • Table 2: added Sensor die-to-package row.

9.2 02/2013

• Updated ordering table, deleted MAG3110FCR2 option.

• Table title for Table 2 and Table 5: Updated VDD = 1.8 V to VDD = 2.4 V and added VDDIO = 1.8 V.

• Updated second paragraph in Section 5.3.1 “The user offsets are automatically added by the MAG3110... “ to

“The user offsets are automatically subtracted by the MAG3110... “

Document Number: MAG 3110

Rev. 9.2

02/2013

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no ex press or implied copyright

licenses gr ant ed her eunder to desig n or fabricate any integr at ed cir cuits based on the

information in this document.

Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation conseq uential or incidental

damages. “Typical” parameter s t hat may be provided in Freescale data sheets and/or

specifications can and do vary in differen t applications, and actual performance may

vary ov er time. All operating par ameters, including “typicals,” must be validated fo r each

customer application by customer’s technical experts. Freescale does not convey any

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