M41T0DW6T - STMicroelectronics, Inc.

1/19April 2003

Rev. 1.2

M41T0

SERIAL REAL-TIME CLOCK

FEATURES SUMMARY

■2.0 TO 5.5V CLOCK OPERA TING V OLT A GE

■COUNTERS FOR SECONDS, MINUTES,

HOU RS , DA Y, DATE, MONT H , YEAR S, and

CENTURY

■YEAR 2000 COMPLIA NT

■I2C BUS COMP A TIBLE (400kHz)

■LOW OPERATING CURRENT OF 130µA

■OPERATING TEMPERATURE OF –40 TO

85°C

■AUTOMATIC LEAP YEAR COMPENSATION

■SPECIAL SOFTWARE PROGRAMMABLE

OUTPUT

■OSCILLATOR STOP DETECTION

Figure 1. 8-pin SOIC Pack ages

SO8 (M)

TSSOP8 (DW)

M41T0
2/19
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. SOIC Connect ions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table  1. Signal Names  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Absol ute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table  3. Operating and AC Measurem ent  Condition s. . . . .  . . . . . .  . . . . . . . .  . . . . . . . . . .  . . . . . .  . 6
Figure 5. AC Testing Input/O utput Waveform . . . . . . . . .  . . . . . .  . . . . . . .  . . .  . . . .  . . . . . .  . . . . . .  . 6
Table  4. Capacitance. . . . .  . . . . . . . . . .  . . . . . . . . . . . . .  . . .  . . . . . . . . . .  . . . . . .  . . .  . . . .  . . . . . . . 6
Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Crystal Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 8
2-Wire Bus Chara cteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . 8
Figure 6. Serial Bus Data Transfer Sequence. . .  . . . . . . . .  . . . .  . . . . . . . .  . . . . . . . . . . . .  . . . . . .  . 9
Figure 7. Acknowle dgem ent  Seque nce.  . . . . . . . . . . . . . . .  . . . . . .  . . . . .  . . . . . .  . . .  . . . .  . . . . . . . 9
Figure 8. Bus Timing  Requirem ents Sequence. . . . . . . . . . .  . . . . . .  . . . . . . . . . . . . .  . . . . . . . . . .  . 9
Table 7. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . 1 0
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Slave  Address L ocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 10. READ Mode Sequence  . . . . . . . . . . .  . . . . . .  . . . . . .  . . . . . . . . .  . . . . . .  . . . . . .  . . . . . 12
Figure 11. Alternate READ Mode Sequence. . . . . . . . . .  . . . . . . .  . . . . . .  . . . . . . . .  . . . . . . . . . . . 12
Figure 12. WRITE Mode Sequen ce. . . . . .  . . . . . .  . . . . . . . .  . . . .  . . . . . .  . . . . . . . . .  . . . .  . . . . . . 12
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Output Driv er Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Oscillator Stop Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 8. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . 14
PACKAGE MECHANICAL INFORMAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3/19

M41T0

SUMMARY DESCRIPTION

The M41T0 TIMEKEEPER® RAM is a low power

Serial T IMEKEEPER wi th a built-in 3 2 .768kHz os-

cillator (external cry stal c ontrolled). Eight registers

are used for the clock/calendar function and are

configured in bina ry cod ed decim al (BCD) form at.

Addresses and data are transferred serially via a

two-line bi-directional bus. The built-in address

WRIT E or READ d at a byte.

The M41T0 is supplied in 8 lead Plastic Small Out -

line package.

Figure 2. Logic Diagram

Figure 3. SOIC Connections

No te : 1. NF pin must be tied to VSS.

Table 1. Signal Names

No te : 1. NF pin must be tied to VSS.

AI07028

OSCI

VCC

M41T0

VSS

SCL

OSCO

SDA

OUT

SDAVSS SCL

OUTOSCO

OSCI VCC

NF(1)

AI07029

M41T0

OSCI Oscillator Input

OCSO Oscillator Output

OUT Output Driver (Open Drain)

SDA Serial Data Address Input / Output

SCL Serial Clock

NF(1) No Function

VCC Supply Voltage

VSS Ground

M41T0

4/19

Figu re 4. Blo ck D ia gra m

AI07030

SECONDS

OSCILLATOR

32.768 kHz

SERIAL

BUS

INTERFACE

DIVIDER

CONTROL

LOGIC

ADDRESS

MINUTES

CENTURY/HOURS

DAY

DATE

MONTH

YEAR

CONTROL

OSCI

OSCO

OUT

VCC

VSS

SCL

SDA

1 Hz

5/19

M41T0

MAX I MUM R A TI N G

Stressing the device ab ove t he rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above t hose indicat -

ed in the Oper ating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics SURE P rogram and oth er rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

Note: 1. Reflow at peak temperature of 255°C to 260°C for < 30 seconds (total thermal budget not to exceed 180°C for between 90 and 150

seconds).

CAUTION: Negative undershoots below –0.3V are not al lowed on any pi n while in the Battery Back-up mode.

Symbol Parameter Value Unit

TSTG Storage Temperature (VCC Off, Oscillator Off) –55 to 125 °C

VCC Supply Voltage –0.3 to 7 V

TSLD(1) Lead Solder Temperature for 10 Seconds 260 °C

VIO Input or Output Voltages –0.3 to VCC + 0.3 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M41T0

6/19

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests pe rformed unde r t he Measure-

ment Conditions listed i n the relevant tables. De-

signers should check that the operating conditi ons

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. Operating and AC Measurem en t Conditions

No te : Output Hi-Z is def i n ed as the point wher e data is no l onger dri ven.

Figure 5. AC Testing Input/Output Waveform

Table 4. Capacitance

No te : 1. Effective capacitance meas ured wit h powe r suppl y at 5V; sampled on ly, not 100% t ested.

2. At 25° C, f = 1M Hz.

3. Outputs desel ected.

Parameter M41T0 Unit

Supply Voltage (VCC)2.0 to 5.5 V

Ambient Operating Temperature (TA)–40 to 85 °C

Load Capacitance (CL)100 pF

Input Rise and Fall Times ≤ 5ns

Input Pulse Voltages 0.2VCC to 0.8VCC V

Input and Output Timing Ref. Voltages 0.3VCC to 0.7VCC V

AI02568

0.8VCC

0.2VCC

0.7VCC

0.3VCC

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance (SCL) 7 pF

COUT(3) Output Capacitance (SDA, OUT) 10 pF

tLP Low-pass filter input time constant (SDA and SCL) 50 ns

7/19

M41T0

Table 5. DC Characteristics

No te : 1. Val i d for Ambient Operatin g T em pera ture: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept wh ere not e d).

2. At 25° C.

Table 6. Crystal Electrical Characteristics

Not e: 1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thru-

hole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kou-

hou@kdsj.co .jp or http://www.kdsj.co.jp for further information on this crystal type.

2. Load ca pa citor s are i nteg rated wit hin the M41T 0. C irc uit boa rd la yo ut con sidera tio ns fo r the 32 .768 kH z cryst al o f minim um trace

lengths and i solati on from RF generating sig nal s should be taken into ac count.

3. RS = 40 kΩ when VCC ≤ 2.5V .

Sym Parameter Test Condition(1) Min Typ Max Unit

ILI Input Leaka ge Curren t 0V ≤ VIN ≤ VCC ±1 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 µA

ICC1 Supply Current Frequency (SCL) = 400kHz 3.0V 35 55 µA

5.5V 130 200 µA

ICC2(2) Supply Current (Standby) All inputs = VCC – 0.2V

Frequency (SCL) = 0Hz 3.0V 0.9 1.2 µA

5.5V 31 µA

VIL Input Low Voltage –0.3 0.3 VCC V

VIH Input High Voltage 0.7 VCC VCC +

0.3 V

VOL

Output Low Voltage IOL = 3mA 0.4 V

Output Low Voltage (Open

Drain) IOL = 10mA 0.4 V

Symbol Parameter(1,2) Min Typ Max Unit

fOResonant Frequency 32.768 kHz

RSSeries Resistance 60(3) KΩ

CLLoad Capacitance 12.5 pF

M41T0

8/19

OPERATION

The M41T0 clock operates as a slave device on

the serial bus . Access is obt ained by implementing

a start condition f ollowed by the correct slave ad-

dress (D0h). The 8 bytes contained in the device

can then be accessed sequentially in the following

order:

1. Seconds Register

2. Minutes Regi st er

3. Century/Hours Register

4. Day Register

5. Date Regist er

6. Month Register

7. Years Register

8. Control Register

2-Wire Bus Characteri stics

This bus is intended for communication between

different ICs. It consists of t wo lines: one bi-direc-

tional fo r dat a signals (SDA) and one for clock sig-

nals (SCL). Both the SDA and the SCL lines must

be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been defined:

– Data transfer may be initiated only when the bus

is not busy.

– During data transfer, the data l ine must remain

stable whenever the clock line is High. Changes

in the data line while the clock line is High will be

interpreted as control signals.

Accordingly, the following bus conditions have

been defined:

Bus not busy. Both data and clock lines remain

High.

Start data transfer. A change in th e state of the

data line, from High to Low, while the clock is High,

defines the START condi tion.

Stop data transfer. A change in the state of the

data line, from Low to High, while the c lock is High,

defines the STOP condition .

Data valid. The state of the data line represents

valid data when after a start condition, the data line

is stable for the duration of the High period of the

clock signal. The data on the line may be changed

during the Low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated wit h a start condition

and terminated with a stop condition. The num ber

of data bytes transferred between the start and

stop conditions is not limited. The information is

transmitted byte-wide and each rec eiver acknowl-

edges with a ninth bit.

By definition, a device t hat gives out a message is

called “transmitter”, the receiving device t hat gets

the message is called “receiver”. The device that

controls the message is called “master”. The de-

vices that are controlled by the master are called

“slaves”.

Acknowledge. Each byt e of eight bits is followed

by one Acknowledge B it. Thi s Acknowledge Bit is

a low level put on the bus by the receiver, whereas

the master generates an extra ac knowled ge relat-

ed clock pulse.

A slave receiver which is a ddressed is obliged to

generate an acknowledge after the reception of

each byte. Also, a master receiver must generate

an acknowledge after the reception of each byte

that has been clocked out of the slave trans mitter.

The device that acknowledges has to pull down

the SDA line during the acknowledge clock pulse

in such a way that the SDA line is a stable Low dur-

ing the High period of the acknowledge related

clock pulse. Of course, setup and hold times must

be taken int o account. A master receiver must sig-

nal an end-of-d ata to the slave transmitter by not

generating an acknowledge on the last byte that

has been clocked out of the slave. I n this case, the

transmitter must leave the data line High to enable

the master to generate the STOP condition.

9/19

M41T0

Figure 6. Serial Bus Data Transfer Sequen ce

Figure 7. Acknowled gement Seq uence

Figure 8. Bus T iming Requirements Sequence

Note: P = STOP and S = START

AI00587

DATA

CLOCK

DATA LINE

STABLE

DATA VALID

START

CONDITION CHANGE OF

DATA ALLOWED STOP

CONDITION

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCLK FROM

MASTER

START CLOCK PULSE FOR

ACKNOWLEDGEMENT

12 89

MSB LSB

AI00589

SDA

PtSU:STOtSU:STA

tHD:STA

SCL

tSU:DAT

tHD:DAT

tHIGH

tLOW

tHD:STAtBUF

M41T0

10/19

Table 7. AC Characteristics

No te : 1. Val i d for Ambient Operatin g T em pera ture: TA = –40 to 85°C; VCC = 2. 0 t o 5.5V (e xcept wh ere not e d).

2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.

Symbol Parameter(1) Min Typ Max Unit

fSCL SCL Clock Frequency 0 400 kHz

tLOW Clock Low Period 1.3 µs

tHIGH Clock High Period 600 ns

tRSDA and SCL Rise Time 300 ns

tFSDA and SCL Fall Time 300 ns

tHD:STA START Condition Hold Time

(after this period the first clock pulse is generated) 600 ns

tSU:STA START Condition Setup Time

(only relevant for a repeated start condition) 600 ns

tSU:DAT Data Setup Time 100 ns

tHD:DAT(2) Data Hold Time 0 µs

tSU:STO STOP Condition Setup Time 600 ns

tBUF Time the bus must be free before a new transmission can start 1.3 µs

11/19

M41T0

READ Mode

In this mode, the master reads the M41T0 slave

after setting the slave address (see Figure 9). Fol-

lowing the WRITE M ode Control B it (R/W = 0) and

the Acknowledge Bit, the word address An is writ-

ten to the on-chip address pointer. Next the

START condition and sl ave address are repeat ed,

followed by the READ Mode Control Bit (R/W =1).

At this point, the master transmitter becomes the

master receiver. The data byte which was ad-

dressed will be transm itted and the mas ter receiv-

er will send an Acknowledge Bit to the slave

transmitter. The address point er is only increment-

ed on reception of an Acknowledge Bit. The

M41T0 slave transmitter will now place the data

byte at address An+1 on the bus. The master re-

ceiver reads and ackno wledge s the n ew byte and

the addr ess point er is incremented to An+2.

This cycle of reading consecutive addresses will

continue until the master receiver se nds a STOP

condition to the slave transmitter.

An alternate READ Mode may also be implement-

ed, whereby the master reads the M41T0 slave

without first w riting to t he (volatile) a ddress point-

er. The first address that is read is the last one

stored in the pointer (see Figure 11, page 12).

WRITE Mod e

In this mode the master transmitter transmits to

the M41T0 slave receiver. Bus protocol is shown

in Figure 12, p age 12. Following the S TART con-

dition and slave address, a logic '0' (R/W = 0) is

placed on the bus and indicates to the addressed

device that word address An will follow and is to be

written to the on-chip address pointer. The data

word to be written to the memory is strobed in next

and the internal address pointer is increme nted to

the next memory location within the RAM on the

reception of an acknowledge clock. The M41T0

slave receiver will send an acknowledge clock to

the master transmitter after it has received the

slave address and again after it has received the

word address and eac h data byte (see Figure 9).

Figure 9. Slave Address Locat ion

AI00602

R/W

SLAVE ADDRESS

START A

0100011

MSB

LSB

M41T0

12/19

Figure 10. READ Mode Sequence

Figu re 11 . Al te rnat e R E A D Mo de S equence

Figu re 12 . WRI TE Mode S equenc e

AI00899

BUS ACTIVITY:

ACK

NO ACK STOP

START

SDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1

DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

START

R/W

SLAVE

ADDRESS

ACK

AI00895

BUS ACTIVITY:

ACK

NO ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

SLAVE

ADDRESS

AI00591

BUS ACTIVITY:

ACK

ACK STOP

START

PSDA LINE

BUS ACTIVITY:

MASTER

R/W

DATA n DATA n+1 DATA n+X

WORD

ADDRESS (An)

SLAVE

ADDRESS

13/19

M41T0

CLOCK OPERATION

The M41T0 is driven by a quartz controlled oscil la-

tor with a nominal frequency of 32.768kHz. The

accuracy of the Real-Time Clock depends on the

frequency of t he quartz crystal that i s used as the

time-base for the RTC. The M41T0 is tested to

meet ± 35 ppm with nominal crystal. The eight-

byte Clock Regi ster (see Table 8, page 14) is used

to both set t he clock and to read the date and time

from the clock, in a binary coded decimal format.

Seconds, Minutes, and Hours are contained within

the first three registers. Bits D6 and D7 of Clock

RY ENABLE Bit (CEB) and the CENTURY Bit

(CB). Setting CEB to a '1' will cause CB to toggle,

either from '0' to '1' or from '1' to '0' at the turn of

the century (depending upon its initial state). If

CEB is set to a '0', CB will not toggle. Bits D0

through D2 of Register 3 contain the Day (day of

week). Registers 4, 5 and 6 contain the Date (day

of month), Month and Years. The final register is

the Control Register. Bit D7 of Register 0 contains

the STOP Bit (ST). Setting this bit to a '1' will cause

the oscillator to stop. If the device is expected to

spend a significant amount of time on the shelf, the

oscillator may be stopped t o reduce cu rrent drain.

When reset to a '0' the oscillator restarts within

four seconds (typically one second).

The seven clock registers may be read one byte at

a time, or in a s equ ential block . T he Control Reg-

ister (Address location 7) may be accessed inde-

pendently. Provision has been made to assure

that a cloc k updat e does not occur while any of the

seven clock addresses are being read. If a clock

address is being read, an update of the clock reg-

isters will be delayed by 250ms to allow the READ

to be completed before the update occurs. This

will pr ev e nt a tran s it ion of da t a d ur ing t he REA D .

Note: This 250ms delay affects only the clock reg-

ister update and does not alter the actual clock

time.

Output Driver Pin

The OUT pin is an output driver that reflects the

contents of D7 of the Control Register. In other

words, when D7 of location 7 is a '0' then the OUT

pin will be driven low.

Note: The OUT pin is open drain which requires

an ext ernal pull-up resist or.

Oscillator Sto p Detecti on

If the Oscillator Fail (OF) Bit is internally set to a '1,'

this indicates that the os cillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of the clock and date da-

ta. T his bit w ill b e se t to ' 1' any ti me the oscilla tor

stops. The following condit ions can cause the OF

Bit to be set:

– The first time power is applied (defaults to a '1'

on power-up).

– The vol tage present on VCC is insufficie nt to

support oscillation.

– The ST Bit is set to '1.'

– External int erference or removal of the crystal.

This bit will remain set to '1' until written to logic '0.'

The oscillator mu st start and have ru n for at le ast

4 seconds before at tempting to reset the OF Bit to

'0.' This function operates both under normal pow-

er and in battery back-up.

Initial Power-on Defaults

Upon initial application of power t o the device, the

OUT Bit and OF Bit will be set to a '1,' while the ST

Bit will be set to '0.' All o ther Register bits will ini-

tially power-on in a ran dom state.

M41T0

14/19

Table 8. Register Map

Keys : ST = STOP Bit

OUT = Output level

X = Don’t c are

0 = Must be set to '0.'

CE B = C entury Enable Bi t

CB = Century B i t

OF = Oscillator Fail Bit

Note: 1. W hen CEB is set to '1', CB will toggle from '0' to '1' or fr om '1' to '0' at the t urn of the ce ntury (dependent upon the initial value set).

When CEB is set to '0', CB will not toggle.

Address Data Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

0 ST 10 Seconds Seconds Seconds 00-59

1 OF 10 Minutes Minutes Minutes 00-59

2CEB (1) CB 10 Hours Hours Century/Hours 0-1/00-23

3 XXXXX Day Day 01-07

4 X X 10 Date Date Date 01 -31

5 X X X 10 M. Month Month 01-12

6 10 Years Years Year 00-99

7OUT0XXXXXX Control

15/19

M41T0

PACKAGE MECHANICAL INF O RMATION

Figure 13. SO8 – 8 lead Plastic Small Outline, 150 mils body wi dth, Package Mechanical Drawing

Not e: Drawing is not to scale.

Table 9. SO8 – 8-lead Plastic Sm all Outline, 150 mils body width, Packag e Mec han ical Data

Symb mm inches

Typ Min Max Typ Min Max

A – 1.35 1.75 – 0.053 0.069

A1 – 0.10 0.25 – 0.004 0.010

B – 0.33 0.51 – 0.013 0.020

C – 0.19 0.25 – 0.007 0.010

D – 4.80 5.00 – 0.189 0.197

ddd – – 0.10 – – 0.004

E – 3.80 4.00 – 0.150 0.157

e 1.27 – – 0.050 – –

H – 5.80 6.20 – 0.228 0.244

h – 0.25 0.50 – 0.010 0.020

L – 0.40 0.90 – 0.016 0.035

α–0°8°–0°8°

N8 8

SO-A

ddd

LA1 α

h x 45˚

M41T0

16/19

Figure 14. TSSOP8 – 8 -lead , Th in Shr ink Sma ll Package Outline

Not e: Drawing is not to scale.

Table 10. TSSOP8 – 8-lead, Thi n Shrink Small Package Outli ne Mechanical Data

Symb mm inches

Typ Min Max Typ Min Max

A – – 1.20 – – 0.047

A1 – 0.05 0.15 – 0.002 0.006

A2 1.00 0.80 1.05 0.039 0.032 0.041

b – 0.19 0.30 – 0.008 0.012

c – 0.09 0.20 – 0.004 0.008

CP – – 0.10 – – 0.004

D 3.00 2.90 3.10 0.118 0.114 0.122

e 0.65 – – 0.026 – –

E 6.40 6.20 6.60 0.252 0.244 0.260

E1 4.40 4.30 4.50 0.173 0.169 0.177

L 0.60 0.45 0.75 0.024 0.018 0.030

L1 1.00 – – 0.039 – –

α–0°8°–0°8°

N8 8

TSSOP8AM

EE1

A2A

17/19

M41T0

PART NUMBERING

Table 11. Ordering Information Scheme

Not e: 1. DW (TSSOP8) package only.

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office near est to you.

Example: M41T 0 M 6 T

Device Type

M41T

Supply Voltage and Write Protect Voltage

0 = VCC = 2.0 to 5.5V

Package

M = SO8 (150mils width)

DW = TSSOP8

Tempera ture Rang e

6 = –40 to 85°C

Shipping Method for SOIC

blank = Tubes

E = Pb-Free Package (ECO PACK®)(1), Tubes

F = Pb-Free Package (ECO PACK®)(1), Tape & Reel

T = Tape & Reel

M41T0
18/19
RE VISION HISTORY
Table 12. Document Revisio n History
Date Rev. # Revision Details
February 2003 1.0 First Issue
18-Feb-03 1.1 Add Pb-Free information (Table 2, 11); update package information (Figure 1, 14; Table 
11)
01-Apr-03 1.2 Fix package outline and data (Figure 1, 14, Table 10, 11)

19/19

M41T0

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