TC59LM914/06AMB-37,-45,-50 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TM 4,194,304-WORDS x 8 BANKS x 16-BITS Network FCRAM TM 8,388,608-WORDS x 8 BANKS x 8-BITS Network FCRAM DESCRIPTION Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMB is Network FCRAMTM containing 536,870,912 memory cells. TC59LM914AMB is organized as 4,194,304-words x 8 banks x 16 bits, TC59LM906AMB is organized as 8,388,608-words x 8 banks x 8 bits. TC59LM914/06AMB feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM914/06AMB can operate fast core cycle compared with regular DDR SDRAM. TC59LM914/06AMB is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition. FEATURES PARAMETER CL = 3 tCK * * * * * * * * * * * * * * Clock Cycle Time (min) -37 TC59LM914/06 -45 -50 5.5 ns 5.5 ns 6.0 ns CL = 4 4.5 ns 5.0 ns 5.5 ns CL = 5 3.75 ns 4.5 ns 5.0 ns tRC Random Read/Write Cycle Time (min) 22.5 ns 25 ns 27.5 ns tRAC Random Access Time (max) 22.0 ns 22.0 ns 24.0 ns IDD1S Operating Current (single bank) (max) TBD TBD TBD lDD2P Power Down Current (max) TBD TBD TBD lDD6 TBD TBD TBD Self-Refresh Current (max) Fully Synchronous Operation * Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. * Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 3.75 ns minimum Clock: 266 MHz maximum Data: 533 Mbps/pin maximum Fast cycle and Short Latency Differential Data Strobe DQS : TC59LM906AMB Distributed Auto-Refresh cycle in 3.9 s Self-Refresh Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length CAS Latency = 3, 4, 5 Burst Length = 2, 4 Organization: TC59LM914AMB : 4,194,304 words x 8 banks x 16 bits TC59LM906AMB : 8,388,608 words x 8 banks x 8 bits Power Supply Voltage VDD: 2.5 V 0.15V VDDQ: 1.4 V ~ 1.9 V Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL. Package: 60Ball BGA, 1mm x 1mm Ball pitch Notice : FCRAM is trademark of Fujitsu Limited, Japan. 2003-08-04 1/57 TC59LM914/06AMB-37,-45,-50 TC59LM906AMB PIN NAMES PIN ASSIGNMENT (TOP VIEW) PIN NAME A0~A13 Address Input BA0~BA2 Bank Address DQ0~DQ7 Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input DQS / DQS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground VDDQ Power (+1.5V / +1.8 V) (for I/O buffer) VSSQ Ground (for I/O buffer) VREF Reference Voltage NC Not Connected ball pitch=1.0 x 1.0mm x8 1 2 3 4 5 6 Index A VSS DQ7 DQ0 VDD B NC VSSQ VDDQ NC C DQ6 VDDQ VSSQ DQ1 D NC DQ5 DQ2 NC E NC VSSQ VDDQ NC F DQ4 VDDQ VSSQ DQ3 G NC VSSQ VDDQ NC H NC DQS DQS NC J VREF VSS VDD BA2 K CLK CLK FN A13 L A12 PD CS NC M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A5 A6 A2 A1 R VSS A4 A3 VDD 2003-08-04 2/57 TC59LM914/06AMB-37,-45,-50 TC59LM914AMB PIN NAMES PIN ASSIGNMENT (TOP VIEW) PIN NAME A0~A13 Address Input BA0~BA2 Bank Address DQ0~DQ15 Data Input/Output CS Chip Select FN Function Control PD Power Down Control CLK, CLK Clock Input UDQS / LDQS Write/Read Data Strobe VDD Power (+2.5 V) VSS Ground VDDQ Power (+1.5V / +1.8 V) (for I/O buffer) VSSQ Ground (for I/O buffer) VREF Reference Voltage NC Not Connected ball pitch=1.0 x 1.0mm X16 1 2 3 4 5 6 Index A VSS DQ15 DQ0 VDD B DQ14 VSSQ VDDQ DQ1 C DQ13 VDDQ VSSQ DQ2 D DQ12 DQ11 DQ4 DQ3 E DQ10 VSSQ VDDQ DQ5 F DQ9 VDDQ VSSQ DQ6 G DQ8 VSSQ VDDQ DQ7 H NC UDQS LDQS NC J VREF VSS VDD BA2 K CLK CLK FN A13 L A12 PD CS NC M A11 A9 BA1 BA0 N A8 A7 A0 A10 P A5 A6 A2 A1 R VSS A4 A3 VDD 2003-08-04 3/57 TC59LM914/06AMB-37,-45,-50 BLOCK DIAGRAM CLK CLK PD CS FN DLL CLOCK BUFFER COMMAND DECODER To each block BANK #7 BANK #6 BANK #5 BANK #4 BANK #3 BANK #2 BANK #1 CONTROL SIGNAL GENERATOR BA0~BA2 ADDRESS BUFFER UPPER ADDRESS LATCH LOWER ADDRESS LATCH REFRESH COUNTER BURST COUNTER DATA CONTROL and LATCH CIRCUIT A0~A13 ROW DECODER BANK #0 MODE REGISTER MEMORY CELL ARRAY COLUMN DECODER READ DATA BUFFER WRITE ADDRESS LATCH/ ADDRESS COMPARATOR DQS DQS WRITE DATA BUFFER DQ BUFFER DQ0~DQn Note: The TC59LM906AMB configuration is 8 Bank of 16384 x 512 x 8 of cell array with the DQ pins numbered DQ0~DQ7. The TC59LM914AMB configuration is 8 Bank of 16384 x 256 x 16 of cell array with the DQ pins numbered DQ0~DQ15. TC59LM906AMB has DQS pin for Differential Data Strobe. TC59LM914AMB has UDQS and LDQS. 2003-08-04 4/57 TC59LM914/06AMB-37,-45,-50 ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER RATING UNIT -0.3~ 3.3 V VDD Power Supply Voltage VDDQ Power Supply Voltage (for I/O buffer) -0.3~VDD+ 0.3 V VIN Input Voltage -0.3~VDD+ 0.3 V VOUT Output and I/O pin Voltage -0.3~VDDQ + 0.3 V VREF Input Reference Voltage -0.3~VDD+ 0.3 V Topr Operating Temperature (Ambient) 0~70 C Tstg Storage Temperature -55~150 C Tsolder Soldering Temperature (10 s) 260 C PD Power Dissipation 2 W IOUT Short Circuit Output Current 50 mA NOTES Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability. RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (TCASE = 0~85C) SYMBOL PARAMETER MIN TYP. MAX UNIT 2.375 2.5 2.625 V 1.4 1.9 V NOTES VDD Power Supply Voltage VDDQ Power Supply Voltage (for I/O buffer) VREF Input Reference Voltage VDDQ/2 x 95% VDDQ/2 VDDQ/2 x 105% V 2 VIH (DC) Input DC High Voltage VREF + 0.125 VDDQ + 0.2 V 5 VIL (DC) Input DC Low Voltage -0.1 VREF - 0.125 V 5 VICK (DC) Differential Clock DC Input Voltage -0.1 VDDQ + 0.1 V 10 VID (DC) Input Differential Voltage. CLK and CLK inputs (DC) 0.4 VDDQ + 0.2 V 7, 10 VIH (AC) Input AC High Voltage VREF + 0.2 VDDQ + 0.2 V 3, 6 VIL (AC) Input AC Low Voltage -0.1 VREF - 0.2 V 4, 6 VID (AC) Input Differential Voltage. CLK and CLK inputs (AC) 0.55 VDDQ + 0.2 V 7, 10 VX (AC) Differential AC Input Cross Point Voltage VDDQ/2 - 0.125 VDDQ/2 + 0.125 V 8, 10 VISO (AC) Differential Clock AC Middle Level VDDQ/2 - 0.125 VDDQ/2 + 0.125 V 9, 10 2003-08-04 5/57 TC59LM914/06AMB-37,-45,-50 Note: (1) All voltages referenced to VSS, VSSQ. (2) VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). (3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width 5 ns. (4) Undershoot limit: VIL (min) = -0.7 V with a pulse width 5 ns. (5) VIH (DC) and VIL (DC) are levels to maintain the current logic state. (6) VIH (AC) and VIL (AC) are levels to change to the new logic state. (7) VID is magnitude of the difference between CLK input level and CLK input level. (8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. (9) VISO means {VICK (CLK) + VICK ( CLK )} /2 (10) Refer to the figure below. CLK Vx Vx Vx Vx Vx VID (AC) CLK VSS VICK VICK VICK VISO (min) VISO (max) VICK |VID (AC)| 0 V Differential VISO VSS (11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) 0.04 V. CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25C) SYMBOL PARAMETER MIN MAX Delta UNIT CIN Input pin Capacitance 1.5 2.5 0.25 pF CINC Clock pin (CLK, CLK ) Capacitance 1.5 2.5 0.25 pF CI/O DQ, DQS, UDQS, LDQS, DQS Capacitance 2.5 4 0.5 pF CNC NC pin Capacitance 4 pF Note: These parameters are periodically sampled and not 100% tested. 2003-08-04 6/57 TC59LM914/06AMB-37,-45,-50 RECOMMENDED DC OPERATING CONDITIONS (VDD=2.5V 0.125V, VDDQ=1.8V 0.1V, TCASE = 0~85C) SYMBOL IDD1S IDD2N IDD2P IDD5 IDD6 MAX PARAMETER Operating Current tCK = min; IRC = min, Read/Write command cycling, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, 1 bank operation, Burst length = 4, Address change up to 2 times during minimum IRC. Standby Current tCK = min, CS = VIH, PD = VIH, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, All banks: inactive state, Other input signals are changed one time during 4 x tCK. Standby (power down) Current tCK = min, CS = VIH, PD = VIL (power down), 0 V VIN VDDQ, All banks: inactive state Auto-Refresh Current tCK = min; IREFC = min, tREFI = min, Auto-Refresh command cycling, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, Address change up to 2 times during minimum IREFC. Self-Refresh Current Self-Refresh mode PD = 0.2 V, 0 V VIN VDDQ NOTES -45 -50 TBD TBD TBD 1, 2 TBD TBD TBD 1 mA TBD TBD TBD 1 TBD TBD TBD 1 TBD TBD TBD MIN MAX UNIT PARAMETER SYMBOL UNIT -37 NOTES ILI Input Leakage Current ( 0 V VIN VDDQ, all other pins not under test = 0 V) -5 5 A ILO Output Leakage Current (Output disabled, 0 V VOUT VDDQ) -5 5 A IREF VREF Current -5 5 A VOH = 1.420 V -5.6 3 VOL = 0.280 V 5.6 3 VOH = 1.420 V -9.8 3 VOL = 0.280 V Output DC Current (VDDQ = 1.7V~1.9V) V OH = 1.420 V 9.8 -2.8 VOL = 0.280 V 2.8 3 VOH = 1.420 V -13.4 3 VOL = 0.280 V 13.4 3 VOH = VDDQ - 0.4V -4 3 VOL = 0.4V 4 3 VOH = VDDQ - 0.4V -8 3 IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) Normal Output Driver Strong Output Driver Weak Output Driver Full Strength Output Driver Normal Output Driver IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) Strong Output Driver Weak Output Driver Full Strength Output Driver mA 3 3 VOL= 0.4V Output DC Current (VDDQ = 1.4V~1.6V) Not defined 8 Not defined VOH = VDDQ - 0.4V -10 3 VOL= 0.4V 10 3 mA 3 Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register. 4. In case of Full Strength Output Driver, OCD calibration (Off chip Driver impedance adjustment) can be used. The specification of Full Strength Output Driver defines the default value after power-up. 2003-08-04 7/57 TC59LM914/06AMB-37,-45,-50 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (VDD=2.5V0.125V, VDDQ=1.8V0.1V, TCASE=0~85C) SYMBOL -37 PARAMETER MIN tRC tCK MAX MIN -50 MAX MIN UNIT NOTES MAX 22.5 25 27.5 3 CL = 3 5.5 8.5 5.5 8.5 6.0 8.5 3 CL = 4 4.5 8.5 5.0 8.5 5.5 8.5 3 CL = 5 3.75 8.5 4.5 8.5 5.0 8.5 3 Random Cycle Time Clock Cycle Time -45 tRAC Random Access Time 22.0 22.0 24 3 tCH Clock High Time 0.45 x tCK 0.45 x tCK 0.45 x tCK 3 tCL Clock Low Time 0.45 x tCK 0.45 x tCK 0.45 x tCK 3 tCKQS DQS Access Time from CLK -0.45 0.45 -0.5 0.5 -0.6 0.6 3, 8 tQSQ Data Output Skew from DQS 0.25 0.3 0.35 4 tAC Data Access Time from CLK -0.5 0.5 -0.6 0.6 -0.65 0.65 3, 8 tOH Data Output Hold Time from CLK -0.5 0.5 -0.6 0.6 -0.65 0.65 3, 8 tQSPRE DQS (read) Preamble Pulse Width 0.9 x tCK 1.1 x tCK 0.9 x tCK 1.1 x tCK 0.9 x tCK 1.1 x tCK 3, 8 tHP CLK half period (minimum of Actual tCH, tCL) min(tCH, tCL) min(tCH, tCL) min(tCH, tCL) 3 tQSP DQS (read) Pulse Width tHP-tQHS tHP-tQHS tHP-tQHS 4, 8 tQSQV Data Output Valid Time from DQS tHP-tQHS tHP-tQHS tHP-tQHS 4, 8 tQHS DQ Hold Skew factor 0.055 x tCK +0.17 0.055 x tCK +0.17 0.055 x tCK +0.17 tDQSS DQS (write) Low to High Setup Time tDSPRE DQS (write) Preamble Pulse Width tDSPRES DQS First Input Setup Time tDSPREH DQS First Low Input Hold Time tDSP DQS High or Low Input Pulse Width 0.35 x tCK 0.65 x tCK 0.35 x tCK 0.65 x tCK 0.35 x tCK 0.65 x tCK tDSS DQS Input Falling Edge to Clock Setup Time 0.75 x tCK 1.25 x tCK 0.75 x tCK 1.25 x tCK 0.75 x tCK 1.25 x tCK 0.25 x tCK 0.25 x tCK 0 0.25 x tCK 0 0.25 x tCK 3 0.25 x tCK 0 3 0.25 x tCK 3 ns 4 4 CL = 3 0.75 0.9 1.0 3, 4 CL = 4 0.75 0.9 1.0 3, 4 CL = 5 0.75 0.9 1.0 3, 4 0.55 0.65 0.75 3, 4 0.4 x tCK 0.4 x tCK 0.4 x tCK 4 CL = 3 0.75 0.9 1.0 3, 4 CL = 4 0.75 0.9 1.0 3, 4 CL = 5 0.75 0.9 1.0 3, 4 -0.5x tCK 0.5x tCK -0.5x tCK 0.5x tCK -0.5x tCK 0.5x tCK tDSH DQS Input Falling Edge Hold Time from CLK tDSPST DQS (write) Postamble Pulse Width tDSPSTH DQS (write) Postamble Hold Time tDSSK UDQS - LDQS Skew (x16) tDS Data Input Setup Time from DQS 0.35 0.4 0.45 4 tDH Data Input Hold Time from DQS 0.35 0.4 0.45 4 tIS Command/Address Input Setup Time 0.5 0.6 0.7 3 tIH Command/Address Input Hold Time 0.5 0.6 0.7 3 2003-08-04 8/57 TC59LM914/06AMB-37,-45,-50 AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued) SYMBOL -37 PARAMETER -45 -50 UNIT MIN MAX MIN MAX MIN MAX NOTES tLZ Data-out Low Impedance Time from CLK -0.5 -0.6 -0.65 3,6,8 tHZ Data-out High Impedance Time from CLK 0.5 0.6 0.65 3,7,8 tQSLZ DQS-out Low Impedance Time from CLK -0.5 -0.6 -0.65 3,6,8 tQSHZ DQS-out High Impedance Time from CLK -0.5 0.5 -0.6 0.6 -0.65 0.65 3,7,8 tQPDH Last output to PD High Hold Time 0 0 0 tPDEX Power Down Exit Time 0.6 0.7 0.8 tT Input Transition Time 0.1 1 0.1 1 0.1 1 tFPDL PD Low Input Window for Self-Refresh Entry -0.5 x tCK 5 -0.5 x tCK 5 -0.5 x tCK 5 tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3.9 tPAUSE Pause Time after Power-up 200 200 200 CL = 3 5 5 5 IRC Random Read/Write Cycle Time (applicable to same bank) CL = 4 5 5 5 CL = 5 6 6 6 IRCD RDA/WRA to LAL Command Input Delay (applicable to same bank) 1 1 1 1 1 1 CL = 3 4 4 4 IRAS LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 4 4 4 4 CL = 5 5 5 5 IRBD Random Bank Access Delay (applicable to other bank) 2 2 2 BL = 2 2 2 2 IRWD LAL following RDA to WRA Delay (applicable to other bank) BL = 4 3 3 3 1 1 1 CL = 3 5 5 5 CL = 4 5 5 5 CL = 5 6 6 6 IWRD LAL following WRA to RDA Delay (applicable to other bank) IRSC Mode Register Set Cycle Time IPD PD Low to Inactive State of Input Buffer 1 1 1 IPDA PD High to Active State of Input Buffer 1 1 1 CL = 3 Power down mode valid CL = 4 from REF command CL = 5 15 15 15 IPDV 18 18 18 22 22 22 CL = 3 15 15 15 CL = 4 18 18 18 CL = 5 22 22 22 IREFC IREFC IREFC 200 200 200 IREFC Auto-Refresh Cycle Time ICKD REF Command to Clock Input Disable at Self-Refresh Entry ILOCK DLL Lock-on Time (applicable to RDA command) ns 3 3 s 5 cycle 2003-08-04 9/57 TC59LM914/06AMB-37,-45,-50 AC TEST CONDITIONS SYMBOL PARAMETER VALUE UNIT VIH (min) Input High Voltage (minimum) VREF + 0.2 V VIL (max) Input Low Voltage (maximum) VREF - 0.2 V VREF Input Reference Voltage VDDQ/2 V VTT Termination Voltage VREF V VSWING Input Signal Peak to Peak Swing 0.7 V Vr Differential Clock Input Reference Level VX (AC) V VID (AC) Input Differential Voltage 1.0 V SLEW Input Signal Minimum Slew Rate 2.5 V/ns VOTR Output Timing Measurement Reference Voltage VDDQ/2 V NOTES 9 VTT VDDQ 50 VIH min (AC) VSWING VREF 25 Z = 50 Output VIL max (AC) Z = 50 50 VSS T VTT T SLEW = (VIH min (AC) - VIL max (AC))/T AC Test Load Note: (1) Transition times are measured between VIH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. (2) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 x tCK, tCK = 5 ns, 0.75 x 5 ns = 3.75 ns is rounded up to 3.8 ns.) (3) There parameters are measured from the differential clock (CLK and CLK ) AC cross point. (4) These parameters are measured from signal transition point of DQS crossing VREF level. In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS . (5) The tREFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distributed refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 s (8 x 400 ns) is to 8 times in the maximum. (6) Low Impedance State is specified at VDDQ/2 0.2 V from steady state. (7) High Impedance State is specified where output buffer is no longer driven. (8) These parameters depend on the clock jitter. These parameters are measured at stable clock. (9) Output timing is measured by using Normal driver strength. 2003-08-04 10/57 TC59LM914/06AMB-37,-45,-50 POWER UP SEQUENCE (1) As for PD , being maintained by the low state ( 0.2 V) is desirable before a power-supply injection. (2) Apply VDD before or at the same time as VDDQ. (3) Apply VDDQ before or at the same time as VREF. (4) Start clock (CLK, CLK ) and maintain stable condition for 200 s (min). (5) After stable power and clock, apply DESL and take PD =H. (6) Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command (A7A9=0). (Note: 1, 2) (7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1) (8) Issue two or more Auto-Refresh commands (Note: 1). (9) Ready for normal operation after 200 clocks from Extended Mode Register programming. (10) If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence. Notes: (1) Sequence 6, 7 and 8 can be issued in random order. (2) Set DQS mode for TC59LM906AMB. (3) L = Logic Low, H = Logic High 2.5V(TYP) VDD 1.8V(TYP) VDDQ 0.9V(TYP) VREF CLK CLK tPDEX lPDA 200us(min) lRSC lRSC lREFC lREFC PD 200clock cycle(min) Command DESL RDA MRS DESL op-code RDA MRS DESL WRA REF DESL WRA REF DESL op-code Address EMRS MRS DQ Hi-Z DQS DQS Hi-Z EMRS MRS Auto Refresh cycle Normal Operation 2003-08-04 11/57 TC59LM914/06AMB-37,-45,-50 TIMING DIAGRAMS Input Timing Command and Address tCK tCK tCH tCL CLK CLK tIS CS tIH tIS 1st tIS FN 2nd tIH tIS 1st tIS A0~A13 BA0~BA2 tIH tIH 2nd tIH tIH tIS UA, BA LA Data * TC59LM906AMB DQS enable mode DQS DQS tDS tDH tDS tDH DQ (input) Data * TC59LM906AMB * TC59LM914AMB DQS disable mode DQS tDS tDH tDS tDH DQ (input) Refer to the Command Truth Table. Timing of the CLK, CLK tCH tCL VIH VIH (AC) VIL (AC) VIL CLK CLK tT tT tCK CLK VIH CLK VIL VID (AC) VX VX VX 2003-08-04 12/57 TC59LM914/06AMB-37,-45,-50 Read Timing (Burst Length = 4) tCH CLK CLK tIS tIH tCL tCK LAL (after RDA) Input (control & addresses) DESL tCKQS tQSLZ CAS latency = 3 tCKQS tQSPRE tCKQS tQSP tQSP tQSHZ Hi-Z DQS/ DQS (output) Preamble Postamble tQSQV tLZ tQSQ tQSQ Hi-Z DQ (output) Q0 tQSQV Q1 tAC tAC tQSLZ CAS latency = 4 tQSQ tQSPRE Q2 tHZ Q3 tAC tOH tCKQS tCKQS tCKQS t tQSHZ QSP tQSP Hi-Z DQS/ DQS (output) Preamble Postamble tLZ tQSQ Hi-Z DQ (output) tQSQV tQSQ Q0 tAC tQSQ tQSQV Q1 tAC Q2 tHZ Q3 tAC tOH tCKQS tQSLZ CAS latency = 5 DQS/ DQS (output) tCKQS tQSPRE tQSHZ Hi-Z Preamble Postamble tLZ tQSQ DQ (output) tCKQS tQSP tQSP Hi-Z tQSQV tQS Q0 tAC tQSQ tQSQV Q1 tAC Q2 tHZ Q3 tAC tOH Note: TC59LM914AMB doesn't have DQS . The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB) LDQS DQ0DQ7 UDQS DQ8DQ15 The condition of DQS is changed from Hi-Z to "Low" at Premble and the condition of DQS is changed from "Low" to Hi-Z at Postamble. DQS is Hi-Z in DQS disable mode. DQS mode is chosen by EMRS. (TC59LM906AMB) When DQS is enable, the condtion of DQS is changed from Hi-Z to "High" at Premble and the condition of DQS is changed from "High" to Hi-Z at Postamble. 2003-08-04 13/57 TC59LM914/06AMB-37,-45,-50 Write Timing (Burst Length = 4) tCH tCL tCK CLK CLK tIS tIH LAL (after WRA) Input (control & addresses) DESL tDSPSTH tDQSS tDSS tDSPRES CAS latency = 3 tDSPREH tDSP tDSP tDSP tDSPST DQS/ DQS (input) tDSS Preamble tDSPRE tDS tDS tDS tDH tDH DQ (input) Postamble D0 D1 D2 tDH D3 tDQSS tDSS tDSPRES CAS latency = 4 tDSPSTH tDSS tDSPREH tDSP tDSP tDSP tDSPST DQS/ DQS (input) Preamble tDSPRE Postamble tDS tDH DQ (input) D0 tDS D1 tDS tDH tDH D3 D2 tDQSS tDQSS tDSS tDSPRES tDSS tDSPSTH tDSPREH tDSP tDSP tDSP tDSPST CAS latency = 5 DQS/ DQS (input) Preamble tDSPRE Postamble tDS tDS tDH DQ (input) D0 tDS tDH D1 D2 tDH D3 tDQSS tDQSS Note: TC59LM914AMB doesn't have DQS . The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB) LDQS DQ0DQ7 UDQS DQ8DQ15 DQS is ignored in DQS disable mode. DQS mode is chosen by EMRS. (TC59LM906AMB) 2003-08-04 14/57 TC59LM914/06AMB-37,-45,-50 tREFI, tPAUSE, Ixxxx Timing CLK CLK tREFI, tPAUSE, IXXXX tIS tIH tIS tIH Input (control & addresses) Command Command Note: "IXXXX" means "IRC", "IRCD", "IRAS", etc. 2003-08-04 15/57 TC59LM914/06AMB-37,-45,-50 Write Timing (x16 device) (Burst Length =4) CLK CLK Input (control & addresses) WRA LAL (DESL) tDSSK tDSSK tDSSK tDSSK CAS latency = 3 LDQS Preamble tDS tDS D0 DQ0~DQ7 tDH tDH tDH Postamble tDS tDS D1 D2 tDH D3 UDQS Preamble tDS tDS tDH DQ8~DQ15 tDS tDH tDH D0 Postamble tDS tDH D1 D3 tDSSK tDSSK tDSSK tDSSK CAS latency = 4 LDQS Preamble tDS tDS tDH tDH D0 DQ0~DQ7 tDS Postamble tDS tDH tDH D1 D2 D3 UDQS Preamble tDS tDS tDH DQ8~DQ15 tDS tDH D0 D1 Postamble tDS tDH D2 tDH D3 tDSSK tDSSK tDSSK tDSSK CAS latency = 5 LDQS Preamble tDS tDS tDH tDH DQ0~DQ7 tDS D0 Postamble tDS tDH tDH D1 D2 D3 UDQS Preamble tDS tDS tDH tDH DQ8~DQ15 tDS D0 D1 tDS tDH D2 Postamble tDH D3 2003-08-04 16/57 TC59LM914/06AMB-37,-45,-50 FUNCTION TRUTH TABLE (Notes: 1, 2, 3) Command Truth Table (Notes: 4) * The First Command SYMBOL FUNCTION CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 DESL Device Deselect H x x x x x x RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA * The Second Command (The next clock of RDA or WRA command) SYMBOL FUNCTION CS FN BA1~ BA0 BA2 A13 A12~ A11 A10~A 9 A8 A7 A6~A0 LAL Lower Address Latch (x16) H x x x V V x x LA LA LAL Lower Address Latch (x8) H x x x V x x LA LA LA REF Auto-Refresh L x x x x x x x x x MRS Mode Register Set L x V L L L L L V V Notes: 1. L = Logic Low, H = Logic High, x = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to "STATE DIAGRAM" and the command table below. Read Command Table COMMAND (SYMBOL) CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 RDA (1st) L H BA UA UA UA UA LAL (2nd) H x x x LA LA LA NOTES 5 Note 5 : For x16 device, A8 is "X" (either L or H). Write Command Table * TC59LM914AMB COMMAND (SYMBOL) CS FN BA1~ BA0 BA2 A13 A12 A11 A10~ A9 A8 A7 A6~A0 WRA (1st) L L BA BA UA UA UA UA UA UA UA LAL (2nd) H x x LVW0 LVW1 UVW0 UVW1 x x LA LA COMMAND (SYMBOL) CS FN BA1~ BA0 BA2 A13 A12 A11 A10~ A9 A8 A7 A6~A0 WRA (1st) L L BA BA UA UA UA UA UA UA UA LAL (2nd) H x x VW0 VW1 x x x LA LA LA * TC59LM906AMB Notes: 6. BA2 and A13~A11 are used for Variable Write Length (VW) control at Write Operation. 2003-08-04 17/57 TC59LM914/06AMB-37,-45,-50 FUNCTION TRUTH TABLE (continued) VW Truth Table Burst Length BL=2 BL=4 Function VW0 VW1 Write All Words L x Write First One Word H x Reserved L L Write All Words H L Write First Two Words L H Write First One Word H H Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7. UVW0 and UVW1 control DQ8~DQ15. Mode Register Set Command Table COMMAND (SYMBOL) CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES RDA (1st) L H x x x x x MRS (2nd) L x V V V V V CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 8 Notes: 8. Refer to "MODE REGISTER TABLE". Auto-Refresh Command Table COMMAND (SYMBOL) CURRENT STATE Active WRA (1st) Auto-Refresh REF (2nd) FUNCTION PD n-1 n Standby H H L L x x x x x Active H H L x x x x x x CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES Self-Refresh Command Table COMMAND (SYMBOL) CURRENT STATE Active WRA (1st) Self-Refresh Entry FUNCTION PD NOTES n-1 n Standby H H L L x x x x x REF (2nd) Active H L L x x x x x x Self-Refresh L L x x x x x x x SELFX Self-Refresh L H H x x x x x x 11 COMMAND (SYMBOL) CURRENT STATE CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES PDEN 10 Self-Refresh Continue Self-Refresh Exit 9, 10 Power Down Table FUNCTION Power Down Entry Power Down Continue Power Down Exit Notes: 9. 10. PD n-1 n Standby H L H x x x x x x Power Down L L x x x x x x x PDEX Power Down L H H x x x x x x 11 PD has to be brought to Low within tFPDL from REF command. PD should be brought to Low after DQ's state turned high impedance. 11. When PD is brought to High from Low, this function is executed asynchronously. 2003-08-04 18/57 TC59LM914/06AMB-37,-45,-50 FUNCTION TRUTH TABLE (continued) CURRENT STATE PD n-1 n CS FN ADDRESS COMMAND ACTION NOTES Idle H H H H H L H H H L L x H L L H L x x H L x x x x BA, UA BA, UA x x x DESL RDA WRA PDEN Row Active for Read H H H H L H H L L x H L H L x x x x x x LA Op-code x x x LAL MRS/EMRS PDEN MRS/EMRS Row Active for Write H H H H L H H L L x H L H L x x x x x x LA x x x x LAL REF PDEN REF (self) Read H H H H H L H H H L L x H L L H L x x H L x x x x BA, UA BA, UA x x x DESL RDA WRA PDEN H H H x x DESL H H H H L H H L L x L L H L x H L x x x BA, UA BA, UA x x x RDA WRA PDEN Data Write & Continue Burst Write to End Illegal Illegal Illegal Illegal Invalid Auto-Refreshing H H H H H L H H H L L x H L L H L x x H L x x x x BA, UA BA, UA x x x DESL RDA WRA PDEN NOP Idle after IREFC Illegal Illegal Self-Refresh Entry Illegal Refer to Self-Refreshing State Mode Register Accessing H H H H H L H H H L L x H L L H L x x H L x x x x BA, UA BA, UA x x x DESL RDA WRA PDEN NOP Idle after IRSC Illegal Illegal Illegal Illegal Invalid H L x L x x x x x x L H H x x PDEX L H L x x Invalid Maintain Power Down Mode Exit Power Down Mode Idle after tPDEX Illegal H L L L x L H H x x H L x x x x x x x x SELFX Invalid Maintain Self-Refresh Exit Self-Refresh Idle after IREFC Illegal Write Power Down Self-Refreshing NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State 12 Begin Read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry Invalid Continue Burst Read to End Illegal Illegal Illegal Illegal Invalid 13 13 13 13 14 Notes: 12. Illegal if any bank is not idle. 13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA). 14. Illegal if tFPDL is not satisfied. 2003-08-04 19/57 TC59LM914/06AMB-37,-45,-50 MODE REGISTER TABLE Regular Mode Register (Notes: 1) *1 ADDRESS *1 BA1 BA0 0 0 Register BA2, A13~A8 0 *3 A7 A6~A4 A3 A2~A0 CL BT BL TE A7 TEST MODE (TE) A3 BURST TYPE (BT) 0 Regular (default) 0 Sequential 1 Test Mode Entry 1 Interleave A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 0 0 x Reserved 0 1 0 Reserved 0 1 1 1 0 1 0 *2 0 0 0 *2 0 0 1 2 3 0 1 0 4 0 4 0 1 1 1 5 1 x x A9~A7 A6 A5~A2 A1 OCD DIC 0 DIC 1 1 0 Reserved *2 1 1 1 Reserved *2 BURST LENGTH (BL) Reserved *2 *2 Reserved Extended Mode Register (Notes: 4) *4 ADDRESS *4 BA1 BA0 0 1 Register BA2, A13~A12 0 *6 A11 0 *7 A10 DQS A6 A1 OUTPUT DRIVE IMPEDANCE CONTROL (DIC) 0 0 Normal Output Driver Drive (1) 0 1 Strong Output Driver 0 Drive (0) 1 0 Weak Output Driver 0 0 Adjust mode 1 1 Full Strength Output Driver 1 1 OCD Calibration default A9 A8 A7 Driver Impedance Adjustment 0 0 0 OCD exit 0 0 1 0 1 1 1 Calibration mode *5 A0 DS A10 DQS Enable A0 DLL SWITCH (DS) 0 Disable 0 DLL Enable 1 Enable 1 DLL Disable Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0" (low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation. 6. A11 in Extended Mode Register must be set to "0". 7. TC59LM914AMB, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMB. 2003-08-04 20/57 TC59LM914/06AMB-37,-45,-50 STATE DIAGRAM SELFREFRESH POWER DOWN SELFX ( PD = H) PDEX ( PD = H) PD = L PDEN ( PD = L) STANDBY (IDLE) PD = H AUTOREFRESH MODE REGISTER WRA RDA REF MRS ACTIVE (RESTORE) ACTIVE LAL WRITE (BUFFER) LAL READ Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input. 2003-08-04 21/57 TC59LM914/06AMB-37,-45,-50 TIMING DIAGRAMS SINGLE BANK READ TIMING (CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRC = 5 cycles Command RDA LAL IRCD=1 cycle Address UA Bank Add. #0 IRC = 5 cycles DESL RDA IRAS = 4 cycles LA LAL IRCD=1 cycle UA IRC = 5 cycles DESL RDA IRAS = 4 cycles LA IRCD=1 cycle UA #0 LAL DESL RDA IRAS = 4 cycles UA LA #0 #0 BL = 2 DQS/ DQS (output) Hi-Z CL = 3 DQ (output) Hi-Z DQS/ DQS (output) Hi-Z CL = 3 Q0 Q1 CL = 3 Q0 Q1 Q0 Q1 BL = 4 CL = 3 DQ (output) Hi-Z CL = 3 Q0 Q1 Q2 Q3 CL = 3 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 22/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK READ TIMING (CL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK Command RDA LAL IRCD=1 cycle Address UA Bank Add. #0 DESL IRAS = 4 cycles LA IRC = 5 cycles IRC = 5 cycles IRC = 5 cycles RDA LAL IRCD=1 cycle UA DESL IRAS = 4 cycles LA RDA IRCD=1 cycle UA #0 LAL DESL RDA IRAS = 4 cycles LA UA #0 #0 BL = 2 DQS/ DQS (output) Hi-Z CL = 4 DQ (output) Hi-Z DQS/ DQS (output) Hi-Z CL = 4 Q0 Q1 CL = 4 Q0 Q1 Q0 BL = 4 CL = 4 DQ (output) Hi-Z CL = 4 Q0 Q1 Q2 Q3 CL = 4 Q0 Q1 Q2 Q3 Q0 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 23/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK READ TIMING (CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL 14 15 CLK CLK IRC = 6 cycles IRC = 6 cycles Command RDA LAL IRCD=1 cycle Address UA Bank Add. #0 DESL IRAS = 5 cycles RDA LAL IRCD=1 cycle LA UA DESL IRAS = 5 cycles LA IRCD=1 cycle UA #0 DESL LA #0 BL = 2 DQS/ DQS (output) Hi-Z CL = 5 DQ (output) Hi-Z CL = 5 Q0 Q1 Q0 Q1 BL = 4 DQS/ DQS (output) Hi-Z CL = 5 DQ (output) Hi-Z CL = 5 Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 24/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK WRITE TIMING (CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRC = 5 cycles IRC = 5 cycles Command WRA LAL IRCD=1 cycle Address UA Bank Add. #0 DESL WRA IRAS = 4 cycles LA LAL DESL IRCD=1 cycle UA IRC = 5 cycles WRA IRAS = 4 cycles LA DESL IRCD=1 cycle UA #0 LAL WRA IRAS = 4 cycles LA UA #0 #0 BL = 2 DQS/ DQS (input) WL = 2 DQ (input) WL = 2 D0 D1 WL = 2 D0 D1 D0 D1 BL = 4 DQS/ DQS (input) WL = 2 DQ (input) WL = 2 D0 D1 D2 D3 WL = 2 D0 D1 D2 D3 D0 D1 D2 D3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 25/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK WRITE TIMING (CL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRC = 5 cycles IRC = 5 Command WRA LAL IRCD=1 cycle Address UA Bank Add. #0 DESL WRA IRAS = 4 cycles LA LAL IRCD=1 cycle UA IRC = 5 cycles DESL WRA IRAS = 4 cycles LA IRCD=1 cycle UA #0 LAL DESL WRA IRAS = 4 cycles LA UA #0 #0 BL = 2 DQS/ DQS (input) WL = 3 DQ (input) WL = 3 D0 D1 WL = 3 D0 D1 D0 D1 BL = 4 DQS/ DQS (input) WL = 3 DQ (input) WL = 3 D0 D1 D2 D3 WL = 3 D0 D1 D2 D3 D0 D1 D2 D3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 26/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK WRITE TIMING (CL = 5) 0 1 2 3 4 6 5 7 8 9 10 11 12 13 WRA LAL 14 15 CLK CLK IRC = 6 cycles Command WRA LAL IRCD=1 cycle Address UA Bank Add. #0 IRC = 6 cycles DESL WRA IRAS = 5 cycles LAL IRCD=1 cycle LA UA DESL IRAS = 5 cycles DESL IRCD=1 cycle LA UA #0 LA #0 BL = 2 DQS/ DQS (input) WL = 4 DQ (input) WL = 4 D0 D1 D0 D1 BL = 4 DQS/ DQS (input) WL = 4 DQ (input) WL = 4 D0 D1 D2 D3 D0 D1 D2 D3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 27/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK READ-WRITE TIMING (CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRC = 5 cycles IRC = 5 cycles RDA LAL Address UA LA Bank Add. #0 Command DESL WRA LAL UA LA DESL IRC = 5 cycles RDA LAL UA LA #0 DESL WRA UA #0 #0 BL = 2 DQS DQS Hi-Z Hi-Z CL = 3 DQ Hi-Z CL = 3 WL = 2 Q0 Q1 D0 D1 Q0 Q1 BL = 4 DQS DQS Hi-Z Hi-Z CL = 3 DQ Hi-Z CL = 3 WL = 2 Q0 Q1 Q2 Q3 D0 D1 D2 D3 Q0 Q1 Q2 Q3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 28/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK READ-WRITE TIMING (CL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRC = 5 cycles IRC = 5 cycles RDA LAL Address UA LA Bank Add. #0 Command DESL WRA LAL UA LA DESL IRC = 5 cycles RDA LAL UA LA #0 DESL WRA UA #0 #0 BL = 2 DQS DQS Hi-Z Hi-Z CL = 4 DQ Hi-Z WL = 3 Q0 Q1 CL = 4 D0 D1 Q0 BL = 4 DQS DQS Hi-Z Hi-Z CL = 4 DQ Hi-Z WL = 3 Q0 Q1 Q2 Q3 CL = 4 D0 D1 D2 D3 Q0 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 29/57 TC59LM914/06AMB-37,-45,-50 SINGLE BANK READ-WRITE TIMING (CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 RDA LAL UA LA 14 15 CLK CLK IRC = 6 cycles IRC = 6 cycles Command RDA LAL Address UA LA Bank Add. #0 BL = 2 DQS DQS DESL WRA LAL UA LA #0 BL = 4 DQS DQS #0 Hi-Z Hi-Z WL = 4 Q0 Q1 D0 D1 Hi-Z Hi-Z WL = 4 CL = 5 DQ DESL Hi-Z CL = 5 DQ DESL Hi-Z Q0 Q1 Q2 Q3 D0 D1 D2 D3 Note : TC59LM914AMB doesn't have DQS . 2003-08-04 30/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK READ TIMING (CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cyclesIRBD = 2 cycles IRBD = 2 cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL RDA UA Bank "b" LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles BL = 2 DQS/ DQS (output) Hi-Z CL = 3 CL = 3 DQ (output) Hi-Z DQS/ DQS (output) Hi-Z Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0Qb1 Qc0Qc1 Qd0Qd1 BL = 4 CL = 3 CL = 3 DQ (output) Hi-Z Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2 Qc3Qd0Qd1 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 31/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK READ TIMING (CL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cyclesIRBD = 2 cycles IRBD = 2 cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL RDA Bank "b" UA LAL RDA LAL RDA LAL RDA LAL RDA LAL RDA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "b" Bank "a" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles BL = 2 DQS/ DQS (output) Hi-Z CL = 4 CL = 4 DQ (output) Hi-Z DQS/ DQS (output) Hi-Z Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0Qb1 Qc0Qc1 BL = 4 CL = 4 CL = 4 DQ (output) Hi-Z Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3Qc0Qc1Qc2 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 32/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK READ TIMING (CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles RDA LAL RDA LAL UA LA UA LA Bank "a" DESL Bank "b" IRBD = 2 cycles RDA LAL RDA LAL RDA LAL RDA LAL RDA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles BL = 2 DQS/ DQS (output) Hi-Z CL = 5 CL = 5 DQ (output) Hi-Z Qa0Qa1 Qb0Qb1 Qa0Qa1 Qb0Qb1 BL = 4 DQS/ DQS (output) Hi-Z CL = 5 CL = 5 DQ (output) Hi-Z Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0Qb1Qb2 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 33/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK WRITE TIMING (CL = 3) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles WRA LAL WRA LAL UA LA UA LA Bank "a" DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA LA UA LA UA LA UA LA UA LA UA UA Bank "b" Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles BL = 2 DQS/ DQS (input) WL = 2 WL = 2 DQ (input) Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 DQS/ DQS (input) WL = 2 WL = 2 DQ (input) Da0 Da1Da2 Da3 Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1Db2Db3 Dc0 Dc1 Dc2 Dc3 Dd0Dd1Dd2Dd3 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 34/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK WRITE TIMING (CL = 4) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles WRA LAL WRA LAL UA LA UA LA Bank "a" DESL WRA UA Bank "b" LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA LA UA LA UA LA UA LA UA LA UA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" Bank "b" IRC (Bank"a") = 5 cycles IRC (Bank"b") = 5 cycles BL = 2 DQS/ DQS (input) WL = 3 WL = 3 DQ (input) Da0 Da1 Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1 Dd0Dd1 BL = 4 DQS/ DQS (input) WL = 3 WL = 3 DQ (input) Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1Db2 Db3 Dc0 Dc1 Dc2Dc3 Dd0Dd1 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 35/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK WRITE TIMING (CL = 5) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CLK IRBD = 2 cycles Command Address Bank Add. IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles WRA LAL WRA LAL UA LA UA LA Bank "a" DESL Bank "b" WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL UA LA UA LA UA LA UA LA UA LA Bank "a" Bank "b" Bank "c" Bank "d" Bank "a" IRC (Bank"a") = 6 cycles IRC (Bank"b") = 6 cycles BL = 2 DQS/ DQS (input) WL = 4 WL = 4 DQ (input) Da0Da1 Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1 BL = 4 DQS DQS (input) WL = 4 WL = 4 DQ (input) Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1Db2Db3Dc0Dc1 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 36/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK READ-WRITE TIMING (BL = 2) 0 CLK 1 2 3 4 5 6 7 8 LAL RDA LAL 9 10 11 12 13 14 15 LAL RDA LAL DESL WRA LA UA LA CLK IRBD = 2 cycles Command WRA LAL RDA IWRD = 1 cycle Address UA Bank "a" Bank Add. LA UA LAL DESL WRA IRWD = 2 cycles IWRD = 1 cycle LA Bank "b" UA Bank "c" LA UA DESL WRA IRWD = 2 cycles LA UA Bank "d" Bank "a" UA Bank "b" Bank "c" IRC (Bank"a") IRC (Bank"b") CL = 3 Hi-Z DQS Hi-Z DQS CL = 3 WL = 2 Hi-Z DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 4 Hi-Z DQS DQS Hi-Z CL = 4 WL = 3 Hi-Z DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 CL = 5 Hi-Z DQS DQS Hi-Z CL = 5 WL = 4 DQ Hi-Z Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 37/57 TC59LM914/06AMB-37,-45,-50 MULTIPLE BANK READ-WRITE TIMING (BL = 4) CLK 0 1 2 3 4 5 6 7 8 9 WRA LAL RDA LAL 10 11 12 13 14 15 WRA LAL RDA LAL CLK IRBD = 2 cycles Command WRA LAL RDA IWRD = 1 cycle Address Bank Add. UA Bank "a" LA UA DESL LAL IRWD = 3 cycles IWRD = 1 cycle LA UA Bank "b" LA Bank "c" UA DESL IRWD = 3 cycles IWRD = 1 cycle LA UA Bank "d" Bank "a" LA UA LA Bank "b" IRC (Bank"a") IRC (Bank"b") CL = 3 DQS DQS Hi-Z Hi-Z CL = 3 WL = 2 DQ Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 CL = 4 DQS DQS Hi-Z Hi-Z CL = 4 WL = 3 DQ Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 CL = 5 DQS DQS Hi-Z Hi-Z CL = 5 WL = 4 DQ Hi-Z Da0 Da1 Da2 Da3 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3 Note: lRC to the same bank must be satisfied. TC59LM914AMB doesn't have DQS . 2003-08-04 38/57 TC59LM914/06AMB-37,-45,-50 WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4) 0 1 2 3 4 5 6 WRA LAL UA LA=#1 VW=1 7 8 9 10 11 12 13 14 15 CLK CLK BL = 2, SEQUENTIAL MODE Command Address Bank Add. WRA LAL UA LA=#3 VW=All Bank "a" VW=A11 DESL DESL Bank VW=1 "a" VW0 = Low VW1 = don't care VW0 = High VW1 = don't care DQS/ DQS (input) DQ (input) Lower Address D0 D1 D0 #3 #2 #1 (#0) Last one data is masked. BL = 4, SEQUENTIAL MODE Command Address Bank Add. WRA LAL UA LA=#3 VW=All Bank "a" VW=A11 DESL WRA LAL UA LA=#1 VW=1 DESL Bank VW=1 "a" VW0 = High VW1 = Low WRA LAL UA LA=#2 VW=2 DESL Bank VW=2 "a" VW0 = High VW1 = High VW0 = Low VW1 = High DQS/ DQS (input) DQ (input) D0 D1 D2 D3 Lower Address #3 #0 #1 #2 D0 D0 D1 #1(#2)(#3)(#0) Last three data are masked. #2 #3 (#0)(#1) Last two data are masked. Note: DQS ( DQS ) input must be continued till end of burst count even if some of laster data is masked. 2003-08-04 39/57 TC59LM914/06AMB-37,-45,-50 POWER DOWN TIMING (CL = 4, BL = 4) Read cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 CLK CLK IPDA Command Address RDA LAL UA LA DESL DESL RDA or WRA UA tIH tIS IPD = 1 cycle PD tQPDH DQS (output) Hi-Z DQS (output) Hi-Z tPDEX lRC(min) , tREFI(max) Hi-Z CL = 4 DQ (output) Hi-Z Hi-Z Q0 Q1 Q2 Q3 Power Down Entry Power Down Exit Note: PD must be kept "High" level until end of Burst data output. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later. TC59LM914AMB doesn't have DQS . 2003-08-04 40/57 TC59LM914/06AMB-37,-45,-50 POWER DOWN TIMING (CL = 4, BL = 4) Write cycle to Power Down Mode 0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3 CLK CLK IPDA Command Address WRA LAL UA LA DESL DESL RDA or WRA UA tIH tIS IPD = 1 cycle PD WL = 3 2 clock cycles tPDEX lRC(min) , tREFI(max) DQS (input) DQS (input) WL = 3 DQ (input) D0 D1 D2 D3 Note: PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to "High" within tREFI(max.) to maintain the data written into cell. In Power Down Mode, PD "Low" must be maintained. When PD is brought to "High", a valid executable command may be applied lPDA cycles later. TC59LM914AMB doesn't have DQS . 2003-08-04 41/57 TC59LM914/06AMB-37,-45,-50 MODE REGISTER SET TIMING (CL = 4, BL = 2) From Read operation to Mode Register Set operation. 0 1 2 3 4 5 6 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA2="0" BA 7 8 9 10 11 12 13 CLK CLK IRSC Command RDA LAL A13~A0 UA LA BA0~BA2 BA DESL RDA MRS DESL CL + BL/2 DQS (output) DQS DQ (output) Hi-Z Hi-Z Q0 Q1 Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2. TC59LM914AMB doesn't have DQS . 2003-08-04 42/57 TC59LM914/06AMB-37,-45,-50 MODE REGISTER SET TIMING (CL = 4, BL = 4) From Write operation to Mode Register Set operation. 0 1 2 3 4 5 6 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="0" BA1="0" BA2="0" BA 7 8 9 10 11 12 13 CLK CLK IRSC Command WRA LAL A13~A0 UA LA BA0~BA2 BA DESL RDA MRS DESL WL+BL/2 DQS (input) DQS (input) DQ (input) D0 D1 D2 D3 Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2. TC59LM914AMB doesn't have DQS . 2003-08-04 43/57 TC59LM914/06AMB-37,-45,-50 EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2) From Read operation to Extended Mode Register Set operation. 0 1 2 3 4 5 6 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="1" BA1="0" BA2="0" BA 7 8 9 10 11 12 13 CLK CLK IRSC RDA LAL A13~A0 UA LA BA0~BA2 BA Command DESL RDA MRS DESL CL + BL/2 DQS (output) Hi-Z DQS (output) Hi-Z DQ (output) Q0 Q1 Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2. DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. TC59LM914AMB doesn't have DQS . 2003-08-04 44/57 TC59LM914/06AMB-37,-45,-50 EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4) From Write operation to Extended Mode Register Set operation. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 RDA or WRA LAL Valid (opcode) UA LA BA0="1" BA1="0" BA2="0" BA CLK CLK IRSC Command WRA LAL A13~A0 UA LA BA0~BA2 BA DESL RDA MRS DESL WL+BL/2 DQS (input) DQS (input) DQ (input) D0 D1 D2 D3 Note: DLL switch in Extended Mode Register must be set to enable mode for normal operation. DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence. Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2. TC59LM914AMB doesn't have DQS . 2003-08-04 45/57 TC59LM914/06AMB-37,-45,-50 AUTO-REFRESH TIMING (CL = 4, BL = 4) 0 1 2 3 4 5 6 7 n-1 n n+1 n+2 RDA or WRA LAL or MRS or REF CLK CLK IRC = 5 cycles Command RDA LAL Bank, Address Bank, UA LA IRCD = 1 cycle DQS/ DQS (output) Hi-Z DQ (output) Hi-Z IREFC = 18 cycles DESL WRA IRAS = 4 cycles REF DESL IRCD = 1 cycle Hi-Z CL = 4 Hi-Z Q0 Q1 Q2 Q3 Note: In case of CL = 4, IREFC must be meet 18 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. TC59LM914AMB doesn't have DQS . t1 t2 t3 t7 t8 CLK WRA REF WRA REF WRA REF WRA REF WRA REF 8 Refresh cycle tREFI = Total time of 8 Refresh cycle 8 = t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 8 tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read / Write operation. 2003-08-04 46/57 TC59LM914/06AMB-37,-45,-50 SELF-REFRESH ENTRY TIMING 0 CLK CLK 1 2 3 4 IRCD = 1 cycle Command WRA m-1 5 m+1 m IREFC REF DESL tFPDL (min) tFPDL (max) Auto Refresh PD Self Refresh Entry *2 IPDV ICKD tQPDH Hi-Z DQS/ DQS (output) DQ (output) Hi-Z Qx Notes: 1. 2. is don't care. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh mode. When PD is brought to "Low" after lPDV, TC59LM914/06AMB perform Auto Refresh and enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM914/06AMB will either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can't be specified which mode TC59LM914/06AMB operates. 3. It is desirable that clock input is continued at least lCKD from REF command even though PD is brought to "Low" for Self-Refresh Entry. 4. TC59LM914AMB doesn't have DQS . 5. In case of Self-Refresh entry after Write Operation, the delay time from the LAL command following WRA to the REF command is Write latency (WL)+3 clock cycles minimum. SELF-REFRESH EXIT TIMING 0 1 2 m-1 m+1 m m+2 n-1 n n+1 p-1 p CLK CLK *2 *6 IREFC *3 DESL Command IPDA = 1 cycles IREFC *5 WRA *4 *5 REF Command (1st) *6 Command (2nd) DESL IRCD = 1 cycle RDA *7 *7 LAL IRCD = 1 cycle PD tPDEX DQS/ DQS (output) Hi-Z DQ (output) Hi-Z ILOCK Self-Refresh Exit Notes: 1. is don't care. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. DESL command must be asserted during IREFC after PD is brought to "High". IPDA is defined from the first clock rising edge after PD is brought to "High". It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after IREFC. 7. Read command (RDA + LAL) can be issued after ILOCK. 8. TC59LM914AMB doesn't have DQS . 2. 3. 4. 5. 2003-08-04 47/57 TC59LM914/06AMB-37,-45,-50 FUNCTIONAL DESCRIPTION Network FCRAM TM FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to perform fast random core access, low latency and high-speed data transfer. PIN FUNCTIONS CLOCK INPUTS: CLK & CLK The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition. POWER DOWN: PD The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed. CHIP SELECT & FUNCTION CONTROL: CS & FN The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs. BANK ADDRESSES: BA0~BA2 The BA0 to BA2 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode Register Set command (MRS or EMRS). BA0 BA1 BA2 Bank #0 0 0 0 Bank #1 1 0 0 Bank #2 0 1 0 Bank #3 1 1 0 Bank #4 0 0 1 Bank #5 1 0 1 Bank #6 0 1 1 Bank #7 1 1 1 ADDRESS INPUTS: A0~A13 Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle. UPPER ADDRESS LOWER ADDRESS TC59LM906AMB A0~A13 A0~A8 TC59LM914AMB A0~A13 A0~A7 2003-08-04 48/57 TC59LM914/06AMB-37,-45,-50 DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15 The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal. DATA STROBE: DQS, DQS The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an output signal provides the read data strobe. TC59LM906AMB has differential data strobe pin ( DQS ). When DQS is enable mode, DQS is differential output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write operation. When DQS is disable mode, DQS is always Hi-Z, and data input are latched at the crossing point of DQS and VREF level. DQS mode is set at Extended Mode Register Set Cycle. TC59LM914AMB doesn't have DQS pin. Data input are latched at the crossing point of L/UDQS and VREF level in Write operation. LDQS is strobe signal for DQ0-DQ7. UDQS is strobe signal for DQ8-DQ15. POWER SUPPLY: VDD, VDDQ, VSS, VSSQ VDD and VSS are power supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer. REFERENCE VOLTAGE: VREF VREF is reference voltage for all input signals. 2003-08-04 49/57 TC59LM914/06AMB-37,-45,-50 COMMAND FUNCTIONS and OPERATIONS TC59LM914/06AMB are introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed. Read Operation (1st command + 2nd command = RDA + LAL) Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS/ DQS output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after lRC. DQS is differential data strobe signal supported TC59LM906AMB. Write Operation (1st command + 2nd command = WRA + LAL) Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DQS/ DQS input signal (Burst Write Operation). The data and DQS/ DQS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DQS/ DQS has to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and VW1 inputs with LAL command. See VW truth table. DQS is differential data strobe signal supported TC59LM906AMB. Auto-Refresh Operation (1st command + 2nd command = WRA + REF) TC59LM914/06AMB are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by lREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 s by the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that be performed within 3.2 s (8 x 400 ns) is to 8 times in the maximum. Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD= "L") In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM914/06AMB become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to "Low" within tFPDL from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 3.9 s after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition, it is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held "Low". During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh exit. Power Down Mode ( PD= "L") When all banks are in the idle state and DQ outputs are in Hi-Z states, the TC59LM914/06AMB become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued for two clock cycle after PD goes high. The Power Down exit function is asynchronous operation. 2003-08-04 50/57 TC59LM914/06AMB-37,-45,-50 Mode Register Set (MRS) and Extended Mode Register Set (EMRS) (1st command + 2nd command = RDA + MRS) When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A13, BA0 to BA2 address inputs. The TC59LM914/06AMB have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows: (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has five function fields. The five fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. (E-3) Off-Chip Driver (OCD) Impedance Adjustment for Full Strength Output Driver (E-4) DQS enable field (E-5) Interface mode select Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation. * Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS BA1 BA0 BA2, A13~A0 0 0 Regular MRS Cycle 0 1 Extended MRS Cycle 1 x Reserved Regular Mode Register Fields (R-1) Burst Length field (A2 to A0), (BL) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words. A2 A1 A0 BURST LENGTH 0 0 0 Reserved 0 0 1 2 words 0 1 0 4 words 0 1 1 Reserved 1 x x Reserved (R-2) Burst Type field (A3), (BT) The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words. A3 BURST TYPE 0 Sequential 1 Interleave 2003-08-04 51/57 TC59LM914/06AMB-37,-45,-50 * Addressing sequence of Sequential mode A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. CAS Latency = 4 CLK CLK Command RDA LAL DQS/ DQS Data Data Data Data 0 1 2 3 DQ Addressing sequence for Sequential mode * DATA ACCESS ADDRESS Data 0 n Data 1 n+1 Data 2 n+2 Data 3 n+3 BURST LENGTH 2 words (address bits is LA0) not carried from LA0~LA1 4 words (address bits is LA1, LA0) not carried from LA1~LA2 Addressing sequence of Interleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following. Addressing sequence for Interleave mode DATA (R-3) ACCESS ADDRESS BURST LENGTH Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0 2 words 4 words CAS Latency field (A6 to A4), (CL) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles - 1. A6 A5 A4 CAS LATENCY 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved (R-4) Test Mode field (A7), (TE) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register * Reserved bits (A8 to A13, BA2) These bits are reserved for future operations. They must be set to "0" for normal operation. 2003-08-04 52/57 TC59LM914/06AMB-37,-45,-50 Extended Mode Register fields (E-1) DLL Switch field (A0), (DS) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. This bit must set to "0" for normal operation. (E-2) Output Driver Impedance Control field (A1, A6) (DIC) This field is used to choose Output Driver Strength. Four types of Driver Strength are supported. Output Driver Strength can be set by field in EMRS with OCD calibration default (A7~A9 = 1 at EMRS) or OCD calibration mode exit (A7~A9 = 0 at EMRS). A6 A1 OUTPUT DRIVER IMPEDANCE CONTROL 0 0 Normal Output Driver 0 1 Strong Output Driver 1 0 Weak Output Driver 1 1 Full Strength Output Driver (E-3) Off-Chip Driver (OCD) Impedance Adjustment (A7 to A9) (OCD) OCD calibration (Off Chip Driver impedance adjustment) is available only for Full Strength Output Driver. When OCD calibration is performed, A1 and A6 inputs at EMRS must be "1" for Full Strength Output Driver. Output Driver Strength can be set by DIC field (E-2). This Driver strength is the initial driver level at OCD Impedance Adjustment. The Network FCRAMTM supports driver calibration feature and the flow chart below is an example of sequence. Every calibration mode command should be followed by "OCD calibration mode exit" before any other command being issued. MRS should be set before entering OCD impedance adjustment. MRS should be set before entering OCD impedance adjustment. Start EMRS: OCD calibration mode exit EMRS: Drive(1) DQ &DQS High; DQS Low Test EMRS: Drive(0) DQ &DQS Low; DQS High ALL OK ALL OK Need Calibration Test Need Calibration EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: Enter Adjust Mode EMRS: Enter Adjust Mode BL=4 code Input to all DQs Inc, Dec, or NOP BL=4 code Input to all DQs Inc, Dec, or NOP EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit EMRS: OCD calibration mode exit End 2003-08-04 53/57 TC59LM914/06AMB-37,-45,-50 Extended Mode Register Set for OCD Impedance adjustment OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven high and DQS signals are driven low. In drive (0) mode, all DQ, DQS signals are driven low and DQS signals are driven high. In adjust mode, BL=4 of operation code data must be used A9 A8 A7 Operation 0 0 0 OCD calibration mode exit 0 0 1 Drive (1) DQ, DQS high and DQS low 0 1 0 Drive (0) DQ, DQS low and DQS high 1 0 0 Adjust mode 1 1 1 OCD calibration default OCD impedance adjust To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to Network FCRAM. For this operation, Burst Length has to be set to BL=4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs simultaneously and after OCD calibration, all DQs of a given Network FCRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. Off-Chip Driver Program 4bit burst code inputs to all DQs Operation DT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength 0 0 0 0 NOP (No operation) NOP (No operation) 0 0 0 1 Increase by 1 step NOP 0 0 1 0 Decrease by 1 step NOP 0 1 0 0 NOP Increase by 1 step 1 0 0 0 NOP Decrease by 1 step 0 1 0 1 Increase by 1 step Increase by 1 step 0 1 1 0 Decrease by 1 step Increase by 1 step 1 0 0 1 Increase by 1 step Decrease by 1 step 1 0 1 0 Decrease by 1 step Decrease by 1 step Other Combinations Reserved For proper operation of adjust mode, WL=CL-1 clocks and tDS / tDH should be met as the following timing diagram. For input data pattern for adjustment, DT0~DT3 is a fixed order and "not affected by MRS addressing mode (i.e. Sequential or interleave). Driver strength is controlled within the following range by OCD impedance adjustment. SYMBOL IOH (DC) IOL (DC) PARAMETER Output Source DC Current for VDDQ = 1.7V~1.9V Full Strength VDDQ = 1.7V VOH = 1.420V Output Driver Output Sink DC Current for VDDQ = 1.7V~1.9V VDDQ = 1.7V VOL = 0.280V MIN MAX -14.0 -18.7 UNIT NOTES mA 14.0 18.7 2003-08-04 54/57 TC59LM914/06AMB-37,-45,-50 OCD adjust mode Command RDA OCD calibration mode exit EMRS NOP NOP NOP NOP RDA EMRS NOP CLK CLK WL 1clock DQS DQS_in tDS tDH DT0 DQ_in DT1 DT2 DT3 Drive mode Drive mode, both Drive (1) and Drive (0), is used for controllers to measure Network FCRAM Driver impedance. In this mode, all outputs are driven out tOIT after "enter drive mode" command and all output drivers are turned-off tOIT after "OCD calibration mode exit" command as the following timing diagram. OCD calibration mode exit Enter Drive mode Command RDA EMRS NOP NOP RDA EMRS NOP CLK CLK DQS, DQS DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0) DQs high for Drive (1), DQs low for Drive (0) DQ tOIT tOIT (E-4) DQS enable field (A10), ( DQS ) This bit is used to enable Differential Data strobe. DQS is available on TC59LM906AMB. This field of TC59LM914AMB is ignored. A10 DQS Enable 0 Disable 1 Enable (E-5) Interface mode select (A11) This bit must be always set "0". (E-6) Reserved field (A2 to A5, A12, A13, BA2) These bits are reserved for future operations and must be set to "0" for normal operation. 2003-08-04 55/57 TC59LM914/06AMB-37,-45,-50 PACKAGE DIMENSIONS P-BGA64-1317-1.00AZ 0.2 S B 0.2 S A 16.5 0 13.086 -0.15 12.7 0 10.975 -0.15 0.15 1.20MAX 0.2 S S 0.4 0.05 0.15MIN 0.1 S 0.5 0.05 0.08 S AB 1.25 B Q P N M L K J H G F E D C B A 3.85 INDEX A 1.0 4 5 6 1.5 1.5 1 2 3 3.85 1.85 1.0 2.0 2003-08-04 56/57 TC59LM914/06AMB-37,-45,-50 RESTRICTIONS ON PRODUCT USE 030619EBA * The information contained herein is subject to change without notice. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. 2003-08-04 57/57