TC59LM914/06AMB-37,-45,-50
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TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS × 8 BANKS × 16-BITS Network FCRAMTM
8,388,608-WORDS × 8 BANKS × 8-BITS Network FCRAMTM
DESCRIPTION
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM914/06AMB is Network
FCRAMTM containing 536,870,912 memory cells. TC59LM914AMB is organized as 4,194,304-words × 8 banks × 16
bits, TC59LM906AMB is organized as 8,388,608-words × 8 banks × 8 bits. TC59LM914/06AMB feature a fully
synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which
enables high performance and simple user interface coexistence. TC59LM914/06AMB can operate fast core cycle
compared with regular DDR SDRAM.
TC59LM914/06AMB is suitable for Network, Server and other applications where large memory density and low
power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data
transfer under light loading condition.
FEATURES
TC59LM914/06
PARAMETER -37 -45 -50
CL = 3 5.5 ns 5.5 ns 6.0 ns
CL = 4 4.5 ns 5.0 ns 5.5 ns
tCK Clock Cycle Time (min)
CL = 5 3.75 ns 4.5 ns 5.0 ns
tRC Random Read/Write Cycle Time (min) 22.5 ns 25 ns 27.5 ns
tRAC Random Access Time (max) 22.0 ns 22.0 ns 24.0 ns
IDD1S Operating Current (single bank) (max) TBD TBD TBD
lDD2P Power Down Current (max) TBD TBD TBD
lDD6 Self-Refresh Current (max) TBD TBD TBD
• Fully Synchronous Operation
• Double Data Rate (DDR)
Data input/output are synchronized with both edges of DQS.
• Differential Clock (CLK and CLK ) inputs
CS , FN and all address input signals ar e sampled on the positive edge of CLK.
Output data (DQs and DQS) is aligned to the crossings of CLK and CLK .
• Fast clock cycle time of 3.75 ns minimum
Clock: 266 MHz maximum
Data: 533 Mbps/pin maximum
• Fast cycle and Short Latency
• Differential Data Strobe DQS : TC59LM906AMB
• Distributed Auto-Refr e sh cycle in 3.9 µs
• Self-Refresh
• Power Down Mode
• Variable Write Length Control
• Write Latency = CAS Latency-1
• Programable CAS Latency and Burst Length
CAS Latency = 3, 4, 5
Burst Length = 2, 4
• Organization: TC59LM914AMB : 4,194,30 4 words × 8 banks × 16 bits
TC59LM906AMB : 8,388,608 words × 8 banks × 8 bits
• Power Supply Voltage VDD: 2.5 V ± 0.15V
VDDQ: 1.4 V ~ 1.9 V
• Low voltage CMOS I/O covered with SSTL-18 (Half strength driver) and HSTL.
• Package: 60Ball BGA, 1mm × 1mm Ball pitch
Notice : FCRAM is trademark of Fujitsu Limited, Japan.
TC59LM914/06AMB-37,-45,-50
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TC59LM906AMB
PIN NAMES PIN ASSIGNMENT (TOP VIEW)
PIN NAME
A0~A13 Address Input
BA0~BA2 Bank Address
DQ0~DQ7 Data Input/Output
CS Chip Select
FN Function Control
PD Power Down Control
CLK, CLK Clock Input
DQS / DQS Write/Read Data Strobe
VDD Power (+2.5 V)
VSS Ground
VDDQ Power (+1.5V / +1.8 V)
(for I/O buffer)
VSSQ Ground
(for I/O buffer)
VREF Reference Voltage
NC Not Connected
5
A
B
C
D
E
F
G
H
J
K
1 3 6 4 2
x8
Index
L
M
N
P
R
V
SS
DQ7 DQ0 VDD
NC V
SS
Q VDDQ NC
DQ6 VDDQ V
SS
Q DQ1
NC DQ5 DQ2 NC
NC V
SS
Q VDDQ NC
DQ4 VDDQ V
SS
Q DQ3
NC V
SS
Q VDDQ NC
NC DQS DQS NC
VREF V
SS
VDD BA2
CLK CLK FN A13
NCA12 PD CS
BA0A11 A9 BA1
A10A8 A7 A0
A1A5 A6 A2
VDD
V
SS
A4 A3
ball pitch=1.0 x 1.0mm
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TC59LM914AMB
PIN NAMES PIN ASSIGNMENT (TOP VIEW)
PIN NAME
A0~A13 Address Input
BA0~BA2 Bank Address
DQ0~DQ15 Data Input/Output
CS Chip Select
FN Function Control
PD Power Down Control
CLK, CLK Clock Input
UDQS / LDQS Write/Read Data Strobe
VDD Power (+2.5 V)
VSS Ground
VDDQ Power (+1.5V / +1.8 V)
(for I/O buffer)
VSSQ Ground
(for I/O buffer)
VREF Reference Voltage
NC Not Connected
5
A
B
C
D
E
F
G
H
J
K
1 3 6 4 2
X16
Index
L
M
N
P
R
V
SS
DQ15 DQ0 VDD
DQ14 V
SS
Q VDDQ DQ1
DQ13 VDDQ V
SS
Q DQ2
DQ12 DQ11 DQ4 DQ3
DQ10 V
SS
Q VDDQ DQ5
DQ9 VDDQ V
SS
Q DQ6
DQ8 V
SS
Q VDDQ DQ7
NC UDQS LDQS NC
VREF V
SS
VDD BA2
CLK CLK FN A13
NCA12 PD CS
BA0A11 A9 BA1
A10A8 A7 A0
A1A5 A6 A2
VDD
V
SS
A4 A3
ball pitch=1.0 x 1.0mm
TC59LM914/06AMB-37,-45,-50
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BLOCK DIAGRAM
Note: The TC59LM906AMB configuration is 8 Bank of 16384 × 512 × 8 of cell array with the DQ pins numbered DQ0~DQ7.
The TC59LM914AMB configuration is 8 Bank of 16384 × 256 × 16 of cell array with the DQ pins numbered DQ0~DQ15.
TC59LM906AMB has
DQS pin for Differential Data Strobe.
TC59LM914AMB has UDQS and LDQS.
DQ0~DQn
DLL
CLOCK
BUFFER
CL
K
CLK
PD
To each block
COMMAND
DECODER
CS
FN
ADDRESS
BUFFER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
REFRESH
COUNTER
A0~A13
BA0~BA2
BURST
COUNTER
WRITE ADDRESS
LATCH/
ADDRESS
COMPARATOR
DATA
CONTROL and LATCH
CIRCUIT
UPPER ADDRESS
LATCH
READ
DATA
BUFFER
DQ BUFFER
DQS
LOWER ADDRESS
LATCH
DQS
WRITE
DATA
BUFFER
BANK #7
BANK #6
BANK #5
BANK #4
BANK #3
BANK #2
BANK #1
BANK #0
MEMORY
CELL ARRAY
COLUMN DECODER
ROW DECODER
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ABSOLUTE MAXIMUM RATINGS
SYMBOL PARAMETER RATING UNIT NOTES
VDD Power Supply Voltage −0.3~ 3.3 V
VDDQ Power Supply Voltage (for I/O buffer) −0.3~VDD+ 0.3 V
VIN Input Voltage −0.3~VDD+ 0.3 V
VOUT Output and I/O pin Voltage −0.3~VDDQ + 0.3 V
VREF Input Reference Voltage −0.3~VDD+ 0.3 V
Topr Operating Temperature (Ambient) 0~70 °C
Tstg Storage Temperature −55~150 °C
Tsolder Soldering Temperature (10 s) 260 °C
PD Power Dissipation 2 W
IOUT Short Circuit Output Current ±50 mA
Caution: Conditions outside the limits listed under “ABSOLUTE MAXIMUM RATINGS” may cause permanent damage to the device.
The device is not meant to be operated under conditions outside the limits described in the operational section of this
specification.
Exposure to “ABSOLUTE MAXIMUM RATINGS” conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1) (TCASE = 0~85°C)
SYMBOL PARAMETER MIN TYP. MAX UNIT NOTES
VDD Power Supply Voltage 2.375 2.5 2.625 V
VDDQ Power Supply Voltage (for I/O buffer) 1.4 1.9 V
VREF Input Reference Voltage VDDQ/2 × 95% VDDQ/2 VDDQ/2 × 105% V 2
VIH (DC) Input DC High Voltage VREF + 0.125 V
DDQ + 0.2 V 5
VIL (DC) Input DC Low Voltage −0.1 V
REF − 0.125 V 5
VICK (DC) Differential Clock DC Input Voltage −0.1 V
DDQ + 0.1 V 10
VID (DC)
Input Differential Voltage.
CLK and CLK inputs (DC) 0.4 V
DDQ + 0.2 V 7, 10
VIH (AC) Input AC High Voltage VREF + 0.2 V
DDQ + 0.2 V 3, 6
VIL (AC) Input AC Low Voltage −0.1 V
REF − 0.2 V 4, 6
VID (AC)
Input Differential Voltage.
CLK and CLK inputs (AC) 0.55 V
DDQ + 0.2 V 7, 10
VX (AC) Differential AC Input Cross Point Voltage VDDQ/2 − 0.125 V
DDQ/2 + 0.125 V 8, 10
VISO (AC) Differential Clock AC Middle Level VDDQ/2 − 0.125 V
DDQ/2 + 0.125 V 9, 10
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Note:
(1) All voltages referenced to VSS, VSSQ.
(2) VREF is expected to track variations in VDDQ DC level of the transmitting device.
Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
(3) Overshoot limit: VIH (max) = VDDQ + 0.7 V with a pulse width ≤ 5 ns.
(4) Undershoot limit: VIL (min) = −0.7 V with a pulse width ≤ 5 ns.
(5) VIH (DC) and VIL (DC) are levels to maintain the current logic state.
(6) VIH (AC) and VIL (AC) are levels to change to the n e w logic state.
(7) VID is magnitude of the difference between CLK input level and CLK input level.
(8) The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device.
(9) VISO means {VICK (CLK) + VICK (CLK )} /2
(10) Refer to the figure below.
(11) In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) ±
0.04 V.
CAPACITANCE (VDD = 2.5V, VDDQ = 1.8 V, f = 1 MHz, Ta = 25°C)
SYMBOL PARAMETER MIN MAX Delta UNIT
CIN Input pin Capacitance 1.5 2.5 0.25 pF
CINC Clock pin (CLK, CLK ) Capacitance 1.5 2.5 0.25 pF
CI/O DQ, DQS, UDQS, LDQS, DQS Capacitance 2.5 4 0.5 pF
CNC NC pin Capacitance 4 pF
Note: These parameters are periodically sampled and not 100% tested.
VISO
(
min
)
VISO
(
max
)
VICK VICK
V
x
V
x
V
x
V
x
V
x
VICK VICK
CL
K
CLK
VSS
|VID (AC)|
0 V Differential
VISO
VSS
VID (AC)
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RECOMMENDED DC OPERATING CONDITIONS
(VDD=2.5V ± 0.125V, VDDQ=1.8V ± 0.1V, TCASE = 0~85°C)
MAX
SYMBOL PARAMETER -37 -45 -50
UNIT NOTES
IDD1S
Operating Current
tCK = min; IRC = min,
Read/Write command cycling,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
1 bank operation, Burst length = 4,
Address change up to 2 times during minimum IRC.
TBD TBD TBD 1, 2
IDD2N
Standby Current
tCK = min, CS = VIH, PD = VIH,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
All banks: inactive state,
Other input signals are changed one time during 4 × tCK.
TBD TBD TBD 1
IDD2P
Standby (power down) Current
tCK = min, CS = VIH, PD = VIL (power down),
0 V ≤ VIN ≤ VDDQ,
All banks: inactive state
TBD TBD TBD 1
IDD5
Auto-Refresh Current
tCK = min; IREFC = min, tREFI = min,
Auto-Refresh command cycling,
0 V ≤ VIN ≤ VIL (AC) (max), VIH (AC) (min) ≤ VIN ≤ VDDQ,
Address change up to 2 times during minimum IREFC.
TBD TBD TBD 1
IDD6
Self-Refresh Current
Self-Refresh mode
PD = 0.2 V, 0 V ≤ VIN ≤ VDDQ
TBD TBD TBD
mA
SYMBOL PARAMETER MIN MAX UNIT NOTES
ILI Input Leakage Current
( 0 V ≤ VIN ≤ VDDQ, all other pins not under test = 0 V) −5 5 µA
ILO Output Leakage Current
(Output disabled, 0 V ≤ VOUT ≤ VDDQ) −5 5 µA
IREF VREF Current −5 5 µA
IOH (DC) VOH = 1.420 V −5.6 3
IOL (DC)
Normal Output Driver
VOL = 0.280 V 5.6 3
IOH (DC) VOH = 1.420 V −9.8 3
IOL (DC)
Strong Output Driver
VOL = 0.280 V 9.8 3
IOH (DC) VOH = 1.420 V −2.8 3
IOL (DC)
Weak Output Driver
VOL = 0.280 V 2.8 3
IOH (DC) VOH = 1.420 V −13.4 3
IOL (DC)
Full Strength Output Driver
Output DC Current
(VDDQ = 1.7V~1.9V)
VOL = 0.280 V 13.4
mA
3
IOH (DC) VOH = VDDQ – 0.4V −4 3
IOL (DC)
Normal Output Driver
VOL = 0.4V 4 3
IOH (DC) VOH = VDDQ – 0.4V −8 3
IOL (DC)
Strong Output Driver
VOL= 0.4V 8 3
IOH (DC) Not defined
IOL (DC)
Weak Output Driver
Not defined
IOH (DC) VOH = VDDQ – 0.4V −10 3
IOL (DC)
Full Strength Output Driver
Output DC Current
(VDDQ = 1.4V~1.6V)
VOL= 0.4V 10
mA
3
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of
tCK, tRC and IRC.
2. These parameters depend on the output loading. The specified values are obtained with the output open.
3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
4. In case of Full Strength Output Driver, OCD calibration (Off chip Driver impedance adjustment) can be used. The
specification of Full Strength Output Driver defines the default value after power-up.
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
(VDD=2.5V±0.125V, VDDQ=1.8V±0.1V, TCASE=0~85°C)
-37 -45 -50
SYMBOL PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT NOTES
tRC Random Cycle Time 22.5 25 27.5 3
CL = 3 5.5 8.5 5.5 8.5 6.0 8.5 3
CL = 4 4.5 8.5 5.0 8.5 5.5 8.5 3
tCK Clock Cycle Time
CL = 5 3.75 8.5 4.5 8.5 5.0 8.5 3
tRAC Random Access Time 22.0 22.0 24 3
tCH Clock High Time 0.45 × tCK 0.45 × tCK 0.45 × tCK 3
tCL Clock Low Time 0.45 × tCK 0.45 × tCK 0.45 × tCK 3
tCKQS DQS Access Time from CLK −0.45 0.45 −0.5 0.5 −0.6 0.6 3, 8
tQSQ Data Output Skew from DQS 0.25 0.3 0.35 4
tAC Data Access Time from CLK −0.5 0.5 −0.6 0.6 −0.65 0.65 3, 8
tOH Data Output Hold Time from CLK −0.5 0.5 −0.6 0.6 −0.65 0.65 3, 8
tQSPRE DQS (read) Preamble Pulse
Width 0.9 × tCK 1.1 × tCK 0.9 × tCK 1.1 × tCK 0.9 × tCK 1.1 × tCK 3, 8
tHP CLK half period (minimum of
Actual tCH, tCL)
min(tCH,
tCL) min(tCH,
tCL) min(tCH,
tCL) 3
tQSP DQS (read) Pulse Width tHP−tQHS t
HP−tQHS t
HP−tQHS 4, 8
tQSQV Data Output Valid Time from
DQS tHP−tQHS t
HP−tQHS t
HP−tQHS 4, 8
tQHS DQ Hold Skew factor 0.055 ×
tCK +0.17
0.055 ×
tCK +0.17
0.055 ×
tCK +0.17
tDQSS DQS (write) Low to High Setup
Time 0.75 × tCK 1.25 × tCK 0.75 × tCK 1.25 × tCK 0.75 × tCK 1.25 × tCK 3
tDSPRE DQS (write) Preamble Pulse
Width
0.25 ×
tCK 0.25 ×
tCK 0.25 ×
tCK 4
tDSPRES DQS First Input Setup Time 0 0 0 3
tDSPREH DQS First Low Input Hold Time 0.25 × tCK 0.25 × tCK 0.25 × tCK 3
tDSP DQS High or Low Input Pulse
Width 0.35 × tCK 0.65 × tCK 0.35 × tCK 0.65 × tCK 0.35 × tCK 0.65 × tCK 4
CL = 3 0.75 0.9 1.0 3, 4
CL = 4 0.75 0.9 1.0 3, 4
tDSS
DQS Input Falling
Edge to Clock Setup
Time
CL = 5 0.75 0.9 1.0 3, 4
tDSH DQS Input Falling Edge Hold Time
from CLK 0.55 0.65 0.75 3, 4
tDSPST DQS (write) Postamble Pulse
Width 0.4 × tCK 0.4 × tCK 0.4 × tCK 4
CL = 3 0.75 0.9 1.0 3, 4
CL = 4 0.75 0.9 1.0 3, 4
tDSPSTH DQS (write)
Postamble Hold Time
CL = 5 0.75 0.9 1.0 3, 4
tDSSK UDQS – LDQS Skew (×16) −0.5× tCK 0.5× tCK
−0.5× tCK 0.5× tCK
−0.5× tCK 0.5× tCK
tDS Data Input Setup Time from DQS 0.35 0.4 0.45 4
tDH Data Input Hold Time from DQS 0.35 0.4 0.45 4
tIS Command/Address Input Setup
Time 0.5 0.6 0.7 3
tIH Command/Address Input Hold
Time 0.5 0.6 0.7
ns
3
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-37 -45 -50
SYMBOL PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT NOTES
tLZ Data-out Low Impedance Time
from CLK −0.5 −0.6 −0.65 3,6,8
tHZ Data-out High Impedance Time
from CLK 0.5 0.6 0.65
3,7,8
tQSLZ DQS-out Low Impedance Time
from CLK −0.5 −0.6 −0.65 3,6,8
tQSHZ DQS-out High Impedance Time
from CLK −0.5 0.5 −0.6 0.6 −0.65 0.65 3,7,8
tQPDH Last output to PD High Hold
Time 0 0 0
tPDEX Power Down Exit Time 0.6 0.7 0.8 3
tT Input Transition Time 0.1 1 0.1 1 0.1 1
tFPDL PD Low Input Window for
Self-Refresh Entry −0.5 × tCK 5 −0.5 × tCK 5 −0.5 × tCK 5
ns
3
tREFI Auto-Refresh Average Interval 0.4 3.9 0.4 3.9 0.4 3.9 5
tPAUSE Pause Time after Power-up 200 200 200
µs
CL = 3 5 5 5
CL = 4 5 5 5
IRC
Random Read/Write
Cycle Time
(applicable to same
bank) CL = 5 6 6 6
IRCD
RDA/WRA to LAL Command Input
Delay
(applicable to same bank)
1 1 1 1 1 1
CL = 3 4 4 4
CL = 4 4 4 4
IRAS
LAL to RDA/WRA
Command Input Delay
(applicable to same
bank) CL = 5 5 5 5
IRBD Random Bank Access Delay
(applicable to other bank) 2 2 2
BL = 2 2 2 2
IRWD
LAL following RDA to
WRA Delay
(applicable to other
bank) BL = 4 3 3 3
IWRD LAL following WRA to RDA Delay
(applicable to other bank) 1 1 1
CL = 3 5 5 5
CL = 4 5 5 5
IRSC Mode Register Set
Cycle Time
CL = 5 6 6 6
IPD PD Low to Inactive State of Input
Buffer 1 1 1
IPDA PD High to Active State of Input
Buffer 1 1 1
CL = 3 15 15 15
CL = 4 18 18 18
IPDV Power down mode valid
from REF command
CL = 5 22 22 22
CL = 3 15 15 15
CL = 4 18 18 18
IREFC Auto-Refresh Cycle
Time
CL = 5 22 22 22
ICKD REF Command to Clock Input
Disable at Self-Refresh Entry IREFC I
REFC I
REFC
ILOCK DLL Lock-on Time (applicable to
RDA command) 200 200 200
cycle
TC59LM914/06AMB-37,-45,-50
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AC TEST CONDITIONS
SYMBOL PARAMETER VALUE UNIT NOTES
VIH (min) Input High Voltage (minimum) VREF + 0.2 V
VIL (max) Input Low Voltage (maximum) VREF − 0.2 V
VREF Input Reference Voltage VDDQ/2 V
VTT Termination Voltage VREF V
VSWING Input Signal Peak to Peak Swing 0.7 V
Vr Differential Clock Input Reference Level VX (AC) V
VID (AC) Input Differential Voltage 1.0 V
SLEW Input Signal Minimum Slew Rate 2.5 V/ns
VOTR Output Timing Measurement Reference Voltage VDDQ/2 V 9
Note:
(1) Transition times are measured between VIH min (DC) and VIL max (DC).
Transition (rise and fall) of in put signals have a fixed slope.
(2) If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is
rounded up to the nearest decimal place.
(i.e., tDQSS = 0.75 × tCK, tCK = 5 ns, 0.75 × 5 ns = 3.75 ns is rounded up to 3.8 ns.)
(3) There parameters are measured from the differential clock (CLK and CLK ) AC cross point.
(4) These parameter s ar e measured from signal transit ion point of DQS crossing VREF level.
In case of DQS enable mode, these parameters are measured from the crossing point of DQS and DQS.
(5) The tREFI (max) applies to equally distributed refresh method.
The tREFI (min) applies to both burst refresh method and distributed refresh method.
In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns
always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 µs (8 × 400 ns)
is to 8 times in the maximu m.
(6) Low Impedance State is specified at VDDQ/2 ± 0.2 V from steady state.
(7) High Impedance State is specified where output buffer is no longer driven.
(8) These parameters depend on the clock jitter. These parameters are measured at stable clock.
(9) Output timing is measured by using Normal driver strength.
SLEW = (VIH min (AC) − VIL max (AC))/∆T
VIH min (AC)
∆T
VREF
VIL max (AC)
VSWING
∆T
VSS
VDDQ
Z = 50 Ω
AC Test Load
Output
VTT
50 Ω
25 Ω
VTT
50 Ω
Z = 50 Ω
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POWER UP SEQUENCE
(1) As for
PD , being maintained by the low state (≤ 0.2 V) is desirable before a power-supply injection.
(2) Apply VDD before or at the same time as VDDQ.
(3) Apply VDDQ before or at the same time as VREF.
(4) Start clock (CLK, CLK ) and maintain stable condition for 200 µs (min).
(5) After stable power and clock, apply DESL and take PD =H.
(6) Issue EMRS to enable DLL and to define driver strength with OCD calibration mode exit command
(A7∼A9=0). (Note: 1, 2)
(7) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1)
(8) Issue two or more Auto-Refresh commands (Note: 1).
(9) Ready for normal operation after 200 clocks from Extended M ode Register programming.
(10) If OCD calibration (Off Chip Driver impedance adjustment) is used, execute OCD calibration sequence.
Notes:
(1) Sequence 6, 7 and 8 c an be issued in random order.
(2) Set
DQS mode for TC59LM906AMB.
(3) L
= Logic Low, H = Logic High
CLK
Command
DQ
Address
VDD
VDDQ
VREF
CLK
PD
2.5V
(
TYP
)
1.8V
(
TYP
)
0.9V
(
TYP
)
200us
(
min
)
tPDEX
lPDA lRSC lRSC lREFC lREFC
200clock c
y
cle
(
min
)
DESL RDA MRS DESL RDA MRS DESL WRA REF DESL WRA REF DESL
op-code
EMRS
op-code
MRS
Hi-Z
DQS
EMRS MRS Auto Refresh cycle Normal Operation
Hi-Z
DQS
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TIMING DIAGRAMS
Input Timing
Timing of the CLK, CLK
tT
tCK
CLK
VIH
VIL
VIH
VIL
tCL
tCH
tT
VIH (AC)
VIL (AC)
CLK
CLK
CLK
VX VX VX
VID (AC)
tIH
tIS
tIH
tCK tCL
tCH
CS
CL
K
CLK
tCK
1st 2nd
tIS tIH
tIS tIH
1st 2nd
tIH
tIS tIH
UA, BA LA
tIS
tIS
FN
A0~A13
BA0~BA2
Command and Address
DQ (input)
tDS tDH tDS tDH
DQS
DQS
Data
• TC59LM906AMB DQS enable mode
DQ (input)
Refer to the Command Truth Table.
tDS tDH tDS tDH
DQS
Data
• TC59LM906AMB DQS disable mode
• TC59LM914AMB
TC59LM914/06AMB-37,-45,-50
2003-08-04 13/57
Read Timing (Burst Length = 4)
CLK
Inpu
t
(control &
addresses)
DQS/ DQS
(output)
DQ
(output)
CAS latency = 3
DQS/ DQS
(output)
DQ
(output)
CAS latency = 4
DQS/ DQS
(output)
DQ
(output)
CAS latency = 5
Hi-Z
LAL (after RDA)
tIS tIH
Hi-Z
tCH tCL tCK
Hi-Z
Hi-Z
tQSQ
tQSLZ
tQSPRE
tCKQS
tCKQS
tQSP tQSP
tCKQS
tQSHZ
tQSQ
tQSQV
tQSQV
tQSQ
tHZ
tLZ
tOH
tAC
tAC
tAC
Preamble Postamble
Preamble Postamble
Q0 Q1 Q2 Q3
tQSQ
tQSQ
tQSQV
tQSQV
tQSQ
tHZ
tLZ
tOH
tAC
tAC
tAC
Q0 Q1 Q2 Q3
tQSLZ
tQSPRE
tCKQS
tCKQS
tQSP tQSP
tCKQS
tQSHZ
Preamble Postamble
tQS
tQSQ
tQSQV
tQSQV
tQSQ
tHZ
tLZ
tAC tAC
tAC
Q0 Q1 Q2 Q3
Hi-Z
Hi-Z
DESL
CL
K
Note: TC59LM914AMB doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB)
LDQS DQ0∼DQ7
UDQS DQ8∼DQ15
The condition of DQS is changed from Hi-Z to “Low” at Premble and the condition of DQS is changed from
“Low” to Hi-Z at Postamble.
DQS is Hi-Z in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMB)
When DQS is enable, the condtion of DQS is changed from Hi-Z to “High” at Premble and the condition
of DQS is chan
g
ed from “Hi
g
h” to Hi-Z at Postamble.
tOH
tQSLZ
tQSPRE
tCKQS
tCKQS
tQSP tQSP
tCKQS
tQSHZ
TC59LM914/06AMB-37,-45,-50
2003-08-04 14/57
Write Timing (Burst Length = 4)
DQ
(input)
DQS/ DQS
(input)
DQ
(input)
CAS latency = 4
DQS/ DQS
(input)
CAS latency = 3
tDSPRE
tDS
tDH
D0 D1
tDS
tDH
D3
tDS
tDH
tDSS
tDQSS
tDSPREH tDSP tDSP
tDS
Preamble Postamble
tDSP
tDQSS
tDSPRES
tDSPST
tDSPSTH
tDH
D1
tDS
tDH
D3
tDS
tDH
tDSS
tDQSS
tDSPREH tDSP tDSP
Preamble Postamble
tDSP
tDSS
tDSPRES tDSPST
tDSS
tDSPSTH
tDQSS
CL
K
CLK
Inpu
t
(control &
addresses)
LAL (after WRA)
tIS tIH
tCH tCL tCK
tDSPRE
DQS/ DQS
(input)
DQ
(input)
CAS latency = 5
tDSPRE
tDSS
tDSPREH tDSP tDSP
tDS
Preamble Postamble
tDSP
tDQSS
tDSPRES
tDSPST
tDSPSTH
tDH
D1
tDS
tDH
D3
tDS
tDH
tDSS
tDQSS
DESL
Note: TC59LM914AMB doesn’t have DQS .
The correspondence of LDQS, UDQS to DQ. (TC59LM914AMB)
LDQS DQ0∼DQ7
UDQS DQ8∼DQ15
DQS is ignored in DQS disable mode.
DQS mode is chosen by EMRS. (TC59LM906AMB)
D2
D2D0
D0 D2
TC59LM914/06AMB-37,-45,-50
2003-08-04 15/57
tREFI, tPAUSE, Ixxxx Timing
CL
K
CLK
Input
(control &
addresses)
Command
tIS t
IH
Note: “IXXXX” means “IRC”, “IRCD”, “IRAS”, etc.
tREFI, tPAUSE, IXXXX
Command
tIS tIH
TC59LM914/06AMB-37,-45,-50
2003-08-04 16/57
Write Timing (x16 device) (Burst Length =4)
CL
K
CLK
Inpu
t
(control &
addresses)
LDQS
DQ0~DQ7
CAS latency = 3
UDQS
DQ8~DQ15
LDQS
DQ0~DQ7
CAS latency = 4
UDQS
DQ8~DQ15
Preamble
LAL WRA
tDS
Postamble
tDSSK
tDH
D0 D1
tDS
tDH
D2 D3
tDS
tDH
tDS
Preamble Postamble
tDH
D0 D1
tDS
tDH
D3
tDS
tDH
tDS
tDH
tDSSK tDSSK tDSSK
tDH
tDS
tDS
Preamble
tDSSK
D0 D1
tDS
tDH
D2 D3
tDS
tDH
tDS
Preamble
D0 D1
tDS
tDH
D2 D3
tDS
tDH
tDS
tDH
tDSSK tDSSK tDSSK
tDS
(DESL)
Postamble
Postamble
tDH
LDQS
DQ0~DQ7
CAS latency = 5
UDQS
DQ8~DQ15
Postamble
tDS
Preamble
tDSSK
tDH
D0 D1
tDS
tDH
D2 D3
tDS
tDH
tDS
Preamble
D0 D1
tDS
tDH
D2 D3
tDS
tDH
tDS
tDH
tDSSK tDSSK tDSSK
tDS Postamble
tDH tDH
tDH
tDH
TC59LM914/06AMB-37,-45,-50
2003-08-04 17/57
FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
• The First Command
SYMBOL FUNCTION CS FN BA2~BA0 A13~A9 A8 A7 A6~A0
DESL Device Deselect H × × × × × ×
RDA Read with Auto-close L H BA UA UA UA UA
WRA Write with Auto-close L L BA UA UA UA UA
• The Second Command (The next clock of RDA or WRA command)
SYMBOL FUNCTION CS FN
BA1~
BA0 BA2 A13 A12~
A11
A10~A
9 A8 A7 A6~A0
LAL Lower Address Latch (x16) H × × × V V × × LA LA
LAL Lower Address Latch (x8) H × × × V × × LA LA LA
REF Auto-Refresh L × × × × × × × × ×
MRS Mode Register Set L × V L L L L L V V
Notes: 1. L = Logic Low, H = Logic High, × = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address,
LA = Lower Address
2. All commands are assumed to issue at a valid state.
3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where
CLK goes to High.
4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to “STATE DIAGRAM” and
the command table below.
Read Command Table
COMMAND (SYMBOL) CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES
RDA (1st) L H BA UA UA UA UA
LAL (2nd) H × × × LA LA LA 5
Note 5 : For x16 device, A8 is “X” (either L or H).
Write Command Table
• TC59LM914AMB
COMMAND (SYMBOL) CS FN
BA1~
BA0 BA2 A13 A12 A11
A10~
A9 A8 A7 A6~A0
WRA (1st) L L BA BA UA UA UA UA UA UA UA
LAL (2nd) H × × LVW0 LVW1 UVW0 UVW1 × × LA LA
• TC59LM906AMB
COMMAND (SYMBOL) CS FN
BA1~
BA0 BA2 A13 A12 A11
A10~
A9 A8 A7 A6~A0
WRA (1st) L L BA BA UA UA UA UA UA UA UA
LAL (2nd) H × × VW0 VW1 × × × LA LA LA
Notes: 6. BA2 and A13~A11 are used for Variable Write Length (VW) control at Write Operation.
TC59LM914/06AMB-37,-45,-50
2003-08-04 18/57
FUNCTION TRUTH TABL E (continued)
VW Truth Table
Burst Length Function VW0 VW1
Write All Words L ×
BL=2
Write First One Word H ×
Reserved L L
Write All Words H L
Write First Two Words L H
BL=4
Write First One Word H H
Note 7 : For x16 device, LVW0 and LVW1 control DQ0~DQ7.
UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL) CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES
RDA (1st) L H × × × × ×
MRS (2nd) L × V V V V V 8
Notes: 8. Refer to “MODE REGISTER TABLE”.
Auto-Refresh Command Table
PD
FUNCTION COMMAND
(SYMBOL)
CURRENT
STATE n − 1n
CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES
Active WRA (1st) Standby H H L L × × × × ×
Auto-Refresh REF (2nd) Active H H L × × × × × ×
Self-Refresh Command Table
PD
FUNCTION COMMAND
(SYMBOL)
CURRENT
STATE n − 1n
CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES
Active WRA (1st) Standby H H L L × × × × ×
Self-Refresh Entry REF (2nd) Active H L L × × × × × × 9, 10
Self-Refresh Continue Self-Refresh L L × × × × × × ×
Self-Refresh Exit SELFX Self-Refresh L H H × × × × × × 11
Power Down Table
PD
FUNCTION COMMAND
(SYMBOL)
CURRENT
STATE n − 1n
CS FN BA2~BA0 A13~A9 A8 A7 A6~A0 NOTES
Power Down Entry PDEN Standby H L H × × × × × × 10
Power Down Continue Power Down L L × × × × × × ×
Power Down Exit PDEX Power Down L H H × × × × × × 11
Notes: 9. PD has to be brought to Low within tFPDL from REF command.
10.
PD should be brought to Low after DQ’s state turned high impedance.
11. When
PD is brought to High from Low, this function is executed asynchronously.
TC59LM914/06AMB-37,-45,-50
2003-08-04 19/57
FUNCTION TRUTH TABLE (continued)
PD
CURRENT STATE n − 1 n CS FN ADDRESS COMMAND ACTION NOTES
H H H × × DESL NOP
H H L H BA, UA RDA Row activate for Read
H H L L BA, UA WRA Row activate for Write
H L H × × PDEN Power Down Entry 12
H L L × × Illegal
Idle
L × × × × Refer to Power Down State
H H H × LA LAL Begin Read
H H L × Op-code MRS/EMRS Access to Mode Register
H L H × × PDEN Illegal
H L L × × MRS/EMRS Illegal
Row Active for Read
L × × × × Invalid
H H H × LA LAL Begin Write
H H L × × REF Auto-Refresh
H L H × × PDEN Illegal
H L L × × REF (self) Self-Refresh Entry
Row Active for Write
L × × × × Invalid
H H H × × DESL Continue Burst Read to End
H H L H BA, UA RDA Illegal 13
H H L L BA, UA WRA Illegal 13
H L H × × PDEN Illegal
H L L × × Illegal
Read
L × × × × Invalid
H H H × × DESL
Data Write & Continue Burst Write to
End
H H L H BA, UA RDA Illegal 13
H H L L BA, UA WRA Illegal 13
H L H × × PDEN Illegal
H L L × × Illegal
Write
L × × × × Invalid
H H H × × DESL NOP → Idle after IREFC
H H L H BA, UA RDA Illegal
H H L L BA, UA WRA Illegal
H L H × × PDEN Self-Refresh Entry 14
H L L × × Illegal
Auto-Refreshing
L × × × × Refer to Self-Refreshing State
H H H × × DESL NOP → Idle after IRSC
H H L H BA, UA RDA Illegal
H H L L BA, UA WRA Illegal
H L H × × PDEN Illegal
H L L × × Illegal
Mode Register
Accessing
L × × × × Invalid
H × × × × Invalid
L L × × × Maintain Power Down Mode
L H H × × PDEX
Exit Power Down Mode → Idle after
tPDEX
Power Down
L H L × × Illegal
H × × × × Invalid
L L × × × Maintain Self-Refresh
L H H × × SELFX Exit Self-Refresh → Idle after IREFC
Self-Refreshing
L H L × × Illegal
Notes: 12. Illegal if any bank is not idle.
13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA).
14. Illegal if tFPDL is not satisfied.
TC59LM914/06AMB-37,-45,-50
2003-08-04 20/57
MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
ADDRESS BA1*1 BA0*1 BA2, A13~A8 A7*3 A6~A4 A3 A2~A0
Register 0 0 0 TE CL BT BL
A7 TEST MODE (TE) A3 BURST TYPE (BT)
0 Regular (default)
0 Sequential
1 Test Mode Entry 1 Interleave
A6 A5 A4 CAS LATENCY (CL) A2 A1 A0 BURST LENGTH (BL)
0 0 × Reserved*2 0 0 0 Reserved*2
0 1 0 Reserved*2 0 0 1 2
0 1 1 3 0 1 0 4
1 0 0 4 0 1 1
1 0 1 5 1 × ×
Reserved*2
1 1 0 Reserved*2
1 1 1 Reserved*2
Extended Mode Register (Notes: 4)
ADDRESS BA1*4 BA0*4 BA2, A13~A12 A11*6A10*7A9~A7 A6 A5~A2 A1 A0*5
Register 0 1 0 0 DQS OCD DIC 0 DIC DS
A9 A8 A7 Driver Impedance Adjustment A6 A1 OUTPUT DRIVE IMPEDANCE
CONTROL (DIC)
0 0 0 OCD Calibration mode
exit 0 0 Normal Output Driver
0 0 1 Drive (1) 0 1 Strong Output Driver
0 1 0 Drive (0) 1 0 Weak Output Driver
1 0 0 Adjust mode
1 1 Full Strength Output Driver
1 1 1 OCD Calibration default
A10 DQS Enable A0 DLL SWITCH (DS)
0 Disable 0 DLL Enable
1 Enable
1 DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0.
2. “Reserved” places in Regular Mode Register should not be set.
3. A7 in Regular Mode Register must be set to “0” (low state).
Because Test Mode is specific mode for supplier.
4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0.
5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
6. A11 in Extended Mode Register must be set to “0”.
7. TC59LM914AMB, A10 in Extended Mode Register is ignored. DQS is available only TC59LM906AMB.
TC59LM914/06AMB-37,-45,-50
2003-08-04 21/57
STATE DIAGRAM
STANDBY
(IDLE)
SELF-
REFRESH
POWER
DOWN
PDEN
(PD = L)
PDEX
(PD = H)
SELFX
( PD = H)
MODE
REGISTER
AUTO-
REFRESH
ACTIVE
ACTIVE
(RESTORE)
READ
WRITE
(BUFFER)
PD = L
PD = H
WRA RDA
MRSREF
Command input
LAL
A
utomatic return
The second command at Active state
must be issued 1 clock after RDA or
WRA command input.
LAL
TC59LM914/06AMB-37,-45,-50
2003-08-04 22/57
TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 3)
CL
K
CLK
Hi-Z
DQ
(output)
BL = 2
IRC = 5 cycles
Hi-Z Q0 Q1
CL = 3
Command
IRC = 5 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL DESL RDA LAL RDA LALDESL DESL
IRC = 5 cycles
Address UA LA UA LA UA LA
IRA
S
= 4 c
y
cles IRCD=1 cycle IRAS = 4 cycles
IRCD=1 cycle IRCD=1 cycle IRA
S
= 4 c
y
cles
Bank Add. #0 #0 #0
DQS/ DQS
(output)
Q0 Q1
Hi-Z
DQ
(output)
BL = 4
Hi
-
Z
Q0 Q1
DQS/ DQS
(output)
Q0 Q1 Q0Q2 Q3 Q2 Q3
RDA
UA
#0
CL = 3 CL = 3
CL = 3 CL = 3 CL = 3
Q1 Q2 Q3
Q0 Q1
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 23/57
SINGLE BANK READ TIMING (CL = 4)
CL
K
CLK
Hi-Z
DQ
(output)
BL = 2
IRC = 5 cycles
Hi-Z Q0 Q1
CL = 4
Command
IRC = 5 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL DESL RDA LAL RDA LALDESL DESL
IRC = 5 cycles
Address UA LA UA LA UA LA
IRAS = 4 cycles IRCD=1 cycle IRAS = 4 cyclesIRCD=1 cycle IRCD=1 cycle IRAS = 4 cycles
Bank Add. #0 #0 #0
DQS/ DQS
(output)
CL = 4
Q0 Q1 Q0
CL = 4
Hi-Z
DQ
(output)
BL = 4
Hi-Z Q0 Q1
CL = 4
DQS/ DQS
(output)
CL = 4
Q0 Q1 Q0
CL = 4
Q2 Q3 Q2 Q3
RDA
UA
#0
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 24/57
SINGLE BANK READ TIMING (CL = 5)
IRC = 6 cycles
CLK
CLK
Hi-Z
DQ
(output)
BL = 2
Hi-Z Q0 Q1
CL = 5
Command
IRC = 6 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL DESL RDA LAL RDA LALDESL
Address UA LA UA LA UA LA
IRAS = 5 cycles IRCD=1 cycle IRAS = 5 cyclesIRCD=1 cycle IRCD=1 cycle
Bank Add. #0 #0 #0
DQS/ DQS
(output)
CL = 5
Q0 Q1
Hi-Z
DQ
(output)
BL = 4
Hi-Z Q0 Q1
CL = 5
DQS/ DQS
(output)
CL = 5
Q0 Q1 Q2 Q3 Q2 Q3
DESL
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 25/57
SINGLE BANK WRITE TIMING (CL = 3)
CL
K
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
IRC = 5 cycles
WL
=
2
Command
IRC = 5 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRA LAL DESL WRA LAL WRA LALDESL DESL
IRC = 5 cycles
Address LA UA LA UA LA
IRAS = 4 c
y
cles IRCD=1 c
y
cle IRAS
=
4 c
y
clesIRCD
=
1 c
y
cle IRCD
=
1 c
y
cle IRAS = 4 c
y
cles
Bank Add. #0 #0 #0
D0 D1
DQS/ DQS
(input)
DQ
(input)
BL = 4
D0 D1 D2 D3
D0 D1 D0 D1
D0 D1 D2 D3
WRA
UA
#0
WL
=
2 WL = 2
WL
=
2 WL
=
2 WL = 2
D0 D1 D2 D3
Note : TC59LM914AMB doesn’t have DQS .
UA
TC59LM914/06AMB-37,-45,-50
2003-08-04 26/57
SINGLE BANK WRITE TIMING (CL = 4)
CL
K
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
IRC = 5
WL = 3
Command
IRC = 5 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRA LAL DESL WRA LAL WRA LALDESL DESL
IRC = 5 cycles
Address UA LA UA LA UA LA
IRAS = 4 cycles IRCD=1 cycle IRAS = 4 cyclesIRCD=1 cycle IRCD=1 cycle IRAS = 4 cycles
Bank Add. #0 #0 #0
WL = 3
D0 D1
WL = 3
DQS/ DQS
(input)
DQ
(input)
BL = 4
WL = 3 WL = 3 WL = 3
D2 D3
Note : TC59LM914AMB doesn’t have DQS .
D0 D1 D0 D1
D0 D1 D2 D3 D0 D1 D2
WRA
UA
#0
D3D0 D1
TC59LM914/06AMB-37,-45,-50
2003-08-04 27/57
SINGLE BANK WRITE TIMING (CL = 5)
IRC = 6 cycles
CL
K
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
WL = 4
Command
IRC = 6 cycles
WRA LAL DESL WRA LAL WRA LALDESL
Address UA LA UA LA UA LA
IRAS = 5 cycles IRCD=1 cycle IRAS = 5 cycles IRCD=1 cycle IRCD=1 cycle
Bank Add. #0 #0 #0
WL = 4
DQS/ DQS
(input)
DQ
(input)
BL = 4
DESL
D0 D1 D0 D1
WL = 4 WL = 4
D0 D1 D0 D1 D2 D3 D2 D3
0 1 2 3 5678 9 10 11 12 13 14 154
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 28/57
SINGLE BANK READ-WRITE TIMING (CL = 3)
CL
K
CLK
Hi-Z
DQS
DQ
BL = 2
IRC = 5 cycles
Hi-Z
Q0 Q1
CL = 3
Command
IRC
=
5 c
y
cles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL DESL RDA LAL WRA LALDESL DESL
IRC = 5 c
y
cles
Address UA LA UA LA UA LA
Bank Add. #0 #0 #0
DQS
WL
=
2
D0 D1
CL = 3
Hi-Z
DQS
DQ
BL = 4
Hi-Z Q0 Q1 D0 D1Q2 Q3 D2 D3
WRA
UA
#0
Q0 Q1
Q0 Q1 Q2 Q3
CL = 3 WL
=
2CL = 3
Hi-Z
Hi-Z
Note : TC59LM914AMB doesn’t have DQS .
DQS
TC59LM914/06AMB-37,-45,-50
2003-08-04 29/57
SINGLE BANK READ-WRITE TIMING (CL = 4)
CL
K
CLK
Hi-Z
DQS
DQ
BL = 2
IRC = 5 cycles
Hi-Z Q0 Q1
CL = 4
Command
IRC = 5 cycles
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL DESL RDA LAL WRA LALDESL DESL
IRC = 5 cycles
Address UA LA UA LA UA LA
Bank Add. #0 #0 #0
DQS
WL
=
3
D0 D1 Q0
CL = 4
Hi-Z
DQS
DQ
BL = 4
Hi-Z Q0 Q1
CL = 4
DQS
WL
=
3
D0 D1 Q0
CL = 4
Q2 Q3 D2 D3
WRA
UA
#0
Hi-Z
Hi-Z
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 30/57
SINGLE BANK READ-WRITE TIMING (CL = 5)
CL
K
CLK
DQS
DQ
BL = 2
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
DESL
Address
Bank Add.
DQS
DQS
DQ
BL = 4
DQS
IRC = 6 cycles
Hi-Z
Hi-Z
Q0 Q1
CL = 5
IRC = 6 cycles
RDA LAL RDA LAL WRA LALDESL
UA LA UA LA UA LA
#0 #0 #0
WL = 4
D0 D1
Hi-Z
Hi-Z Q0 Q1
CL = 5
Q2 Q3 D0 D1 D2 D3
DESL
WL = 4
Hi-Z
Hi-Z
Note : TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 31/57
MULTIPLE BANK READ TIMING (CL = 3)
RDA
UA
Bank
"b"
CLK
CLK
Hi-Z
DQ
(output)
BL = 2
IRBD = 2 cycles
Hi-Z Qa0 Qa1
CL = 3
Command
0 1 23 4 56789101112 13 14 15
LAL RDARDA LAL RDA LAL
Address UA LA UA LA UA LA
Bank Add. Bank
"a"
DQS/ DQS
(output)
CL = 3
DQ
(output)
BL = 4
Hi-Z
DQS/ DQS
(output)
RDA LAL DESL
IRBD = 2 cycles
RDA LAL RDA
IRBD = 2 cyclesIRBD =2 cycles
LAL RDA LAL
UA LA UA LA UA LA UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0 Qc1
Hi-Z
Qa0 Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2Qa3Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
IRBD = 2 cycles
LA
CL = 3
CL = 3
Qc3Qd0Qd1
Qd0Qd1
TC59LM914/06AMB-37,-45,-50
2003-08-04 32/57
MULTIPLE BANK READ TIMING (CL = 4)
RDA
UA
Bank
"b"
CLK
CLK
Hi-Z
DQ
(output)
BL = 2
IRBD = 2 cycles
Hi-Z
Qa0Qa1
CL = 4
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LAL RDA RDA LAL RDA LAL
Address UA LA UA LA UA LA
Bank Add. Bank
"a"
DQS/ DQS
(output)
CL
=
4
DQ
(output)
BL = 4
Hi-Z
DQS/ DQS
(output)
RDA LAL DESL
IRBD = 2 cycles
RDA LAL RDA
IRBD = 2 cyclesIRBD = 2 cycles
LAL RDA LAL
UA LA UA LA UA LA UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Qb0Qb1 Qa0Qa1 Qb0 Qb1 Qc0Qc1
Hi-Z
CL = 4
CL
=
4
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0Qa1Qa2 Qa3 Qb0 Qb1 Qb2 Qb3Qc0Qc1Qc2
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
IRBD = 2 cycles
LA
TC59LM914/06AMB-37,-45,-50
2003-08-04 33/57
MULTIPLE BANK READ TIMING (CL = 5)
CLK
CLK
DQ
(output)
BL = 2
Hi-Z
CL = 5
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
RDA LAL RDA LAL RDA
Address UA LA UA LA UA
Bank Add. Bank
"a"
DQS/ DQS
(output)
CL
=
5
DQ
(output)
BL = 4
Hi-Z
DQS/ DQS
(output)
RDA LAL LAL RDA LAL RDA LAL RDA
UA LA LA UA LA UA LA UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
IRC (Bank"a") = 6 cycles
IRC (Bank"b") = 6 cycles
Hi-Z
Hi-Z
CL = 5
CL
=
5
DESL
Bank
"a"
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
LAL
LA
Qa0Qa1Qa2Qa3Qb0Qb1Qb2Qb3 Qa0 Qa1 Qa2 Qa3Qb0Qb1Qb2
Qa0Qa1 Qb0Qb1 Qa0 Qa1 Qb0Qb1
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 34/57
MULTIPLE BANK WRITE TIMING (CL = 3)
CLK
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
WL =2
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LAL WRAWRA LAL WRA LAL
Address UA LA UA LA UA LA
Bank Add. Bank
"a"
WL = 2
DQS/ DQS
(input)
DQ
(input)
BL = 4
WRA LAL DESL WRA LAL WRA LAL WRA LAL
UA LA UA LA UA LA UA LA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1
Da0 Da1 Da2 Da3 Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1Db2Db3 Dc0 Dc1 Dc2 Dc3
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
Da0 Da1 Dd0Dd1
Dd0Dd1
WRA
UA
Bank
"b"
WL =2
WL = 2
Dd2Dd3
TC59LM914/06AMB-37,-45,-50
2003-08-04 35/57
MULTIPLE BANK WRITE TIMING (CL = 4)
CLK
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
WL = 3
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
LAL WRA WRA LAL WRA LAL
Address UA LA UA LA UA LA
Bank Add. Bank
"a"
WL =3
DQS/ DQS
(input)
DQ
(input)
BL = 4
WRA LAL DESL WRA LAL WRA LAL WRA LAL
UA LA UA LA UA LA UA LA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 5 cycles
IRC (Bank"b") = 5 cycles
Db0Db1 Da0Da1 Db0Db1 Dc0 Dc1
Da0 Da1Da2Da3Db0Db1Db2Db3 Da0Da1Da2Da3Db0Db1 Db2 Db3 Dc0 Dc1 Dc2Dc3
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
Da0 Da1 Dd0Dd1
WL = 3
WL = 3
Dd0Dd1
WRA
UA
Bank
"b"
TC59LM914/06AMB-37,-45,-50
2003-08-04 36/57
MULTIPLE BANK WRITE TIMING (CL = 5)
CLK
CLK
DQS/ DQS
(input)
DQ
(input)
BL = 2
WL = 4
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRA LAL WRA LAL WRA
Address UA LA UA LA UA LA
Bank Add. Bank
"a"
WL
=
4
DQS DQS
(input)
DQ
(input)
BL = 4
WRA LAL LAL WRA LAL WRA LAL WRA
UA LA UA LA UA LA UA
Bank
"b"
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
IRC (Bank"a") = 6 cycles
IRC (Bank"b") = 6 cycles
Db0Db1 Da0Da1 Db0 Db1 Dc0Dc1
Da0Da1Da2Da3Db0Db1Db2Db3 Da0Da1 Da2 Da3 Db0 Db1 Db2Db3Dc0Dc1
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles IRBD = 2 cycles
Da0Da1
DESL
WL = 4
WL
=
4
LAL
LA
TC59LM914/06AMB-37,-45,-50
2003-08-04 37/57
MULTIPLE BANK READ-WRITE TIMING (BL = 2)
CL
K
CLK
DQS
CL = 4
IRBD = 2 cycles
WL = 3
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
Bank Add.
CL
=
4
IRC (Bank"a")
IRC (Bank"b")
IWRD = 1 cycle IRWD = 2 cycles IWRD
=
1 cycle IRWD
=
2 cycles
DQS
Hi
-
Z
DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
Hi
-
Z
DQS
CL = 5
WL = 4
DQS
CL
=
5
Hi
-
Z
WRADESLWRAWRAWRA RDALAL LAL DESLDESL RDALAL LAL RDA LAL LAL
UA LA UA LA UA LA UA LA UA LA UA LA UA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
Bank
"c"
DQ
Hi
-
Z
Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
DQS
CL = 3
WL =2
CL = 3
DQS
Hi
-
Z
DQ Da0 Da1 Qb0 Qb1 Dc0 Dc1 Qd0 Qd1 Da0 Da1
Hi
-
Z
Hi
-
Z
Hi
-
Z
Hi
-
Z
TC59LM914/06AMB-37,-45,-50
2003-08-04 38/57
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
CL
K
CLK
DQS
CL = 4
IRBD = 2 cycles
WL = 3
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Address
Bank Add.
CL
=
4
IRC (Bank"a")
IRC (Bank"b")
IWRD = 1 cycle IRWD = 3 cycles IWRD
=
1 cycle IRWD
=
3 cycles
DQS
Hi
-
Z
DQ
Hi
-
Z
DQS
CL = 5
WL = 4
DQS
CL
=
5
Hi
-
Z
LALRDAWRA RDALAL LAL LALLALWRA RDA WRA LAL
UA LA UA LA UA LA UA UA LA LA
Bank
"a"
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
DQ
Hi
-
Z
Note: lRC to the same bank must be satisfied.
TC59LM914AMB doesn’t have DQS .
DESL DESL
UALA
Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
IWRD = 1 cycle
DQS
CL = 3
WL =2
CL = 3
DQS
Hi
-
Z
DQ
H
i
-
Z
Qb0 Qb1Da0 Da1 Da2 Da3 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 Qd0 Qd1 Qd2 Qd3
Hi
-
Z
Hi
-
Z
Hi
-
Z
TC59LM914/06AMB-37,-45,-50
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WRITE with VARIAVLE WRITE LENGTH (VW) CONTROL (CL = 4)
CL
K
CLK
DQS/ DQS
(input)
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
WRA LAL WRA LALDESL
Address UA LA=#3
VW=All UA
Bank Add. Bank
"a"
Bank
"a"
BL = 2, SEQUENTIAL MODE
DESL
LA=#1
VW=1
VW0 = Low
VW1 = don't care
VW0 = High
VW1 = don't care
DQ
(input) D0D0 D1
Lower Address #3 #2 #1
(
#0
)
Last one data is masked.
DQS/ DQS
(input)
Command WRA LAL WRA LALDESL
Address UA LA=#3
VW=All UA
Bank Add. Bank
"a"
Bank
"a"
BL = 4, SEQUENTIAL MODE
DESL
LA=#1
VW=1
DQ
(input) D0D0 D1
Lower Address #3 #0 #1
(
#2
)(
#3
)(
#0
)
Last three data are masked.
DESL WRA LAL
VW0 = High
VW1 = Low
VW0 = High
VW1 = High
UA LA=#2
VW=2
VW0 = Low
VW1 = High
Bank
"a"
D2 D3 D0 D1
#1 #2
Last two data are masked.
(
#0
)(
#1
)
#2 #3
Note: DQS ( DQS ) input must be continued till end of burst count even if some of laster data is masked.
VW=1
VW=A11
VW=A11 VW=1 VW=2
TC59LM914/06AMB-37,-45,-50
2003-08-04 40/57
POWER DOWN TIMING (CL = 4, BL = 4)
Read cycle to Power Down Mode
CLK
CLK
0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3
IPDA
tIH
tIS IPD = 1 cycle
tPDEX
Power Down Entry Power Down Exit
Note: PD must be kept "High" level until end of Burst data output.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
TC59LM914AMB doesn’t have DQS .
DQS
(output)
Command RDA LAL DESL
Address UA UA
DESL RDA
or
WRA
LA
lRC(min) , tREFI(max)
tQPDH
DQS
(output)
Hi-Z
Hi-Z Q0 Q1
CL = 4
Q2 Q3
Hi-Z
Hi-Z
DQ
(output)
PD
Hi-Z
TC59LM914/06AMB-37,-45,-50
2003-08-04 41/57
POWER DOWN TIMING (CL = 4, BL = 4)
Write cycle to Power Down Mode
CLK
CLK
0 1 2 3 4 5 6 7 8 9 10 n-1 n n+1 n+2 n+3
IPDA
tIH
tIS IPD = 1 cycle
tPDEX
Note: PD must be kept "High" level until WL+2 clock cycles from LAL command.
PD should be brought to "High" within tREFI(max.) to maintain the data written into cell.
In Power Down Mode, PD "Low" must be maintained.
When PD is brought to "High", a valid executable command may be applied lPDA cycles later.
TC59LM914AMB doesn’t have DQS .
DQS
(input)
Command WRA LAL DESL
Address UA UA
DESL RDA
or
WRA
LA
lRC(min) , tREFI(max)
DQS
(input)
WL = 3
D0 D1 D2 D3
DQ
(input)
PD
2 clock cyclesWL = 3
TC59LM914/06AMB-37,-45,-50
2003-08-04 42/57
MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Mode Register Set operation.
CL
K
CLK
DQS
(output)
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
RDA LAL RDA MRSDESL
A13~A0 UA Valid
(opcode)
DQS
IRSC
DESL RD
A
or
WR
A
LA UA
BA0~BA2 BA BA0="0"
BA1="0"
BA2="0" BA
LAL
DQ
(output)
CL + BL/2
Hi-Z
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of MRS operation is CL+BL/2.
TC59LM914AMB doesn’t have DQS .
15
LA
Hi-Z
TC59LM914/06AMB-37,-45,-50
2003-08-04 43/57
MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Mode Register Set operation.
CL
K
CLK
DQS
(input)
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
WRA LAL RDA MRSDESL
A13~A0 UA Valid
(opcode)
DQS
(input)
IRSC
DESL RD
A
or
WR
A
LA UA
BA0~BA2 BA BA0="0"
BA1="0"
BA2="0" BA
D0 D1 D2 D3
DQ
(input)
15
WL+BL/2
LA
LAL
Note: Minimum delay from LAL following WRA to RDA of MRS operation is WL+BL/2.
TC59LM914AMB doesn’t have DQS .
TC59LM914/06AMB-37,-45,-50
2003-08-04 44/57
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 2)
From Read operation to Extended Mode Register Set operation.
CL
K
CLK
DQS
(output)
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
RDA LAL RDA MRSDESL
A13~A0 UA Valid
(opcode)
DQS
(output)
IRSC
DESL RD
A
or
WR
A
LA UA
BA0~BA2 BA BA0="1"
BA1="0"
BA2="0" BA
DQ
(output)
Hi-Z
Q0 Q1
Note: Minimum delay from LAL following RDA to RDA of EMRS operation is CL+BL/2.
DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
TC59LM914AMB doesn’t have DQS .
15
LA
LAL
Hi-Z
CL + BL/2
TC59LM914/06AMB-37,-45,-50
2003-08-04 45/57
EXTENDED MODE REGISTER SET TIMING (CL = 4, BL = 4)
From Write operation to Extended Mode Register Set operation.
CL
K
CLK
DQS
(input)
Command
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
WRA LAL RDA MRSDESL
A13~A0 UA Valid
(opcode)
DQS
(input)
WL+BL/2
IRSC
DESL RD
A
or
WR
A
LA UA
BA0~BA2 BA BA0="1"
BA1="0"
BA2="0" BA
D0 D1 D2 D3
DQ
(input)
Note: DLL switch in Extended Mode Register must be set to enable mode for normal operation.
DLL lock-on time is needed after initial EMRS operation. See Power Up Sequence.
Minimum delay from LAL following WRA to RDA of EMRS operation is WL+BL/2.
TC59LM914AMB doesn’t have DQS .
15
LAL
LA
TC59LM914/06AMB-37,-45,-50
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AUTO-REFRESH TIMING (CL = 4, BL = 4)
CL
K
WRA REF WRA REF WRA REF WRA REF WRA REF
t1 t2 t3t7t8
8 Refresh cycle
tREFI =Total time of 8 Refresh cycle
8
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8
8
=
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area
than Read / Write operation.
CL
K
CLK
Hi-Z DQS/ DQS
(output)
DQ
(output)
0 1 2 3 4 5 6 7 n − 1n n + 1 n + 2
RDA LAL
Hi-Z Hi-Z
CL = 4
Command
IRC = 5 cycles
DESL RD
A
or
WR
A
LAL o
r
MRS or
REF
IRCD = 1 cycle
Note: In case of CL = 4, IREFC must be meet 18 clock cycles.
When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command
specified by tREFI must be satisfied.
tREFI is average interval time in 8 Refresh cycles that is sampled randomly.
TC59LM914AMB doesn’t have DQS .
WRA REF
IREFC = 18 cycles
Hi-Z
IRAS = 4 cycles IRCD = 1 cycle
DESL
Bank,
UA LA Bank, Address
Q0 Q1 Q2 Q3
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SELF-REFRESH ENTRY TIMING
SELF-REFRESH EXIT TIMING
Notes: 1. is don’t care.
2. Clock should be stable prior to PD = “High” if clock input is suspended in Self-Refresh mode.
3. DESL command must be asserted during IREFC after PD is brought to “High”.
4. IPDA is defined from the first clock rising edge after PD is brought to “High”.
5. It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any
other operation.
6. Any command (except Read command) can be issued after IREFC.
7. Read command (RDA + LAL) can be issued after ILOCK.
8. TC59LM914AMB doesn’t have DQS .
CL
K
CLK
Hi-Z
DQS/ DQS
(output)
DQ
(output)
0 1 2 m − 1mm + 1m + 2
Hi-Z
Command
ILOCK
tPDEX
IPD
A
= 1 cycles
*
4
PD
DESL*3 LAL*7
WRA*5REF*5DESL RDA*7
n − 1nn + 1 p − 1 p
Command (1st)
*
6
Command (2nd)
*
6
IRCD
=
1 cycle
Self-Refresh Exit
*
2
IREFC
IREFC
IRCD
=
1 cycle
Notes: 1. is don’t care.
2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self Refresh
mode. When PD is brought to "Low" after lPDV, TC59LM914/06AMB perform Auto Refresh and
enter Power down mode. In case of PD fall between tFPDL(max) and lPDV, TC59LM914/06AMB will
either entry Self-Refresh mode or Power down mode after Auto-Refresh operation. It can’t be
specified which mode TC59LM914/06AMB operates.
3. It is desirable that clock input is continued at least lCKD from REF command even though PD is
brought to “Low” for Self-Refresh Entry.
4. TC59LM914AMB doesn’t have DQS .
5. In case of Self-Refresh entry after Write Operation, the delay time from the LAL command following
WRA to the REF command is Write latency (WL)+3 clock cycles minimum.
CL
K
CLK
Hi-Z
DQS/ DQS
(output)
DQ
(output)
0 1 2 3 4 5 m − 1mm + 1
WRA REF
Qx Hi-Z
Command
IRCD = 1 cycle IREFC
DESL
tFPDL (min) tFPDL (max)
IPDV
*
2
PD
ICKD
tQPDH
Auto Refresh
Self Refresh Entry
TC59LM914/06AMB-37,-45,-50
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FUNCTIONAL DESCRIPTION
Network FCRAMTM
FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to
perform fast random core access, low latency and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK &
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input.
The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the
negative edge of CLK . The DQS and DQ output are aligned to the crossing point of CLK and CLK . The
timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN:
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a
Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into
low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each
operation mode is decided by the combination of the two consecutive operation commands using the CS and
FN inputs.
BANK ADDRESSES: BA0~BA2
The BA0 to BA2 inputs are latched at the time of a ssertion of the RDA or WRA command and are selected th e
bank to be used for the operation. BA0 and BA1 also define which mode register is loaded during the Mode
Register Set command (MRS or EMRS).
BA0 BA1 BA2
Bank #0 0 0 0
Bank #1 1 0 0
Bank #2 0 1 0
Bank #3 1 1 0
Bank #4 0 0 1
Bank #5 1 0 1
Bank #6 0 1 1
Bank #7 1 1 1
ADDRESS INPUTS: A0~A13
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The
Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are
latched at the LAL command. The A0 to A13 inputs are also used for setting the data in the Regular or
Extended Mode Register set cycle.
UPPER ADDRESS LOWER ADDRESS
TC59LM906AMB A0~A13 A0~A8
TC59LM914AMB A0~A13 A0~A7
CLK
PD
CS
TC59LM914/06AMB-37,-45,-50
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DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The
output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
DATA STROBE: DQS, DQS
The DQS is bi-directional signal. Both edge of DQS are used as the reference of data input or output. In write
operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS is an
output signal provides the read data strobe.
TC59LM906AMB has differential data strobe pin (DQS ). When DQS is enable mode, DQS is differential
output signal for DQS in read operation, data input are latched at the crossing point of DQS and DQS in Write
operation. When DQS is disable mode, DQS is always Hi-Z, and data input are latched at the crossing poin t
of DQS and VREF level. DQS mode is set at Extended Mode Register Set Cycle.
TC59LM914AMB doesn’ t have DQS pin. Data input are latched at the crossing point of L/UDQS and VREF
level in Write operation. LDQS is strobe signal for DQ0-DQ7. UDQS is strobe signal for DQ8-DQ15.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits.
VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
TC59LM914/06AMB-37,-45,-50
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COMMAND FUNCTIONS and OPERATIONS
TC59LM914/06AMB are introduced the two consecutive command input method. Therefore, except for Power
Down mode, each operation mode decided by the combination of the first command and the second command from
stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Addr ess in a r ead mod e. Wh en th e LAL command with Lower Addresses i s i ssu ed at the ne xt
clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS/DQS
output signal (Burst Read Operation ). The initial valid read data appears after CAS latency from the issuing of
the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read
data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back
automatically to the idle state after lRC. DQS is differential data strobe signal supported TC59LM906AM B.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank
designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the
next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of
DQS/DQS in put signal (Burst Write Operation). The data and DQS/DQS inputs have to be asserted in keeping
with clock input after CAS late ncy-1 from the issuing of the LAL command. The DQS/DQS has to be provided
for a burst length. Th e CAS latency and the burst type must be set in the Mode Register beforeh and. The write
operated bank goes back automatically to the idle state after lRC. Write Burst Length is controlled by VW0 and
VW1 inputs with LAL command. See VW truth table. DQS is differential data strobe signal supported
TC59LM906AMB.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM914/06AMB are r equ ired to r efresh like a standar d SDRAM. The Auto-Refresh operation is begu n with
the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks
are in the idle state and all outpu ts are in Hi-Z states. In a point to notice, the write mode started with the WRA
command is canceled by the REF command having gone into the next clock of the WRA command instead of the
LAL command. The minimum period between the Auto-Refresh command and the next command is specified by
lREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of
equally distributed refresh, Auto-Refresh command has to be issued within once for every 3.9 µs by the maximum.
In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh
command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles that be
performed within 3.2 µs (8 × 400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with = “L”)
In case of Self-Refresh operation, refresh operation can be performed automatically by using an internal timer.
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM914/06AMB become
Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to “Low” within tFPDL from the
REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh
period, the Self-Refresh entry command should be asserted within 3.9 µs after the latest Au to-Refresh command.
Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition, it
is desirable that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held “Low”.
During Self-Refresh mode, all input and output buffers are disabled except for PD , therefore the power
dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from “Low” to “High” along
with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified
by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh
command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh exit.
Power Down Mode ( = “L”)
When all banks are in the idle state an d DQ outputs are in Hi-Z states, th e TC59LM914/06AMB bec ome Power
Down Mode by asserting PD is “Low”. When the device enters the Power Down Mode, all input and output
buffers are disabled after specified time except for PD . Therefore, the power dissipation lowers. To exit the
Power Down Mode, PD has to be brought to “High” and the DESL command has to be issued for two clock cycle
after PD goes high. The Power Down exit function is asynchronous operation.
PD
PD
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Mode Register Set (MRS) and Extended Mode Register Set (EMRS)
(1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program
the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS
command having gone into the next clock of the RDA command instead of the LAL command. The data to be set
in the Mode Register is transferred using A0 to A13, BA0 to BA2 address inputs. The TC59LM914/06AMB have
two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is
chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a
read or write cycle. The Regular Mode Register has four function fields.
The four fields are as follows:
(R-1) Burst Length field to set the length of burst data
(R-2) Burst Type field to designate the lower address access sequence in a burst cycle
(R-3) CAS Latency field to set the access time in clock cycle
(R-4) Test Mode field to use for supplier only.
The Extended Mode Register has five function fields.
The five fields are as follows:
(E-1) DLL Switch field to choose either DLL enable or DLL disable
(E-2) Output Driver Impedance Control field.
(E-3) Off-Chip Driver (OCD) Impedance Adjustment for Full Strength Output Driver
(E-4)DQS enable field
(E-5) Interface mode select
Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register
is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended
Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before
proper operation.
• Regular Mode Register/Extended Mode Register change bits (BA0, BA1)
These bits are used to choose either Regular MRS or Extended MRS
BA1 BA0 BA2, A13~A0
0 0 Regular MRS Cycle
0 1 Extended MRS Cycle
1 × Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0), (BL)
This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length
to be 2 or 4 words.
A2 A1 A0 BURST LENGTH
0 0 0 Reserved
0 0 1 2 words
0 1 0 4 words
0 1 1 Reserved
1 × × Reserved
(R-2) Burst Type field (A3), (BT)
The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is “0”, Sequ ential
mode is selected. When the A3 bit is “1”, Interleave mode is selected. Both burst types support burst
length of 2 and 4 words.
A3 BURST TYPE
0 Sequential
1 Interleave
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• Addressing sequence of Sequential mode
A column access is started from the inputted lower address and is performed by incrementing the lower
address input to the device.
Addressing sequence for Sequential mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n
Data 1 n + 1
Data 2 n + 2
Data 3 n + 3
2 words (address bits is LA0)
not carried from LA0~LA1
4 words (address bits is LA1, LA0)
not carried from LA1~LA2
• Addressing sequence of Interleave mode
A column access is started from the inputted lower address and is performed by interleaving the address bits
in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 ּּּA8 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 ּּּA8 A7 A6 A5 A4 A3 A2 A1 0A
Data 2 ּּּA8 A7 A6 A5 A4 A3 A2 1A A0
Data 3 ּּּA8 A7 A6 A5 A4 A3 A2 1A 0A
2 words
4 words
(R-3) CAS Latency field (A6 to A4), (CL)
This field specifies the number of clock cycles from the assertion of the LAL command following the
RDA command to the first data read. The minimum values of CAS Latency depends on the frequency
of CLK. In a write mode, the place of clock that should input write data is CAS Latency cycles − 1.
A6 A5 A4 CAS LATENCY
0 0 0 Reserved
0 0 1 Reserved
0 1 0 Reserved
0 1 1 3
1 0 0 4
1 0 1 5
1 1 0 Reserved
1 1 1 Reserved
(R-4) Test Mode field (A7), (TE)
This bit is used to enter Test Mode for supplier only and must be set to “0” for normal operation.
(R-5) Reserved field in the Regular Mode Register
• Reserved bits (A8 to A13, BA2)
These bits are reserved for future operations. They must be set to “0” for normal operation.
CL
K
CLK
Command
DQS/ DQS
DQ Data
0
Data
1
Data
2
Data
3
RDA LAL
CAS Latency = 4
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Extended Mode Register fields
(E-1) DLL Switch field (A0), (DS)
This bit is used to enable DLL. When the A0 bi t is set “0”, DLL is enabled. This bit must set to “0” for
normal operation.
(E-2) Output Driver Impedance Control field (A1, A6) (DIC)
This field is used to choose Output Driver Strength. Four types of Driver Strength are supported.
Output Driver Strength can be set by field in EMRS with OCD calibration default (A7~A9 = 1 at EMRS)
or OCD calibration mode exit (A7~A9 = 0 at EMRS).
A6 A1 OUTPUT DRIVER IMPEDANCE CONTROL
0 0 Normal Output Driver
0 1 Strong Output Driver
1 0 Weak Output Driver
1 1 Full Strength Output Driver
(E-3) Off-Chip Driver (OCD) Impedance Adjustment (A7 to A9) (OCD)
OCD calibration (Off Chip Driver impedance adjustment) is available only for Full Strength Output
Driver. When OCD calibration is performed, A1 and A6 inputs at EMRS must be “1” for Full Strength
Output Driver.
Output Driver Strength can be set by DIC field (E-2). This Driver strength is the initial driver level at
OCD Impedance Adjustment.
The Network FCRAMTM supports driver calibration feature and the flow chart below is an example of
sequence. Every calibration mode command should be followed by “OCD calibration mode exit” before
any other command being issued. MRS should be set before entering OCD impedance adjustment.
EMRS: OCD calibration mode exit
MRS should be set before entering OCD impedance adjustment.
EMRS: Drive(1)
DQ &DQS High; DQS Low
Tes t
Start
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code Input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
EMRS: Drive(0)
DQ &DQS Low; DQS High
A
LL OK Tes t
EMRS: OCD calibration mode exit
EMRS:
Enter Adjust Mode
BL=4 code Input to all DQs
Inc, Dec, or NOP
EMRS: OCD calibration mode exit
A
LL OK
Need Calibration Need Calibration
EMRS: OCD calibration mode exit
End
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Extended Mode Register Set for OCD Impedance adjustment
OCD impedance adjustment can be done using the following EMRS mode. In drive mode all outputs are
driven out by Network FCRAM. In drive (1) mode, all DQ, DQS signals are driven high and DQS signals are
driven low. In drive (0) mode, all DQ, DQS signals are driven low and DQS signals are driven high. In adjust
mode, BL=4 of operation code data must be used
A9 A8 A7 Operation
0 0 0 OCD calibration mode exit
0 0 1 Drive (1) DQ, DQS high and DQS low
0 1 0 Drive (0) DQ, DQS low and DQS high
1 0 0 Adjust mode
1 1 1 OCD calibration default
OCD impedance adjust
To adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit
burst code to Network FCRAM. For this operation, Burst Length has to be set to BL=4 via MRS command
before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 means all
DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjusted for all DQs
simultaneously and after OCD calibration, all DQs of a given Network FCRAM will be adjusted to the same
driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further
increment or decrement code has no effect.
Off-Chip Driver Program
4bit burst code inputs to all DQs Operation
DT0 D
T1 D
T2 D
T3 Pull-up driver strength Pull-down driver strength
0 0 0 0 NOP (No operation) NOP (No operation)
0 0 0 1 Increase by 1 step NOP
0 0 1 0 Decrease by 1 step NOP
0 1 0 0 NOP Increase by 1 step
1 0 0 0 NOP Decrease by 1 step
0 1 0 1 Increase by 1 step Increase by 1 step
0 1 1 0 Decrease by 1 step Increase by 1 step
1 0 0 1 Increase by 1 step Decrease by 1 step
1 0 1 0 Decrease by 1 step Decrease by 1 step
Other Combinations Reserved
For proper operation of adjust mode, WL=CL-1 clocks and tDS / tDH should be met as the following timing
diagram. For input data pattern for adjustment, DT0~DT3 is a fixed order and “not affected by MRS
addressing mode (i.e. Sequential or interleave).
Driver strength is controlled within the following range by OCD impedance adjustment.
SYMBOL PARAMETER MIN MAX UNIT NOTES
IOH (DC) Output Source DC Current for VDDQ = 1.7V~1.9V
VDDQ = 1.7V VOH = 1.420V −14.0 −18.7
IOL (DC)
Full Strength
Output Driver Output Sink DC Current for VDDQ = 1.7V~1.9V
VDDQ = 1.7V VOL = 0.280V 14.0 18.7
mA
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Drive mode
Drive mode, both Drive (1) and Drive (0), is used for controllers to measure Network FCRAM Driver
impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output
drivers are turned-off tOIT after “OCD calibration mode exit” command as the following timing diagram.
(E-4) DQSenable field (A10), (DQS)
This bit is used to enable Differential Data strobe.
DQS is available on TC59LM906AMB. This field of TC59LM914AMB is ign o red.
A10 DQS Enable
0 Disable
1 Enable
(E-5) Interface mode select (A11)
This bit must be always set “0”.
(E-6) Reserved field (A2 to A5, A12, A13, BA2)
These bits are reserved for future operations and must be set to “0” for normal operation.
Command
Enter Drive mode
DQS,
DQS
DQ
DQS high & DQS low for Drive (1), DQS low & DQS high for Drive (0)
CLK
CL
K
OCD calibration mode exit
DQs high for Drive (1), DQs low for Drive (0)
RDA EMRS NOP NOP RDA EMRS NOP
tOIT
tOIT
Command RDA EMRS
OCD adjust mode
NOP NOP NOP NOP RDA EMRS NOP
DQS_in
DQ_in DT0 DT1 DT2 DT3
DQS
tDS tDH
CLK
CL
K
OCD calibration mode exit
WL 1clock
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PACKAGE DIMENSIONS
0.2 SB
0.2 SA
0.08 SAB
13.086
0
-0.15
16.5
10.975
0
-0.15
12.7
0.15 0.1
0.2 S
0.15MIN
1.20MAX 0.4 0.05
1.5 1.5
123456
INDEX
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1.0
2.0
1.25
3.85 3.85
1.85
1.0
A
B
SS
0.5 0.05
P-BGA64-1317-1.00AZ
TC59LM914/06AMB-37,-45,-50
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030619EB
A
RESTRICTIONS ON P RODUCT USE
