CQV1640L10BBI - High Bandwidth Access, Inc.

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

3.3 Volt Synchronous 16 Channel Queue

Memory Configuration Device

65,536 x 80 CQV16100

32,768 x 80 CQV1690

16,384 x 80 CQV1680

8,192 x 80 CQV1670

4,096 x 80 CQV1660

2,048 x 80 CQV1650

1,024 x 80 CQV1640

512 x 80 CQV1630

Key Features

• Single device solution providing complete data queuing and switching functions (up to 166 MHz)

• Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns)

• Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns)

• 3.3V power supply

• 5V input tolerant on all control and data input pins

• 5V output tolerant on all flags and data output pins

• 5-bit wide data channels, up to sixteen channels per chip (80 bits total)

• Reconfigurable data switching supporting channel unicast, multicast and broadcast

• Master Reset clears all previously programmed configurations including Write and Read pointers

• Partial Reset clears Write and Read pointers but maintains all previously programmed configurations

• First Word Fall Through (FWFT) and Standard Timing modes

• Presets for eight different Almost Full and Almost Empty offset values

• Parallel/Serial programming of PRAF and PRAE offset values

• Programmable 8-bit or 10-bit parallel programming modes for offset values

• Full, Empty, Almost Full, Almost Empty, and Half Full indicators

• PRAF and PRAE operates in either synchronous or asynchronous modes

• Individual synchronous channel output enable signals controlling tri-state data output drivers

• Asynchronous device output enable signals controlling tri-state data output drivers

• Synchronous Read Chip Select

• Data retransmission with programmable zero or normal latency modes

• Switching management

• Boundary Scan (JTAG)

• Available package: 256 - pin Fine Pitch Ball Grid Array (BGA)

• (0°C to 70°C) Commercial operating temperature available for cycle time of 6.0ns and above

• (-40°C to 85°C) Industrial operating temperature available for cycle time of 7.5ns and above

Product Description

HBA’s ChannelQTM product family represents the next generation bandwidth management solutions by providing advanced data

queuing and switching functions within a single chip. System designers can take full advantage of the flexible data switching

functions offered by the ChannelQ products while maintaining access to all the advanced features available in HBA’s existing

FlexQTM family, such as programmable FIFO status flags, programmable data access timing (First-Word-Fall-Through and

Standard modes), data retransmission with programmable latency mode, and tri-state output data drivers.

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TM

Rev 1.0

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Product Description (Continued)

The channel switching capability provides a means for unicast / multicast / broadcast of individual channel data when they are

written to the internal FIFO memory. The configuration of the channel switch can be reprogrammed on the fly. Because the

device combines data queuing and switching into a single chip, it in effect implements a switching fabric with input data queuing,

which has a broad range of applications in data communication. For detailed information on programming and using the

ChannelQTM devices, please refer to the ChannelQ Application Note.

5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous

Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select and synchronous channel

output enables are also available to control the state of data output drivers, allowing multiple ChannelQ devices to share a single

output data bus. Independent Write and Read controls provide rate-matching capability.

Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and

Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will

initialize Write and Read pointers to zero.

In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high

transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing

depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively.

In Standard mode, always assert REN for a read operation. FULL and EMPTY are used instead of DRDY and

QRDY respectively.

Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial

programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit

parallel programming modes for offset values can be selected for convenience.

PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either

synchronous or asynchronous modes.

At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of

RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the

physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit

operation.

ChannelQ devices have low power consumption, hence minimizing system power requirements. In addition, industry standard

256 - pin BGA is offered to save system board space.

These devices are ideal for applications such as data communication, telecommunication, test equipment, network switching, etc.

July 200

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TM

Rev 1.0

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3C080B

Programming Modes

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

88

Channel In Channel Out

Output Channel

Channel Source 76543210

76543210

Channels Channels

Figure 1. 8x5-to-8x5 ChannelQ Configured in Unicast Mode

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

88

Channel In Channel Out

Output Channel

Channel Source 22222222

76543210

Channels Channels

Figure 2. 8x5-to-8x5 ChannelQ Configured in Broadcast Mode

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TM

Rev 1.0

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3C080B

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

88

Channel In Channel Out

Output Channel

Channel Source 76763233

76543210

Channels Channels

Figure 3. 8x5-to-8x5 ChannelQ Configured in Multicast Mode

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

88

Channel In Channel Out

Output Channel

Channel Source 10547632

76543210

Channels Channels

Figure4. 8x5-to-8x5 ChannelQ Configured as a 4x10-to-4x10 Switch in Switching Mode

July 200

2

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TM

Rev 1.0

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3C080B

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TM

Rev 1.0

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3C080B

CQV16100

CQV1690

CQV1680

CQV1670

CQV1660

CQV1650

CQV1640

CQV1630

WRITE CLOCK (WCLK)

DATA IN (D79 - 0)

FIRST WORD FALL THROUGH/

SERIAL DATA INPUT (FWFT/SDI)

READ CLOCK (RCLK)

DATA OUT (Q79 - 0)

PROGRAMMABLE ALMOST-

EMPTY ( )

PARTIAL RESET ( ) MASTER RESET ( )

Block Diagram of Single Channel Queue

65,536 x 80 / 32,768 x 80 / 16,384 x 80 / 8,192 x 80 / 4,096 x 80 / 2,048 x 80 / 1,024 x 80 / 512 x 80

JTAG CLOCK (TCLK)

PRST MRST

PRAE

RETRANSMIT ( )

RET

OUTPUT ENABLE ( )

OE

READ ENABLE ( )

AREN

EMPTY FLAG / OUTPUT READY

( / )

QRDY

EMPTY

FULL FLAG / INPUT READY

( / )

FULL DRDY

PROGRAMMABLE ALMOST-

FULL ( )

PRAF

READ CHIP SELECT ( )

RCS

HALF-FULL FLAG ( )

HALF

JTAG RESET ( )

TRST

JTAG MODE (TMS)

(TDO)

(TDI)

INTERSPERSED PARITY (IPAR)

SERIAL IN CLOCK (SCLK)

LOAD ( )

LOAD

WRITE ENABLE ( )

WEN

SERIAL DATA ENABLE ( )

SDEN

(SFM)

(PFS0)

(PFS1) )RETLZ(

SWTICHING CONTROL REGISTER

WRITE ENABLE ( )

AWEN

READ ENABLE ( )REN

SWITCHING CONTROL REGISTER

Figure 5. Single Device Configuration Signal Flow Diagram

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TM

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3C080B

Offset Register

Write Control

Logic

Write Pointer

SRAM

Input Register Output Register

Flag Logic

Output

Buffer

Ch 0, Ch 1, Ch 2, Ch 3,

Ch 4, Ch 5, Ch 6, Ch 7,

Ch 8, Ch 9, Ch 10, Ch 11,

Ch 12, Ch 13, Ch 14, Ch 15

Read Control

Logic Reset

FWFT/

SDI

IPAR LOAD SDEN

WCLK

FWFT/SDI

SFM

PFS1

PFS0

PRAF

/

FULL DRD

Y

PRAE

HALF

EMPTY QRDY

/

OE

MRST PRST

RCLK

RETZ

L

RET REN

WEN

Channel

Switch

Read Pointer

Switching

Control

Register

AWEN AREN

Ch 0, Ch 1, Ch 2, Ch 3,

Ch 4, Ch 5, Ch 6, Ch 7,

Ch 8, Ch 9, Ch 10, Ch 11,

Ch 12, Ch 13, Ch 14, Ch 15

RCS

SCLK

Figure 6. ChannelQ Device Architecture

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TM

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Q36 Q38 Q52 Q55 Q58 Q72 Q75 Q78 D78 D75 D72 D58 D55 D52 D38 D36

Q35 Q37 Q51 Q54 Q57 Q71 Q74 Q77 D77 D74 D71 D57 D54 D51 D37 D35

Q34 Q33 Q50 Q53 Q56 Q70 Q73 Q76 D76 D73 D70 D56 D53 D50 D33 D34

Q32 Q31 Q30 Q39 Q59 Q79 GND TCK TDI TDO TMS D59 D30 D31 D32

Q18 Q17 Q16 Q19 GND VCC GND VCC GND VCC GND D79 D39 D16 D17 D18

Q15 Q14 Q13 VCC GND VCC GND VCC GND VCC GND VCC D19 D13 D14 D15

Q12 Q11 Q10 VCC GND VCC GND VCC GND VCC GND VCC GND D10 D11 D12

Q68 Q67 Q66 VCC GND VCC GND VCC GND VCC GND VCC GND D66 D67 D68

Q65 Q64 Q63 VCC GND VCC GND VCC GND VCC GND VCC D69 D63 D64 D65

Q62 Q61 Q60 GND VCC D49 D60 D61 D62

Q48 Q47 Q46 Q49 GND VCC GND VCC GND GND D29 DC D46 D47 D48

Q45 Q44 Q43 Q29 Q9 GND GND PFS1 PFS0 GND D9 SCLK D43 D44 D45

Q42 Q41 Q40 SFM IPAR DC FWFT/SDI D40 D41 D42

Q28Q27Q20Q6Q3Q0 D0D3D6D20D27D28

Q26Q23Q21Q7Q4Q1 D1D4D7D21D23D26

Q25Q24Q22Q8Q5Q2 RCLK WCLKD2D5D8D22D24D25

TRST

Q69 GND VCC GND VCC GND VCC

RET RETZL LOADHALF SDENGND

RCS PRAE MRST PRST

WEN

PRAFEMPTYOE

REN FULL

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

12345678910111213141516

A1 BALL PAD CORNER

AWEN

AREN

PBGA -256 (Order code: BB)

Top View

Figure 7. Device Pin Out

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Q

TM

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3C080B

Pin # Pin Name Pin Symbol Input/Output Description

P9 Master Reset MRST Input

Master Reset is required to initialize Write and Read

pointers to the first position of the queue by setting

MRST low. In Standard mode, FULL and PRAF will go

high; EMPTY and PRAE will go low. In FWFT mode,

DRD

Y

will go low and QRDY will go high. PRAF

and PRAE will go to the same state as Standard mode. In

both modes, all data outputs will go low. Previous

programmed configurations will not be maintained.

P10 Partial Reset PRST Input

Partial Reset is required to initialize Write and Read

pointers to the first position of the queue by setting PRST

low. In Standard mode, FULL and PRAF will go high;

EMPTY and PRAE will go low. In FWFT mode,

DRD

Y

will go low and QRDY will go high. PRAF and

PRAE will go to the same state as Standard mode. In

both modes, all data outputs will go low. Previous

programmed configurations will be maintained.

T10 Write Clock WCLK Input

Writes data into queue during low to high transitions of

WCLK if WEN is set to low.

R10 Write Enable WEN Input

Controls write operation into queue or offset registers

during low to high transition of WCLK.

N12 Load Enable LOAD Input

During Master Reset, set LOAD low to select parallel

programming or one of eight default offset values. Set

LOAD high to select serial programming or one of eight

default offset values. After Master Reset, LOAD controls

write/read to/from offset registers during low to high

transition of WCLK/RCLK respectively. Use in

conjunction with WEN /REN .

M9 Default

Programming 1 PFS1 Input

During Master Reset, select one of eight default offset

values. Use in conjunction with LOAD and PFS0.

M10 Default

Programming 0 PFS0 Input

During Master Reset, select one of eight default offset

values. Use in conjunction with LOAD and PFS1.

P11,R11,T11,P12,R12 Ch 0 D4-0

T12,P13,R13,T13,M12 Ch 1 D9-5

G14,G15,G16,F14,F15 Ch 2 D14-10

F16,E14,E15,E16,F13 Ch 3 D19-15

P14,R14,T14,R15,T15 Ch 4 D24-20

T16,R16,P15,P16,L12 Ch 5 D29-25

D14,D15,D16,C15,C16 Ch 6 D34-30

B16,A16,B15,A15,E13 Ch 7 D39-35

N14,N15,N16,M14,M15 Ch 8 D44-40

M16,L14,L15,L16,K13 Ch 9 D49-45

C14,B14,A14,C13,B13 Ch 10 D54-50

A13,C12,B12,A12,D13 Ch 11 D59-55

K14,K15,K16,J14,J15 Ch 12 D64-60

J16,H14,H15,H16,J13 Ch 13 D69-65

C11,B11,A11,C10,B10 Ch 14 D74-70

A10,C9,B9,A9,E12 Ch 15 D79-75

Input 80 - bit wide input data bus.

Table 1. Pin Descriptions

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TM

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3C080B

Pin # Pin Name Pin Symbol Input/Output Description

T8 Read Clock RCLK Input

Reads data from queue during low to high transitions of

RCLK if REN is set to low.

T7 Read Enable REN Input

Controls read operation from queue or offset registers

during low to high transition of RCLK.

P7 Read Chip Select RCS Input

Setting RCS low during the low to high transition of

RCLK activates the data output drivers. Setting RCS

high during the low to high transition of RCLK deactivates

the data output drivers. OE must be set low when using

RCS to control the state of the drivers.

R7 Output Enable OE Input

Setting OE low activates the data output drivers. Setting

OE high deactivates the data output drivers (High-Z).

P6,R6,T6,P5,R5 Ch 0 Q4-0

T5,P4,R4,T4,M5 Ch 1 Q9-5

G3,G2,G1,F3,F2 Ch 2 Q14-10

F1,E3,E2,E1 ,E4 Ch 3 Q19-15

P3,R3,T3,R2,T2 Ch 4 Q24-20

T1,R1,P2,P1,M4 Ch 5 Q29-25

D3,D2,D1,C2,C1 Ch 6 Q34-30

B1,A1,B2,A2,D4 Ch 7 Q39-35

N3,N2,N1,M3,M2 Ch 8 Q44-40

M1,L3,L2,L1,L4 Ch 9 Q49-45

C3,B3,A3,C4,B4 Ch 10 Q54-50

A4,C5,B5,A5,D5 Ch 11 Q59-55

K3,K2,K1,J3,J2 Ch 12 Q64-60

J1,H3,H2,H1,K4 Ch 13 Q69-65

C6,B6,A6,C7,B7 Ch 14 Q74-70

A7,C8,B8,A8,D6 Ch 15 Q79-75

Output 80 - bit wide output data bus.

N11

First Word Fall

Through/Serial

Data Input

FWFT/SDI Input

Selects FWFT timing or Standard timing mode during

Master Reset. After Master Reset, if serial programming

is selected ( LOAD = high), FWFT/SDI is used as the

serial data input for the offset registers. Serial data is

written during the low to high transition of WCLK. Use in

conjunction with SDEN .

M13 Serial Clock SCLK Input

During serial programming, SCLK is used to program

offset values through SDI.

N13 Serial Data Input

Enable SDEN Input

If serial programming is selected, setting SDEN and

LOAD low enables serial data input to be written into

offset registers during the low to high transition of SCLK.

N4 Retransmit RET Input

Data previously read from the queue can be retransmitted

by asserting RET pin at the low to high transition of

RCLK for a retransmit operation. Retransmit initializes

the Read pointer to zero. Hence, all re-reads will always

start from the physical 0th (Read pointer = zero) location of

the queue.

Table 1. Pin Descriptions (Continued)

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Channel

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TM

Rev 1.0

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3C080B

Pin # Pin Name Pin Symbol Input/Output Description

N5 Zero Latency

Retransmit RETZ

L

Input

During Master Reset, set RETZ

L

low to select zero

latency retransmit or RETZ

L

high to select normal

latency retransmit.

T9 Full/Data Input

Ready Flag FULL / DRD

Y

Output

Queue is full when FULL goes low during the low to

high transition of WCLK. This prohibits further

writes into the queue. In FWFT mode, queue is full

when DRD

Y

goes high during low to high transition

of WCLK. This prohibits further writes into the

queue.

R8

Empty/Data

Output Ready

Flag

EMPTY / QRDY Output

Queue is empty when EMPTY goes low during the

low to high transition of RCLK. This prohibits further

reads from the queue. In FWFT mode, queue is empty

when QRDY goes high during the low to high

transition of RCLK. This prohibits further reads from

the queue.

N8 Interspersed

Parity IPAR Input

During Master Reset, set IPAR low to select 10-bit

parallel programming mode or IPAR high to select 8-

bit parallel programming mode.

N6

Synchronous

Partial Flag

Mode

SFM Input

During Master Reset, set SFM high to select

Synchronous Partial Flag mode or SFM low to select

Asynchronous Partial Flag mode.

R9 Almost Full PRAF Output

Queue is almost full when PRAF goes low during the

low to high transition of WCLK. Default (Full-offset)

or programmed offset values determine the status of

PRAF .

P8 Almost Empty PRAE Output

Queue is almost empty when PRAE goes low during

the low to high transition of RCLK. Default

(Empty+offset) or programmed offset values

determine the status of PRAE .

N10 Half Full HALF Output

Queue is more than half full when HALF goes low.

Triggered by both WCLK and RCLK.

L13, N7 Don’t Care DC N/A This pin can be tied high or low, cannot be left open.

E6, E8, E10, F4,

F6, F8, F10, F12,

G4, G6, G8, G10,

G12, H4, H6, H8,

H10, H12, J4, J6,

J8, J10, J12, K6,

K8, K10, K12,

L6, L8

Power Vcc N/A 3.3V power supply.

D7, E5, E7, E9,

E11, F5, F7, F9,

F11, G5, G7, G9,

G11, G13, H5,

H7, H9, H11,

H13, J5, J7, J9,

J11, K5, K7, K9,

K11, L5, L7, L9,

L11, M7, M8,

M11, N7

Ground GND N/A 0V Ground.

Table 1. Pin Description (Continued)

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Pin # Pin Name Pin Symbol Input/Output Description

D8 JTAG Clock TCK Input

Clock for JTAG function. TMS and TDI are loaded during

low to high transitions of TCK. TDO is loaded during

high to low transitions of TCK.

D10 JTAG Reset TRST Input

Reset control for JTAG function. An asynchronous input

for the JTAG controller.

D12 JTAG Mode

Selection TMS Input

Mode select for JTAG function. TMS bits are loaded

serially during low to high transitions of the TCK.

D9 Test Data Input TDI Input Serial data input for JTAG function. TDI is loaded during

low to high transitions of the TCK.

D11 Test Data

Output TDO Output

Serial data output for JTAG function. TDO is unloaded

during high to low transitions of the TCK. During SHIFT-

DR and SHIFT-IR operations, TDO bus will be tri-stated.

L10

Switching

Control Register

Write Enable

AWEN Input

Setting AWEN low causes the value on the input data bus

to be written into the switching control register during the

low to high transition of WCLK, provided WEN is held

high at the same transition.

M6

Switching

Control Register

Read Enable

AREN Input

Setting AREN low allows reading from the switching

control register during the low to high transition of RCLK,

provided REN is held high at the same transition.

Table 1. Pin Description (Continued)

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Symbol Rating Com’l & Ind’l Unit

VTERM Terminal Voltage with

respect to GND -0.5 to + 4.5 V

TSTG Storage Temperature -55 to +125 °C

IOUT DC Output Current -50 to +50 mA

NOTES:

Absolute Max Ratings are for reference only. Permanent damage to the device may

occur if extended period of operation is outside this range. Standard operation should

fall within the Recommended Operating Conditions.

Table 2. Absolute Maximum Ratings

CQV16100, CQV1690, CQV1680, CQV1670,

CQV1660, CQV1650, CQV1640, CQV1630

Commercial

Clock = 6ns, 7.5ns, 10ns

Industrial

Clock = 7.5ns, 10ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

Recommended Operating Conditions

Vcc Supply Voltage Com’l / Ind’l 3.15 3.3 3.45 3.15 3.3 3.45 V

GND Supply Voltage 0 0 0 0 0 0 V

VIH Input High Voltage Com’l /

Ind’l 2.0 - 5.5 2.0 - 5.5 V

VIL Input Low Voltage Com’l /

Ind’l - - 0.8 - - 0.8 V

TA Operating Temperature

Commercial 0 - 70 0 - 70 °C

TA Operating Temperature

Industrial -40 - 85 -40 - 85 °C

DC Electrical Characteristics

ILI(1) Input Leakage Current (any

input) -10 - 10 -10 - 10 µA

ILO Output Leakage Current -10 - 10 -10 - 10 µA

VOH Output Logic “1” Voltage,

IOH=-2mA 2.4 - - 2.4 - - V

VOL Output Logic “0” Voltage, IOL

= 8mA - - 0.4 - - 0.4 V

Power Consumption

Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA

Icc2(4) Standby Current - - 15 - - 15 mA

Table 3. DC Specifications

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Capacitance at 100MHz Ambient Temperature (25°C)

Symbol Parameter Conditions Max. Unit

CIN(2) Input Capacitance VIN= 0V 10 pF

COUT(2,4) Output Capacitance VOUT= 0V 10 pF

NOTES:

1. Measurement with 0.4<=VIN<=Vcc

2. With output tri-stated ( OE = High)

3. Icc(1,2) is measured with WCLK and RCLK at 20 MHz

4. Design simulated, not tested.

Table 3. DC Specifications (Continued)

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Commercial Commercial & Industrial

CQV16100-6

CQV1690-6

CQV1680-6

CQV1670-6

CQV1660-6

CQV1650-6

CQV1640-6

CQV1630-6

CQV16100-7.5

CQV1690-7.5

CQV1680-7.5

CQV1670-7.5

CQV1660-7.5

CQV1650-7.5

CQV1640-7.5

CQV1630-7.5

CQV16100-10

CQV1690-10

CQV1680-10

CQV1670-10

CQV1660-10

CQV1650-10

CQV1640-10

CQV1630-10

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fS Clock Cycle Frequency - 166 - 133 - 100 MHz

tA Data Access Time 1 4 2 5 2 6.5 ns

tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - ns

tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - ns

tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - ns

tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - ns

tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - ns

tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - ns

tDS Data Set-up Time 2.0 - 2.5 - 3.5 - ns

tDH Data Hold Time 0.5 - 0.5 - 0.5 - ns

tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - ns

tENH Enable Hold Time 0.5 - 0.5 - 0.5 - ns

tRST Reset Pulse Width(1) 8 - 10 - 10 - ns

tRSTS Reset Set-up Time 10 - 15 15 - ns

tRSTR Reset Recovery Time 10 - 10 - 10 - ns

tRSTF Reset to Flag and Output Time - 10 - 15 - 15 ns

tOLZ Output Enable to Output in Low-Z(1) 0 - 0 - 0 - ns

tOE Output Enable to Output Valid 2 4 2 6 2 6 ns

tOHZ Output Enable to Output in High-Z(1) 2 4 2 6 2 6 ns

tFULL Write Clock to Full Flag - 4 - 5 - 6.5 ns

tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 ns

tPRAFS Write Clock to Synchronous Almost-Full

Flag - 4 - 5 - 6.5 ns

tPRAES Read Clock to Synchronous Almost-

Empty Flag - 4 - 5 - 6.5 ns

tRCSS RCS Setup Time 2 - 3.5 - 3.5 - ns

tRCSH RCS Hold Time 0.5 - 0.5 - 0.5 - ns

tRCSLZ RCLK to Active from High-Z 2 4 1 6.5 1 6.5 ns

tRCSHZ RCLK to High-Z 2 4 1 6.5 1 6.5 ns

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Table 4. AC Electrical Characteristics

Commercial Commercial & Industrial

CQV16100-6

CQV1690-6

CQV1680-6

CQV1670-6

CQV1660-6

CQV1650-6

CQV1640-6

CQV1630-6

CQV16100-7.5

CQV1690-7.5

CQV1680-7.5

CQV1670-7.5

CQV1660-7.5

CQV1650-7.5

CQV1640-7.5

CQV1630-7.5

CQV16100-10

CQV1690-10

CQV1680-10

CQV1670-10

CQV1660-10

CQV1650-10

CQV1640-10

CQV1630-10

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

tSKEW1

Skew time between Read Clock &

Write Clock for Full Flag / Empty

Flag

4 - 5 - 7 - ns

tSKEW2 Skew time between Read Clock &

Write Clock for PRAE & PRAF 6 - 7 - 10 - ns

tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - ns

tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - ns

tRETS Retransmit Setup Time 2.5 - 3.5 - 3.5 - ns

tHALF Clock to HALF - 12 - 12.5 - 16 ns

tPRAFA Write Clock to Asynchronous

Programmable Almost-Full Flag - 12 - 12.5 - 16 ns

tPRAEA Read Clock to Asynchronous

Programmable Almost-Empty Flag - 12 - 12.5 - 16 ns

NOTES:

1. Design simulated, not tested.

Table 4. AC Electrical Characteristics (Continued)

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Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load, clock = 6ns, 7.5ns, 10ns Refer to Figure 8

Table 5. AC Test Condition

V

cc

/

2

50 Ω

Z0 = 5 0 ΩI/O

Figure 8. AC Test Load

for clock = 6ns, 7.5ns, 10ns

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Pin Functions

MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting

MRST low. In Standard mode, FULL and PRAF will go high, EMPTY and PRAE will go low. In

FWFT mode, DRD

Y

will go low and QRDY will go high. PRAF and PRAE will go to the same state

as Standard mode. In both modes, all data outputs will go low, and previous programmed configurations

will not be maintained.

PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting

PRST low. In Standard mode, FULL and PRAF will go high. EMPTY and PRAE will go low. In

FWFT mode, DRD

Y

will go low and QRDY will go high. PRAF and PRAE will go to the same state

as Standard mode. In both modes, all data outputs will go low, and previously programmed

configurations will be maintained.

WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes

FULL /DRD

Y

and PRAF flags. WCLK and RCLK are independent of each other.

WEN Controls write operation into queue or offset registers during low to high transition of WCLK.

LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values.

Set LOAD high to select serial programming or one of eight default offset values. After Master Reset,

LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK

respectively for parallel programming. Use in conjunction with WEN /REN . During programming of

offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to

enable serial loading of offset registers together with SDEN . Refer to Figure 9 for details.

PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0.

Refer to Table 11 for details.

PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1.

Refer to Table 11 for details.

D79..0 80 - bit wide input data bus.

RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the

EMPTY /QRDY and PRAE flags. RCLK and WCLK are independent of each other.

REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances

the Read pointer of the queue.

RCS

Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting

RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be

set low when using RCS to control the state of the drivers.

OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers

(High-Z). OE does not control advancement of Read pointer.

D79..0 80 - bit wide output data bus.

FWFT/SDI Selects First Word Fall Through timing or Standard timing mode during Master Reset. After Master

Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for

the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction

with SDEN . In FWFT mode, DRD

Y

and QRDY is used instead of FULL and EMPTY . In Standard

mode, FULL and EMPTY is used instead of DRD

Y

and QRDY . Refer to Table 8 & 9 for all flags

status.

SCLK During serial programming, SCLK is used to program offset values through SDI.

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Pin Functions (Continued)

SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written

into offset registers during the low to high transition of SCLK. During serial programming, PRAF

and PRAE flags status is invalid. Refer to Figure 9 for details.

RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high

transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence,

all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer

to Diagram 9 & 10 for details.

RETZL During Master Reset, set RETZ

L

low to select zero latency retransmit. Set RETZ

L

high to select

normal latency retransmit.

FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK.

This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT

mode, queue is full when DRD

Y

goes low during the low to high transition of WCLK. This

prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8

& 9 for behavior of FULL / DRD

Y

.

EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of

RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In

FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK.

This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to

Table 8 & 9 for behavior of EMPTY / QRDY .

IPAR During Master Reset, set IPAR low to select 10-bit parallel programming mode or set IPAR high to

select 8-bit parallel programming mode. In 10-bit mode, 10-bit wide data input / output bus width is

used for storing / fetching offset values. In 8-bit mode, 8-bit wide data input / output bus is used for

storing / fetching offset values.

SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select

Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to

WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of

PRAF and de-assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of

PRAF .

PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default

(Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 & 9 for

behavior of PRAF .

PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default

(Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 & 9

for behavior of PRAE .

Pin Functions (Continued)

HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK.

Queue is less than half full when HALF goes high during low to high transition of RCLK when.

Refer to Table 8 & 9 for details.

AWEN Setting AWEN low causes the value on the input data bus to be written into the switching control

register during the low to high transition of WCLK, provided WEN is held high at the same

transition.

AREN Setting AREN low allows reading from the switching control register during the low to high

transition of RCLK, provided REN is held high at the same transition.

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LOAD WEN REN AWEN AREN SDEN WCLK RCLK SCLK

CQV16100

CQV1690

CQV1680

CQV1670

CQV1660

CQV1650

CQV1640

CQV1630

Selection / Sequence

0 0 1 1 1 1

X X

Parallel write to offset

registers:

Empty Offset

Full Offset

Parallel write to

registers:

1. PRAE

2. PRAF

0 1 0 1 1 1 X

X

Parallel read from offset

registers:

Empty Offset

Full Offset

Parallel read

from registers:

1. PRAE

2. PRAF

0 1 1 1 1 0 X X

Serial shift into registers:

32 bits for the CQV16100

30 bits for the CQV1690

28 bits for the CQV1680

26 bits for the CQV1670

24 bits for the CQV1660

22 bits for the CQV1650

20 bits for the CQV1640

18 bits for the CQV1630

1 bit for each rising WCLK edge

Starting with Empty Offset (Low Byte)

Ending with Full Offset (High Byte)

X 1 1 1 1 1 X X X

No Operation

X 1 X 0 X X

X X Write Switching Control Register

X X 1 X 0 X X

X

Read Switching Control Register

1 0 X X X X

X X Write Memory

1 X 0 X X X X

X

Read Memory

1 1 1 1 1 X X X X No Operation

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Figure 9. Programmable Flag Offset Programming Sequence

(CQV16100, CQV1690, CQV1680, CQV1670, CQV1660, CQV1650, CQV1640 and CQV1630)

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Device PRAF Programming (bits) PRAE Programming (bits)

D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR

CQV16100 D/Q17 –10 & D/Q7 – 0 IPAR D/Q17 – 10 & D/Q7 – 0 IPAR

D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR

CQV1690 D/Q16 – 10 & D/Q7 – 0 IPAR D/Q16 – 10 & D/Q7 – 0 IPAR

D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR

CQV1680 D/Q15 – 10 & D/Q7 – 0 IPAR D/Q15 – 10 & D/Q7 – 0 IPAR

D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR

CQV1670

D/Q14 – 10 & D/Q7 – 0 IPAR D/Q14 – 10 & D/Q7 – 0 IPAR

D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR

CQV1660

D/Q13 – 10 & D/Q7 – 0 IPAR D/Q13 – 10 & D/Q7 – 0 IPAR

D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR

CQV1650 D/Q12 – 10 & D/Q7 – 0 IPAR D/Q12 – 10 & D/Q7 – 0 IPAR

D/Q9 - 0 Non-IPAR D/Q9 - 0 Non-IPAR

CQV1640

D/Q11 – 10 & D/Q7 – 0 IPAR D/Q11 – 10 & D/Q7 – 0 IPAR

D/Q8 - 0 Non-IPAR D/Q8 - 0 Non-IPAR

CQV1630 D/Q10 & D/Q7 – 0 IPAR D/Q10 & D/Q7 – 0 IPAR

Table 6. Parallel Offset Register Data Mapping Table

Device Standard Mode FWFT Mode

CQV16100 65,536 x 80 65,537 x 80

CQV1690 32,768 x 80 32,769 x 80

CQV1680 16,384 x 80 16,385 x 80

CQV1670 8,192 x 80 8,193 x 80

CQV1660 4,096 x 80 4,097 x 80

CQV1650 2,048 x 80 2,049 x 80

CQV1640 1,024 x 80 1,025 x 80

CQV1630 512 x 80 513 x 80

Table 7. Maximum Depth of Queue for Standard and FWFT Mode

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Data Width

Non-Interspersed Parity

Interspersed Parity

Data Width

Non-Interspersed Parity

Interspersed Parity

PRAE

PRAF

1st Cycle

2nd Cycle

13 12 11 10 9875316420

75316420

8

9101112

13

12

11

10

98

9875316420

75316420

D/Q18

D/Q19D/Q~ D/Q~D/Q~

D/Q79 D/Q17 D/Q15 D/Q13 D/Q11 D/Q9

D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0

D/Q7 D/Q5 D/Q3 D/Q1

D/Q17 D/Q15 D/Q13 D/Q11 D/Q9

D/Q16 D/Q14 D/Q12 D/Q10 D/Q8 D/Q6 D/Q4 D/Q2 D/Q0

D/Q7 D/Q5 D/Q3 D/Q1

D/Q18D/Q19D/Q~ D/Q~D/Q~D/Q79

15 14

1415

15 14

1415

CQV16100, CQV1690, CQV1680, CQV1670, CQV1660, CQV1650, CQV1640, CQV1630

Parallel Offset Write/Read Cycles

# of Bits for Offset Registers

16 bits for CQV16100

15 bits for CQV1690

14 bits for CQV1680

13 bits for CQV1670

12 bits for CQV1660

11 bits for CQV1650

10 bits for CQV1640

9 bits for CQV1630

Note: Don’t Care applies to all unused bits

Figure 10. Parallel Offset Write/Read Cycles Diagram (Continued)

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CQV16100 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 32,768 H H H H H

32,769 to [65,536-(x+1)] H H L H H

(65,536 –x(2)) to 65,535 H L L H H

65,536 L L L H H

CQV1690 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 16,384 H H H H H

16,385 to [32,768-(x+1)] H H L H H

(32,768 –x(2)) to 32,767 H L L H H

32,768 L L L H H

CQV1680 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 8,192 H H H H H

8,193 to [16,384-(x+1)] H H L H H

(16,384 –x(2)) to 16,383 H L L H H

16,384 L L L H H

CQV1670 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 4,096 H H H H H

4,097 to [8,192-(x+1)] H H L H H

(8,192 -x(2)) to 8,191 H L L H H

8,192 L L L H H

CQV1660 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 2,048 H H H H H

2,049 to [4,096-(x+1)] H H L H H

(4,096 –x(2)) to 4,095 H L L H H

4,096 L L L H H

CQV1650 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 1,024 H H H H H

1,025 to [2,048-(x+1)] H H L H H

(2,048 -x(2)) to 2,047 H L L H H

2,048 L L L H H

Table 8. Status Flags (Standard Mode)

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CQV1640 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 512 H H H H H

513 to [1,024-(x+1)] H H L H H

(1,024 –x(2)) to 1,023 H L L H H

1,024 L L L H H

CQV1630 FULL PRAF HALF PRAE EMPTY

0 H H H L L

1 to y(1) H H H L H

(y+1) to 256 H H H H H

257 to [512-(x+1)] H H L H H

(512 –x(1)) to 511 H L L H H

512 L L L H H

NOTES:

1. See Table 11 for values x, y.

Table 8. Status Flags (Standard Mode)(Continued)

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CQV16100 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 32,769 L H H H L

32,770 to [65,537-(x+1)] L H L H L

(65,537 –x) to 65,536 L L L H L

65,537 H L L H L

CQV1690 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 16,385 L H H H L

16,386 to [32,769-(x+1)] L H L H L

(32,769 –x) to 32,768 L L L H L

32,769 H L L H L

CQV1680 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 8,193 L H H H L

8,194 to [16,385-(x+1)] L H L H L

(16,385 -x) to 16,384 L L L H L

16,385 H L L H L

CQV1670 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 4,097 L H H H L

4,098 to [8,193-(x+1)] L H L H L

(8,193-x) to 8,192 L L L H L

8,193 H L L H L

CQV1660 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 2,049 L H H H L

2,050 to [4,097-(x+1)] L H L H L

(4,097 -x) to 4,096 L L L H L

4,097 H L L H L

CQV1650 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 1,025 L H H H L

1,026 to [2,049-(x+1)] L H L H L

(2,049 -x) to 2,048 L L L H L

2,049 H L L H L

Table 9. Status Flags (FWFT Mode)

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CQV1640 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 513 L H H H L

514 to [1,025-(x+1)] L H L H L

(1,025 -x) to 1,024 L L L H L

1,025 H L L H L

CQV1630 DRDY PRAF HALF PRAE QRDY

0 L H H L H

1 to y+1 L H H L L

(y+2) to 257 L H H H L

258 to [513-(x+1)] L H L H L

(513 -x) to 512 L L L H L

513 H L L H L

Table 9. Status Flags (FWFT Mode)(Continued)

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CQV1640

CQV1630

LOAD PFS1 PFS0

Default Offsets x, y(1)

0 0 0 127

0 0 1 255

0 1 0 511

0 1 1 63

1 0 0 31

1 0 1 7

1 1 0 15

1 1 1 3

CQV1640

CQV1630

LOAD PFS1 PFS0

Program Mode

1 X X Serial

0 X X Parallel

CQV1680

CQV1670

CQV1660

CQV1650

LOAD PFS1 PFS0

Default Offsets x, y(1)

0 0 0 127

0 0 1 255

0 1 0 511

0 1 1 63

1 0 0 1,023

1 0 1 15

1 1 0 31

1 1 1 7

CQV1680

CQV1670

CQV1660

CQV1650

LOAD PFS1 PFS0

Program Mode

1 X X Serial

0 X X Parallel

NOTES:

1. y = PRAE offset, x = PRAF offset

Table 10. Default Programmable Flag Offsets

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CQV16100

CQV1690

LOAD PFS1 PFS0

Default Offsets x, y(1)

0 0 0 127

0 0 1 8,191

0 1 0 16,383

0 1 1 4,095

1 0 0 1,023

1 0 1 511

1 1 0 2,047

1 1 1 255

CQV16100

CQV1690

LOAD PFS1 PFS0

Program Mode

1 X X Serial

0 X X Parallel

NOTES:

1. y = PRAE offset, x = PRAF offset

Table 10. Default Programmable Flag Offsets (Continued)

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JTAG Interface

Standard JTAG interface is used for boundary scan purposes. For a complete description, please refer to the IEEE Standard Test

Access Port Specification (IEEE STD.1149.1 – 1990)

JTAG TIMING SPECIFICATIONS

t2t1t4

t3

tTCK

tDO

TDO

t5

t6

tDS tDH

TRST

TDO

TMS/TDI

TCK

Figure 11. Standard JTAG Timing

CQV16100

CQV1690

CQV1680

CQV1670

CQV1660

CQV1650

CQV1640

CQV1630

Parameter Symbol

Test

Conditions Min. Max. Units

System Interface Parameters

Data Output tDO = Max - 5 50 ns

Data Output Hold tDOH - 5 - ns

tDS trise = 3ns 30 -

Data Input tDH tfall = 3ns 30 - ns

JTAG AC Electrical Characteristics

JTAG Clock Input Period tTCK - 100 - ns

JTAG Clock HIGH tTCKHIGH (t2) - 40 - ns

JTAG Clock Low tTCKLOW (t1) - 40 - ns

JTAG Clock Rise Time tTCKRise (t4) - - 5 ns

JTAG Clock Fall Time tTCKFall (t3) - - 5 ns

JTAG Reset tRST (t5) - 50 - ns

JTAG Reset Recovery tRSR (t6) - 50 - ns

Table 12. JTAG AC Electrical Characteristics

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JTAG BLOCK DIAGRAM

HBA’s FlexQ™ offers IEEE Std. 1149.1-1990 standard JTAG interface to facilitate system debugging in all PBGA packages.

STANDARD JTAG INTERFACE ELEMENTS:

1. TAP – TEST ACCESS PORT

2. TAPCNTL – TAP CONTROLLER

3. IR – INSTRUCTION REGISTER

4. DR – DATA REGISTER

TAP

Controller

Instruction Decode

Instruction Register

Boundary Scan Reg.

Device ID Reg.

Bypass Reg.

TDO

TDI

TMS

TCLK

TRST DR

IR

Figure 12. Boundary Scan Architecture Diagram

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1. TAP The basic ports to access the JTAG function. That includes four general input ports: TRST ,

TCK, TMS, and TDI, and one general output port: TDO.

2. TAPCNTL A finite state machine that provide instructions to the Instruction and Data Registers for data

capture and update. Individual states are explained blow.

Test-Logic

Reset

Run-Test /

Idle

Select-DR-

Scan

Select-IR-

Scan

Capture-DR Capture-IR

Shift-DR Shift-IR

Exit1-DR Exit1-IR

Pause-DR Pause-IR

Exit2-DR Exit2-IR

Update-DR Update-IR

Input = TMS

1

01

011

11

00 00

00

11

00 00

11

00

101

0

Figure 13. TAP Controller State Diagram

• Capture-IR Data are captured in parallel into the instruction register.

• Capture-DR Data are captured in parallel into the data register.

• SHIFT-IR LSB of the instruction register is shift in serially during a low to high transition of the

TCK through TDI/TDO path

• SHIFT-DR LSB of the data register is shift in serially during a low to high transition of the TCK

through TDI/TDO path.

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3. INSTRUCTION

REGISTER

A 4 - bit instruction register that is shifted serially at the rising edge of TCLK. The instruction is

latched through the least significant bits of the nearest serial OUTPUT.

Hex Value Instruction Function

0 x 00 EXTEST Select Boundary Scan Register

0 x 02 IDCODE Select Chip Identification data register

0 x 01 SAMPLE/PRELOAD Select Boundary Scan Register

0 x 03 HI-Z JTAG

0 x 0F BYPASS Select Bypass Register

Table 13. JTAG Instruction Register Decoding Table

• EXTEST An instruction to facilitate external circuitry and board level interconnection verification.

• IDCODE An instruction to read out manufacture’s identification, part number and version number.

• SAMPLE/

PRE-LOAD

An instruction to allow snapshots of data flowing through the system pins. SAMPLE

instruction MUST be executed prior to the selection of Boundary Scan test.

• HIGH Z An Instruction to place all output pins to high impedance state.

• BYPASS An Instruction to allow direct serial data shifting through TDI and TDO without any device

operation.

4. DATA REGISTER There are three data registers, Device ID register, BYPASS register, and Boundary Scan register.

These parallel-connected registers are access through the common serial input and the common

serial output.

• Device ID

Register

A 32-bit register that contains the specific manufacturer, part number and version

number.

• UPDATE-IR To shift Instruction Register Data to the parallel outputs. Instruction Register Data can

be accessed through the internal bus.

• UPDATE-DR To shift Data Register Data to the parallel outputs. Data Register Data can be accessed

through the internal bus.

• EXIT1-IR/

EXIT2-IR

A transition state that terminates the scanning process. All Instruction Register data

selected will retain their previous instruction state.

• EXIT1-DR/

EXIT2-DR

A transition state that terminates the scanning process. All Data Register data selected

will retain their previous data state.

• PAUSE-IR The temporary state to halt all serial shifting process between TDI and TDO. All data

will retain their previous instruction state.

• PAUSE-DR The temporary state to halt all serial shifting process between TDI and TDO. All data

will retain their previous data state.

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31(MSB) 28 27 12 11 1 0(LSB)

Version (4 bits)

0x0

Part Number (16-bit) Manufacturer ID (11-bit)

0x16E

1

Device Part # Field

CQV16100 0 x C050

CQV1690 0 x C056

CQV1680 0 x C055

CQV1670 0 x C054

CQV1660 0 x C053

CQV1650 0 x C052

CQV1640 0 x C051

CQV1630 0 x C057

Table 14. Device ID Register Decode Table

• BYPASS

Register

The data register that allows direct serial data shifting through TDI and TDO without

any device operation.

• BOUNDARY

SCAN Register

The data register that allows the serial writes and read through TDI and TDO.

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Timing Diagrams

tRST

tRSTR

tRSTS

FWFT/SDI

tRSTR

tRSTS

PFS1/PFS0

tRSTS

RETZL

tRSTS

SFM

tRSTS

IPAR

Q79- 0

tRSTF

tRSTS

MRST

REN

WEN

LOAD

RET

SDEN

/EMPTY QRDY

PRAE

PRAF HALF/

/

FULL DRDY

If FWFT = 0, = 1FULL

If FWFT = 1, = 0

DRDY

If FWFT = 1, = 1QRDY

If FWFT = 0, = 0EMPTY

= 0

OE

= 1OE

tRSTS

RSTR

t

AREN

AWEN

RSTR

t

Diagram 1. Master Reset Timing

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tRST

tRSTR

tRSTF

tRSTS

If FWFT = 0, = 1FULL

If FWFT = 1, = 0

DRDY

If FWFT = 1, = 1QRDY

If FWFT = 0, = 0EMPTY

= 0OE

= 1

OE

Q79-0

RET

SDEN

/

EMPTY QRDY

PRAE

PRAF HALF/

/

FULL DRDY

WEN

REN

PRST

tRSTR

tRSTS

AWEN

AREN

Diagram 2. Partial Reset Timing

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DW

i + 1

DW

i

No

Write

No

Write

No

Write

t

WCLK

t

WCLKH

t

WCLKL

t

FULL

t

FULL

t

FULL

t

FULL

t

DS

t

DH

t

DS

t

DH

t

SKEW1

t

RCSS

t

A

t

A

Next Data ReadData Read

WCLK

D

79 - 0

RCLK

Q

79 - 0

FULL

RCS

WEN

12 12

t

ENS

t

ENH

t

ENS

t

ENH

REN

t

RCSLZ

NOTES:

1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL

___________

will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL

__________

will assert 1

or more WCLK cycles.

2. LOAD

___________

= High, OE

______

= Low.

Diagram 3. Write Cycle and Full Flag Timing (Standard Mode)

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DW

1

DW

2

DW

1

Last Word Last Word DW

2

t

RCLK

t

RCLKH

t

RCLKL

t

ENH

t

ENS

t

ENH

t

ENS

t

EMPTY

t

EMPTY

t

EMPTY

t

A

t

A

t

OEN

t

OHZ

t

OLZ

t

OLZ

t

SKEW1

t

ENS

t

ENH

t

ENS

t

ENH

t

ENH

t

ENS

t

DS

t

DH

t

DS

t

DH

t

A

RCLK

Q

79- 0

WCLK

D

79 - 0

OE

WEN

EMPTY

REN

12

No Operation No Operation

NOTES:

1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY

______________

will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY

______________

will assert 1 or

more RCLK cycles.

2. LOAD

___________

= High.

3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.

Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode)

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DW

1

DW

2

DW

1

Last Word Last Word DW

2

t

RCLK

t

RCLKH

t

RCLKL

t

ENH

t

ENS

t

ENH

t

ENS

t

EMPTY

t

EMPTY

t

EMPTY

t

A

t

A

t

OEN

t

OHZ

t

OLZ

t

OLZ

t

SKEW1

t

ENS

t

ENH

t

ENS

t

ENH

t

ENH

t

ENS

t

DS

t

DH

t

DS

t

DH

t

A

RCLK

Q

79 - 0

WCLK

D

79 - 0

OE

WEN

EMPTY

REN

12

NOTES:

1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY

______________

will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY

______________

will assert 1 or

more RCLK cycles.

2. LOAD

___________

= High.

3. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK.

Diagram 5. Read Cycle and Read Chip Select Timing (Standard Mode)

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DW

[y+2]

DW

D

DW

[D-1 ]

DW

[D-x+3]

DW

[D-x+2]

DW

[D-x +1]

DW

[D-x ]

DW

[D-x-1]

DW

[(D-1)/ 2+3]

DW

[(D-1)/2+2]

DW

[(D-1)/ 2+1]

DW

[y+4]

DW

[y+3]

DW

4

DW

3

DW

2

DW

1

312 12

WCLK

D

79 - 0

RCLK

t

ENS

t

DH

t

DS

t

DS

t

DS

t

DS

t

ENH

t

SKEW1

t

SKEW2

1

WEN

2

Q

79 - 0

QRDY

PRAE

HALF

PRAF

DRDY

t

FULL

t

HALF

t

PRAES

t

A

t

EMPTY

Previous Output Register Data

DW

1

REN

RCS

t

RCSS

t

PRAFS

t

RCLZ

NOTES:

1. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY

____________

will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY

____________

will assert 1 or more

RCLK cycles.

2. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE

___________

will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE

___________

will assert 1 or more

RCLK cycles.

3. LOAD

___________

= High, OE

______

= Low.

4. y = PRAE

___________

offset, x = PRAF

___________

offset.

5. D = maximum queue depth. Please refer to Table 7 for Depth.

6. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK

Diagram 6. Write Timing (FWFT Mode)

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DW

1

DW

D

DW

[D-1]

DW

[D-y+2]

DW

[D-y+1]

DW

[D-y-1]

DW

[(D-1)/2+2]

DW

x+3

DW

x+2

DW

x+1

DW

3

DW

2

DW

1

DW

[D-y]

DW

[(D-1)/2+1]

DW

D

t

ENS

t

ENH

t

SKEW1

t

SKEW2

t

DS

t

DH

t

ENS

t

OHZ

t

OE

t

A

t

A

t

A

t

A

t

A

t

A

t

ENS

t

EMPTY

t

PRAES

t

HALF

t

PRAFS

t

FULL

t

FULL

WCLK

WEN

D

79 - 0

RCLK

REN

OE

Q

79 - 0

QRDY

PRAE

HALF

PRAF

DRDY

1212

12

NOTES:

1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY

____________

will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY

____________

will assert 1 or more

WCLK cycles.

2. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF

___________

will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF

___________

will assert 1 or more

WCLK cycles.

3. LOAD

____________

= High, RCS

________

= Low

4. y = PRAE

___________

Offset, x = PRAF

___________

offset.

5. D = maximum queue depth. Please refer to Table 7 for Depth.

Diagram 7. Read Timing (FWFT Mode)

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DW

1

DW

D

DW

[D-1]

DW

[D-y+2]

DW

[D-y+1]

DW

[D-y-1]

DW

[(D-1)/2+2]

DW

x+4

DW

x+3

DW

x+2

DW

3

DW

2

DW

[D-y]

DW

[(D-1)/2+1]

DW

D

t

ENS

t

ENH

t

SKEW1

t

SKEW2

t

DS

t

DH

t

ENS

t

A

t

A

t

A

t

A

t

A

t

ENS

t

EMPTY

t

PRAES

t

HALF

t

PRAFS

t

FULL

t

FULL

WCLK

WEN

D

79 - 0

RCLK

REN

RCS

Q

79 - 0

QRDY

PRAE

HALF

PRAF

DRDY

12

t

RCSHZ

t

RCSS

t

RCSH

t

RCSLZ

NOTES:

1. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY

____________

will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY

____________

will assert 1 or more

WCLK cycles.

2. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF

___________

will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF

___________

will assert 1 or more

WCLK cycles.

3. LOAD

____________

= High, OE

______

= Low.

4. y = PRAE

___________

Offset, x = PRAF

___________

offset.

5. D = maximum queue depth. Please refer to Table 7 for Depth.

Diagram 8. Read Cycle and Read Chip Select Timing (FWFT Mode)

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DWiDWi+1 DW1DW2

RCLK

Q 79- 0

WCLK

tENS tENH tRETS

tAtA

tENS tENH

tA

tSKEW2

tRETS

tENS tENH

tEMPTY

tHALF

tEMPTY

tPRAES

tPRAFS

REN

WEN

RET

EMPTY

PRAE

HALF

PRAF

12

NOTES:

1. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high.

2. OE = Low.

3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.

4. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.

Diagram 9. Retransmit Timing (Standard Mode)

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DW3

DW1

DWiDWi+1 DW2

RCLK

Q 79 - 0

WCLK

tENS tENH tRETS

tA

tSKEW2

tRETS

tENS tENH

tEMPTY

tHALF

tEMPTY

tPRAES

tPRAFS

1

tENH

tA

23

DW4

tAtA

tENS

PRAF

HALF

PRAE

QRDY

RET

WEN

REN

4

12

NOTES:

1. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low.

2. OE = Low.

3. DWi = Words written to the queue after MRST . Where i = 1,2,3… depth.

4. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid.

5. Please refer to Table 7 for Depth.

Diagram 10. Retransmit Timing (FWFT Mode)

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RCLK

Q 79- 0

WCLK

DWiDWi+1 DW1DW2DW3DW4

tRETS

tENS tENH

tSKEW2

tAtAtAtAtA

tENS tENH

tPRAES

tHALF

tPRAFS

WEN

REN

RET

EMPTY

PRAE

HALF

PRAF

123

12

NOTES:

1. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data

will appear on the output.

2. OE = Low; enables data to be read on outputs Q79 – 0.

3. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset.

4. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high

throughout the retransmit setup procedure. Please refer to Table 7 for Depth.

5. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked.

6. RETZL is set Low during MRST .

Diagram 11. Zero Latency Retransmit Timing (Standard Mode)

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RCLK

Q 79 - 0

WCLK

DWiDW i+1 DW1DW2DW3DW4

tRETS

tENS tENH

tSKEW2

tAtAtAtAtA

tENS tENH

tPRAES

tHALF

tPRAFS

DW5

tA

PRAF

HALF

PRAE

QRDY

RET

WEN

REN

12345

NOTES:

1. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid

data will appear on the output.

2. No more than D-2 words maybe written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low

throughout the retransmit setup procedure. Please refer to Table 7 for Depth.

3. OE = Low.

4. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset.

5. There must be at least two words written to the queue before a retransmit operation can be invoked.

6. RETZL is set low during MRST .

Diagram 12. Zero Latency Retransmit Timing (FWFT Mode)

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SCLK

SDI

tENHtENS

tLOADHtLOADS

tDS

offset offset

tENH

tLOADH

tDH

BIT 0 BIT MSB BIT 0 BIT MSB

SDEN

LOAD

PRAE PRAF

*Refer to Table 13

Diagram 13. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode)

CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630

MSB 15 14 13 12 11 10 9 8

Table 13. Reference Table for Diagram 13

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tLOADS

tENS

tLOADH

tENH

tLOADH

tENH

tWCLKH tWCLKL

tWCLK

WCLK

D 79 - 0

offset

tDS tDH tDS tDH

WEN

LOAD

PRAE offset

PRAF

Diagram 14. Parallel Loading of Programmable Flag Registers for (Standard and FWFT Mode)

tLOADS

tENS

tLOADH

tENH

tLOADH

tENH

RCLK

Q 79- 0 Output Register Data

tAtA

offset offset

LOAD

REN

PRAE PRAF

tRCLK

tRCLKH tRCLKL

Diagram 15. Parallel Read of Programmable Flag Registers for (Standard and FWFT Mode)

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tENS tENH

tWCLKH tWCLKL

tWCLK

WCLK

D 79 - 0

Data for Switching

Control Register

tDS tDH

WEN

AWEN

Diagram 16. Programming the Switching Control Register

tENS tENH

RCLK

Q 79- 0 Output Register Data

tA

Switching Control

Register Content

REN

tRCLK

tRCLKH tRCLKL

AREN

Diagram 17. Reading the Switching Control Register

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

tWCLKH tWCLKL

tENHtENS

tSKEW2

tENS tENH

tPRAFS tPRAFS

12 12

D - ( x + 1 ) words in Queue D - x words in Queue D - ( x + 1 )

words in Queue

WCLK

WEN

PRAF

RCLK

REN

NOTES:

1. x = PRAF

___________

offset.

2. D = maximum queue depth. Please refer to Table 7 for Depth.

3. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF

___________

will go high (after on WCLK cycle

plus tPRAFS). If tSKEW2 is not met, then PRAF

___________

will assert 1 or more WCLK cycles.

4. PRAF

___________

synchronizes to the rising edge of WCLK only.

Diagram 18. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

tWCLKH tWCLKL

tWCLKLtWCLKH

tENS tENH

y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3)

y words in Queue(2) ;

y+1 words in Queue(3)

tPRAEStPRAEStSKEW2

12 1 2

WCLK

RCLK

WEN

PRAE

REN

NOTES:

1. y = PRAE offset.

2. For Standard Mode.

3. For FWFT Mode.

4. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle

plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles.

5. PRAE synchronizes to the rising edge of RCLK only.

Diagram 19. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

tWCLKH tWCLKL

tENS tENH

tPRAFA

tENS

D - ( x + 1) words in Queue

D - x words in

Queue D - ( x + 1) words in Queue

WCLK

RCLK

WEN

PRAF

REN

NOTES:

1. x = PRAF offset.

2. D = maximum queue depth. Please refer to Table 7 for Depth.

3. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition.

4. Select this mode by setting SFM low during Master Reset.

Diagram 20. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode)

tWCLKH tWCLKL

tENS tENH

tPRAEA

tENS

y words in Queue(2); y+1 words in Queue(3) y+1 words in

Queue(2); y+2

words in Queue (3)

y words in Queue(2); y+1 words in Queue(3)

WCLK

RCLK

WEN

PRAE

REN

NOTES:

1. y = PRAE offset.

2. For Standard Mode.

3. For FWFT Mode.

4. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition.

5. Select this mode by setting SFM low during Master Reset.

Diagram 21. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode)

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

D/2 words in Queue(1); [(D+1)/2] words in Queue(2)

D/2 + 1 words in

Queue(1);

[(D+1)/2 + 1] words

in Queue(2)

D/2 words in Queue(1);

[(D+1)/2] words in Queue(2)

tWCLKH tWCLKL

tENS tENH

tHALF

tENS

WCLK

RCLK

WEN

HALF

REN

NOTES:

1. For Standard Mode.

2. For FWFT Mode.

3. Please refer to Table 7 for Depth.

Diagram 22. Half-Full Flag Timing (Standard and FWFT Mode)

July 200

2

Channel

Q

TM

Rev 1.0

CQV16100 · CQV1690 · CQV1680 · CQV1670 · CQV1660 · CQV1650 · CQV1640 · CQV163

0

3C080B

Order Information:

HBA

Device Family

Device Type

Power

Speed (ns) *

Package**

Temperature Range

XX XXXXX X XX XX X

CQ V16100 (65,536 x 80) Low 6 – 166 MHz BB Blank – Commercial (0°C to 70°C)

V1690 (32,768 x 80) 7-5 – 133 MHz I – Industrial (-40° to 85°C)

V1680 (16,384 x 80) 10 – 100 MHz

V1670 (8,192 x 80)

V1660 (4,096 x 80)

V1650 (2,048 x 80)

V1640 (1,024 x 80)

V1630 (512 x 80)

*Speed – 6ns available only in Commercial temp (0°C to 70°C)

**Package – 256 pin Fine Pitch Ball Grid Array (BGA)

Example:

CQV1670L6BB (8k x 80, 6ns, Commercial temp)

CQV1660L10BBI (4k x 80, 10ns, Industrial temp)

USA

Taiwan

2107 North First Street, Suite 415

San Jose, CA 95131, USA

www.hba.com

Tel: 408.453.8885

Fax: 408.453.8886

No. 81, Suite 8F-9, Shui-Lee Rd.

Hsinchu, Taiwan, R.O.C.

www.hba.com

Tel: 886.3.516.9118

Fax: 886.3.516.9181