CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM 3.3 Volt Synchronous 16 Channel Queue Memory Configuration Device 65,536 x 80 32,768 x 80 16,384 x 80 8,192 x 80 4,096 x 80 2,048 x 80 1,024 x 80 512 x 80 CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 Key Features * * * * * * * * * * * * * * * * * * * * * * * * * Single device solution providing complete data queuing and switching functions (up to 166 MHz) Write cycle time of 6.0ns independent of Read cycle time (Data Setup time = 2.0ns) Read cycle time of 6.0ns independent of Write cycle time (Data Access time = 4.0ns) 3.3V power supply 5V input tolerant on all control and data input pins 5V output tolerant on all flags and data output pins 5-bit wide data channels, up to sixteen channels per chip (80 bits total) Reconfigurable data switching supporting channel unicast, multicast and broadcast Master Reset clears all previously programmed configurations including Write and Read pointers Partial Reset clears Write and Read pointers but maintains all previously programmed configurations First Word Fall Through (FWFT) and Standard Timing modes Presets for eight different Almost Full and Almost Empty offset values Parallel/Serial programming of PRAF and PRAE offset values Programmable 8-bit or 10-bit parallel programming modes for offset values Full, Empty, Almost Full, Almost Empty, and Half Full indicators PRAF and PRAE operates in either synchronous or asynchronous modes Individual synchronous channel output enable signals controlling tri-state data output drivers Asynchronous device output enable signals controlling tri-state data output drivers Synchronous Read Chip Select Data retransmission with programmable zero or normal latency modes Switching management Boundary Scan (JTAG) Available package: 256 - pin Fine Pitch Ball Grid Array (BGA) (0C to 70C) Commercial operating temperature available for cycle time of 6.0ns and above (-40C to 85C) Industrial operating temperature available for cycle time of 7.5ns and above Product Description HBA's ChannelQTM product family represents the next generation bandwidth management solutions by providing advanced data queuing and switching functions within a single chip. System designers can take full advantage of the flexible data switching functions offered by the ChannelQ products while maintaining access to all the advanced features available in HBA's existing FlexQTM family, such as programmable FIFO status flags, programmable data access timing (First-Word-Fall-Through and Standard modes), data retransmission with programmable latency mode, and tri-state output data drivers. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 1 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Product Description (Continued) The channel switching capability provides a means for unicast / multicast / broadcast of individual channel data when they are written to the internal FIFO memory. The configuration of the channel switch can be reprogrammed on the fly. Because the device combines data queuing and switching into a single chip, it in effect implements a switching fabric with input data queuing, which has a broad range of applications in data communication. For detailed information on programming and using the ChannelQTM devices, please refer to the ChannelQ Application Note. 5V tolerant on all input and output pins allow easy interfacing with devices operating at higher voltage levels. Asynchronous Output Enable pin configures the tri-state data output drivers. In addition, synchronous read chip select and synchronous channel output enables are also available to control the state of data output drivers, allowing multiple ChannelQ devices to share a single output data bus. Independent Write and Read controls provide rate-matching capability. Master Reset clears all previously programmed configurations by providing a low pulse on MRST pin. In addition, Write and Read pointers to the queue are initialized to zero. Partial Reset will not alter previously programmed configurations but will initialize Write and Read pointers to zero. In FWFT mode, first data written into the queue appears on output data bus after the specified latency period at the low to high transition of RCLK. Subsequent reads from the queue will require asserting REN . This feature is useful when implementing depth expansion functions. In this mode, DRDY and QRDY are used instead of FULL and EMPTY respectively. In Standard mode, always assert REN for a read operation. FULL and EMPTY are used instead of DRDY and QRDY respectively. Eight different default offset values are available for Almost Full ( PRAF ) and Almost Empty ( PRAE ) flags. Parallel and Serial programming of these offset values provide total flexibility other than the pre-defined default values. Both 8-bit and 10-bit parallel programming modes for offset values can be selected for convenience. PRAF , PRAE , and HALF are available in either FWFT or Standard mode. In addition, PRAF and PRAE can operate in either synchronous or asynchronous modes. At any time, data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Both zero and normal latency timing modes are available for retransmit operation. ChannelQ devices have low power consumption, hence minimizing system power requirements. In addition, industry standard 256 - pin BGA is offered to save system board space. These devices are ideal for applications such as data communication, telecommunication, test equipment, network switching, etc. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 2 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Programming Modes Channels 8 Channel In Channel Out 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 Channels 8 Output Channel 7 6 5 4 3 2 1 0 Channel Source 7 6 5 4 3 2 1 0 Figure 1. 8x5-to-8x5 ChannelQ Configured in Unicast Mode Channels 8 Channel In Channel Out 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Output Channel 7 6 5 4 3 2 1 0 Channel Source 2 2 2 2 2 2 2 2 Channels Figure 2. 8x5-to-8x5 ChannelQ Configured in Broadcast Mode July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 3 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Channels 8 Channel In Channel Out 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Output Channel 7 6 5 4 3 2 1 0 Channel Source 7 6 7 6 3 2 3 3 Channels Figure 3. 8x5-to-8x5 ChannelQ Configured in Multicast Mode Channels 8 Channel In Channel Out 0 0 1 1 2 2 3 3 4 4 5 5 6 6 7 7 8 Output Channel 7 6 5 4 3 2 1 0 Channel Source 1 0 5 4 7 6 3 2 Channels Figure4. 8x5-to-8x5 ChannelQ Configured as a 4x10-to-4x10 Switch in Switching Mode July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 4 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 5 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Block Diagram of Single Channel Queue 65,536 x 80 / 32,768 x 80 / 16,384 x 80 / 8,192 x 80 / 4,096 x 80 / 2,048 x 80 / 1,024 x 80 / 512 x 80 PARTIAL RESET (PRST ) MASTER RESET (MRST) READ CLOCK (RCLK) WRITE CLOCK (WCLK) SWTICHING CONTROL REGISTER WRITE ENABLE ( AWEN) SWITCHING CONTROL REGISTER READ ENABLE ( AREN) WRITE ENABLE ( WEN) READ ENABLE (REN ) OUTPUT ENABLE ( OE ) LOAD ( LOAD) READ CHIP SELECT ( RCS ) (SFM) (PFS0) (PFS1) DATA IN (D79 - 0) SERIAL IN CLOCK (SCLK) SERIAL DATA ENABLE (SDEN ) CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 FIRST WORD FALL THROUGH/ SERIAL DATA INPUT (FWFT/SDI) FULL FLAG / INPUT READY ( FULL / DRDY ) PROGRAMMABLE ALMOSTFULL (PRAF ) DATA OUT (Q79 - 0) (RETLZ) RETRANSMIT ( RET ) EMPTY FLAG / OUTPUT READY ( EMPTY / QRDY ) PROGRAMMABLE ALMOSTEMPTY ( PRAE ) HALF-FULL FLAG ( HALF ) JTAG CLOCK (TCLK) JTAG RESET ( TRST ) JTAG MODE (TMS) INTERSPERSED PARITY (IPAR) (TDO) (TDI) Figure 5. Single Device Configuration Signal Flow Diagram July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 6 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM WCLK WEN FWFT/ IPAR LOAD SDEN SDI SCLK FULL / DRDY Write Control Logic PRAF EMPTY/ QRDY Offset Register PRAE HALF FWFT/SDI SFM Flag Logic Write Pointer PFS1 PFS0 Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5, Ch 6, Ch 7, Ch 8, Ch 9, Ch 10, Ch 11, Ch 12, Ch 13, Ch 14, Ch 15 Channel Switch Input Register SRAM Output Register Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5, Ch 6, Ch 7, Ch 8, Ch 9, Ch 10, Ch 11, Ch 12, Ch 13, Ch 14, Ch 15 Output Buffer OE Read Pointer Switching Control Register AWEN AREN Read Control Logic RCS RETZL RET RCLK REN Reset MRST PRST Figure 6. ChannelQ Device Architecture July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 7 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM A1 BALL PAD CORNER A Q36 Q 38 Q52 Q55 Q58 Q72 Q75 Q78 D78 D75 D72 D58 D55 D 52 D 38 D36 Q35 Q 37 Q51 Q54 Q57 Q71 Q74 Q77 D77 D74 D71 D57 D54 D 51 D 37 D35 Q34 Q 33 Q50 Q53 Q56 Q70 Q73 Q76 D76 D73 D70 D56 D53 D 50 D 33 D34 Q32 Q 31 Q30 Q39 Q59 Q79 GND TCK TDI T RST TDO TM S D59 D 30 D 31 D32 Q18 Q 17 Q16 Q19 GND VCC GND V CC GND VCC GND D79 D39 D 16 D 17 D18 Q15 Q 14 Q13 VCC GND VCC GND V CC GND VCC GND VCC D19 D 13 D 14 D15 Q12 Q 11 Q10 VCC GND VCC GND V CC GND VCC GND VCC GN D D 10 D 11 D12 Q68 Q 67 Q66 VCC GND VCC GND V CC GND VCC GND VCC GN D D 66 D 67 D68 Q65 Q 64 Q63 VCC GND VCC GND V CC GND VCC GND VCC D69 D 63 D 64 D65 Q62 Q 61 Q60 Q69 GND VCC GND V CC GND VCC GND VCC D49 D 60 D 61 D62 Q48 Q 47 Q46 Q49 GND VCC GND V CC GND AW EN GND D29 DC D 46 D 47 D48 Q45 Q 44 Q43 Q29 Q9 AREN GND GND PFS1 PFS0 GND D9 SCLK D 43 D 44 D45 Q42 Q 41 Q40 RET RETZL SFM GND IPAR DC HALF FW FT/SDI LOAD SDEN D 40 D 41 D42 Q28 Q 27 Q20 Q6 Q3 Q0 RCS PRAE M RST PRST D0 D3 D6 D 20 D 27 D28 Q26 Q 23 Q21 Q7 Q4 Q1 OE EM PTY PRAF WEN D1 D4 D7 D 21 D 23 D26 Q25 Q 24 Q22 Q8 Q5 Q2 REN RCLK FULL W CLK D2 D5 D8 D 22 D 24 D25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 B C D E F G H J K L M N P R T PBGA -256 (Order code: BB) Top View Figure 7. Device Pin Out July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 8 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Pin # P9 Pin Name Master Reset Pin Symbol MRST Input/Output Description Input Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will not be maintained. P10 Partial Reset PRST Input Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high; EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low. Previous programmed configurations will be maintained. T10 Write Clock WCLK Input Writes data into queue during low to high transitions of WCLK if WEN is set to low. R10 Write Enable WEN Input Controls write operation into queue or offset registers during low to high transition of WCLK. N12 Load Enable LOAD Input During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read to/from offset registers during low to high transition of WCLK/RCLK respectively. Use in conjunction with WEN / REN . M9 Default Programming 1 PFS1 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. M10 Default Programming 0 PFS0 Input During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. P11,R11,T11,P12,R12 T12,P13,R13,T13,M12 G14,G15,G16,F14,F15 F16,E14,E15,E16,F13 P14,R14,T14,R15,T15 T16,R16,P15,P16,L12 D14,D15,D16,C15,C16 B16,A16,B15,A15,E13 N14,N15,N16,M14,M15 M16,L14,L15,L16,K13 C14,B14,A14,C13,B13 A13,C12,B12,A12,D13 K14,K15,K16,J14,J15 J16,H14,H15,H16,J13 C11,B11,A11,C10,B10 A10,C9,B9,A9,E12 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch 10 Ch 11 Ch 12 Ch 13 Ch 14 Ch 15 D4-0 D9-5 D14-10 D19-15 D24-20 D29-25 D34-30 D39-35 D44-40 D49-45 D54-50 D59-55 D64-60 D69-65 D74-70 D79-75 Input 80 - bit wide input data bus. Table 1. Pin Descriptions July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 9 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Description Pin # Pin Name Pin Symbol Input/Output T8 Read Clock RCLK Input Reads data from queue during low to high transitions of RCLK if REN is set to low. T7 Read Enable REN Input Controls read operation from queue or offset registers during low to high transition of RCLK. P7 Read Chip Select RCS Input Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be set low when using RCS to control the state of the drivers. R7 Output Enable OE Input Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). P6,R6,T6,P5,R5 T5,P4,R4,T4,M5 G3,G2,G1,F3,F2 F1,E3,E2,E1 ,E4 P3,R3,T3,R2,T2 T1,R1,P2,P1,M4 D3,D2,D1,C2,C1 B1,A1,B2,A2,D4 N3,N2,N1,M3,M2 M1,L3,L2,L1,L4 C3,B3,A3,C4,B4 A4,C5,B5,A5,D5 K3,K2,K1,J3,J2 J1,H3,H2,H1,K4 C6,B6,A6,C7,B7 A7,C8,B8,A8,D6 Ch 0 Ch 1 Ch 2 Ch 3 Ch 4 Ch 5 Ch 6 Ch 7 Ch 8 Ch 9 Ch 10 Ch 11 Ch 12 Ch 13 Ch 14 Ch 15 Q4-0 Q9-5 Q14-10 Q19-15 Q24-20 Q29-25 Q34-30 Q39-35 Q44-40 Q49-45 Q54-50 Q59-55 Q64-60 Q69-65 Q74-70 Q79-75 Output 80 - bit wide output data bus. N11 First Word Fall Through/Serial Data Input FWFT/SDI Input Selects FWFT timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . M13 Serial Clock SCLK Input During serial programming, SCLK is used to program offset values through SDI. N13 Serial Data Input Enable SDEN Input If serial programming is selected, setting SDEN and LOAD low enables serial data input to be written into offset registers during the low to high transition of SCLK. Input Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. N4 Retransmit RET Table 1. Pin Descriptions (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 10 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Pin # Pin Name Pin Symbol Input/Output N5 Zero Latency Retransmit RETZL Input During Master Reset, set RETZL low to select zero latency retransmit or RETZL high to select normal latency retransmit. Output Queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue. In FWFT mode, queue is full when DRDY goes high during low to high transition of WCLK. This prohibits further writes into the queue. EMPTY / QRDY Output Queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue. In FWFT mode, queue is empty when QRDY goes high during the low to high transition of RCLK. This prohibits further reads from the queue. Interspersed Parity IPAR Input During Master Reset, set IPAR low to select 10-bit parallel programming mode or IPAR high to select 8bit parallel programming mode. Synchronous Partial Flag Mode SFM Input During Master Reset, set SFM high to select Synchronous Partial Flag mode or SFM low to select Asynchronous Partial Flag mode. Output Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . T9 Full/Data Input Ready Flag R8 Empty/Data Output Ready Flag N8 N6 R9 Description Almost Full FULL / DRDY PRAF P8 Almost Empty PRAE Output Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . N10 Half Full HALF Output Queue is more than half full when HALF goes low. Triggered by both WCLK and RCLK. L13, N7 Don't Care DC N/A This pin can be tied high or low, cannot be left open. E6, E8, E10, F4, F6, F8, F10, F12, G4, G6, G8, G10, G12, H4, H6, H8, H10, H12, J4, J6, J8, J10, J12, K6, K8, K10, K12, L6, L8 Power Vcc N/A 3.3V power supply. D7, E5, E7, E9, E11, F5, F7, F9, F11, G5, G7, G9, G11, G13, H5, H7, H9, H11, H13, J5, J7, J9, J11, K5, K7, K9, K11, L5, L7, L9, L11, M7, M8, M11, N7 Ground GND N/A 0V Ground. Table 1. Pin Description (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 11 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Pin # Pin Name Pin Symbol Input/Output Description D8 JTAG Clock TCK Input Clock for JTAG function. TMS and TDI are loaded during low to high transitions of TCK. TDO is loaded during high to low transitions of TCK. D10 JTAG Reset TRST Input Reset control for JTAG function. An asynchronous input for the JTAG controller. D12 JTAG Mode Selection TMS Input Mode select for JTAG function. TMS bits are loaded serially during low to high transitions of the TCK. D9 Test Data Input TDI Input Serial data input for JTAG function. TDI is loaded during low to high transitions of the TCK. D11 Test Data Output TDO Output Serial data output for JTAG function. TDO is unloaded during high to low transitions of the TCK. During SHIFTDR and SHIFT-IR operations, TDO bus will be tri-stated. L10 Switching Control Register Write Enable AWEN Input Setting AWEN low causes the value on the input data bus to be written into the switching control register during the low to high transition of WCLK, provided WEN is held high at the same transition. M6 Switching Control Register Read Enable AREN Input Setting AREN low allows reading from the switching control register during the low to high transition of RCLK, provided REN is held high at the same transition. Table 1. Pin Description (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 12 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Symbol VTERM Rating Terminal Voltage with respect to GND Com'l & Ind'l Unit -0.5 to + 4.5 V TSTG Storage Temperature -55 to +125 IOUT DC Output Current -50 to +50 NOTES: Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. C mA Table 2. Absolute Maximum Ratings CQV16100, CQV1690, CQV1680, CQV1670, CQV1660, CQV1650, CQV1640, CQV1630 Commercial Clock = 6ns, 7.5ns, 10ns Industrial Clock = 7.5ns, 10ns Symbol Parameter Recommended Operating Conditions Min. Typ. Max. Min. Typ. Max. Unit Vcc Supply Voltage Com'l / Ind'l 3.15 3.3 3.45 3.15 3.3 3.45 V GND Supply Voltage 0 0 0 0 0 0 V 2.0 - 5.5 2.0 - 5.5 V - - 0.8 - - 0.8 V 0 - 70 0 - 70 -40 - 85 -40 - 85 Input High Voltage Com'l / Ind'l Input Low Voltage Com'l / Ind'l Operating Temperature Commercial Operating Temperature Industrial VIH VIL TA TA C C DC Electrical Characteristics ILI(1) Input Leakage Current (any input) -10 - 10 -10 - 10 A ILO Output Leakage Current -10 - 10 -10 - 10 A 2.4 - - 2.4 - - V - - 0.4 - - 0.4 V Output Logic "1" Voltage, IOH=-2mA Output Logic "0" Voltage, IOL = 8mA VOH VOL Power Consumption Icc1(2,3) Active Power Supply Current - - 40 - - 40 mA Icc2(4) Standby Current - - 15 - - 15 mA Table 3. DC Specifications July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 13 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Capacitance at 100MHz Ambient Temperature (25C) Symbol CIN Parameter (2) Input Capacitance COUT(2,4) Output Capacitance Conditions Max. Unit VIN= 0V 10 pF VOUT= 0V 10 pF NOTES: 1. 2. 3. 4. Measurement with 0.4<=VIN<=Vcc With output tri-stated ( OE = High) Icc(1,2) is measured with WCLK and RCLK at 20 MHz Design simulated, not tested. Table 3. DC Specifications (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 14 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Commercial CQV16100-6 CQV1690-6 CQV1680-6 CQV1670-6 CQV1660-6 CQV1650-6 CQV1640-6 CQV1630-6 Symbol Parameter Commercial & Industrial CQV16100-7.5 CQV1690-7.5 CQV1680-7.5 CQV1670-7.5 CQV1660-7.5 CQV1650-7.5 CQV1640-7.5 CQV1630-7.5 CQV16100-10 CQV1690-10 CQV1680-10 CQV1670-10 CQV1660-10 CQV1650-10 CQV1640-10 CQV1630-10 Min. Max. Min. Max. Min. Max. Unit fS Clock Cycle Frequency - 166 - 133 - 100 MHz tA Data Access Time 1 4 2 5 2 6.5 ns tWCLK Write Clock Cycle Time 6 - 7.5 - 10 - ns tWCLKH Write Clock High Time 2.5 - 3.5 - 4.5 - ns tWCLKL Write Clock Low Time 2.5 - 3.5 - 4.5 - ns tRCLK Read Clock Cycle Time 6 - 7.5 - 10 - ns tRCLKH Read Clock High Time 2.5 - 3.5 - 4.5 - ns tRCLKL Read Clock Low Time 2.5 - 3.5 - 4.5 - ns tDS Data Set-up Time 2.0 - 2.5 - 3.5 - ns tDH Data Hold Time 0.5 - 0.5 - 0.5 - ns tENS Enable Set-up Time 2.0 - 2.5 - 3.5 - ns tENH Enable Hold Time 0.5 - 0.5 - 0.5 - ns 8 - 10 - 10 - ns 15 - ns (1) tRST Reset Pulse Width tRSTS Reset Set-up Time 10 - 15 tRSTR Reset Recovery Time 10 - 10 - 10 - ns tRSTF Reset to Flag and Output Time - 10 - 15 - 15 ns 0 - 0 - 0 - ns 2 4 2 6 2 6 ns 2 4 2 6 2 6 ns tOLZ Output Enable to Output in Low-Z tOE Output Enable to Output Valid (1) (1) tOHZ Output Enable to Output in High-Z tFULL Write Clock to Full Flag - 4 - 5 - 6.5 ns tEMPTY Read Clock to Empty Flag - 4 - 5 - 6.5 ns tPRAFS Write Clock to Synchronous Almost-Full Flag - 4 - 5 - 6.5 ns tPRAES Read Clock to Synchronous AlmostEmpty Flag - 4 - 5 - 6.5 ns tRCSS RCS Setup Time 2 - 3.5 - 3.5 - ns tRCSH RCS Hold Time 0.5 - 0.5 - 0.5 - ns tRCSLZ RCLK to Active from High-Z 2 4 1 6.5 1 6.5 ns tRCSHZ RCLK to High-Z 2 4 1 6.5 1 6.5 ns July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 15 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Table 4. AC Electrical Characteristics Commercial CQV16100-6 CQV1690-6 CQV1680-6 CQV1670-6 CQV1660-6 CQV1650-6 CQV1640-6 CQV1630-6 Symbol Parameter Commercial & Industrial CQV16100-7.5 CQV1690-7.5 CQV1680-7.5 CQV1670-7.5 CQV1660-7.5 CQV1650-7.5 CQV1640-7.5 CQV1630-7.5 CQV16100-10 CQV1690-10 CQV1680-10 CQV1670-10 CQV1660-10 CQV1650-10 CQV1640-10 CQV1630-10 Min. Max. Min. Max. Min. Max. Unit tSKEW1 Skew time between Read Clock & Write Clock for Full Flag / Empty Flag 4 - 5 - 7 - ns tSKEW2 Skew time between Read Clock & Write Clock for PRAE & PRAF 6 - 7 - 10 - ns tLOADS Load Setup Time 2.0 - 2.5 - 3.5 - ns tLOADH Load Hold Time 0.5 - 0.5 - 0.5 - ns tRETS Retransmit Setup Time 2.5 - 3.5 - 3.5 - ns tHALF Clock to HALF - 12 - 12.5 - 16 ns tPRAFA Write Clock to Asynchronous Programmable Almost-Full Flag - 12 - 12.5 - 16 ns tPRAEA Read Clock to Asynchronous Programmable Almost-Empty Flag - 12 - 12.5 - 16 ns NOTES: 1. Design simulated, not tested. Table 4. AC Electrical Characteristics (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 16 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load, clock = 6ns, 7.5ns, 10ns Refer to Figure 8 Table 5. AC Test Condition Vcc/ 2 50 I/O Z0 = 50 Figure 8. AC Test Load for clock = 6ns, 7.5ns, 10ns July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 17 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Pin Functions MRST Master Reset is required to initialize Write and Read pointers to the first position of the queue by setting MRST low. In Standard mode, FULL and PRAF will go high, EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low, and previous programmed configurations will not be maintained. PRST Partial Reset is required to initialize Write and Read pointers to the first position of the queue by setting PRST low. In Standard mode, FULL and PRAF will go high. EMPTY and PRAE will go low. In FWFT mode, DRDY will go low and QRDY will go high. PRAF and PRAE will go to the same state as Standard mode. In both modes, all data outputs will go low, and previously programmed configurations will be maintained. WCLK Writes data into queue during low to high transitions of WCLK if WEN is activated. Synchronizes FULL / DRDY and PRAF flags. WCLK and RCLK are independent of each other. WEN Controls write operation into queue or offset registers during low to high transition of WCLK. LOAD During Master Reset, set LOAD low to select parallel programming or one of eight default offset values. Set LOAD high to select serial programming or one of eight default offset values. After Master Reset, LOAD controls write/read, to/from offset registers during low to high transition of WCLK/RCLK respectively for parallel programming. Use in conjunction with WEN / REN . During programming of offset registers, PRAF and PRAE flag status is invalid. For Serial programming, LOAD is used to enable serial loading of offset registers together with SDEN . Refer to Figure 9 for details. PFS1 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS0. Refer to Table 11 for details. PFS0 During Master Reset, select one of eight default offset values. Use in conjunction with LOAD and PFS1. Refer to Table 11 for details. D79..0 80 - bit wide input data bus. RCLK Reads data from queue during low to high transitions of RCLK if REN is set low. Synchronizes the EMPTY / QRDY and PRAE flags. RCLK and WCLK are independent of each other. REN Reads data from queue during low to high transitions of RCLK if REN is set to low. This also advances the Read pointer of the queue. RCS Setting RCS low during the low to high transition of RCLK activates the data output drivers. Setting RCS high during the low to high transition of RCLK deactivates the data output drivers. OE must be set low when using RCS to control the state of the drivers. OE Setting OE low activates the data output drivers. Setting OE high deactivates the data output drivers (High-Z). OE does not control advancement of Read pointer. D79..0 80 - bit wide output data bus. FWFT/SDI Selects First Word Fall Through timing or Standard timing mode during Master Reset. After Master Reset, if serial programming is selected ( LOAD = high), FWFT/SDI is used as the serial data input for the offset registers. Serial data is written during the low to high transition of WCLK. Use in conjunction with SDEN . In FWFT mode, DRDY and QRDY is used instead of FULL and EMPTY . In Standard mode, FULL and EMPTY is used instead of DRDY and QRDY . Refer to Table 8 & 9 for all flags status. SCLK During serial programming, SCLK is used to program offset values through SDI. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 18 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Pin Functions (Continued) SDEN If serial programming is selected, setting SDEN and LOAD low enables serial data to be written into offset registers during the low to high transition of SCLK. During serial programming, PRAF and PRAE flags status is invalid. Refer to Figure 9 for details. RET Data previously read from the queue can be retransmitted by asserting RET pin at the low to high transition of RCLK for a retransmit operation. Retransmit initializes the Read pointer to zero. Hence, all re-reads will always start from the physical 0th (Read pointer = zero) location of the queue. Refer to Diagram 9 & 10 for details. RETZL During Master Reset, set RETZL low to select zero latency retransmit. Set RETZL high to select normal latency retransmit. FULL / DRDY In Standard mode, queue is full when FULL goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. In FWFT mode, queue is full when DRDY goes low during the low to high transition of WCLK. This prohibits further writes into the queue and prevents advancement of Write pointer. Refer to Table 8 & 9 for behavior of FULL / DRDY . EMPTY / QRDY In Standard mode, queue is empty when EMPTY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. In FWFT mode, queue is empty when QRDY goes low during the low to high transition of RCLK. This prohibits further reads from the queue and prevents advancement of Read pointer. Refer to Table 8 & 9 for behavior of EMPTY / QRDY . IPAR During Master Reset, set IPAR low to select 10-bit parallel programming mode or set IPAR high to select 8-bit parallel programming mode. In 10-bit mode, 10-bit wide data input / output bus width is used for storing / fetching offset values. In 8-bit mode, 8-bit wide data input / output bus is used for storing / fetching offset values. SFM During Master Reset, set SFM high to select Synchronous Partial Flag mode or set SFM low to select Asynchronous Partial Flag mode. In Synchronous mode, PRAF and PRAE are synchronous to WCLK and RCLK respectively. In Asynchronous mode, WCLK synchronizes the assertion of PRAF and de-assertion of PRAE . RCLK synchronizes the assertion of PRAE and de-assertion of PRAF . PRAF Queue is almost full when PRAF goes low during the low to high transition of WCLK. Default (Full-offset) or programmed offset values determine the status of PRAF . Refer to Table 8 & 9 for behavior of PRAF . PRAE Queue is almost empty when PRAE goes low during the low to high transition of RCLK. Default (Empty+offset) or programmed offset values determine the status of PRAE . Refer to Table 8 & 9 for behavior of PRAE . Pin Functions (Continued) HALF Queue is more than half full when HALF goes low during the low to high transition of WCLK. Queue is less than half full when HALF goes high during low to high transition of RCLK when. Refer to Table 8 & 9 for details. AWEN Setting AWEN low causes the value on the input data bus to be written into the switching control register during the low to high transition of WCLK, provided WEN is held high at the same transition. AREN Setting AREN low allows reading from the switching control register during the low to high transition of RCLK, provided REN is held high at the same transition. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 19 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 Selection / Sequence LOAD WEN REN AWEN AREN SDEN WCLK RCLK SCLK 0 0 0 1 1 0 1 1 1 1 1 1 X X X X Parallel write to offset registers: Empty Offset Full Offset Parallel write to registers: Parallel read from offset registers: Empty Offset Full Offset Parallel read from registers: 1. PRAE 2. PRAF 1. PRAE 2. PRAF 0 1 1 1 1 0 X X X 1 1 1 1 1 X X X Serial shift into registers: 32 bits for the CQV16100 30 bits for the CQV1690 28 bits for the CQV1680 26 bits for the CQV1670 24 bits for the CQV1660 22 bits for the CQV1650 20 bits for the CQV1640 18 bits for the CQV1630 1 bit for each rising WCLK edge Starting with Empty Offset (Low Byte) Ending with Full Offset (High Byte) No Operation X 1 X 0 X X X X Write Switching Control Register X X 1 X 0 X X Read Switching Control Register 1 0 X X X X X Write Memory 1 X 0 X X X X X Read Memory 1 1 1 1 1 X X X No Operation X X X July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 20 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Figure 9. Programmable Flag Offset Programming Sequence (CQV16100, CQV1690, CQV1680, CQV1670, CQV1660, CQV1650, CQV1640 and CQV1630) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 21 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Device CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 PRAF Programming (bits) PRAE Programming (bits) D/Q15 - 0 Non-IPAR D/Q15 - 0 Non-IPAR D/Q17 -10 & D/Q7 - 0 IPAR D/Q17 - 10 & D/Q7 - 0 IPAR D/Q14 - 0 Non-IPAR D/Q14 - 0 Non-IPAR D/Q16 - 10 & D/Q7 - 0 IPAR D/Q16 - 10 & D/Q7 - 0 IPAR D/Q13 - 0 Non-IPAR D/Q13 - 0 Non-IPAR D/Q15 - 10 & D/Q7 - 0 IPAR D/Q15 - 10 & D/Q7 - 0 IPAR D/Q12 - 0 Non-IPAR D/Q12 - 0 Non-IPAR D/Q14 - 10 & D/Q7 - 0 IPAR D/Q14 - 10 & D/Q7 - 0 IPAR D/Q11 - 0 Non-IPAR D/Q11 - 0 Non-IPAR D/Q13 - 10 & D/Q7 - 0 IPAR D/Q13 - 10 & D/Q7 - 0 IPAR D/Q10 - 0 Non-IPAR D/Q10 - 0 Non-IPAR D/Q12 - 10 & D/Q7 - 0 IPAR D/Q12 - 10 & D/Q7 - 0 IPAR D/Q9 - 0 Non-IPAR D/Q11 - 10 & D/Q7 - 0 IPAR D/Q9 - 0 Non-IPAR D/Q11 - 10 & D/Q7 - 0 IPAR D/Q8 - 0 Non-IPAR D/Q8 - 0 Non-IPAR D/Q10 & D/Q7 - 0 IPAR D/Q10 & D/Q7 - 0 IPAR Table 6. Parallel Offset Register Data Mapping Table Device Standard Mode FWFT Mode CQV16100 65,536 x 80 65,537 x 80 CQV1690 32,768 x 80 32,769 x 80 CQV1680 16,384 x 80 16,385 x 80 CQV1670 8,192 x 80 8,193 x 80 CQV1660 4,096 x 80 4,097 x 80 CQV1650 2,048 x 80 2,049 x 80 CQV1640 1,024 x 80 1,025 x 80 CQV1630 512 x 80 513 x 80 Table 7. Maximum Depth of Queue for Standard and FWFT Mode July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 22 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Data Width D/Q79 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 15 14 13 12 11 10 D/Q9 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 5 4 3 2 1 0 6 5 4 3 2 1 0 D/Q8 D/Q7 D/Q6 8 7 6 7 D/Q5 1st Cycle PRAE Non-Interspersed Parity Interspersed Parity 9 15 14 13 12 11 10 9 8 D/Q17 D/Q16 D/Q15 D/Q14 D/Q13 D/Q12 D/Q11 D/Q10 D/Q9 D/Q8 D/Q7 D/Q6 D/Q5 D/Q4 D/Q3 D/Q2 D/Q1 D/Q0 Non-Interspersed Parity 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interspersed Parity 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data Width D/Q79 D/Q~ D/Q~ D/Q~ D/Q19 D/Q18 2nd Cycle PRAF 15 14 CQV16100, CQV1690, CQV1680, CQV1670, CQV1660, CQV1650, CQV1640, CQV1630 Parallel Offset Write/Read Cycles # of Bits for Offset Registers 16 bits for CQV16100 15 bits for CQV1690 14 bits for CQV1680 13 bits for CQV1670 12 bits for CQV1660 11 bits for CQV1650 10 bits for CQV1640 9 bits for CQV1630 Note: Don't Care applies to all unused bits Figure 10. Parallel Offset Write/Read Cycles Diagram (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 23 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM CQV16100 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 32,768 32,769 to [65,536-(x+1)] (65,536 -x(2)) to 65,535 65,536 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1690 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 16,384 16,385 to [32,768-(x+1)] (32,768 -x(2)) to 32,767 32,768 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1680 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 8,192 8,193 to [16,384-(x+1)] (16,384 -x(2)) to 16,383 16,384 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1670 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 4,096 4,097 to [8,192-(x+1)] (8,192 -x(2)) to 8,191 8,192 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1660 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 2,048 2,049 to [4,096-(x+1)] (4,096 -x(2)) to 4,095 4,096 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1650 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 1,024 1,025 to [2,048-(x+1)] (2,048 -x(2)) to 2,047 2,048 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H Table 8. Status Flags (Standard Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 24 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM CQV1640 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 512 513 to [1,024-(x+1)] (1,024 -x(2)) to 1,023 1,024 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H CQV1630 FULL PRAF HALF PRAE EMPTY 0 1 to y(1) (y+1) to 256 257 to [512-(x+1)] (512 -x(1)) to 511 512 H H H H H L H H H H L L H H H L L L L L H H H H L H H H H H NOTES: 1. See Table 11 for values x, y. Table 8. Status Flags (Standard Mode)(Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 25 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM CQV16100 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 32,769 32,770 to [65,537-(x+1)] (65,537 -x) to 65,536 65,537 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1690 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 16,385 16,386 to [32,769-(x+1)] (32,769 -x) to 32,768 32,769 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1680 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 8,193 8,194 to [16,385-(x+1)] (16,385 -x) to 16,384 16,385 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1670 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 4,097 4,098 to [8,193-(x+1)] (8,193-x) to 8,192 8,193 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1660 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 2,049 2,050 to [4,097-(x+1)] (4,097 -x) to 4,096 4,097 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1650 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 1,025 1,026 to [2,049-(x+1)] (2,049 -x) to 2,048 2,049 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L Table 9. Status Flags (FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 26 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM CQV1640 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 513 514 to [1,025-(x+1)] (1,025 -x) to 1,024 1,025 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L CQV1630 DRDY PRAF HALF PRAE QRDY 0 1 to y+1 (y+2) to 257 258 to [513-(x+1)] (513 -x) to 512 513 L L L L L H H H H H L L H H H L L L L L H H H H H L L L L L Table 9. Status Flags (FWFT Mode)(Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 27 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM LOAD PFS1 PFS0 CQV1640 CQV1630 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 31 1 0 1 7 1 1 0 15 1 1 1 3 LOAD PFS1 PFS0 CQV1640 CQV1630 Program Mode 1 X X Serial 0 X X Parallel LOAD PFS1 PFS0 CQV1680 CQV1670 CQV1660 CQV1650 Default Offsets x, y(1) 0 0 0 127 0 0 1 255 0 1 0 511 0 1 1 63 1 0 0 1,023 1 0 1 15 1 1 0 31 1 1 1 7 PFS0 CQV1680 CQV1670 CQV1660 CQV1650 Program Mode LOAD PFS1 1 X X Serial 0 X X Parallel NOTES: 1. y = PRAE offset, x = PRAF offset Table 10. Default Programmable Flag Offsets July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 28 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM LOAD PFS1 PFS0 CQV16100 CQV1690 Default Offsets x, y(1) 0 0 0 127 0 0 1 8,191 0 1 0 16,383 0 1 1 4,095 1 0 0 1,023 1 0 1 511 1 1 0 2,047 1 1 1 255 LOAD PFS1 PFS0 CQV16100 CQV1690 Program Mode 1 X X Serial 0 X X Parallel NOTES: 1. y = PRAE offset, x = PRAF offset Table 10. Default Programmable Flag Offsets (Continued) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 29 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM JTAG Interface Standard JTAG interface is used for boundary scan purposes. For a complete description, please refer to the IEEE Standard Test Access Port Specification (IEEE STD.1149.1 - 1990) JTAG TIMING SPECIFICATIONS t3 t1 tTCK t4 t2 TCK TDI / TMS tDS tDH TDO TDO t6 tDO TRST t5 Figure 11. Standard JTAG Timing Parameter System Interface Parameters Data Output Data Output Hold Data Input Symbol Test Conditions Min. CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 Max. tDO = Max tDOH tDS tDH trise = 3ns tfall = 3ns 5 5 30 30 50 - - 100 40 40 50 50 5 5 - JTAG AC Electrical Characteristics JTAG Clock Input Period tTCK JTAG Clock HIGH tTCKHIGH (t2) JTAG Clock Low tTCKLOW (t1) JTAG Clock Rise Time tTCKRise (t4) JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery tTCKFall (t3) tRST (t5) tRSR (t6) Units ns ns ns ns ns ns ns ns ns ns Table 12. JTAG AC Electrical Characteristics July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 30 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM JTAG BLOCK DIAGRAM HBA's FlexQTM offers IEEE Std. 1149.1-1990 standard JTAG interface to facilitate system debugging in all PBGA packages. STANDARD JTAG INTERFACE ELEMENTS: 1. 2. 3. 4. TAP TAPCNTL IR DR - TEST ACCESS PORT - TAP CONTROLLER - INSTRUCTION REGISTER - DATA REGISTER Boundary Scan Reg. TDO TDI TMS Device ID Reg. Bypass Reg. TAP TCLK TRST Instruction Decode DR Instruction Register IR TAP Controller Figure 12. Boundary Scan Architecture Diagram July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 31 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM 1. TAP The basic ports to access the JTAG function. That includes four general input ports: TRST , TCK, TMS, and TDI, and one general output port: TDO. 2. TAPCNTL A finite state machine that provide instructions to the Instruction and Data Registers for data capture and update. Individual states are explained blow. 1 0 T est-Logic R eset 0 R un-T est / Idle 1 1 1 Select-D R Scan Select-IR Scan 0 1 0 1 C apture-D R 0 C apture-IR 0 0 Shift-D R Shift-IR 1 Input = T M S 1 1 E xit1-D R 0 0 0 0 Pause-IR 1 1 E xit2-D R 0 U pdate-D R 1 1 E xit1-IR Pause-D R 0 0 0 E xit2-IR U pdate-IR 1 0 Figure 13. TAP Controller State Diagram * Capture-IR Data are captured in parallel into the instruction register. * Capture-DR Data are captured in parallel into the data register. * SHIFT-IR LSB of the instruction register is shift in serially during a low to high transition of the TCK through TDI/TDO path * SHIFT-DR LSB of the data register is shift in serially during a low to high transition of the TCK through TDI/TDO path. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 32 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM * UPDATE-IR To shift Instruction Register Data to the parallel outputs. Instruction Register Data can be accessed through the internal bus. * UPDATE-DR To shift Data Register Data to the parallel outputs. Data Register Data can be accessed through the internal bus. * EXIT1-IR/ EXIT2-IR A transition state that terminates the scanning process. All Instruction Register data selected will retain their previous instruction state. * EXIT1-DR/ EXIT2-DR A transition state that terminates the scanning process. All Data Register data selected will retain their previous data state. * PAUSE-IR The temporary state to halt all serial shifting process between TDI and TDO. All data will retain their previous instruction state. * PAUSE-DR The temporary state to halt all serial shifting process between TDI and TDO. All data will retain their previous data state. A 4 - bit instruction register that is shifted serially at the rising edge of TCLK. The instruction is latched through the least significant bits of the nearest serial OUTPUT. 3. INSTRUCTION REGISTER Hex Value Instruction Function 0 x 00 EXTEST Select Boundary Scan Register 0 x 02 IDCODE Select Chip Identification data register 0 x 01 SAMPLE/PRELOAD Select Boundary Scan Register 0 x 03 HI-Z JTAG 0 x 0F BYPASS Select Bypass Register Table 13. JTAG Instruction Register Decoding Table * EXTEST An instruction to facilitate external circuitry and board level interconnection verification. * IDCODE An instruction to read out manufacture's identification, part number and version number. * SAMPLE/ PRE-LOAD An instruction to allow snapshots of data flowing through the system pins. SAMPLE instruction MUST be executed prior to the selection of Boundary Scan test. * HIGH Z An Instruction to place all output pins to high impedance state. * BYPASS An Instruction to allow direct serial data shifting through TDI and TDO without any device operation. 4. DATA REGISTER * Device ID Register There are three data registers, Device ID register, BYPASS register, and Boundary Scan register. These parallel-connected registers are access through the common serial input and the common serial output. A 32-bit register that contains the specific manufacturer, part number and version number. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 33 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM 31(MSB) Version (4 bits) 0x0 28 27 Part Number (16-bit) 12 11 Manufacturer ID (11-bit) 0x16E Device Part # Field CQV16100 0 x C050 CQV1690 0 x C056 CQV1680 0 x C055 CQV1670 0 x C054 CQV1660 0 x C053 CQV1650 0 x C052 CQV1640 0 x C051 CQV1630 0 x C057 1 0(LSB) 1 Table 14. Device ID Register Decode Table * BYPASS Register The data register that allows direct serial data shifting through TDI and TDO without any device operation. * BOUNDARY SCAN Register The data register that allows the serial writes and read through TDI and TDO. July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 34 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Timing Diagrams tRST MRST tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR REN WEN FWFT/SDI LOAD AREN AWEN tRSTS PFS1/PFS0 tRSTS RETZL tRSTS SFM tRSTS IPAR tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q79- 0 OE = 0 Diagram 1. Master Reset Timing July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 35 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tRST PRST tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR tRSTS tRSTR REN WEN AREN AWEN tRSTS RET tRSTS SDEN tRSTF If FWFT = 1,QRDY = 1 EMPTY / QRDY If FWFT = 0, EMPTY = 0 tRSTF If FWFT = 0, FULL = 1 FULL / DRDY If FWFT = 1, DRDY = 0 tRSTF PRAE tRSTF PRAF / HALF tRSTF OE = 1 Q79-0 OE = 0 Diagram 2. Partial Reset Timing July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 36 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 1. tRCSS tENS tRCSLZ tSKEW1 tA tENH 1 No Write tFULL 2 tDS tWCLKH DWi tENS tFULL tDH ___________ Data Read tWCLK tWCLKL tA tENH 1 No Write tFULL 2 DWi + 1 __________ Next Data Read tDS ______ LOAD = High, OE = Low. ___________ Diagram 3. Write Cycle and Full Flag Timing (Standard Mode) tDH tFULL If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, FULL will go high (after one WCLK cycle plus tFULL). If tSKEW1 is not met, then FULL will assert 1 or more WCLK cycles. NOTES: Q 79 - 0 RCS REN RCLK WEN FULL D 79 - 0 WCLK No Write CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 37 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tENS tOLZ tA tEMPTY tENS tENH tDS tSKEW1 DW1 tOEN tDH tENH tOHZ Last Word No Operation 1 tDS tENS DW2 ______________ tDH tENH tOLZ tEMPTY No Operation 2 tRCLK Last Word tENS tA tRCLKL tENH tA ______________ DW1 tEMPTY tENS tENH DW2 Diagram 4. Read Cycle, Empty Flag and First Data Word Latency Timing (Standard Mode) LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D79 - 0 WEN WCLK OE Q79- 0 EMPTY REN RCLK tRCLKH CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 38 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. 2. 3. 1. tENS tOLZ tA tEMPTY tENH tENS tDS tSKEW1 DW1 tOEN tDH tENH tOHZ Last Word 1 tDS tENS DW2 ______________ tDH tENH tOLZ tEMPTY 2 tRCLK Last Word tENS tA tRCLKL tENH DW1 tEMPTY tENS ______________ tA tENH DW2 LOAD = High. First word latency: tSKEW1 + tEMPTY + 1 * tRCLK. ___________ Diagram 5. Read Cycle and Read Chip Select Timing (Standard Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW11, EMPTY will go high (after RCLK cycle plus tEMPTY). If tSKEW1 is not met, then EMPTY will assert 1 or more RCLK cycles. NOTES: D79 - 0 WEN WCLK OE Q79 - 0 EMPTY REN RCLK tRCLKH CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 39 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 6. 3. 2. 1. tRCSS 1 DW2 tSKEW1 tDH 2 DW3 Previous Output Register Data DW1 tRCLZ 3 tDS tEMPTY tA DW4 DW[y+2] 1 DW[y+3] tSKEW2 2 DW1 DW[y+4] tDS tPRAES DW[(D-1)/2+1] DW[(D-1)/2+2] ____________ tHALF DW[(D-1)/2+3] tDS DW[D-x-1] DW[D-x] DW[D-x+1] 1 DW[D-x+2] 2 tPRAFS DW[D-x+3] DW[D-1] DWD ____________ tFULL tENH ___________ ______ ___________ y = PRAE offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. First word latency: tSKEW1 + tEMPTY + 2 * tRCLK ___________ LOAD = High, OE = Low. ___________ Diagram 6. Write Timing (FWFT Mode) If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. ___________ If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW1, QRDY will go low (after two RCLK cycle plus tEMPTY). If tSKEW1 is not met, then QRDY will assert 1 or more RCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 79 - 0 REN RCS RCLK D 79 - 0 WEN WCLK CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 40 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 3. 2. 1. DW1 tOHZ DWD tDH tOE DW1 tSKEW1 tENS tFULL tENH tA 1 DW2 DW3 tA 2 tFULL DWx+1 tSKEW2 tA 1 DWx+2 2 tPRAFS DWx+3 DW[(D-1)/2+1] DW[D-y+1] tPRAES DW[D-y+2] DW[D-1] tA ___________ DW[D-y] ___________ tA tENS ____________ DW[D-y-1] 2 ____________ tHALF DW[(D-1)/2+2] tA 1 DWD tEMPTY ________ ___________ y = PRAE Offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ LOAD = High, RCS= Low ____________ Diagram 7. Read Timing (FWFT Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more WCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 79 - 0 OE REN RCLK D79 - 0 WEN WCLK CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 41 of 54 Rev 1.0 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. tDS tENS 4. 5. 3. 2. 1. DW1 tRCSS DWD tDH tSKEW1 tENS tFULL tRCSHZ tRCSH tENH DW2 tRCSLZ 1 DW3 tA 2 tFULL DWx+2 tSKEW2 tA DWx+3 tPRAFS DWx+4 DW[(D-1)/2+1] tPRAES DW[D-y+1] DW[D-y+2] DW[D-1] tA ___________ DW[D-y] ___________ tA ____________ DW[D-y-1] ____________ tHALF DW[(D-1)/2+2] tA tENS DWD tEMPTY ______ ___________ y = PRAE Offset, x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ LOAD = High, OE = Low. ____________ Diagram 8. Read Cycle and Read Chip Select Timing (FWFT Mode) If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after one WCLK cycle plus tPRAFS) If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW1, DRDY will go low (after one WCLK cycle plus tFULL) . If tSKEW1 is not met, then DRDY will assert 1 or more WCLK cycles. NOTES: DRDY PRAF HALF PRAE QRDY Q 79 - 0 RCS REN RCLK D79 - 0 WEN WCLK CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM July 2002 Page 42 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM RCLK 1 tENS tENH 2 tRETS tENS tENH REN tA Q 79- 0 tA DWi DWi+1 tA DW1 DW2 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET tEMPTY tEMPTY EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. Upon completion of retransmit setup, a read operation can begin only after EMPTY returns high. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. Diagram 9. Retransmit Timing (Standard Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 43 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM RCLK 1 t ENS t ENH 2 t RETS 4 3 t ENS t ENH REN tA Q 79 - 0 DW i DW i+1 tA DW 1 tA DW 2 tA DW 3 DW 4 t SKEW 2 W CLK 1 2 t RETS W EN t ENS t ENH RET t EM PTY t EM PTY QRDY t PRAES PRAE t HALF HALF t PRAFS PRAF NOTES: 1. 2. 3. 4. 5. Upon completion of retransmit setup, a read operation can begin only after QRDY returns low. OE = Low. DWi = Words written to the queue after MRST . Where i = 1,2,3... depth. Upon reset completion, there must be more than 2 words written to the queue for a retransmit setup to be valid. Please refer to Table 7 for Depth. Diagram 10. Retransmit Timing (FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 44 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM RCLK 1 2 3 tENS tENH REN tA Q 79- 0 tA tA DWi+1 DWi DW1 tA DW2 tA DW3 DW4 tSKEW2 WCLK 1 2 tRETS WEN tENS tENH RET EMPTY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the Empty Flag ( EMPTY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. OE = Low; enables data to be read on outputs Q79 - 0. DW1= first word written to the queue after Master Reset; DW2= second word written to the queue after Master Reset. No more than D-2 may be written to the queue between reset (Master or Partial) and retransmit setup. Therefore, FULL will be high throughout the retransmit setup procedure. Please refer to Table 7 for Depth. There must be at least two words written to zero latency retransmit from the queue before a retransmit operation can be invoked. RETZL is set Low during MRST . Diagram 11. Zero Latency Retransmit Timing (Standard Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 45 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM RCLK 1 2 3 4 5 tENH tENS REN tA tA DWi Q 79 - 0 tA DW i+1 tA DW1 DW2 tA tA DW3 DW4 DW5 tSKEW2 WCLK tRETS WEN tENS tENH RET QRDY tPRAES PRAE tHALF HALF tPRAFS PRAF NOTES: 1. 2. 3. 4. 5. 6. If the part is empty at the point of retransmit, the output ready flag ( QRDY ) will be updated based on RCLK (Retransmit Clock cycle). Valid data will appear on the output. No more than D-2 words maybe written to the queue between reset (Master or Partial) and retransmit setup. Therefore, DRDY will be low throughout the retransmit setup procedure. Please refer to Table 7 for Depth. OE = Low. DW1, DW2, DW3 = first, second and third words written to the queue after Master Reset. There must be at least two words written to the queue before a retransmit operation can be invoked. RETZL is set low during MRST . Diagram 12. Zero Latency Retransmit Timing (FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 46 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM SCLK tENS tENH tENH tLOADH tLOADH SDEN tLOADS LOAD tDS SDI tDH BIT 0 BIT MSB BIT 0 BIT MSB PRAF offset PRAE offset *Refer to Table 13 Diagram 13. Serial Loading of Programmable Flag Registers (Standard and FWFT Mode) MSB CQV16100 CQV1690 CQV1680 CQV1670 CQV1660 CQV1650 CQV1640 CQV1630 15 14 13 12 11 10 9 8 Table 13. Reference Table for Diagram 13 July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 47 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLK tWCLKH tWCLKL WCLK tLOADS tLOADH tLOADH LOAD tENS tENH tENH WEN tDS tDH tDS tDH D 79 - 0 PRAE offset PRAF offset Diagram 14. Parallel Loading of Programmable Flag Registers for (Standard and FWFT Mode) tRCLK tRCLKH tRCLKL RCLK tLOADS tLOADH tLOADH tENH tENH LOAD tENS REN tA Q 79- 0 tA Output Register Data PRAE offset PRAF offset Diagram 15. Parallel Read of Programmable Flag Registers for (Standard and FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 48 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLK tWCLKH tWCLKL WCLK tENS tENH AWEN WEN tDS tDH D 79 - 0 Data for Switching Control Register Diagram 16. Programming the Switching Control Register tRCLK tRCLKH tRCLKL RCLK tENS tENH AREN REN tA Q 79- 0 Output Register Data Switching Control Register Content Diagram 17. Reading the Switching Control Register July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 49 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLKH tWCLKL WCLK 1 tENS 2 1 WEN tPRAFS PRAF 2 tENH tPRAFS D - x words in Queue D - ( x + 1 ) words in Queue tSKEW2 D-(x+1) words in Queue RCLK tENS tENH REN NOTES: 1. 2. 3. 4. ___________ x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. ___________ If the time between a rising edge of RCLK to the rising edge of WCLK is greater than or equal to tSKEW2, PRAF will go high (after on WCLK cycle ___________ plus tPRAFS). If tSKEW2 is not met, then PRAF will assert 1 or more WCLK cycles. ___________ PRAF synchronizes to the rising edge of WCLK only. Diagram 18. Synchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 50 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLKH tWCLKL WCLK tWCLKH tWCLKL WEN y words in Queue(2) ; y+1 words in Queue(3) PRAE tSKEW2 RCLK tPRAES 1 y words in Queue(2) ; y+1 words in Queue(3) y+1 words in Queue(2) ; y+2 words in Queue(3) tPRAES 2 1 tENS 2 tENH REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. If the time between a rising edge of WCLK to the rising edge of RCLK is greater than or equal to tSKEW2, PRAE will go high (after one RCLK cycle plus tPRAES). If tSKEW2 is not met, then PRAE will assert 1 or more RCLK cycles. PRAE synchronizes to the rising edge of RCLK only. Diagram 19. Synchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 51 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLKH tWCLKL WCLK tENS tENH WEN tPRAFA D - x words in Queue D - ( x + 1) words in Queue PRAF D - ( x + 1) words in Queue tPRAFA RCLK tENS REN NOTES: 1. 2. 3. 4. x = PRAF offset. D = maximum queue depth. Please refer to Table 7 for Depth. PRAF is asserted to low on WCLK transition and reset to high on RCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 20. Asynchronous Programmable Almost-Full Flag Timing (Standard and FWFT Mode) tWCLKH tWCLKL WCLK tENS tENH WEN tPRAEA PRAE y+1 words in Queue(2); y+2 words in Queue (3) y words in Queue(2); y+1 words in Queue(3) y words in Queue(2); y+1 words in Queue(3) tPRAEA RCLK tENS REN NOTES: 1. 2. 3. 4. 5. y = PRAE offset. For Standard Mode. For FWFT Mode. PRAE is asserted to low on RCLK transition and reset to high on WCLK transition. Select this mode by setting SFM low during Master Reset. Diagram 21. Asynchronous Programmable Almost-Empty Flag Timing (Standard and FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 52 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM tWCLKH tWCLKL WCLK tENS tENH WEN D/2 + 1 words in Queue(1); [(D+1)/2 + 1] words in Queue(2) tHALF HALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) tHALF D/2 words in Queue(1); [(D+1)/2] words in Queue(2) RCLK tENS REN NOTES: 1. 2. 3. For Standard Mode. For FWFT Mode. Please refer to Table 7 for Depth. Diagram 22. Half-Full Flag Timing (Standard and FWFT Mode) July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 53 of 54 CQV16100 * CQV1690 * CQV1680 * CQV1670 * CQV1660 * CQV1650 * CQV1640 * CQV1630 ChannelQTM Order Information: HBA Device Family Device Type Power Speed (ns) * Package** Temperature Range XX XXXXX X XX XX X CQ V16100 (65,536 x 80) Low 6 BB Blank - Commercial (0C to 70C) - 166 MHz V1690 (32,768 x 80) 7-5 - 133 MHz V1680 (16,384 x 80) 10 - 100 MHz I - Industrial (-40 to 85C) V1670 (8,192 x 80) V1660 (4,096 x 80) V1650 (2,048 x 80) V1640 (1,024 x 80) V1630 (512 x 80) *Speed - 6ns available only in Commercial temp (0C to 70C) **Package - 256 pin Fine Pitch Ball Grid Array (BGA) Example: CQV1670L6BB CQV1660L10BBI (8k x 80, 6ns, Commercial temp) (4k x 80, 10ns, Industrial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA www.hba.com Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 Tel: 886.3.516.9118 Fax: 886.3.516.9181 July 2002 3C080B (c) 2001 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Rev 1.0 Page 54 of 54