Integrated
Circuit
Systems, Inc.
ICS9S857
Preliminary Product Preview
Low-Voltage 10-Bit FET BUS Switch With
Internal Pulldown Resistors
9S857 Rev A 7/31/00
Pin Configuration
24-Pin TSSOP
Product Features:
Full DDR solution provided when used with
ICSSSTV16857 and ICS93857
Enable signal is SSTL_2 compatible
Flow-through architecture optimizes PCB layout
Designed for use with 200 Mbit/s Double Data-Rate
(DDR) SDRAM applications
Switch On-state restance is designed to eliminate series
resistor to DDR SDRAM
Internal 10W pulldown resistors to ground on B port
Internal 50W pullup resistor on Output-Enable
(OE#) input
Latch-up perfromance exceeds 100 mA per JESD 78,
Class II
Available in 24 pin TSSOP package
VREF
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
GND
VDD
OE#
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
ICS9S857
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
OE#
A1 B1
222
1311
1
23
A10 B10
VREF
RINT
RINT
SW
SW
(OE#)
AB
Logic Diagram (Positive Logic) Simplified Shcematic, Each FET Switch
Function Table
TUPNI #EO NOITCNUF
L
HtropB=tropA tcennocsiD
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
2
ICS9S857
Preliminary Product Preview
Pin Descriptions
REBMUNNIPEMANNIPEPYTNOITPIRCSED
1FERVTUOegatlovtuptuoecnerefeR
,9,8,7,6,5,4,3,2 11,01 01A-1ANIstupnI
21DNGRWPdnuorG
,81,91,02,12,22 ,31,41,51,61,71 01B-1BTUOstuptuO
32#EONIelbanEtuptuO
42DDVRWP)V6.3(ylppusrewoP
LOBMYSRETEMARAPSNOITIDNOCGNITARTINU
V
DD
egatloVylppusCD 6.4+ot5.0-V
I
KI
tnerrucpmalctupniCDV
O/I
0<05-Am
V
I
)ylno#EO(egnaregatlovtupniCD
2
V
DD
5.0+V
T
gts
egnarerutarepmetegarotS 051ot56-C°
V
I
)#EOtpecxe(egatlovtupniCD
2
6.4ot5.0-V
Absolute Maximum Ratings
Notes:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under " recommended operating
conditions' is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings
are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
LOBMYSRETEMARAP STIMIL
NIMPYTXAMTINU
V
DD
egatloVylppusCD33.36.3V
V
FER
Vx83.0(egatlovecnerefeR
DD
)51.152.153.1V
V
HI
tupnilevel-hgihCA V
FER
+
Vm053 V
V
LI
egatlovtupnilevel-wolCAV
FER
Vm053-V
V
HI
egatlovtupnilevel-hgihCD V
FER
+
Vm081 V
V
LI
egatlovtupnilevel-wolCDV
FER
Vm081-V
T
bma
egnarerutarepmetria-eerfgnitarepO058+C°
Recommended Operating Condidions
3
ICS9S857
Preliminary Product Preview
Ordering Information
ICS9S857yGT
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
MIN MAX MIN MAX
A - 1.20 - 0.047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 4.30 4.50 .169 .177
e 0.50 BASIC 0.020 BASIC
L 0.45 0.75 .018 .030
N
α0° 8° 0° 8°
aaa - 0.10 - .004
VARIATIONS
MIN MAX MIN MAX
20 4.90 5.10 .193 .201
24 6.40 6.60 .252 .260
28 7.70 7.90 .303 .311
30 7.70 7.90 .303 .311
36 9.60 9.80 .378 .386
38 9.60 9.80 .378 .386
44 10.90 11.10 .429 .437
50 12.40 12.60 .488 .496
MO-153 JEDEC
Doc.# 10-0036 7/6/00 Rev B
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
In Millimeters
COMMON DIMENSIONS In Inches
COMMON DIMENSIONS
SEE VARIATIONS
6.40 BASIC 0.252 BASIC
ND mm. D (inch)
SEE VARIATIONS
4.40 mm. Body, 0.50 mm. pitch TSSOP
(173 mil) (0.020 mil)
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
