LT8580IDD#PBF - ANALOG DEVICES

LT8580

Rev. B

For more information www.analog.com

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Boost/SEPIC/Inverting

DC/DC Converter with 1A, 65V

Switch, Soft-Start and Synchronization

The LT

8580 is a PWM DC/DC converter containing an

internal 1A, 65V switch. The LT8580 can be configured

as either a boost, SEPIC or inverting converter.

The LT8580 has an adjustable oscillator, set by a resistor

from the RT pin to ground. Additionally, the LT8580 can be

synchronized to an external clock. The switching frequency

of the part may be free running or synchronized, and can

be set between 200kHz and 1.5MHz.

The LT8580 also features innovative SHDN pin circuitry

that allows for slowly varying input signals and an adjust-

able undervoltage lockout function.

Additional features such as frequency foldback and

soft-start are integrated. The LT8580 is available in tiny

thermally enhanced 3mm × 3mm 8-lead DFN and 8-lead

MSOP packages.

1.5MHz, 5V to 12V Boost Converter

n 1A, 65V Power Switch

n Adjustable Switching Frequency

n Single Feedback Resistor Sets VOUT

n Synchronizable to External Clock

n High Gain SHDN Pin Accepts Slowly Varying

Input Signals

n Wide Input Voltage Range: 2.55V to 40V

n Low VCESAT Switch: 400mV at 0.75A (Typical)

n Integrated Soft-Start Function

n Easily Configurable as a Boost, SEPIC, or Inverting

Converter

n User Configurable Undervoltage Lockout (UVLO)

n Pin Compatible with LT3580

n Tiny Thermally Enhanced 8-Lead 3mm × 3mm DFN

and 8-Lead MSOP Packages

n AEC-Q100 Qualification in Progress

n VFD Bias Supplies

n TFT-LCD Bias Supplies

n GPS Receivers

n DSL Modems

n Local Power Supply

Efficiency and Power Loss

All registered trademarks and trademarks are the property of their respective owners.

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100

8580 TA01b

50 150 200

180

300

480

240

120

360

420

EFFICIENCY

POWER LOSS

4.7µF

VOUT

12V

200mA

15µH

130k

VIN

VIN SW

8580 TA01a

LT8580

10k

6.04k

56.2k

SHDN

GND

FBX

VCSYNC

SSRT

3.3nF

47pF

0.22µF

2.2µF

Document Feedback

LT8580

Rev. B

For more information www.analog.com

ABSOLUTE MAXIMUM RATINGS

VIN Voltage .................................................–0.3V to 40V

SW Voltage ................................................–0.4V to 65V

RT Voltage ...................................................–0.3V to 5V

SS Voltage ................................................–0.3V to 2.5V

FBX Voltage .................................................................5V

FBX Current ............................................................–1mA

VC Voltage ...................................................–0.3V to 2V

(Note 1)

TOP VIEW

DD PACKAGE

8-LEAD (3mm × 3mm) PLASTIC DFN

GND

1FBX

VIN

SYNC

SHDN

θJA = 43°C/W

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

FBX

VIN

SYNC

SHDN

TOP VIEW

GND

MS8E PACKAGE

8-LEAD PLASTIC MSOP

θJA = 35°C/W TO 40°C/W

EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT8580EDD#PBF LT8580EDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT8580IDD#PBF LT8580IDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 125°C

LT8580HDD#PBF LT8580HDD#TRPBF LGKH 8-Lead (3mm × 3mm) Plastic DFN –40°C to 150°C

LT8580EMS8E#PBF LT8580EMS8E#TRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 125°C

LT8580IMS8E#PBF LT8580IMS8E#TRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 125°C

LT8580HMS8E#PBF LT8580HMS8E#TRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 150°C

AUTOMOTIVE PRODUCTS**

LT8580EMS8E#WPBF LT8580EMS8E#WTRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 125°C

LT8580IMS8E#WPBF LT8580IMS8E#WTRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 125°C

LT8580HMS8E#WPBF LT8580HMS8E#WTRPBF LTGKJ 8-Lead Plastic MSOP –40°C to 150°C

Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These

models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your

local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for

thesemodels.

SHDN Voltage ............................................–0.3V to 40V

SYNC Voltage ............................................–0.3V to 5.5V

Operating Junction Temperature Range

LT8580E (Notes 2, 5) .........................–40°C to 125°C

LT8580I (Notes 2, 5) ..........................–40°C to 125°C

LT8580H (Notes 2, 5) ........................–40°C to 150°C

Storage Temperature Range ..................–65°C to 150°C

LT8580

Rev. B

For more information www.analog.com

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LT8580E is guaranteed to meet performance specifications

from 0°C to 125°C junction temperature. Specifications over the –40°C

to 125°C operating junction temperature range are assured by design,

characterization and correlation with statistical process controls. The

LT8580I is guaranteed over the full –40°C to 125°C operating junction

temperature range. The LT8580H is guaranteed over the full –40°C to

150°C operating junction temperature range. Operating lifetime is derated

at junction temperatures greater than 125°C.

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN unless otherwise noted. (Note 2)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Operating Voltage Range LT8580E, LT8580I

LT8580H

2.55

2.9 40

40 V

Positive Feedback Voltage l1.185 1.204 1.220 V

Negative Feedback Voltage l–3 3 12 mV

Positive FBX Pin Bias Current VFBX = Positive Feedback Voltage, Current Into Pin l81 83.3 85 µA

Negative FBX Pin Bias Current VFBX = Negative Feedback Voltage, Current Out of Pin l81 83.3 86 µA

Error Amplifier Transconductance 200 µmhos

Error Amplifier Voltage Gain 60 V/V

Quiescent Current VSHDN = 2.5V, Not Switching 1.2 1.7 mA

Quiescent Current in Shutdown VSHDN = 0V 0 1 µA

Reference Line Regulation 2.5V ≤ VIN ≤ 40V 0.01 0.05 %/V

Switching Frequency, fOSC RT = 56.2k

RT = 422k

1.23

165 1.5

200 1.77

235 MHz

kHz

Switching Frequency in Foldback Compared to Normal fOSC 1/6 Ratio

Switching Frequency Set Range SYNCing or Free Running l200 1500 kHz

SYNC High Level for Synchronization l1.3 V

SYNC Low Level for Synchronization l0.4 V

SYNC Clock Pulse Duty Cycle VSYNC = 0V to 2V 35 65 %

Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4

Minimum Off-Time 100 ns

Minimum On-Time 120 ns

Switch Current Limit Minimum Duty Cycle (Note 3)

Maximum Duty Cycle (Notes 3, 4), fOSC = 1.5MHz

Maximum Duty Cycle (Notes 3, 4), fOSC = 200kHz

1.2

0.6

0.4

1.5

0.8

1.8

1.5

1.4

Switch VCESAT ISW = 0.75A 400 mV

Switch Leakage Current VSW = 5V 0.01 1 µA

Soft-Start Charging Current VSS = 0.5V l4 6 8 µA

SHDN Minimum Input

Voltage High Active Mode, SHDN Rising

Active Mode, SHDN Falling

1.23

1.21 1.31

1.27 1.4

1.33 V

SHDN Input Voltage Low Shutdown Mode l0.3 V

SHDN Pin Bias Current VSHDN = 3V

VSHDN = 1.3V

VSHDN = 0V

944

0.1

µA

SHDN Hysteresis 40 mV

Note 3: Current limit guaranteed by design and/or correlation to static test.

Note 4: Current limit measured at equivalent of listed switching frequency.

Note 5: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

LT8580

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

Switch Current Limit vs Duty Cycle Switch Saturation Voltage Commanded Switch Current vs SS

Switch Current Limit

vs Temperature

Positive and Negative Output

Voltage Regulation

Positive and Negative FBX Current

at Output Voltage Regulation Oscillator Frequency

TA = 25°C, unless otherwise specified

DUTY CYCLE (%)

SWITCH CURRENT LIMIT (A)

0.50

0.75

0.25

1.00

1.25

1.50

1.75

30 50 70 90

8580 G01

2.00

20 40 60 80

SWITCH CURRENT (A)

SATURATION VOLTAGE (mV)

400

500

600

1.5

8580 G02

300

200

00.50.25 0.75 11.25

100

700

SS VOLTAGE (V)

SWITCH CURRENT (A)

0.5

1.0

1.5

2.0

0.2 0.4 0.6 0.8

8580 G03

1 1.2

TEMPERATURE (°C)

–50 –25

SWITCH CURRENT LIMIT (A)

0.5

1.0

1.5

2.0

0 5025 125 15010075

8580 G04

TEMPERATURE (°C)

–50 –25

1.170

POSITIVE FBX VOLTAGE (V)

NEGATIVE FBX VOLTAGE (mV)

1.200

1.220

050 75

8580 G05

1.175

1.180

1.185

1.190

1.195

1.215

1.210

1.205

–20

–10

–15

–5

25 100 150125

TEMPERATURE (°C)

–50 –25

POSITIVE FBX CURRENT INTO PIN (µA)

NEGATIVE FBX CURRENT OUT OF PIN (µA)

050 75

8580 G06

25 100 150125

TEMPERATURE (°C)

–50 –25

FREQUENCY (MHz)

0.8

1.0

1.2

1.4

8580 G07

0.6

0.4

005025 75 100 125 150

0.2

1.8

1.6 RT = 56.2k

RT = 422k

LT8580

Rev. B

For more information www.analog.com

TYPICAL PERFORMANCE CHARACTERISTICS

SHDN Pin Current

SHDN Pin Current Active/Lockout Threshold

TA = 25°C, unless otherwise specified

Oscillator Frequency During

Soft-Start Internal UVLO

FBX VOLTAGE (V)

NORMALIZED OSCILLATOR FREQUENCY (F/FNOM)

1/4

1/2

1/3

1/6

1/5

0.2 0.4

INVERTING

CONFIGURATIONS NONINVERTING

CONFIGURATIONS

0.6 0.8

8580 G08

1 1.2

TEMPERATURE (°C)

–50 –25

2.1

VIN VOLTAGE (V)

2.2

2.7

2.4

2.3

0 5025 75

8580 G09

2.5

2.6

125100 150

SHDN VOLTAGE (V)

SHDN PIN CURRENT (µA)

0.50.25 1 1.50.75 1.25 1.75 2

8580 G10

125°C

25°C

–40°C

SHDN VOLTAGE (V)

SHDN PIN CURRENT (µA)

200

250

300

350

400

15 25

8580 G11

150

100

5 10 20 30 35 40

125°C

25°C

–40°C

TEMPERATURE (°C)

–50 –25

1.20

SHDN VOLTAGE (V)

1.22

1.26

1.28

1.30

1.40

1.34

0 50 75

8580 G12

1.24

1.36

1.38

1.32

100 125 150

SHDN RISING

SHDN FALLING

Minimum On Time

vs Temperature

TEMPERATURE (°C)

–50 –25

MINIMUM ON TIME (NS)

100

150

400

250

0 50 75

8580 G13

300

350

200

100 125 150

RECOMMENDED MINIMUM ON TIME

MEASURED MINIMUM ON TIME

LT8580

Rev. B

For more information www.analog.com

BLOCK DIAGRAM

PIN FUNCTIONS

FBX (Pin 1): Positive and Negative Feedback Pin. For a

noninverting or inverting converter, tie a resistor from the

FBX pin to VOUT according to the following equations:

RFBX =VOUT −1.204V

( )

83.3µA ; Noninverting Converter

RFBX =VOUT + 3mV

( )

83.3µA ; Inverting Converter

VC (Pin 2): Error Amplifier Output Pin. Tie external com-

pensation network to this pin.

VIN (Pin 3): Input Supply Pin. Must be locally bypassed.

SW (Pin 4): Switch Pin. This is the collector of the internal

NPN Power switch. Minimize the metal trace area connec-

ted to this pin to minimize EMI.

SHDN (Pin 5): Shutdown Pin. In conjunction with the

UVLO (undervoltage lockout) circuit, this pin is used

to enable/disable the chip and restart the soft-start

sequence. Drive below 1.21V to disable the chip. Drive

above 1.40V to activate the chip and restart the soft-start

sequence. Do not float this pin.

RT (Pin 6): Timing Resistor Pin. Adjusts the switching

frequency. Place a resistor from this pin to ground to set

the frequency to a fixed free running level. Do not float

this pin.

SS (Pin 7): Soft-Start Pin. Place a soft-start capacitor here.

Upon start-up, the SS pin will be charged by a (nominally)

280k resistor to about 2.1V.

SYNC (Pin 8): To synchronize the switching frequency to

an outside clock, simply drive this pin with a clock. The

high voltage level of the clock needs to exceed 1.3V, and

the low level should be less 0.4V. Drive this pin to less

than 0.4V to revert to the internal free-running clock. See

the Applications Information section for more information.

GND (Exposed Pad Pin 9): Ground. Exposed pad must

be soldered directly to local ground plane.

–

∑

31.204V

REFERENCE

ADJUSTABLE

OSCILLATOR

FREQUENCY

FOLDBACK

SLOPE

COMPENSATION

COMPARATOR

DISCHARGE

DETECT

SS VC

280k

SR2

14.5k

QSR1

SYNC

÷N

SHDN

FBX

1.3V

0.02Ω

GND

RFBX

DRIVER

ILIMIT

VIN

VOUT

CSS CCCIN

RCVIN

SOFT-

START

SYNC

BLOCK

UVLO

RSQ

8580 BD

50k

LT8580

Rev. B

For more information www.analog.com

OPERATION

Figure 1. SEPIC Topology Allows for the Input to Span

the Output Voltage. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

Figure 2. Dual Inductor Inverting Topology Results in

Low Output Ripple. Coupled or Uncoupled Inductors

Can Be Used. Follow Noted Phasing if Coupled

SHUTDOWN

VIN > VOUT

VIN = VOUT

VIN < VOUT

OUT

VIN SW

8580 F01

LT8580

SHDN

GND

FBX

SYNC SS

CSS

•

SHUTDOWN

VIN VOUT

VIN SW

8580 F02

LT8580

SHDN

GND

FBX

SYNC SS

CSS

•

The LT8580 uses a constant-frequency, current mode con-

trol scheme to provide excellent line and load regulation.

Refer to the Block Diagram for the following description

of the part’s operation. At the start of each oscillator cycle,

the SR latch (SR1) is set, which turns on the power switch,

Q1. The switch current flows through the internal current

sense resistor, generating a voltage proportional to the

switch current. This voltage (amplified by A4) is added

to a stabilizing ramp and the resulting sum is fed into the

positive terminal of the PWM comparator A3. When this

voltage exceeds the level at the negative input of A3, the

SR latch is reset, turning off the power switch. The level

at the negative input of A3 (VC pin) is set by the error

amplifier A1 (or A2) and is simply an amplified version of

the difference between the feedback voltage (FBX pin) and

the reference voltage (1.204V or 3mV, depending on the

configuration). In this manner, the error amplifier sets the

correct peak current level to keep the output in regulation.

The LT8580 has an FBX pin architecture that can be used

for either noninverting or inverting configurations. When

configured as a noninverting converter, the FBX pin is

pulled up to the internal bias voltage of 1.204V by the

RFBX resistor connected from VOUT to FBX. Amplifier A2

becomes inactive and amplifier A1 performs the invert-

ing amplification from FBX to VC. When the LT8580 is in

an inverting configuration, the FBX pin is pulled down to

3mV by the RFBX resistor connected from VOUT to FBX.

Amplifier A1 becomes inactive and amplifier A2 performs

the noninverting amplification from FBX to VC.

SEPIC Topology

As shown in Figure 1, the LT8580 can be configured as

a SEPIC (single-ended primary inductance converter).

This topology allows for the input to be higher, equal, or

lower than the desired output voltage. Output disconnect

is inherently built into the SEPIC topology, meaning no DC

path exists between the input and output. This is useful

for applications requiring the output to be disconnected

from the input source when the circuit is in shutdown.

Inverting Topology

The LT8580 can also work in a dual inductor inverting

topology, as shown in Figure 2. The part’s unique feedback

pin allows for the inverting topology to be built by simply

changing the connection of external components. This

solution results in very low output voltage ripple due to

the inductor L2 in series with the output. Abrupt changes

in output capacitor current are eliminated because the

output inductor delivers current to the output during both

the off-time and the on-time of the LT8580 switch.

LT8580

Rev. B

For more information www.analog.com

Start-Up Operation

Several functions are provided to enable a very clean

start-up for the LT8580.

• First, the SHDN pin voltage is monitored by an internal

voltage reference to give a precise turn-on voltage level.

An external resistor (or resistor divider) can be connected

from the input power supply to the SHDN pin to provide

a user-programmable undervoltage lockout function.

• Second, the soft-start circuitry provides for a gradual

ramp-up of the switch current. When the part is brought

out of shutdown, the external SS capacitor is first

discharged (providing protection against SHDN pin

glitches and slow ramping), then an integrated 280k

resistor pulls the SS pin up to ~2.1V. By connecting an

external capacitor to the SS pin, the voltage ramp rate

on the pin can be set. Typical values for the soft-start

capacitor range from 100nF to 1µF.

• Finally, the frequency foldback circuit reduces the switch-

ing frequency when the FBX pin is in a nominal range

of 300mV to 920mV. This feature reduces the minimum

duty cycle that the part can achieve thus allowing better

control of the switch current during start-up. When the

FBX voltage is pulled outside of this range, the switching

frequency returns to normal.

Current Limit and Thermal Shutdown Operation

The LT8580 has a current limit circuit not shown in the

Block Diagram. The switch current is constantly monitored

and not allowed to exceed the maximum switch current at

a given duty cycle (see the Electrical Characteristics table).

If the switch current reaches this value, the SR latch (SR1)

is reset regardless of the state of the comparator (A1/

A2). Also, not shown in the Block Diagram is the thermal

shutdown circuit. If the temperature of the part exceeds

approximately 165°C, the SR2 latch is set regardless of the

state of the amplifier (A1/A2). When the part temperature

falls below approximately 160°C, a full soft-start cycle will

then be initiated. The current limit and thermal shutdown

circuits protect the power switch as well as the external

components connected to the LT8580.

OPERATION

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

For the SEPIC or dual inductor inverting topology (see

Figure 1 and Figure 2):

DC ≅VD+|VOUT|

+|V

OUT

|+V

−V

CESAT

The LT8580 can be used in configurations where the duty

cycle is higher than DCMAX, but it must be operated in the

discontinuous conduction mode so that the effective duty

cycle is reduced.

Inductor Selection

General Guidelines

: The high frequency operation of the

LT8580 allows for the use of small surface mount inductors.

For high efficiency, choose inductors with high frequency

core material, such as ferrite, to reduce core losses. To

improve efficiency, choose inductors with more volume

for a given inductance. The inductor should have low

DCR (copper wire resistance) to reduce I2R losses, and

must be able to handle the peak inductor current without

saturating. Note that in some applications, the current

handling requirements of the inductor can be lower, such

as in the SEPIC topology, where each inductor only carries

a fraction of the total switch current. Multilayer or chip

inductors usually do not have enough core area to sup-

port peak inductor currents in the 1A to 2A range. To

minimize radiated noise, use a toroidal or shielded induc-

tor. Note that the inductance of shielded types will drop

more as current increases, and will saturate more easily.

See Table 1 for a list of inductor manufacturers. Thorough

lab evaluation is recommended to verify that the following

guidelines properly suit the final application.

Table 1. Inductor Manufacturers

Coilcraft XAL5050, MSD7342, MSS7341 and

LPS4018 Series www.coilcraft.com

Coiltronics DR, DRQ, LD and CD Series www.coiltronics.com

Sumida CDRH8D58/LD, CDRH64B, and

CDRH70D430MN Series www.sumida.com

Würth WE-PD, WE-DD, WE-TPC,

WE-LHMI and WE-LQS Series www.we-online.com

Minimum Inductance

: Although there can be a trade-off

with efficiency, it is often desirable to minimize board

space by choosing smaller inductors. When choosing

Setting Output Voltage

The output voltage is set by connecting a resistor (RFBX)

from VOUT to the FBX pin. RFBX is determined from the

following equation:

RFBX =|VOUT −VFBX|

83.3µA

where VFBX is 1.204V (typical) for noninverting topologies

(i.e., boost and SEPIC regulators) and 3mV (typical) for

inverting topologies (see the Electrical Characteristics).

Power Switch Duty Cycle

In order to maintain loop stability and deliver adequate

current to the load, the power NPN (Q1 in the Block Dia-

gram) cannot remain “on” for 100% of each clock cycle.

The maximum allowable duty cycle is given by:

DCMAX =(TP−MinOff Time)

• 100%

where TP is the clock period and Min Off Time (found in

the Electrical Characteristics) is typically 100ns.

The application should be designed so that the operating

duty cycle does not exceed DCMAX.

The minimum allowable duty cycle is given by:

DCMIN =

Min On Time

•100%

where TP is the clock period and Minimum On Time is as

shown in the Typical Performance Characteristics.

The application should be designed so that the operating

duty cycle is at least DCMIN.

Duty cycle equations for several common topologies are

given below, where VD is the diode forward voltage drop

and VCESAT is typically 400mV at 0.75A.

For the boost topology:

DC ≅

OUT −

IN +

OUT

−V

CESAT

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

an inductor, there are two conditions that limit the mini-

mum inductance: (1) providing adequate load current,

and (2) avoiding subharmonic oscillation. Choose an

inductance that is high enough to meet both of these

requirements.

Adequate Load Current

: Small value inductors result in

increased ripple currents and thus, due to the limited peak

switch current, decrease the average current that can be

provided to a load (IOUT). In order to provide adequate

load current, L should be at least:

LBOOST >

DC • V

2(f) ILIM −|VOUT| • IOUT

•h

⎛

⎝

⎜⎞

⎠

⎟

for boost, topologies, or:

LDUAL >DC • VIN

2(f) ILIM−VOUT • IOUT

VIN •h−IOUT

⎛

⎝

⎜⎞

⎠

⎟

for the SEPIC and inverting topologies.

where:

LBOOST = L1 for boost topologies (see Figure 15)

LDUAL = L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

LDUAL = L1||L2 for uncoupled dual inductor topologies

(see Figure 16 and Figure 17)

DC = switch duty cycle (see previous section)

ILIM = switch current limit, typically about 1.2A at 50%

duty cycle (see the Typical Performance Characteristics

section).

h = power conversion efficiency (typically 85% for boost

and 83% for dual inductor topologies at high currents).

f = switching frequency

IOUT = maximum load current

Negative values of L indicate that the output load current

IOUT exceeds the switch current limit capability of the

LT8580.

Avoiding Subharmonic Oscillations

: The LT8580’s internal

slope compensation circuit can prevent subharmonic oscil-

lations that can occur when the duty cycle is greater than

50%, provided that the inductance exceeds a minimum

value. In applications that operate with duty cycles greater

than 50%, the inductance must be at least:



LMIN >

1.25 • (DC −300ns • f) • f 



−

1−DC

LMIN = L1 for boost topologies (see Figure 15)

LMIN = L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

LMIN = L1||L2 for uncoupled dual inductor topologies

(see Figure 16 and Figure 17)

Maximum Inductance

: Excessive inductance can reduce

current ripple to levels that are difficult for the current com-

parator (A3 in the Block Diagram) to cleanly discriminate,

thus causing duty cycle jitter and/or poor regulation. The

maximum inductance can be calculated by:

LMAX =VIN −VCESAT

MIN-RIPPLE

•DC

where

LMIN = L1 for boost topologies (see Figure 15)

LMIN = L1 = L2 for coupled dual inductor topologies

(see Figure 16 and Figure 17)

LMIN = L1||L2 for uncoupled dual inductor topologies

(see Figure 16 and Figure 17)

IMIN(RIPPLE) = typically 80mA

Current Rating

: Finally, the inductor(s) must have a rating

greater than its peak operating current to prevent inductor

saturation resulting in efficiency loss. In steady state, the

peak input inductor current (continuous conduction mode

only) is given by:

IL1-PEAK =

OUT

• I

OUT

•

+VIN • DC

2 • L1• f

for the boost, SEPIC and dual inductor inverting topologies.

LT8580

Rev. B

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APPLICATIONS INFORMATION

For dual dual inductor topologies, the peak output inductor

current is given by:

IL2-PEAK = IOUT +VOUT • 1−DC

( )

2 • L2 • f

For the dual inductor topologies, the total peak current is:

IL-PEAK =IOUT 1+VOUT

h• V

⎡

⎣

⎢

⎤

⎦

⎥+VIN • DC

2 • L • f

Note: Peak inductor current is limited by the switch current

limit. Refer to the Electrical Characteristics table and to

the Switch Current Limit vs Duty Cycle plot in the Typical

Performance Characteristics.

Capacitor Selection

Low ESR (equivalent series resistance) capacitors should

be used at the output to minimize the output ripple voltage.

Multilayer ceramic capacitors are an excellent choice, as

they have an extremely low ESR and are available in very

small packages. X5R or X7R dielectrics are preferred, as

these materials retain their capacitance over wider voltage

and temperature ranges. A 0.47µF to 10µF output capacitor

is sufficient for most applications. Always use a capacitor

with a sufficient voltage rating. Many ceramic capacitors,

particularly 0805 or 0603 case sizes, have greatly reduced

capacitance at the desired output voltage. Solid tantalum

or OS-CON capacitors can be used, but they will occupy

more board area than a ceramic and will have a higher

ESR with greater output ripple.

Ceramic capacitors also make a good choice for the input

decoupling capacitor, which should be placed as closely

as possible to the VIN pin of the LT8580 as well as to the

inductor connected to the input of the power path. If it is

not possible to optimally place a single input capacitor,

then use one at the VIN pin of the chip (CVIN) and one at

the input of the power path (CPWR). See equations in

Table 4, Table 5 and Table 6 for sizing information. A 1µF

to 2.2µF input capacitor is sufficient for most applications.

Table 2 shows a list of several ceramic capacitor manufac-

turers. Consult the manufacturers for detailed information

on their entire selection of ceramic parts.

Table 2. Ceramic Capacitor Manufacturers

Kemet www.kemet.com

Murata www.murata.com

Taiyo Yuden www.t-yuden.com

TDK www.tdk.com

Compensation—Adjustment

To compensate the feedback loop of the LT8580, a series

resistor-capacitor network in parallel with a single capacitor

should be connected from the VC pin to GND. For most

applications, the series capacitor should be in the range

of 470pF to 2.2nF with 1nF being a good starting value.

The parallel capacitor should range in value from 10pF to

100pF with 47pF a good starting value. The compensation

resistor, RC, is usually in the range of 5k to 50k. A good

technique to compensate a new application is to use a

100kΩ potentiometer in place of series resistor RC. With

the series capacitor and parallel capacitor at 1nF and 47pF

respectively, adjust the potentiometer while observing

the transient response and the optimum value for RC can

be found. Figure 3 (3a to 3c) illustrates this process for

the circuit of Figure 4 with a load current stepped be-

tween 60mA and 160mA. Figure 3a shows the transient

response with RC equal to 2k. The phase margin is poor,

as evidenced by the excessive ringing in the output

voltage and inductor current. In Figure 3b, the value of

RC is increased to 3k, which results in a more damped

response. Figure 3c shows the results when RC is increased

further to 6.04k. The transient response is nicely damped

and the compensation procedure is complete.

Compensation—Theory

Like all other current mode switching regulators, the

LT8580 needs to be compensated for stable and efficient

operation. Two feedback loops are used in the LT8580—

a fast current loop which does not require compensation,

and a slower voltage loop which does. Standard bode plot

analysis can be used to understand and adjust the voltage

feedback loop.

LT8580

Rev. B

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APPLICATIONS INFORMATION

(3a) Transient Response Shows Excessive Ringing

Figure 3. Transient Response

(3b) Transient Response Is Better

(3c) Transient Response Is Well Damped

Figure 4. 1.5MHz, 5V to 12V Boost Converter

VOUT

500mV/DIV

AC-COUPLED

IL1

200mA/DIV

ISTEP

100mA/DIV

100µs/DIV 8580 F03a

VOUT

500mV/DIV

AC-COUPLED

IL1

200mA/DIV

ISTEP

100mA/DIV

100µs/DIV

8580 F03b

VOUT

500mV/DIV

AC-COUPLED

IL1

200mA/DIV

ISTEP

100mA/DIV

100µs/DIV 8580 F03c

COUT

4.7µF

VOUT

12V

200mA

15µH D1

RFBX

130k

VIN

VIN SW

8580 F04

LT8580

10k

6.04k

56.2k

SHDN

GND

FBX

VCSYNC

SSRT

3.3nF

47pF

CSS

0.22µF

CIN

2.2µF

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

As with any feedback loop, identifying the gain and phase

contribution of the various elements in the loop is critical.

Figure 5 shows the key equivalent elements of a boost con-

verter. Because of the fast current control loop, the power

stage of the IC, inductor and diode have been replaced by

a combination of the equivalent transconductance ampli-

fier gmp and the current controlled current source which

converts IVIN to (hVIN/VOUT) • IVIN. gmp acts as a current

source where the peak input current, IVIN, is proportional

to the VC voltage. h is the efficiency of the switching

regulator, and is typically about 85%.

Note that the maximum output currents of gmp and gma are

finite. The limits for gmp are in the Electrical Characteristics

section (switch current limit), and gma is nominally limited

to about +15µA and –17µA.

Figure 5. Boost Converter Equivalent Model

–

gma

RCRO

CC: COMPENSATION CAPACITOR

COUT: OUTPUT CAPACITOR

CPL: PHASE LEAD CAPACITOR

CF: HIGH FREQUENCY FILTER CAPACITOR

gma: TRANSCONDUCTANCE AMPLIFIER INSIDE IC

gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER

RC: COMPENSATION RESISTOR

RL: OUTPUT RESISTANCE DEFINED AS VOUT DIVIDED BY ILOAD(MAX)

RO: OUTPUT RESISTANCE OF gma

R1, R2: FEEDBACK RESISTOR DIVIDER NETWORK

RESR: OUTPUT CAPACITOR ESR

η: CONVERTER EFFICIENCY (~85% AT HIGHER CURRENTS)

8580 F05

FBX

COUT

CPL

RESR

VOUT

IVIN

gmp

1.204V

REFERENCE

η•VIN

VOUT

•IVIN

From Figure 5, the DC gain, poles and zeros can be cal-

culated as follows:

Output Pole: P1=

2 • π • RL• COUT

Error Amp Pole: P2 = 1

2 • π • RO+RC

[ ]

• CC

Error Amp Zero: Z1= 1

2 • π • RC• CC

DC Gain:

(Breaking Loop at FBX Pin)

ADC = AOL(0) = ∂VC

∂VFBX

•∂IVIN

∂VC

•∂VOUT

∂IVIN

•∂VFBX

∂VOUT

gma • R0

( )

• gmp •h•VIN

VOUT

•RL

⎛

⎝

⎜⎞

⎠

⎟•0.5R2

R1+ 0.5R2

ESR Zero: Z2 = 1

2 • π • RESR • COUT

RHP Zero: Z3 = VIN

2• RL

4 • π • VOUT

2• L

High Frequency Pole: P3 > fS

Phase Lead Zero: Z4 = 1

2 • π • R1 • CPL

Phase Lead Pole: P4 = 1

2 • π •

R1• R2

R1+ R2

• CPL

Error Amp Filter Pole:

P5 = 1

2 • π • RC• RO

+ R

• CF

, CF<CC

The current mode zero (Z3) is a right-half plane zero

which can be an issue in feedback control design, but is

manageable with proper external component selection.

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Using the circuit in Figure 4 as an example, Table 3 shows

the parameters used to generate the bode plot shown in

Figure 6.

In Figure 6, the phase is –126° when the gain reaches 0dB

giving a phase margin of 54°. The crossover frequency is

14kHz, which is more than three times lower than the fre-

quency of the RHP zero to achieve adequate phase margin.

Diode Selection

Schottky diodes, with their low forward-voltage drops and

fast switching speeds, are recommended for use with the

LT8580. For applications where VR (see Tables 4, 5 and

6) < 40V, the Diodes, Inc. SBR1V40LP is a good choice.

Where VR > 40V, the Diodes Inc. DFLS1100 works well.

These diodes are rated to handle an average forward

current of 1A.

Oscillator

The operating frequency of the LT8580 can be set by the

internal free-running oscillator. When the SYNC pin is

driven low (< 0.4V), the frequency of operation is set by a

resistor from RT to ground. An internally trimmed timing

capacitor resides inside the IC. The oscillator frequency

is calculated using the following formula:

fOSC =85.5

(RT+1)

where fOSC is in MHz and RT is in kΩ. Conversely, RT

(in kΩ) can be calculated from the desired frequency

(in MHz) using:

RT=85.5

OSC

−1

Clock Synchronization

The operating frequency of the LT8580 can be synchronized

to an external clock source. To synchronize to the external

source, simply provide a digital clock signal into the SYNC

pin. The LT8580 will operate at the SYNC clock frequency.

The LT8580 will revert to the internal free-running oscilla-

tor clock after SYNC is driven low for a few free-running

clock periods.

Figure 6. Bode Plot for Example Boost Converter

FREQUENCY (Hz)

GAIN (dB)

PHASE (DEG)

100

120

100 1k 10k 100k 1M

8580 F06

–20

140

–180

–135

–90

–45

–225

–270

–315

–360

54° AT

14kHz

PHASE

GAIN

Table 3. Bode Plot Parameters

PARAMETER VALUE UNITS COMMENT

RL60 WApplication Specific

COUT 4.7 µF Application Specific

RESR 10 mWApplication Specific

RO300 kWNot Adjustable

CC3300 pF Adjustable

CF47 pF Optional/Adjustable

CPL 0 pF Optional/Adjustable

RC6.04 kWAdjustable

R1 130 kWAdjustable

R2 14.6 kWNot Adjustable

VOUT 12 V Application Specific

VIN 5 V Application Specific

gma 200 µmho Not Adjustable

gmp 7 mho Not Adjustable

L 15 µH Application Specific

fS1.5 MHz Adjustable

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Driving SYNC high for an extended period of time effec-

tively stops the operating clock and prevents latch SR1

from becoming set (see the Block Diagram). As a result,

the switching operation of the LT8580 will stop.

The duty cycle of the SYNC signal must be between 35%

and 65% for proper operation. Also, the frequency of the

SYNC signal must meet the following two criteria:

(1) SYNC may not toggle outside the frequency range of

200kHz to 1.5MHz unless it is stopped low to enable

the free-running oscillator.

(2) The SYNC frequency can always be higher than the

free-running oscillator frequency, fOSC, but should not

be less than 25% below fOSC.

Operating Frequency Selection

There are several considerations in selecting the operat-

ing frequency of the converter. The first is staying clear

of sensitive frequency bands, which cannot tolerate any

spectral noise. For example, in products incorporating RF

communications, the 455kHz IF frequency is sensitive to

any noise, therefore switching above 600kHz is desired.

Some communications have sensitivity to 1.1MHz, and in

that case, a 1.5MHz switching converter frequency may be

employed. The second consideration is the physical size

of the converter. As the operating frequency goes up, the

inductor and filter capacitors go down in value and size.

The trade-off is efficiency, since the switching losses due

to NPN base charge (see Thermal Calculations), Schottky

diode charge, and other capacitive loss terms increase

proportionally with frequency.

Soft-Start

The LT8580 contains a soft-start circuit to limit peak switch

currents during start-up. High start-up current is inherent

in switching regulators in general since the feedback loop

is saturated due to VOUT being far from its final value. The

regulator tries to charge the output capacitor as quickly as

possible, which results in large peak currents.

The start-up current can be limited by connecting an

external capacitor (typically 100nF to 1µF) to the SS pin.

This capacitor is slowly charged to ~2.1V by an internal

280k resistor once the part is activated. SS pin voltages

below ~1.1V reduce the internal current limit. Thus, the

gradual ramping of the SS voltage also gradually increases

the current limit as the capacitor charges. This, in turn,

allows the output capacitor to charge gradually toward its

final value while limiting the start-up current.

In the event of a commanded shutdown or lockout (SHDN

pin), internal undervoltage lockout (UVLO) or a thermal

lockout, the soft-start capacitor is automatically discharged

to ~200mV before charging resumes, thus assuring that

the soft-start occurs after every reactivation of the chip.

Shutdown

The SHDN pin is used to enable or disable the chip. For

most applications, SHDN can be driven by a digital logic

source. Voltages above 1.4V enable normal active op-

eration. Voltages below 300mV will shutdown the chip,

resulting in extremely low quiescent current.

While the SHDN voltage transitions through the lockout

voltage range (0.3V to 1.21V) the power switch is disabled

and the SR2 latch is set (see the Block Diagram). This

causes the soft-start capacitor to begin discharging, which

continues until the capacitor is discharged and active op-

eration is enabled. Although the power switch is disabled,

SHDN voltages in the lockout range do not necessarily

reduce quiescent current until the SHDN voltage is near

or below the shutdown threshold.

Also note that SHDN can be driven above VIN or VOUT as

long as the SHDN voltage is limited to less than 40V.

Figure 7. Chip States vs SHDN Voltage

(HYSTERESIS AND TOLERANCE)

SHUTDOWN

(LOW QUIESCENT CURRENT)

ACTIVE

(NORMAL OPERATION)

LOCKOUT

(POWER SWITCH OFF,

SS CAPACITOR DISCHARGED)

1.21V

0.0V

1.40V

0.3V

8580 F07

SHDN (V)

LT8580

Rev. B

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APPLICATIONS INFORMATION

Configurable Undervoltage Lockout

Figure 8 shows how to configure an undervoltage lock-

out (UVLO) for the LT8580. Typically, UVLO is used in

situations where the input supply is current-limited, has

a relatively high source resistance, or ramps up/down

slowly. A switching regulator draws constant power from

the source, so source current increases as source voltage

drops. This looks like a negative resistance load to the

source and can cause the source to current-limit or latch

low under low source voltage conditions. UVLO prevents

the regulator from operating at source voltages where

these problems might occur.

The shutdown pin comparator has voltage hysteresis with

typical thresholds of 1.31V (rising) and 1.27V (falling). Re-

sistor RUVLO2 is optional. RUVLO2 can be included to reduce

the overall UVLO voltage variation caused by variations

in SHDN pin current (see the Electrical Characteristics).

A good choice for RUVLO2 is ≤10k ±1%. After choosing a

value for RUVLO2, RUVLO1 can be determined from either

of the following:

RUVLO1 =VIN

−1.31V

1.31V

RUVLO2

⎛

⎝

⎜⎞

⎠

⎟+12µA

RUVLO1 =VIN−−1.27V

1.27V

RUVLO2

⎛

⎝

⎜⎞

⎠

⎟+12µA

where VIN+ and VIN– are the VIN voltages when rising or

falling, respectively.

Figure 8. Configurable UVLO

For example, to disable the LT8580 for VIN voltages below

3.5V using the single resistor configuration, choose:

RUVLO1 =3.5V −1.27V

1.27V

∞

⎛

⎝

⎜⎞

⎠

⎟+12µA

= 187k

To activate the LT8580 for VIN voltages greater than

4.5V using the double resistor configuration, choose

RUVLO2 = 10k and:

RUVLO1 =4.5V −1.31V

1.31V

10k

⎛

⎝

⎜⎞

⎠

⎟+12µA

= 22.1k

Internal Undervoltage Lockout

The LT8580 monitors the VIN supply voltage in case VIN

drops below a minimum operating level (typically about

2.35V). When VIN is detected low, the power switch is

deactivated, and while sufficient VIN voltage persists, the

soft-start capacitor is discharged. After VIN is detected

high, the power switch will be reactivated and the soft-

start capacitor will begin charging.

Thermal Considerations

For the LT8580 to deliver its full output power, it is impera-

tive that a good thermal path be provided to dissipate the

heat generated within the package. This is accomplished

by taking advantage of the thermal pad on the underside of

the IC. It is recommended that multiple vias in the printed

circuit board be used to conduct heat away from the IC

and into a copper plane with as much area as possible.

RUVLO2

(OPTIONAL)

1.3V

RUVLO1

8580 F08

VIN

ACTIVE/

LOCKOUT

GND

12µA

AT 1.3V

–

SHDN

LT8580

Rev. B

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APPLICATIONS INFORMATION

Thermal Lockout

If the die temperature reaches approximately 165°C, the

part will go into thermal lockout, the power switch will be

turned off and the soft-start capacitor will be discharged.

The part will be enabled again when the die temperature

has dropped by ~5°C (nominal).

Thermal Calculations

Power dissipation in the LT8580 chip comes from four

primary sources: switch I2R loss, NPN base drive (AC),

NPN base drive (DC), and additional input current. The

following formulas can be used to approximate the power

losses. These formulas assume continuous mode opera-

tion, so they should not be used for calculating efficiency

in discontinuous mode or at light load currents.

Average Input Current: IIN =VOUT • IOUT

VIN •h

Switch Conduction Loss: PSW = (DC)(IIN)(VSW )

Base Drive Loss (AC): PBAC = 20ns(IIN)(VOUT)(f)

Base Drive Loss (DC): PBDC =(VIN)(IIN)(DC)

Input Power Loss: P

INP

= 6mA (V

)

where:

VSW = switch on voltage (see Typical Performance

Characteristics for Switch Saturation Voltage)

DC = duty cycle (see the Power Switch Duty Cycle sec-

tion for formulas)

h = power conversion efficiency (typically 85% at high

currents)

Example: boost configuration, VIN = 5V, VOUT = 12V,

IOUT = 0.2A, f = 1.25MHz, VD = 0.5V:

IIN = 0.56A

DC = 62.0%

PSW = 117mW

PBAC = 169mW

PBDC = 44mW

PINP = 30mW

Total LT8580 power dissipation (PTOT) = 361mW

Thermal resistance for the LT8580 is influenced by the pres-

ence of internal, topside or backside planes. To calculate

die temperature, use the appropriate thermal resistance

number and add in worst-case ambient temperature:

TJ = TA + θJA • PTOT

where TJ = junction temperature, TA = ambient temperature,

and θJA is the thermal resistance from the silicon junction

to the ambient air.

The published θJA value is 43°C/W for the 3mm × 3mm

DFN package and 35°C/W to 40°C/W for the MSOP ex-

posed pad package. In practice, lower θJA values can be

obtained if the board layout uses ground as a heat sink.

For instance, thermal resistances of 34.7°C/W for the

DFN package and 22.5°C/W for the MSOP package were

obtained on a board designed with large ground planes.

VIN Ramp Rate

While initially powering a switching converter application,

the VIN ramp rate should be limited. High VIN ramp rates can

cause excessive inrush currents in the passive components

of the converter. This can lead to current and/or voltage

overstress and may damage the passive components or

the chip. Ramp rates less than 500mV/µs, depending on

component parameters, will generally prevent these issues.

Also, be careful to avoid hot-plugging. Hot-plugging occurs

when an active voltage supply is “instantly” connected or

switched to the input of the converter. Hot-plugging results

in very fast input ramp rates and is not recommended.

Finally, for more information, refer to Linear application

note AN88, which discusses voltage overstress that can

occur when an inductive source impedance is hot-plugged

to an input pin bypassed by ceramic capacitors.

LT8580

Rev. B

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APPLICATIONS INFORMATION

the board reduces die temperature and increases the power

capability of the LT8580. Provide as much copper area as

possible around this pad. Adding multiple feedthroughs

around the pad to the ground plane will also help. Figure 10

and Figure 11 show the recommended component place-

ment for the boost and SEPIC configurations, respectively.

Layout Hints for Inverting Topology

Figure 12 shows recommended component placement for

the dual inductor inverting topology. Input bypass capaci-

tor, C1, should be placed close to the LT8580, as shown.

The load should connect directly to the output capacitor,

C2, for best load regulation. The local ground may be tied

into the system ground plane at the C3 ground terminal.

The cut ground copper at D1’s cathode is essential to

obtain low noise. This important layout issue arises due

to the chopped nature of the currents flowing in Q1 and

D1. If they are both tied directly to the ground plane before

being combined, switching noise will be introduced into

the ground plane. It is almost impossible to get rid of this

noise, once present in the ground plane. The solution

is to tie D1’s cathode to the ground pin of the LT8580

before the combined currents are dumped in the ground

plane as drawn in Figure 2, Figure 13 and Figure 14. This

single layout technique can virtually eliminate high

frequency “spike” noise, so often present on switching

regulator outputs.

DIFFERENCES FROM LT3580

LT8580 is very similar to LT3580. However, LT8580 does

deviate from LT3580 in a few areas:

• 65V, 1A switch

• 40V VIN and SHDN absolute maximum rating

• FB renamed to FBX

• 5V FBX absolute maximum rating

Figure 9. High Speed “Chopped” Switching

Path for Boost Topology

Layout Hints

As with all high frequency switchers, when considering

layout, care must be taken to achieve optimal electrical,

thermal and noise performance. One will not get adver-

tised performance with a careless layout. For maximum

efficiency, switch rise and fall times are typically in the

10ns to 20ns range. To prevent noise, both radiated and

conducted, the high speed switching current path, shown in

Figure 9, must be kept as short as possible. This is imple-

mented in the suggested layout of a boost configuration in

Figure 10. Shortening this path will also reduce the parasitic

trace inductance. At switch-off, this parasitic inductance

produces a flyback spike across the LT8580 switch. When

operating at higher currents and output voltages, with poor

layout, this spike can generate voltages across the LT8580

that may exceed its absolute maximum rating. A ground

plane should also be used under the switcher circuitry to

prevent interplane coupling and overall noise.

The VC and FBX components should be kept as far away

as practical from the switch node. The ground for these

components should be separated from the switch cur-

rent path. Failure to do so can result in poor stability or

subharmonic oscillation.

Board layout also has a significant effect on thermal re-

sistance. The exposed package ground pad is the copper

plate that runs under the LT8580 die. This is a good thermal

path for heat out of the package. Soldering the pad onto

8580 F09

VOUT

GND

LT8580

VIN

HIGH

FREQUENCY

SWITCHING

PATH

LOAD

LT8580

Rev. B

For more information www.analog.com

Figure 10. Suggested Component Placement for Boost Topology

(Both DFN and MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 11. Suggested Component Placement for SEPIC Topology

(Both DFN And MSOP Packages. Not to Scale). Pin 9 (Exposed

Pad) Must Be Soldered Directly to the Local Ground Plane for

Adequate Thermal Performance. Multiple Vias to Additional

Ground Planes Will Improve Thermal Performance

Figure 12. Suggested Component Placement for Inverting Topology (Both DFN and MSOP Packages. Not to Scale).

Note Cut in Ground Copper at Diode’s Cathode. Pin 9 (Exposed Pad) Must be Soldered Directly to Local Ground Plane

for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance

APPLICATIONS INFORMATION

8580 F11

VOUT

VIN

D1 C3

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

8580 F12

VOUT

VIN

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

8580 F10

VOUT

VIN

SHDN

SYNC

GND

VIAS TO GROUND

PLANE REQUIRED

TO IMPROVE

THERMAL

PERFORMANCE

LT8580

Rev. B

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APPLICATIONS INFORMATION

Figure 13. Switch-On Phase of an Inverting Converter. L1 and L2 Have Positive dI/dt

Figure 14. Switch-Off Phase of an Inverting Converter. L1 and L2 Currents Have Negative dI/dt

L1 L2

–(VIN + VOUT)

SW SWX

8580 F13

C1 C3 RLOAD

–VOUT

VIN

VCESAT

L1 L2

VIN + VOUT+ VD

SW SWX

C1 C3 RLOAD

–VOUT

VIN

8580 F14

LT8580

Rev. B

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Figure 15. Boost Converter: The Component Values and Voltages

Given Are Typical Values for a 1.5MHz, 5V to 12V Boost

APPLICATIONS INFORMATION

COUT

4.7µF

VOUT

12V

200mA

15µH D1

RFBX

130k

VIN

VIN SW

8580 F15

LT8580

10k

6.04k

56.2k

SHDN

GND

FBX

VCSYNC

SSRT

3.3nF

47pF

CSS

0.22µF

CIN

2.2µF

BOOST CONVERTER COMPONENT SELECTION

The LT8580 can be configured as a boost converter as in

Figure 15. This topology allows for positive output voltages

that are higher than the input voltage. A single feedback

resistor sets the output voltage. For output voltages higher

than 60V, see the Charge Pump Aided Regulators section.

Table 4 is a step-by-step set of equations to calculate com-

ponent values for the LT8580 when operating as a boost

converter. Input parameters are input and output voltage,

and switching frequency (VIN, VOUT and fOSC respectively).

Refer to the Applications Information section for further

information on the design equations presented in Table 4.

Variable Definitions:

VIN = Input Voltage

VOUT = Output Voltage

DC = Power Switch Duty Cycle

fOSC = Switching Frequency

IOUT = Maximum Average Output Current

IRIPPLE = Inductor Ripple Current

Table 4. Boost Design Equations

PARAMETERS/EQUATIONS

Step 1:

Inputs

Pick VIN, VOUT, and fOSC to calculate equations below

Step 2:

DCMAX =VOUT – VIN(MIN) +0.5 V

VOUT +0.5 V – 0.4 V

DCMIN =VOUT – VIN(MAX) +0.5 V

VOUT +0.5 V – 0.4 V

Step 3:

LTYP =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.3 A

(1)

LMIN =(VIN(MIN) – 0.4V) • (2 • DCMAX – 1)

1.25 • (DCMAX −300ns • fOSC) • fOSC • (1– DCMAX )

(2)

LMAX1 =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.08 A

(3)

LMAX2 =(VIN(MAX) – 0.4V) • DCMIN

OSC

• 0.08 A

(4)

• Solve equations 1 to 4 for a range of L values

• The minimum of the L value range is the higher of LTYP and LMIN

• The maximum of the L value range is the lower of LMAX1 and LMAX2.

Step 4:

IRIPPLE

IRIPPLE(MIN) =(VIN(MIN) – 0.4V) • DCMAX

fOSC • L1

IRIPPLE(MAX) =(VIN(MAX) – 0.4V) • DCMIN

OSC

• L

Step 5:

IOUT

IOUT(MIN) =1A −IRIPPLE(MIN)

⎛

⎝

⎜⎞

⎠

⎟• (1−DCMAX )

IOUT(MAX) =1A −IRIPPLE(MAX)

⎛

⎝

⎜⎞

⎠

⎟• (1−DCMIN)

Step 6:

VR > VOUT; IAVG > IOUT

Step 7:

COUT

COUT ≥IOUT • DCMAX

fOSC • 0.005 • VOUT

Step 8:

CIN

CIN ≥CVIN +CPWR ≥

1A • DCMAX

40 • f

OSC

• 0.005 • VIN(MIN)

+IRIPPLE(MAX)

8 • f

OSC

• 0.005 • VIN(MAX)

• Refer to the Capacitor Selection Section for definition of CVIN and CPWR

Step 9:

RFBX

RFBX =VOUT −1.204V

83.3µA

Step

10:

RT=85.5

OSC

–1 ; fOSC in MHz and R T in kΩ

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

Note 2: The final values for COUT and CIN may deviate from the previous

equations in order to obtain desired load transient performance.

LT8580

Rev. B

For more information www.analog.com

Figure 16. SEPIC Converter: The Component Values and Voltages

Given Are Typical Values for a 1MHz, 9V to 16V Input to 12V

Output SEPIC Converter

APPLICATIONS INFORMATION

COUT

4.7µF

VOUT

12V

240mA

22µH D1

1µF

RFBX

130k

VIN

9V TO 16V

VIN SW

8580 F16

LT8580

487k

16.2k

84.5k

SHDN

GND

FBX

VCSYNC

SSRT

1nF

22pF

CSS

0.22µF

CIN

4.7µF

22µH

•

SEPIC CONVERTER COMPONENT SELECTION

(COUPLED OR UNCOUPLED INDUCTORS)

The LT8580 can also be configured as a SEPIC, as shown

in Figure 16. This topology allows for positive output

voltages that are lower, equal or higher than the input volt-

age. Output disconnect is inherently built into the SEPIC

topology, meaning no DC path exists between the input

and output due to capacitor C1.

Table 5 is a step-by-step set of equations to calculate com-

ponent values for the LT8580 when operating as a SEPIC

converter. Input parameters are input and output voltage,

and switching frequency (VIN, VOUT and fOSC, respectively).

Refer to the Applications Information section for further

information on the design equations presented in Table 5.

Variable Definitions:

VIN = Input Voltage

VOUT = Output Voltage

DC = Power Switch Duty Cycle

fOSC = Switching Frequency

IOUT = Maximum Average Output Current

IRIPPLE = Inductor Ripple Current

Table 5. SEPIC Design Equations

PARAMETERS/EQUATIONS

Step 1:

Inputs

Pick VIN, VOUT and fOSC to calculate equations below

Step 2:

DCMAX =VOUT +0.5 V

VIN(MIN) +VOUT +0.5 V – 0.4V

DCMIN =VOUT +0.5 V

VIN(MAX) +VOUT +0.5 V – 0.4V

Step 3:

LTYP =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.3 A

(1)

LMIN =(VIN(MIN) – 0.4V) • (2 • DCMAX – 1)

1.25 • (DCMAX −300ns • fOSC) • fOSC • (1– DCMAX )

(2)

LMAX =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.08 A

(3)

• Solve equations 1, 2 and 3 for a range of L values

• The minimum of the L value range is the higher of LTYP and LMIN

• The maximum of the L value range is LMAX

• L = L1 = L2 for coupled inductors

• L = L1|| L2 for uncoupled inductors

Step 4:

IRIPPLE

IRIPPLE(MIN) =(VIN(MIN) – 0.4V) • DCMAX

fOSC • L

IRIPPLE(MAX) =(VIN(MAX) – 0.4V) • DCMIN

fOSC • L

Step 5:

IOUT

IOUT(MIN) =1A −IRIPPLE(MIN)

⎛

⎝

⎜⎞

⎠

⎟• 1−DCMAX

( )

IOUT(MAX) =1A −IRIPPLE(MAX)

⎛

⎝

⎜⎞

⎠

⎟• 1−DCMIN

( )

Step 6:

VR > VIN + VOUT; IAVG > IOUT

Step 7:

C1 ≥ 1µF; VRATING ≥ VIN

Step 8:

COUT

COUT ≥IOUT(MIN) • DCMAX

fOSC • 0.005 • VOUT

Step 9:

CIN

CIN ≥CVIN +CPWR ≥

1A • DCMAX

40 • fOSC • 0.005 • VIN(MIN)

+IRIPPLE(MAX)

8 • fOSC • 0.005 • VIN(MAX)

• Refer to the Capacitor Selection Section for definition of CVIN and CPWR

Step 10:

RFBX

RFBX =VOUT −1.204V

83.3µA

Step 11:

RT=85.5

OSC

–1 ; fOSC in MHz and R T in kΩ

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

Note 2: The final values for COUT, CIN and C1 may deviate from the

previous equations in order to obtain desired load transient performance.

LT8580

Rev. B

For more information www.analog.com

APPLICATIONS INFORMATION

Figure 17. Dual Inductor Inverting Converter: The Component

Values and Voltages Given Are Typical Values for a 750kHz

Wide Input (5V to 40V) to –15V Inverting Topology Using

Coupled Inductors

COUT

4.7µF

VOUT

–15V

90mA (VIN = 5V)

210mA (VIN = 12V)

420mA (VIN = 40V)

22µH L2

22µH

1µF

RFBX

182k

VIN

5V TO 40V

VIN SW

8580 F17

LT8580

10k

13.7k

113k

SHDN

GND

FBX

VCSYNC

SSRT

10nF

47pF

CSS

0.22µF

CIN

4.7µF

• •

DUAL INDUCTOR INVERTING CONVERTER COMPONENT

SELECTION (COUPLED OR UNCOUPLED INDUCTORS)

Due to its unique FBX pin, the LT8580 can work in a dual

inductor inverting configuration as in Figure 17. Chang-

ing the connections of L2 and the Schottky diode in the

SEPIC topology results in generating negative output

voltages. This solution results in very low output voltage

ripple due to inductor L2 being in series with the output.

Output disconnect is inherently built into this topology

due to the capacitor C1.

Table 6 is a step-by-step set of equations to calculate

component values for the LT8580 when operating as a

dual inductor inverting converter. Input parameters are

input and output voltage, and switching frequency (VIN,

VOUT and fOSC respectively). Refer to the Applications

Information section for further information on the design

equations presented in Table 6.

Variable Definitions:

VIN = Input Voltage

VOUT = Output Voltage

DC = Power Switch Duty Cycle

fOSC = Switching Frequency

IOUT = Maximum Average Output Current

IRIPPLE = Inductor Ripple Current

Table 6. Dual Inductor Inverting Design Equations

PARAMETERS/EQUATIONS

Step 1:

Inputs

Pick VIN, VOUT and fOSC to calculate equations below

Step 2:

DCMAX =VOUT +0.5 V

VIN(MIN) +VOUT +0.5 V – 0.4 V

DCMIN =VOUT +0.5 V

VIN(MAX) +V

OUT

+0.5 V – 0.4 V

Step 3:

LTYP =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.3 A

(1)

LMIN =(VIN(MIN) – 0.4V) • (2 • DCMAX – 1)

1.25 • (DCMAX −300ns • fOSC) • fOSC • (1– DCMAX )

(2)

LMAX =(VIN(MIN) – 0.4V) • DCMAX

OSC

• 0.08 A

(3)

• Solve equations 1, 2 and 3 for a range of L values

• The minimum of the L value range is the higher of LTYP and LMIN

• The maximum of the L value range is LMAX

• L = L1 = L2 for coupled inductors

• L = L1|| L2 for uncoupled inductors

Step 4:

IRIPPLE

IRIPPLE(MIN) =(VIN(MIN) – 0.4V) • DCMAX

fOSC • L

IRIPPLE(MAX) =(VIN(MAX) – 0.4V) • DCMIN

OSC

• L

Step 5:

IOUT

IOUT(MIN) =1A −IRIPPLE(MIN)

⎛

⎝

⎜⎞

⎠

⎟• 1−DCMAX

( )

IOUT(MAX) =1A −IRIPPLE(MAX)

⎛

⎝

⎜⎞

⎠

⎟• 1−DCMIN

( )

Step 6:

VR > VIN + |VOUT|; IAVG > IOUT

Step 7:

C1 ≥ 1µF; VRATING ≥ VIN(MAX) + |VOUT|

Step 8:

COUT

COUT ≥IRIPPLE(MAX)

8 • fOSC (0.005 • VOUT )

Step 9:

CIN

CIN ≥CVIN +CPWR ≥

1A • DCMAX

40 • fOSC • 0.005 • VIN(MIN)

+IRIPPLE(MAX)

8 • fOSC • 0.005 • VIN(MAX)

• Refer to the Capacitor Selection Section for definition of CVIN and CPWR

Step 10:

RFBX

RFBX =VOUT +3mV

83.3µA

Step 11:

RT=85.5

OSC

–1 ; fOSC in MHz and RT in kΩ

Note 1: This table uses 1A for the peak switch current. Refer to the

Electrical Characteristics Table and Typical Performance Characteristics

plots for the peak switch current at an operating duty cycle.

Note 2: The final values for COUT, CIN and C1 may deviate from the

previous equations in order to obtain desired load transient performance.

LT8580

Rev. B

For more information www.analog.com

TYPICAL APPLICATIONS

1.5MHz, 5V to 12V Output Boost Converter

50mA to 150mA to 50mA Output Load Step

Efficiency and Power Loss

COUT

4.7µF

VOUT

12V

200mA

15µH D1

130k

VIN

VIN SW

8580 TA02a

LT8580

10k

6.04k

56.2k

SHDN

GND

FBX

VCSYNC

SSRT

3.3nF

47pF

0.22µF

L1: WÜRTH 15µH WE-LQS 74404054150

D1: DIODES INC. SBR1U40LP

CIN: 2.2µF, 35V, 0805, X7R

COUT: 4.7µF, 16V, 0805, X7R

CIN

2.2µF

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100

8580 TA02b

50 150 200

180

300

480

240

120

380

420

EFFICIENCY

POWER LOSS

VOUT

500mV/DIV

AC-COUPLED

ISTEP

100mA/DIV

IL1

500mA/DIV

100µs/DIV 8580 TA02c

LT8580

Rev. B

For more information www.analog.com

750kHz, –15V Output Inverting Converter Accepts 5V to 40V Input

TYPICAL APPLICATIONS

Efficiency and Power Loss (VIN = 12V)

60mA to 160mA to 60mA Output Load Step (VIN = 12V)

COUT

4.7µF

VOUT

–15V

90mA (VIN = 5V)

210mA (VIN = 12V)

420mA (VIN = 40V)

22µH L2

22µH

1µF

182k

VIN

5V TO 40V

VIN SW

8580 TA03a

LT8580

10k

13.7k

113k

SHDN

GND

FBX

VCSYNC

SSRT

10nF

47pF

0.22µF

CIN

4.7µF

• •

L1, L2: COILCRAFT 22µH MSD7342-223

D1: CENTRAL SEMI CMMSH1-60

CIN: 4.7µF, 50V, 1206, X5R

COUT: 4.7µF, 25V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

100

8580 TA03b

50 150 200

240

400

640

320

160

480

560

EFFICIENCY

POWER LOSS

VOUT

200mV/DIV

AC-COUPLED

ISTEP

100mA/DIV

IL1 + IL2

200mA/DIV

200µs/DIV 8580 TA03c

LT8580

Rev. B

For more information www.analog.com

TYPICAL APPLICATIONS

1.2MHz Inverting Converter Generates –48V Output From 12V Input

Switching Waveforms

Efficiency and Power Loss

Start-Up Waveforms

COUT

2.2µF

VOUT

–48V

70mA

150µH L2

330µH

1µF

576k

VIN

12V

VIN SW

8580 TA04a

LT8580

619k

20.5k

69.8k

SHDN

GND

FBX

VCSYNC

SSRT

4.7nF

47pF

0.33µF

CIN

1µF

2.2µF

L1: COOPER 150µH DR74-151

L2: COOPER 330µH DR74-331

D1: DIODES, INC. DFLS1100

CIN: 1µF, 50V, 0805, X7R

COUT: 2.2µF, 100V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

C2: 2.2µF, 100V, 1206, X7S

49.9Ω

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

8580 TA04b

40 602010 30 70

200

560

800

1040

680

320

440

920

EFFICIENCY

POWER LOSS

VOUT

20mV/DIV

AC-COUPLED

VSW

20V/DIV

IL1 + IL2

200mA/DIV

200µs/DIV

8580 TA04c

VOUT

10V/DIV

VSW

20V/DIV

IL1 + IL2

200mA/DIV

200µs/DIV

8580 TA04d

LT8580

Rev. B

For more information www.analog.com

TYPICAL APPLICATIONS

Start-Up Waveforms

VFD (Vacuum Fluorescent Display) Power Supply Switches at 1MHz

Danger High Voltage! Operation by High Voltage Trained Personnel Only

Efficiency and Power Loss

(VIN = 12V with Load on VOUT3)

1µF

VOUT1

60V

60mA*

VOUT3

180V

20mA*

VOUT2

120V

30mA*

68µH C2

1µF D1

698k

VIN

9V TO 16V

VIN SW

8580 TA05a

LT8580

487k

22.1k

84.5k

SHDN

GND

FBX

VCSYNC

SSRT

4.7nF

330pF

0.47µF

CIN

1µF

L1: WÜRTH 68µH WE-LQS 74404084680

D1-D5: DIODES, INC. DFLS1100

CIN: 1µF, 100V, 1206, X7R

C1-C5: 1µF, 100V, 1206, X7S

*MAX TOTAL OUTPUT POWER 3.5W

22Ω

OUTPUT POWER (W)

EFFICIENCY (%)

POWER LOSS (mW)

2.5

8580 TA05b

2 310.5 1.5 3.5

400

640

800

960

720

480

560

880

EFFICIENCY

POWER LOSS

VOUT3

50V/DIV

VOUT2

50V/DIV

VOUT1

50V/DIV

IL1

200mA/DIV

2ms/DIV 8580 TA05c

LT8580

Rev. B

For more information www.analog.com

550kHz SEPIC Converter Generates 24V from 15V to 30V Input

Transient Response with 100mA to 225mA

to 100mA Output Load Step (VIN = 24V)

TYPICAL APPLICATIONS

Efficiency and Power Loss

(VIN = 24V)

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

200

8580 TA06b

150 25050 100 300

200

800

1100

1400

950

500

350

650

1250

EFFICIENCY

POWER LOSS

VOUT

500mV/DIV

AC-COUPLED

ISTEP

100mA/DIV

IL1 + IL2

500mA/DIV

100µs/DIV

8580 TA06c

COUT

4.7µF

VOUT

24V

195mA (VIN = 15V)

300mA (VIN = 24V)

47µH

1µF D1

274k

VIN

15V TO 30V

VIN SW

8580 TA06a

LT8580

12.7k

154k

SHDN

GND

FBX

VCSYNC

SSRT

3.3nF

22pF

0.1µF

CIN

2.2µF

•

L1, L2: COILCRAFT 47µH MSD7342-473

D1: DIODES INC. DFLS1100

CIN: 2.2µF, 35V, 0805, X7R

COUT: 4.7µF, 35V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

LT8580

Rev. B

For more information www.analog.com

3.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON TOP AND BOTTOM OF PACKAGE

0.40 ±0.10

BOTTOM VIEW—EXPOSED PAD

1.65 ±0.10

(2 SIDES)

0.75 ±0.05

R = 0.125

TYP

2.38 ±0.10

PIN 1

TOP MARK

(NOTE 6)

0.200 REF

0.00 – 0.05

(DD8) DFN 0509 REV C

0.25 ±0.05

2.38 ±0.05

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

1.65 ±0.05

(2 SIDES)2.10 ±0.05

0.50

BSC

0.70 ±0.05

3.5 ±0.05

PACKAGE

OUTLINE

0.25 ±0.05 0.50 BSC

DD Package

8-Lead Plastic DFN (3mm × 3mm)

(Reference LTC DWG # 05-08-1698 Rev C)

PACKAGE DESCRIPTION

LT8580

Rev. B

For more information www.analog.com

PACKAGE DESCRIPTION

MSOP (MS8E) 0213 REV K

0.53 ±0.152

(.021 ±.006)

SEATING

PLANE

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD

SHALL NOT EXCEED 0.254mm (.010") PER SIDE.

0.18

(.007)

0.254

(.010)

1.10

(.043)

MAX

0.22 – 0.38

(.009 – .015)

TYP

0.86

(.034)

REF

0.65

(.0256)

BSC

0° – 6° TYP

DETAIL “A”

GAUGE PLANE

1 2 34

4.90 ±0.152

(.193 ±.006)

BOTTOM VIEW OF

EXPOSED PAD OPTION

765

3.00 ±0.102

(.118 ±.004)

(NOTE 3)

3.00 ±0.102

(.118 ±.004)

(NOTE 4)

0.52

(.0205)

REF

1.68

(.066)

1.88

(.074)

5.10

(.201)

MIN

3.20 – 3.45

(.126 – .136)

1.68 ±0.102

(.066 ±.004)

1.88 ±0.102

(.074 ±.004) 0.889 ±0.127

(.035 ±.005)

RECOMMENDED SOLDER PAD LAYOUT

0.65

(.0256)

BSC

0.42 ±0.038

(.0165 ±.0015)

TYP

0.1016 ±0.0508

(.004 ±.002)

DETAIL “B”

CORNER TAIL IS PART OF

THE LEADFRAME FEATURE.

FOR REFERENCE ONLY

NO MEASUREMENT PURPOSE

0.05 REF

0.29

REF

MS8E Package

8-Lead Plastic MSOP, Exposed Die Pad

(Reference LTC DWG # 05-08-1662 Rev K)

LT8580

Rev. B

For more information www.analog.com

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications

subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 09/16 Changed Minimum On-Time in the Electrical Characteristics table to typical room value instead of worst case.

Added Minimum On-Time vs Temperature graph.

Added text and equations explaining minimum on-time.

Clarified inductor paragraph in the Applications Information section.

Adjusted RC, RL, RO, gma and resultant gain and phase margin numbers and plot to better reflect applications and the

Electrical Characteristics table.

Clarified Thermal Calculations section.

Corrected LMIN equation.

Clarified the Related Parts table.

10, 11

11, 14

21, 22, 23

B 11/19 Add AEC-Q100 Qualification in Progress

Add #W Part Numbers

LT8580

Rev. B

For more information www.analog.com

 ANALOG DEVICES, INC. 2014–2019

www.analog.com

11/19

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Current Protection VIN: 2.5V to 24V, VOUT(MAX) = 40V, IQ = 5mA, ISD < 1µA,

DFN, TSSOP Packages

LT3580 2A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

Converter VIN: 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD = <1µA,

3mm × 3mm DFN-8, MSOP-8E

LT3581 3.3A (ISW), 42V, 2.5MHz, High Efficiency Step-Up DC/DC

Converter VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = <1µA,

4mm × 3mm DFN-14, MSOP-16E

LT3579 6A (ISW), 42V, 2.5MHz, High Efficiency, Step-Up DC/DC

Converter VIN: 2.5V to 16V, VOUT(MAX) = 42V, IQ = 1.9mA, ISD = <1µA,

4mm × 5mm QFN-20, TSSOP-20

LT8582 Dual Channel, 3A (ISW), 42V, 2.5MHz, High Efficiency Step-Up

DC/DC Converter VIN: 2.5V to 22V, VOUT(MAX) = 42V, IQ = 2.1mA, ISD = <1µA,

4mm × 7mm DFN-24

Efficiency and Power Loss

(VIN = 12V)

12V Battery Stabilizer Survives 40V Transients

COUT

4.7µF

VOUT

12V

240mA

22µH

1µF D1

130k

VIN

9V TO 16V

UP TO 40V

TRANSIENT

VIN SW

8580 TA07a

LT8580

487k

16.2k

84.5k

SHDN

GND

FBX

VCSYNC

SSRT

1nF

22pF

0.22µF

CIN

4.7µF

•

L1, L2: WÜRTH 22µH WE-DD 744877220

D1: DIODES INC. DFLS1100

CIN: 4.7µF, 50V, 1206, X7R

COUT: 4.7µF, 25V, 1206, X7R

C1: 1µF, 100V, 0805, X7S

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

160

8580 TA07b

120 20040 80 240

400

600

800

500

200

100

300

700

EFFICIENCY

POWER LOSS