PDU53
3-BIT, ECL-INTERFACED
PROGRAMMABLE DELAY LINE
(SERIES PDU53)
d
a
ta
delay
devices, inc.
3
FEATURES PACKAGES
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
IN
A
2
A
1
VEE
A
0
N/C
N/C
N/C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
N/C
N/C
GND
OUT
N/C
N/C
N/C
N/C
IN
A
2
A
1
VEE
A
0
N/C
N/C
N/C
• Digitally programmable in 8 delay steps
• Monotonic delay-versus-address variation
• Precise and stable delays
• Input & outputs fully 100K-ECL interfaced & buffered
• Available in 16-pin DIP (600 mil) socket or SMD
PDU53-xx DIP
PDU53-xxM Military DIP
PDU53-xxC3 SMD
PDU53-xxMC3 Mil SMD
FUNCTIONAL DESCRIPTION
The PDU53-series device is a 3-bit digitally programmable delay line. The
delay, TDA, from the input pin (IN) to the output pin (OUT) depends on the
address code (A2-A0) according to the following formula:
TDA = TD0 + TINC * A
where A is the address code, TINC is the incremental delay of the device,
and TD0 is the inherent delay of the device. The incremental delay is
specified by the dash number of the device and can range from 100ps through 3000ps, inclusively. The
address is not latched and must remain asserted during normal operation.
PIN DESCRIPTIONS
IN Signal Input
OUT Signal Output
A2 Address Bit 2
A1 Address Bit 1
A0 Address Bit 0
VEE -5 Volts
GND Ground
SERIES SPECIFICATIONS
• Total programmed delay tolerance: 5% or 40ps,
whichever is greater
• Inherent delay (TD0): 2.2ns typical
• Address to input setup (TAIS): 2.9ns
• Operating temperature: 0° to 85° C
• Temperature coefficient: 100PPM/°C (excludes TD0)
• Supply voltage VEE: -5VDC ± 0.7V
• Power Supply Current: -150ma typical (50Ω to -2V)
• Minimum pulse width: 3ns or 15% of total delay,
whichever is greater
• Minimum period: 8ns or 2 x pulse width, whichever
is greater
DASH NUMBER SPECIFICATIONS
Part
Number
Incremental Delay
Per Step (ps)
Total Delay
Change (ns)
PDU53-100 100 ± 50 0.70
PDU53-200 200 ± 60 1.40
PDU53-250 250 ± 60 1.75
PDU53-400 400 ± 80 2.80
PDU53-500 500 ± 100 3.50
PDU53-750 750 ± 100 5.25
PDU53-1000 1000 ± 200 7.00
PDU53-1200 1200 ± 200 8.40
PDU53-1500 1500 ± 200 10.50
PDU53-2000 2000 ± 400 14.00
PDU53-2500 2500 ± 400 17.50
PDU53-3000 3000 ± 500 21.00
NOTE: Any dash number between 100 and 3000
not shown is also available.
TOAX
PWIN
TDAPWOUT
A
2-A0
IN
OUT
Figure 1: Timing Diagram
A
i-1
A
i
TAIS
1997 Data Delay Devices
Doc #98003 DATA DELAY DEVICES, INC. 1
3/18/98 3 Mt. Prospect Ave. Clifton, NJ 07013
PDU53
APPLICATION NOTES
ADDRESS UPDATE
The PDU53 is a memory device. As such,
special precautions must be taken when
changing the delay address in order to prevent
spurious output signals. The timing restrictions
are shown in Figure 1.
After the last signal edge to be delayed has
appeared on the OUT pin, a minimum time, TOAX,
is required before the address lines can change.
This time is given by the following relation:
TOAX = max { (Ai - A i-1) * TINC , 0 }
where A i-1 and Ai are the old and new address
codes, respectively. Violation of this constraint
may, depending on the history of the input signal,
cause spurious signals to appear on the OUT
pin. The possibility of spurious signals persists
until the required TOAX has elapsed.
INPUT RESTRICTIONS
There are three types of restrictions on input
pulse width and period listed in the AC
Characteristics table. The recommended
conditions are those for which the delay
tolerance specifications and monotonicity are
guaranteed. The suggested conditions are
those for which signals will propagate through the
unit without significant distortion. The absolute
conditions are those for which the unit will
produce some type of output for a given input.
When operating the unit between the
recommended and absolute conditions, the
delays may deviate from their values at low
frequency. However, these deviations will
remain constant from pulse to pulse if the input
pulse width and period remain fixed. In other
words, the delay of the unit exhibits frequency
and pulse width dependence when operated
beyond the recommended conditions. Please
consult the technical staff at Data Delay Devices
if your application has specific high-frequency
requirements.
Please note that the increment tolerances listed
represent a design goal. Although most delay
increments will fall within tolerance, they are not
guaranteed throughout the address range of the
unit. Monotonicity is, however, guaranteed over
all addresses.
PACKAGE DIMENSIONS
.870±.010
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
.380
MAX.
.015 TYP.
.070 MAX.
.018
TYP. .700±.010
7 Equal spaces
each .100±.010
Non-Accumulative
.580
MAX.
.600
±.00
.010
±.002
Lead Material:
Nickel-Iron alloy 42
TIN PLATE
PDU53-xx (Commercial DIP)
PDU53-xxM (Military DIP)
Doc #98003 DATA DELAY DEVICES, INC. 2
3/18/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU53
Doc #98003 DATA DELAY DEVICES, INC. 3
3/18/98 3 Mt. Prospect Ave. Clifton, NJ 07013
PACKAGE DIMENSIONS (cont’d)
PDU53-xxC3 (Commercial SMD)
PDU53-xxMC3 (Military SMD)
.880
±
.020
.882
±.00
.020 TYP. .040
TYP.
.100.090
.700
.380
MAX.
.590
MAX.
.010
±
.002
.050
±.01
.710
±.00 .007
±.00
1 2 3 4 5 6 7 8
91011121314
15
16
DEVICE SPECIFICATIONS
TABLE 1: AC CHARACTERISTICS
PARAMETER SYMBOL MIN TYP UNITS
Total Programmable Delay TDT 7 TINC
Inherent Delay TD0 2.2 ns
Address to Input Setup Time TAIS 2.9 ns
Output to Address Change TOAX See Text
Absolute PERIN 30 % of TDT
Input Period Suggested PERIN 50 % of TDT
Recommended PERIN 200 % of TDT
Absolute PWIN 15 % of TDT
Input Pulse Width Suggested PWIN 25 % of TDT
Recommended PWIN 100 % of TDT
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL MIN MAX UNITS NOTES
DC Supply Voltage VEE -7.0 0.3 V
Input Pin Voltage VIN V
EE - 0.3 0.3 V
Storage Temperature TSTRG -65 150 C
Lead Temperature TLEAD 300 C 10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 85C)
PARAMETER SYMBOL MIN MAX UNITS NOTES
High Level Output Voltage VOH -1.025 -0.880 V
VIH = MAX,50Ω to -2V
Low Level Output Voltage VOL -1.810 -1.620 V
VIL = MIN, 50Ω to -2V
High Level Input Voltage VIH -1.165 -0.880 V
Low Level Input Voltage VIL -1.810 -1.475 V
High Level Input Current IIH 340
µA VIH = MAX
Low Level Input Current IIL 0.5
µA VIL = MIN
PDU53
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: OUTPUT:
Ambient Temperature: 25oC ± 3oC Load: 50Ω to -2V
Supply Voltage (Vcc): -4.5V ± 0.1V Cload: 5pf ± 10%
Input Pulse: Standard 100K ECL Threshold: (VOH + VOL) / 2
levels (Rising & Falling)
Source Impedance: 50Ω Max.
Rise/Fall Time: 1.0 ns Max. (measured
between 20% and 80%)
Pulse Width: PWIN = 10ns
Period: PERIN = 100ns
NOTE: The above conditions are for test only and do not in any way restrict the operation of the device.
OUTOUT
TRIG
IN
REF
TRIG
Test Setup
DEVICE UNDER
TEST (DUT) OSCILLOSCOPE
PULSE
GENERATOR
IN
ADDRESS SELECT
Timing Diagram For Testing
TRISE TFALL
PERIN
PWIN
TRISE TFALL
20%20% 50%50%
80% 80%
50%50%
VIH
VIL
VOH
VOL
INPUT
SIGNAL
OUTPUT
SIGNAL
Doc #98003 DATA DELAY DEVICES, INC. 4
3/18/98 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
