RD38F3350WWZDQ1 - Intel Corporation

Intel® Wirel ess Fl a s h Me m o ry

(W18/W30 SCSP)

128-Mbit WQ Family with Asynchronous SRAM

Datasheet

This versat ile an d compact S tacked Chip Scal e Package (SCSP) solut ion from Intel i s created by

combi ning the Intel® Wi reles s Flash Memory (W18/W30 ) device with low-po we r PSRAM.

Ideal for high-perform ance, low-powe r, board-con s trained memory application s, the Intel®

Wireless Flas h Memory (W18/W30 SC SP ) f a mily retains all th e features of the Intel® Wireless

Flash Memory (W18/W30) disc rete device, such as a flexible multi-parti tion architecture that

prov ides d ual-ope ratio n Read-W hile-W r ite/Read- While- Erase (R WW/RWE) c apabi lity an d high

perfor mance asynchronous /s ynchronous burs t read s . Device upgrades and migrations are easy

with a c ommon package footprint and s i gnal ballout fo r a l l SCS P combi na tions . Manufactured

on Intel® 0.13 micron ETOX™ VIII process technology, this device provides the hig hes t levels of

quality and reliability.

■Flash Architecture

— Flexible, Multiple-Partition, Dual-Operation:

Read-While-Write / Read-While-Erase

—32 Partitions, 4 Mbits each

—31 Main Partitions, 8 Main Blocks each

—1 Pa rameter Partiti on, 8 Paramete r + 7

Main Blocks

—32-Kword Main Blocks, 4-Kword

Parameter Blocks

—Top or Bottom Parameter - single Flash die

—Dual Parameter - dual Flash die

■Flash Performance

— 65 ns Initial Access at 1.8 V or 3.0 V I/O

—25 ns Async Page at 1.8 V or 3.0 V I/O

— 14 ns Sync Read (tCHQV) at 1.8V I/O

— 20 ns Sync Read (tCHQV) at 3.0 V I/O

—4-, 8-, 16-, Continuous-Word Burst Lengths

— Burst Sus pend

—Programmable WAIT Configuration

—Enhanced Factory Programming Mode:

3.1µs/Word

— Flash Protec tion Register

—64 Unique Device Identifier Bits

—64 User-Programmable OTP Bits

■Flash Automation Suspend Operations

— Erase Suspend to Program or Read

— Program Suspend to Read

—5/9 µs (typ) Program/Erase Suspend Latency

■Flash Data Protection

—Absolute Protection with VPP and WP#

—Individual Dynamic zero-Latency Block

Locking

—Individual Block Lock-Down

—Erase/Program Lockout during Power

Transitions

■Flash Software

—Intel

® Flash Data Integrator (FDI) Optimized

—Common Flash Interface (CFI)

■SCSP Architecture

—Flash

—Flash + Flash

—Flash + PSRAM

—Flash + Flash + PSRAM

—Reduces Board Space Requirement

— Simplifies PCB Design Complexity

— Easy Migration to Future SCSP Devices

■SCSP Voltage

—Core: VCC =1.8 V (Typ)

—I/O: V

CCQ = 1.8 V or 3.0 V (Typ)

■SCSP Packaging

—0.8 mm Ball-Pitch Intel® SCSP

—Area: 8x10 mm

—Height: 1.2mm and 1.4mm

— 88-Ball (8 x 10 Matrix): 80 Active Balls with

2 Support Balls at Each Corner

■PSRAM Architecture and Performance

—2.7 V to 3.1 V P-VCC

— 65 ns Access Speed

—8-Word Page Read

— 18 ns for 32 M/64 M Page Read Speed

— Low Power Mode

■Flash Quality and Reliability

—Extended Temperature: –25 °C to +85 °C

—Minimum 100K Block Erase Cycles

—0.13 µm ETOX™ VIII Process

Order Number: 252063-007

June 2005

Notice: T hi s document c ontains informati on on ne w products in production. Th e specificat ions

are s ubje ct t o chang e wit hou t notic e . Verify with your l ocal Intel sale s of fi ce tha t you have th e lat -

est datasheet before finalizing a desi gn.

2Datasheet

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION W ITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

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ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LI ABILITY OR W ARRANTIES

RELATING TO FI TNESS FOR A PARTICUL AR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLE CT UAL PROPE RTY RIGHT. Intel products are not intended for use in medi cal , life saving, or life sustaining applications.

Intel may make cha nges to speci ficatio ns and prod uct descript io ns at any time, witho ut noti ce.

This document contains information on products in the design phase of development. The information here is subject to change without notice. Do not

finalize a design with this information.

The Intel® Wireless Flash Memory (W18/W30 SCSP); 128-Mbit WQ Family with Asynchronous SRAM may contain design defects or errors known as

errata which may cause the produc t to deviate from publishe d specificat i ons. Current characterized errata are available on request.

Contact your local Intel sale s office or your distribu tor to obtain the latest specifi cation s and befo re placing your product order.

Copies of documents which have an ordering numb er and are referenc ed in this docume nt, or other Intel literature may be obtained by cal lin g 1-800-

548-4725 or by visiting In tel's we bsite at http://ww w.intel.com.

Copyrigh t © Intel Corpor at ion, 2005.

*Other names and br ands m ay be claimed as the proper ty of others.

Datasheet 3

Contents

1.0 Introduction....................................................................................................................................7

1.1 Nomenclature .......................................................................................................................7

1.2 Conventions..........................................................................................................................7

2.0 Fu n ctional Overview .....................................................................................................................9

2.1 Block Di a gram ....... .... ...... ....... ... ....... ....... ... ....... ...... ....... ... ....... ....... ... ....... ...... .... ...... ...........9

2.2 Flash Memory Map and Partitioning...................................................................................10

3.0 Package Information...................................................................................................................12

3.1 80-Acti v e Ball Single or Doub le -D ie SCSP........ ...... .... ...... ....... ... ....... ....... ... ....... ...... .... .....12

3.2 80-Acti v e Ball Tripl e -Di e SCSP ..... ...... .... ...... ....... ... ....... ....... ... ....... ...... .... ...... ....... ... ....... ..13

4.0 Ball out an d Signa l Descri ptions ................................................................................................14

4.1 Signal Ballout......................................................................................................................14

4.2 Signal Descriptions.............................................................................................................15

5.0 Ma xim um Ratings and Operat i ng Conditions...........................................................................17

5.1 Absolute Maximum Ratings................................................................................................17

5.2 Operati n g Cond iti o n s....... .... ...... ....... ... ....... ....... ... ....... ...... .... ...... ....... ... ....... ....... ... ....... .....18

5.3 Capacitance........................................................................................................................18

6.0 Electrical Specifications.............................................................................................................19

6.1 DC Characteristics..............................................................................................................19

7.0 AC Characteristics ......................................................................................................................20

7.1 Flash AC Char ac te ris ti cs..... ...... ....... ... ....... ....... ... ....... ...... .... ...... ....... ... ....... ....... ... ....... .....20

7.2 PSRAM AC Characteristics................................................................................................21

7.3 PSRAM Operations ............................................................................................................25

7.4 Power- up Seq uenc e and Ini tia l iza ti o n ..... ... ....... ...... .... ...... ....... ... ....... ....... ... ....... ...... .... .....25

7.5 Mode Register ....................................................................................................................25

7.5.1 Mode Register Setting...................................................................................................26

7.5.2 Cautions for setting Mode Register ...............................................................................28

7.6 Low Power mode....... ...... ....... ... ....... ....... ... ....... ...... .... ...... ....... ... ....... ... ....... ....... ... ....... .....29

8.0 Device Op erat ion.........................................................................................................................30

8.1 Bus Operations...................................................................................................................30

8.2 Flash Co mmand De fin i tio ns.... ....... ... ....... ...... .... ...... ....... ... ....... ....... ... ....... ...... ....... ... ....... ..32

4Datasheet

9.0 Flash Read Operations ...............................................................................................................32

10.0 Flash Program Operations .........................................................................................................32

11.0 Flash Erase Operations ..............................................................................................................33

12.0 Flash Security Modes..................................................................................................................33

13.0 Flash Read Configuration Register ...........................................................................................33

14.0 Flas h Power Consumption .........................................................................................................33

Appendix A Writ e S tate M achi n e ........................................................................................................34

Appendix B C ommon Flash Interface.................................................................................................34

Appendix C Flas h Flowcha rts .............................................................................................................34

Appendix D A dditi onal Inform at io n ....................................................................................................35

Appendix E Ordering Infor mation.......................................................................................................36

Datasheet 5

Revision History

Date of

Revision Version Description

10/02 -001 Initial draft

4/4/03 -002 General language and format edit; also edited out some line items.

5/6/03 -003 Update the 64M-bit PS, ICC, ISB, and IDP current.

10/03 -004 Updated to resolve some format issues.

5/04 -005 Restructured the datasheet according to the new layout.

6/04 -006 Added part number 128W18+128W18 to Table 1 and Table 16.

Updated the DC and AC specifications.

6/05 -007 Updated Table 16

6Datasheet

Datasheet 7

1.0 Introduction

This document contain s information pe rtaining to the S tacked Chip Scale Package (SCSP)

products included in the Intel® Wireless Flash Memory (W18/W30 SCSP) family. The intent of

this document is to provide information where the SCSP family differs fr om the Intel® Wireless

Flash Memor y (W18/W30) dis crete device.

Refer to the late st revision Intel® Wirele ss Flash Mem ory (W18) datasheet (order number 290 701)

and Intel® Wirele ss Flash Memory (W30) da ta sheet (order number 290702) for flash product

details not included in this document.

1.1 Nomenclature

0x Hexadecimal prefix

0b Bi na ry pr e fix

Byte 8 bits

CUI Comman d User Interface

DU Do not Use

ETOX EPROM T unnel Oxide

k (noun) 1 thousand

Kb 1024 bits

KB 1024 bytes

Kword 1024 words

M (noun) 1 million

Mb 1,048, 576 bits

MB 1,048,576 bytes

O TP One Time Programmabl e

PLR Protection Lock Register

PR Protection Register

PRD Protection Register Data

RCR Re ad Configuratio n Re giste r

RFU Reserved for Future Us e

SCSP Stacked Chip Scale Pack age

SR Status Register

SRD Status Register Data

Word 16 bits

1.2 Conventions

Group Membership Brackets: Squa re bracket s will be used to des ign ate group membersh ip or to

defi ne a group of signals with a similar fu nc tion, such as A[21:1] a nd SR[4,1], for

example.

VCC vs. VCC: When referr ing to a signal or pack age-connect ion name, the notation used is VCC,

etc. When referring to a timing or electrical level, the notation used i s sub scripted such as

VCC, etc.

Device: This term is used interchangeably throughout this document to denote either a particular

die, or the combination of the four die.

8Datasheet

CE #[2:1], O E #[ 2:1]: This is the method us ed to refer to more than one chip-enable or outp ut

enable at the same tim e. When ea ch is refer red to individually, the reference will be CE#1

an d OE#1 (for die #1), and CE#2 an d OE#2 (for die #2).

VCC, P-VCC, S-VCC: When r e ferencing flash memory signals or timi ngs, the notation used is

VCC or VCC, respectively. When the reference is to PSRAM signals or timi ngs, the

notation is prefixed with “P-” (e.g., P-VCC, P-VCC). When refere ncing SRAM si gnals or

timings, the notation is prefixed with “S-” (e.g., S-VCC or S-VCC).

R-OE# , R-L B# , R- UB # , R-WE #: Used to identif y OE#, LB#, UB#, WE# RAM signals , and ar e

usually shared between 2 or more RAM die.

Datasheet 9

2.0 Functional Overview

This sect ion provides an overview of the features and cap abilities of the Intel® Wireless Flash

Memory (W18/30 SCSP) family .

The Intel® Wireless Flash Mem ory (W18/W30 SCSP) family encompasses m ultip le flash memory

+ PSRAM die comb inations. Product s range from a flas h-only, dual-flash , dual-flash + PS RAM

device. The user can choose PSRAM combined with one or two flash memory dies, all offered in

the same package footprint and signal ballout.

2.1 Block Diagram

Figure 1 is a block diagram showing all inter nal package con nections for the SCSP fam ily with

mul tiple dies. Refer to Table 1, “W1 8/30 SCSP Family Ma trix” on pa ge 9 for valid combinations

of flas h and PSRAM die. Unused co nnections on combinations with less tha n triple die are

reserve d a nd should no t be used.

Figure 1. Block Diagram

Fla sh Di e #2

PSRAM Di e

Fla sh Di e #1

VCC2

P-VCC

CE#2

OE#2

R-WE#

R-UB#

R-LB#

P-MODE

VSS

VCC1

CE#1

OE#1

A[MAX:0]

P-CS#

R-OE#

A[MAX:0] D[15:0]

CLK

WP#

ADV#

RST#

WE#

VCCQ

VPP

WAIT

10 Datasheet

2.2 Flash Me mory Map and Partitionin g

Consult the la te st Intel® Wirel e ss Flash Me mory (W18) datas hee t (or der number 290701) and

Intel® Wi re less Flas h Me mory (W30) datas he et (order numbe r 290702) for i ndividual fla sh di e

memory m a p and par titioning informati on.

Refer to Table 1, “W 18/30 S C SP Family Matrix” on page 9 for valid conf igura tions pe r SCSP

combination. Table 1, “Fla sh Die Me mory Map and Par titioning” on pa ge 10 shows the Memory

Map and Partitioning informat ion for two flash mem ory die . Fl ash Die#1(wi th CE #1 as its Chip

Select) is confi gured to bottom boot while Flash Die#2 (with CE#2 as its Chip Select) is configu red

to top boot.

Table 1. Flash Die Memory Map and Partitioning

Flash

Die# Partitioning Block Size

(KW) Blk# Address Range

Flash die (Top Parameter)

128M-bit

Parameter Partition One Partition 4 255-262 7F8000-7FFFFF

32 248-254 7C0000-7F7FFF

Main Partitions

One Partition 32 240-247 780000-7BFFFF

One Partition 32 232-239 740000-77FFFF

One Partition 32 224-231 700000-73FFFF

Four Partitions 32 192-223 600000-6FFFFF

Eight Partitions 32 128-191 400000-5FFFFF

Sixteen Partitions 32 0-127 000000-3FFF FF

Flash die (Bottom

Parameter)

128 Mbit

Main Partitions

Sixteen Partitions 32 135-262 400000-7FFFFF

Eight Partition 32 71-134 200000-3FFFFF

Four Partitions 32 39-70 100000-1FFFFF

One Partition 32 31-38 0C0000-0FFFFF

One Partition 32 23-30 080000-0BFFFF

One Partition 32 15-22 040000-07FFFF

Parameter Partition One Partition 32 8-14 008000-03FFFF

4 0-7 000000-007FFF

Datasheet 11

3.0 Package Information

3.1 80-Active Ball Single or Double-Die SCSP

Fig ur e 2. SCSP QUAD + Mechanical Specificat ions (8x10 x1.2 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.200 0.0472

Ball Height A1 0.200 0.0079

Pa c kage Body Thickness A2 0 .860 0. 0339

Ball (Lead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Pa c kage Body Length D 9.900 10.00 0 10. 10 0 0. 3898 0.3937 0.3976

Pa c kage Body Width E 7. 900 8. 00 0 8.100 0. 3110 0.3150 0.3189

Pitch e 0.800 0.0315

Ball ( Lea d) Count N 88 88

Seating Plane Coplanarity Y 0.100 0.0039

Corne r to Ball A1 Distanc e Along E S1 1. 10 0 1. 20 0 1.300 0. 0433 0.0472 0.0512

Corne r to Ball A1 Distanc e Along D S2 0. 50 0 0. 60 0 0.700 0. 0197 0.0236 0.0276

T op View - Ball D own Bot tom View - Ball Up

Drawing not to scale.

2345678

A1 I ndex

Mark

12345678

12 Datasheet

3.2 80-Active Ball Triple-Die SCSP

Fig ur e 3. SC S P QUAD+ Mechani cal Spe cificatio n s (8x1 0x1. 4 mm)

Millimeters Inches

Dimensions Symbol Min Nom Max Notes Min Nom Max

Package Height A 1.400 0.0551

Ball Height A1 0.200 0.0079

Pac kage Body Thickness A2 1.070 0. 04 21

Ball (L ead) Width b 0.325 0.375 0.425 0.0128 0.0148 0.0167

Pac kage Body Length D 9. 900 10.000 10 .1 00 0.3898 0.3937 0.3976

Pac kage Body Width E 7.90 0 8. 000 8. 10 0 0. 3110 0.3150 0.3189

Pitch e 0.8 0 0 0.031 5

Ball (Lead) Count N 88 88

Seating Plane Coplanarity Y 0.100 0.0039

Corner to Ball A1 Distance Along E S1 1.100 1.200 1.300 0.0433 0.0472 0.0512

Corner to Ball A1 Distance Along D S2 0.500 0.600 0.700 0.0197 0.0236 0.0276

T op Vi ew - Ba ll D ow n Bot tom View - Ball U p

Drawing not to scale.

12345678

Index

Mark 12345678

Datasheet 13

4.0 Ballout and Signal Descriptions

4.1 Signal Ballout

The Intel® W ireless Flash Memor y (W30 SCSP) fam ily is availab le in an 88-ball (80 -active ball)

Stacked Chip Scal e Package (SCSP) with a ball pitch of 0.8 mm, as show n in Figure 4.

Fig u re 4. 88-Bal l (8 0-Active Bal l) SCS P Pack ag e Bal l o u t

NOTE: Solid balls are sh own as ballout d ifferenc es be tween va r ious stacked combinations

acro ss the Stacked-CSP Family. See Signal Descriptions for de ta ils on the electrical

conne ctions pe r stacked combination .

Top View - Ball Side Down

87654321

DU DU DU

DUDUDU DU

A2 A7

A1 A6

A18 A19 VSS

VSSA23

A24

A25

A17

VCC2

CLK

A21

A22 A12

A11

A13A9P-CS#

VPP,

VPEN

A20 A10 A15

WE# A8

D8 D2 D10 D5 D13 WAIT

A14 A16

CE#1 P-Mode

VSS VSS VSS

RFU

VCC1

VCC2 VCCQRFU

D0 D1

D4 D6

D15D11

D12 D14

OE#1

OE#2

P-VCC

S-CS2

R-WE#

R-UB#

R-LB#

R-OE#

S-VCC

S-CS1#

VCC1

WP# ADV#

RST#

CE#2

VCCQ

VSS VSSVCCQ VSS

Bottom V ie w - Ball S i de Up

87654321

DUDUDU

DU DU DUDU

A2A7

A1A6

A18A19VSS

VSS A23

A24

A25

A17

VCC2

CLK

A21

A22A12

A11

A13 A9 P-CS# VPP,

VPEN

A20A10A15

WE#A8

D8D2D10D5D13WAIT

A14A16

CE#1P-Mode

VSSVSSVSS

RFU

VCC1

VCC2VCCQ RFU

D0D1

D4D6

D15 D11

D12D14

OE#1

OE#2

P-VCC

S-CS2

R-WE#

R-UB#

R-LB#

R-OE#

S-VCC

S-CS1#

VCC1

WP#ADV#

RST#

CE#2

VCCQ

VSSVSS VCCQVSS

14 Datasheet

4.2 Signal De scrip tions

Table 2 describe s the activ e signa ls used on th e Intel® Wireless Flash Memory (W30 SCSP) family.

Table 2. Signal Desc ri ptions (She et 1 of 2)

Symbol Type Descriptions

A[Max:0] Input

ADDRESS INPUTS for memory addresses of a SCSP device with:

•4 Mbit density: A[Max]=A17

•8 Mbit density: A[Max]=A18

•32 Mbit density: A[Max]=A20

•64 Mbit density: A[Max]=A21

•128 Mbit density: A[Max]=A22

D[15:0] Input/

Output

DATA INPUTS/OUTPUTS: Inputs dat a a nd c ommands durin g w riting cy cles, output s data

during memory, status register, protection register and configuration code reads. These

signals float when the die or outputs are deselected. Data is internally latched during

writes.

CE#1

CE#2 Input

FLASH CHIP ENABLE: CE#-low selects the flash component. When asserted, the flash

internal control logic, input buffers, decoders, and sense amplifiers are activated. When

deasserted, the flash die is deselected, power reduces to standby levels, and data and

WAIT outputs are placed in high-Z state.

CE#1 connects to Flash Die#1 Chip Enable while CE#2 connects to Flash Die#2 Chip

Enable. CE#2 is only connected for SCSP combinations with 2 flash dies.

RST# Input

FLASH RESET: RST#-low resets flash internal circuitry and inhibit s write o per ations. This

function may be employed to provide data protection during power transitions. After

exiting the reset state (RST# returned to logic-high), the selected flash die resumes

operation in asynchronous read-array mode.

OE#1

OE#2 Input

FLASH OUTPUT ENABLE: OE#-low activates device output through the flash data

buffers during a flash read cycle. When deasserted, the flash outputs tri-state to high-Z.

OE#1 connects to Flash Die#1 Output Enable while OE#2 connects to Flash Die#2

Output Enable. OE#2 is only connected for SCSP combinations with 2 flash dies.

WE# Input FLASH WRITE ENABLE: WE# controls writes to the selected flash die. WE#-low allows

input to the flash CUI, array, PR/PLR, RCR, or block lock bits. Addresses and data are

latched on this signal’s rising edge.

ADV# Input

FLASH ADDRESS VALID: ADV# indicates valid address presence on address inputs of

the selected flash die. During synchronous read operations, all addresses are latched on

ADV#’s rising edge or CLK’s rising (or falling) edge, whichever occurs first.

CLK Input

FLASH CLOCK: CLK synchronizes the selected flash die to the system bus frequency in

synchronous-read configuration and increments an internal burst address generator.

During synchronous read operations, addresses are latched on ADV#’s rising edge or

CLK’s rising (or falling) edge , whiche ver o ccurs first.

CLK is only used for synchronous mode. Refer to flash product discrete datasheet for

information how to use this signal in asynchronous mode.

WAIT Output

FLASH WAIT: Wait is driven when CE# is asserted. Flash RCR[10][WP] determines the

WAIT asserted logic level.

•In synchronous array read modes, WAIT indicates invalid data when asserted and

valid data when de-asserted.

•In synchronous non-array read modes, asynchronous page mode, and all write

modes, WAIT is asserted.

Refer to flash product discrete datasheet for more information.

Datasheet 15

WP# Input

FLASH WRITE PROTECT: Enables/disables the lock-down mechanism of the selected

flash die.

When WP# is logic low, the lock-down mechanism is enabled and blocks marked lock-

down can not be unlocked through software.

VPP Power FLASH PROGRAM / ERASE SUPPLY: Valid VPP voltage on this ball allow block erase

and pr ogram fu nctions . Flas h m emory array c ontent s c annot be al ter ed when VPP<VPPLK.

Block Erase and program at invalid VPP Voltage should not be attempted.

VCC1

VCC2 Power FL A S H POWE R SUP PLY: Supplies power to the flash core. VCC1 connects to Flash

Die#1 power supply while VCC2 connects to Flash Die#2 power supply.

VCC2 is only connected for SCSP combinations with 2 flash dies.

VCCQ Power OUTPUT BUFFER POWER SUPPLY: Supplies power for the input and output buffers.

VSS Power GROUND: Do not float any VSS connection.

S-CS1#

S-CS2 Input

SRAM CHIP SELECTS: Activates the SRAM internal control logic, input buffers,

decoders, and sense amplifiers. When either are deasserted (S-CS1# = VIH or S-CS2 =

VIL), the SRAM is deselected and its power reduces to standby levels.

S-CS1# and S-CS2 are only connected for SCSP combinations with SRAM die.

R-OE# Input

RAM OUTPUT ENABLE: R-OE#-low activates device output through the selected RAM

data buffers during a RAM read cycle. When deasserted, the selected RAM outputs tri-

state to high-Z.

R-OE# is only connected for SCSP combinations with 1 or more RAM die.

R-WE# Input RAM WRITE ENABLE: R-WE#-low allows writes to the selected RAM array.

R-WE# is only connected for SCSP combinations with 1 or more RAM die.

R-UB#

R-LB# Input RAM UPPER / LOWER BYTE ENABLES: R-UB#-low enables the selected RAM high-

order bytes (D[15:8]). R-LB#-low enables the selected RAM low-order bytes (D[7:0]).

R-UB# and R-LB# are only connected for SCSP combinations with 1 or more RAM die.

S-VCC Power SRAM POWER SU PPLY: S upplies power for SRAM operations.

S-VCC is only connected for SCSP combinations with SRAM die.

P-CS# Input

PSRAM CHIP SELECT: Activates the PSR AM internal control logic, input buffers,

decoders, and sense amplifiers. When deasserted, the PSRAM is deselected and its

power reduces to standby levels.

P-CS# is only connected for SCSP combinations with PSRAM die.

P-Mode Input PSRAM REFRESH: When deasserted, it enables PSRAM Lower Power Mode with partial

array refresh or zero array refresh according to the Mode register setting.

P-Mode is only connected for SCSP combinations with PSRAM die.

P-VCC Power PSRAM POWER SUPPLY: Supplies power for PSRAM operations.

P-VCC is only connected for SCSP combinations with PSRAM die.

RFU — RESERVED for FUTURE USE : Do not drive RFU balls and leave them disconnected.

Contact Intel regarding their future use.

DU — DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.

Table 2. Signal Descriptions (Sheet 2 of 2)

Symbol Type Descriptions

16 Datasheet

5.0 Maximum Ratings and Op erating Con ditions

5.1 Absolute Max i mum Ratings

Warning: Stress ing the device beyon d the “ Absolute Maximum Ratings” may cause permanent damage.

These a re stress ratings only. Ope ration beyond the “Operating Conditions” is not recom mend e d

and extended exp os ure beyond the “Op erating Conditions” may af fect device reliabil ity.

NOTICE: This document contains information available at the time of its release. The specifications are

subject to change without notice. V er ify with your local Intel sales office that you have the latest datasheet

before finalizing a design.

Table 3. Absolute Maximum Ratings

Parameter Min Max Unit Notes

Temperature under Bias Expanded –25 +85 °C

Storage Temperature –55 +125 °C

Voltage On Any Signal (except VCC1, VCC2,

VCCQ, VPP, and P-VCC)

1.8 V I/O –0.2 +2.45 V 1

3.0 V I/O –0.2 +3.6 V 1

VCC1 and VCC2 Voltage –0.2 +2.45 V 1

VCCQ, and P-VCC Voltage –0.2 +3.6 V 1

VPP Voltage –0.2 +14.0 V 1,2,3

ISH Output Short Circuit Current – 100 mA 4

Notes:

1. All Specified voltages are relative to VSS. Minimum DC voltage is –0.2 V on input/output signals, –

0.2 V on VCCX and VPP sig nals. D uring trans itions, this le vel may overshoot to –2.0 V for per iods <

20 ns, during transitions, may overshoot to VCC + 2.0 V for periods < 20 ns.

2. Maximum DC voltage on VPP may overshoot to +14.0 V for periods < 20 ns.

3. VPP program voltage is normally VPP1. The maximum DC voltage on VPP may overshoot to +14 V

for periods < 20 ns. VPP can be VPP2 for 1000 erase cycles on main blocks, 2500 cycles on

parameter blocks.

4. Output shorted for no more than one second. No more than one output shorted at a time.

Datasheet 17

5.2 Operating Conditions

5.3 Capacitance

Tab le 4. E xtend ed Temperature Operat ion

Symbol Parameter

Flash/

Flash+Flash Flash+PSRAM/

Flash+Flash+PSRAM

Unit

Min Max Min Max

TCOperating Temperature –25 +85 –25 +85 °C

VCC Flash Supply Voltage 1.7 1.95 1.7 1.95 V

VCCQ

P-VCC

Flash I/O Voltage

PSRAM Supply Voltage

1.8 V I/O 1.7 1.95 — — V

3.0 V I/O 2.2 3.3 2.7 3.1 V

VPP1 Flash Program Logic Level 0.9 1.95 0.9 1.95 V

VPP2 Flash Factory Program Voltage 11.4 12.6 11.4 12.6 V

Note: VPP is norma lly VPP1. VPP can be connected to 11 .4 V–12.6 V for 1000 c ycles on main blocks for extended

temperatures and 2500 cycles on parameter blocks at extended temperature.

NOTICE: Refer to the Intel® Wirel ess Flash Memory (W18 and W30) dat a sheets (order number

290701 and 29702) for flash capacitance details. For SCSP products with two flash die, flash

capacitances for each of the flash die need to be considered accordingly.

Table 5. PSRAM Capacitance

Symbol Parameter Max Unit Condition

CIN Input Capacitance 8 pF TA=25°C, f=1MHz,

VIN=0V

COUT Output Capacitance 1 0 pF

18 Datasheet

6.0 Electrical Specifications

6.1 DC Characteristics

PSRAM DC characteris tics are show n in Table 6. Refer to the Intel® W i rel ess Flash Memory (W18

and W30) Datasheets (order number 290701 and 290702) for Flash DC Characteristics.

NOTICE: DC Characteristics of all die in a SCSP device need to be considered accordingly,

depending on the SCSP device operation.

Tab le 6. P S RAM DC Characte ristics

Parameter Description Test Conditions Min Typ Max Unit

P-VCC Voltage Range 2.7 – 3.1 V

ICC Operating

Current at min

cycle time Iout=0mA 32M – – 45 mA

64M – – 50

ISB1 Standby Current P-CS#>=P-VCC-0.2V, P-

Mode>=P-VCC-0.2V 32M – 90 100 µA

64M – 110 150

ISB2 Partial Array

Refresh Current

(S t andby M ode 2)

P-CS#>=P-VCC-0.2V, P-

Mode<=0.2V

32M

16Mbits – 60 70

µA

8Mbits – 50 60

4Mbits – 40 50

0Mbits – 20 30

64M

16Mbits – 90 110

8Mbits – 80 100

4Mbits – 70 90

0Mbits – 60 80

Isbd De ep Po w e r

Down P-CS#>=P-VCC-0.2V, P-

Mode<=0.2V 32M – 20 30 µA

64M – 60 80

VOH Output High

Voltage IOH = -0.5m A 32M 0.8P-Vcc – – V

64M 0.8P-Vcc – –

VOL Output Low

Voltage IOL = 1mA 32M – – 0.2P-Vcc V

64M – – 0.2P-Vcc

VIH Input High

Voltage 0.8P-Vcc – P-VCC + 0.3 V

VIL Input Low

Voltage -0.3 – 0.2P-VCC V

*IIL Input Leakage

Current VIN=0V to P-Vcc –1.0 – +1.0

µA

*IOL Input/Output

Leakage Current VI/O= 0V to P-V cc, P-C S# =V IH or R-WE#=VIH or

R-OE#=VIH –1.0 – +1.0

* VIN: Input voltage, VI/O: Input/O utput v oltage

Datasheet 19

7.0 AC Characteristics

7.1 Flash AC Characteri stics

Refer to the Intel® Wirele ss Flash Memory (W 18/W30) Datashe e t s (o rder number 290701 and

290702) for Flash AC Characteristics de tails not included in Table 7 bel ow.

Tab l e 7. Fl ash AC R ead Charact eri stic s

Spec

Number Sym Parameter 128W18 128W30 64W30 Unit

Min Max Min Max Min Max

Asynchronous Specifications

R1 tAVAV Read Cycle Time 65 65 65 ns

R2 tAVQV Address to Output Delay 65 65 65 ns

R3 tELQV CE# Low to Output Delay 65 65 65 ns

R103 tVLQV ADV# Low to Output Delay 65 65 65 ns

Latching Specifications

R108 tAPA Page Address Access Time 25 25 25 ns

Clock Specifications

R304 tCHQV CLK to Output Delay 1 4 20 20 ns

20 Datasheet

7.2 PSRAM AC Characteristics

Table 8. PSRAM AC Characteristics—Read-Only Operations

# Symbol Parameter 32M 64M Unit Note

Min Max Min Max

Read Cycle

R1 tRC Read Cycle Time 65 – 65 – ns

R2 tAA Address access time – 65 – 65 ns

R3 tCO P-CS# Low to Output Valid – 65 – 65 ns

R4 tOE R-OE# Low to Output Valid – 45 – 45 ns

R5 tBA R-UB#, R-LB# Low to Output Valid – 65 – 65 ns

R6 tLZ P-CS# Low to Output in Low-Z 10 – 10 – ns

R7 tOLZ R-OE# Low to Output in Low-Z 5 – 5 – ns

R8 tHZ P-CS# High to Output in High-Z – 25 – 25 ns

R9 tOHZ R-OE# High to Output in High-Z – 25 – 25 ns

R10 tOH Output Hold from Address change 5 – 5 – ns

R11 tBLZ R-UB#, R-LB# Low to Output in Low-Z 5 – 5 – ns

R12 tBHZ R-UB#, R-LB# High to Output in High-Z – 25 – 25 ns

R13 tASO Address set to R -OE# low level 0 – 0 – ns 1

R14 tOHAH R-OE# high level to address hold -5 – -5 – ns

R15 tCHAH P-CS# high level to address hold 0 – 0 – 1

R16 tBHAH R-LB#, R-UB# high level to address hold 0 – 0 – 1,2

R17 tCLOL P-CS# low level to R-OE# low level 0 10,000 0 10,000 3

R18 tOLCH R-OE# low level to P-CS# high level 45 – 45 –

R19 tCP P-CS# high level pulse width 10 – 10 –

R20 tBP R -UB#, R-LB# high level pulse width 10 – 10 –

R21 tOP R -OE# high level pulse width – 10,000 – 10,000 3

Page Mode

PR1 tPC Page Cycle Time 18 – 18 – ns 4

PR2 tPA Page Mode Address Access Time – 18 – 18 ns

Note:

1. When.R13>=|R15|, |R16|. The minimum of R15 and R16 are -15ns. (See Figure 5, “Conditions for Calculating

R15 and R16 Minimum Values” on page 22.)

2. R16 is specified from when both R-LB# and R-UB# become high level.

3. R17and R21(MAX) are applied while P-CS# is being hold at low level.

4. See Figure 7, “AC Waveform of PSRAM Read Operations” on page 23.

Datasheet 21

Figure 5. Conditions for Calculati ng R15 and R16 Minimum Values

Table 9. PSRAM AC Characteristics—Write Operations

# Symbol Parameter 32M 64M Unit Note

Min Max Min Max

W1 tWC Write Cycle Ti me 65 – 65 – ns

W2 tAS Address Setup Time 0 – 0 – ns

W3 tWP Write Pulse Width 50 – 50 – ns

W4 tDW Data valid to Write End 30 – 30 – ns

W5 tAW Address valid to end of write 55 – 55 – ns

W6 tCW P-CS# to end of write 55 – 55 – ns

W7 tDH Data Hold time 0 – 0 – ns

W8 tWR Write Recovery 0 – 0 – ns

W9 tBW R-UB#, R-LB# Setup to end of Write 55 – 55 – ns

W10 tCP P-CS# High level pulse width 10 – 10 – ns

W11 tBP R-UB#, R-LB# High level pulse width 10 – 10 – ns

W12 tWHP R-WE# High level pulse width 10 – 10 – ns

W13 tOHAH R-OE# High level to address hold -5 – -5 – ns

W14 tCHAH P-CS# High level to address hold 0 – 0 – ns 1

W15 tBHAH R-UB#, R-LB# High level to address hold 0 – 0 – ns 1,2

W16 tOES R-OE# High level to R-WE# set 0 10,000 0 10,000 ns 3

W17 tOEH R-WE# High level to R-OE# set 0 10,000 0 10,000 ns

Notes:

1. When W2>=|W14|, |W15| and W10>=18ns, W14 and W15 (MIN) are -15ns. (See Figure 6, “Conditions for

Calculating R14 and R15 Minimum Values” on page 23.)

2. W15 is specified from when both R-LB# and R-UB# become high level.

3. W16 and W17(MAX) are applied while P-CS# is being hold at low level.

4. See Figure 9, “AC Waveform PSRAM Write Operation”

Address

R-UB#,R-LB#,

P-CS#

R15, R16

R13R-OE#

22 Datasheet

Note: In read cycle, P-Mode and R-WE# should be fixed to high level

Figure 6. C ondi tions for Calculating R14 and R15 Minimum Values

Figure 7. AC Waveform of PSRAM Rea d Opera tions

Address

R-UB#,R-LB#,

P-CS#

W14, W15

W2R-WE#

W10

Vih

Vil R2

Vih R3

Vil R8

Vih R5

Vil R12

Vih R4

Vil R9

R11

R6 R10

Voh High-Z High-Z

Vol

Data

out Valid

Output

Address

P-CS#

R-UB#,

R-LB#

R-OE#

Datasheet 23

Note: In page read cycle, P-Mode and R-WE# should be fixed to high level, and R-UB#, R-LB# are low level.

Notes:

1. During address transition, at least one of pins P-CS#, R-WE#, or both of R-UB# and R-LB# pins should

be inactivated.

2. Do not input data to the I/O pins while they are in the output state.

3. In write cycle, P-Mode and R-OE# should be fixed to high level.

4. Write operation is done during the overlap time of a low level P-CS#, R-WE#, R-LB# and/or R-UB#.

Fig ur e 8. AC Wa veform of PSRAM 8-Wo rd P ag e Read Operation

Vih

A3-A

MAX

Valid

Vil Address

Vih

A0,A1,A2 Vil 000

R2 PR1

P-CS# R3

PR2R-OE#,

R-UB#,

R-LB# R4

Voh High-Z Qn

Vol

Data o ut Qn+

Qn+

001 111

Figure 9. AC Waveform PSRA M Write Operation

Vih

Vil W2 W8

Vih W6

Vil

Vih W9

Vil

Vih W3

Vil

Voh W4 W7

High-Z High-Z

Vol

Address

P-CS#

R-UB#,

R-LB#

R-WE#

Data I/O Valid Data In

Low-Z

24 Datasheet

7.3 PSRA M Ope rations

7.4 Power-up Sequence and Initialization

The PSRAM func tionality an d re liabilit y a re independent of the power-up slew rate of the c ore P -

VCC. Any powe r-up slew rate is possible under use conditions.

The following po we r up sequence a nd operation should be used before sta rting normal opera tion.

The PSRAM power-up sequence is represented in Figure 10. Following power a pplication, make

P-Mod e high level after f ixing P-Mode to low level for the period of tVHMH. Make P-CS# high

leve l be fore making P-Mode high level. Then, P-CS# and P-Mode are fixed to high level for the

period of tMHCL.

Normal Operation is possible once the power up sequence is complete.

Notes:

1. Make P-Mode low level when starting the power supply.

2. tVHMH is specif ied fro m when the power supply volt age r eaches the presc ri bed minimum value (P-Vcc

(MIN))

7.5 Mode Registe r

The PSRAM die has an internal register that helps c ontrol the Low Power mode of the PSRAM.

This register is called the Mode register, or Mode register. The densitie s that can be selected for

performing refresh are 16 Mbits, 8 Mbits, 4 Mbits and 0 Mbit. The density for performing refresh

can be set with the Mode register. Once the refresh density has been set in the Mode reg is ter, these

Figure 10. Timing Wave form for Power up sequenc e

tVHMH

tMHCL

tCHMH

Initialization

Vcc (MIN )

N ormal O perat i on

P-CS#

P-Mode

P-Vcc

Table 10. Initialization timing

Parameter Symbol MIN MAX Unit

Power application to P-Mode low level hold tVHMH 50 us

P-CS# high level to P-Mode high level tCHMH 0ns

Following power applicatio n, P-Mode high level

hold to P-CS# low level tMHCL 200 us

Datasheet 25

settings are retained until they are set again, while applying the power suppl y. However, the Mode

after power application.

7.5.1 Mode Register Setting

Since the initial value of the Mode register at power app lication is undefin e d, be sure to se t the

Mode register after initialization at po we r application. Wh e n setti ng the dens ity of pa rtial refresh,

data before entering the Low Power Mode is no t guaran teed.(This is the same for re-setu p)

However, sinc e Lo w Power Mode is no t e ntered unless P-Mode=L, whe n par tia l refresh is not

used, it is not necessary to set the Mode register. Moreover, when using page read without using

partial refr esh, it is not necess a ry to set the Mode regis ter.

The Mode regi ster sett ing mode can be entered by successively writing two spec ific data after two

continuous reads of the highe st add ress. The Mode re giste r s e tting is a continuous four-cyc le

operatio n -two read cycles and two writes cycles. See Table 11 fo r set ting Mode re gis te r com mand

sequence.

For the timing chart and flow chart, refer to Figure 11 and Figur e 12 .

Table 11. Setting Mode Register Command Sequence

Command

Sequence 1st Bus Cycle

(Read Cycle) 2nd Bus Cycle

(Read Cycle) 3r d Bus Cycle

(Write Cycle) 4th Bu s Cycle

(Write Cycle)

Partial refresh

density Address Data Address Data Address Data Address Data

16 Mbits Highest

Address _Highest

Address 00H Highest

Address 04H

8 Mbits Highest

Address _Highest

Address 00H Highest

Address 05H

4 Mbits Highest

Address _Highest

Address 00H Highest

Address 06H

0 Mbit Highest

Address _Highest

Address 00H Highest

Address 07H

26 Datasheet

Note: xxH=04H, 05H, 06H or 07H

Figure 11. Mod e Registe r Update--Timing Waveform

Figure 12. Mode Registe r Setting Flow Chart

Highest Addre ss Highest Address Highest Address Highest Address

0000H 000XH

W4W7W4

Mode Register Setting

W1W1W1W1R1R1R1R1

Address

P-CS#

R-OE#

R-WE#

Data I/O

R-UB#, R-LB #

Data=00H

Write to Highest Address

Data=xxH

Begin Normal

Operation

Rea d High est Address

by Toggling both P-CS#

and R-OE#

START

Write to Highest Address

Rea d High est Address

by Toggling both P-CS#

and R-OE#

Fail

Mod e Register

setting exit

Datasheet 27

7.5.2 Cautions for setting Mode Register

Sin ce, f or the Mode regis ter settin g, the internal cou nter status is judged by toggling P-CS# and R-

OE#, togg le P-CS# at every cycle during entry (read cycle twice, write cycle twice) , and toggle R-

OE# like P-CS# at the fi rs t and second read cycles. If incorrect addresses or data are written, or if

addr es sed or data are written in the incorrect order, the setting of the Mod e register is not

pe rformed cor re ctly.

When the hig hes t address is read consecutively three or mor e tim es , the Mode regist er setting

entr ies ar e not per for med cor rectly. (Immed iately af ter the hi ghest addr ess is read, the s ett ing of the

Mode regist er is not perform e d corre c tly.) Pe rform the set ting of t he Mode register after power

appli cation or after accessing other than th e highest address.

Once t he refresh density has been set in the M ode register, these settings are retain ed until they are

set again, while applyi ng the power supply. However, the Mode register setting will become

unde fin ed if the power is turned off, so set the Mode regis te r again after power a pplicat ion.

28 Datasheet

7.6 Low Power mode

In addition to the regular Standby mode with a full density data hold, Low Power mode performs

partial dens ity data ref resh or ze ro density data refresh .

The Low Power mode allows cust om ers to turn off sections of the PSRAM die to save refresh

curren t. The PSRAM die is d ivid ed int o four sect ion s allo wing c ert ain sectio ns to be refre she d with

P-Mode tied Low.

In regular Standby mode, both P-CS# and P-Mode are high level. But in Low Power mode, P-

Mode is low level. In Low Power mode, if 0M bit is set as the density, it is necessary to perfor m

initializat ion the same w ay as after app lying power, in order to return to normal operation from

Low P o wer mode. R e fer to Fi gure 10, “Timing Wave form for Power up sequence” on page 25 fo r

timin g charts. When the densi ty has be en to set to 16 Mbits, 8 Mb its, or 4 Mbits in Low Power

mode, it is not neces sary to per form ini tialization to return to normal operatio n from Low Power

mode. For timing charts, refer to Figure 13, “Low Power mode -Entry/Exit (16/ 8/ 4/ 0 Mbits)” .

Figure 13. Low Po wer m ode -Entry/Exit (16/ 8/ 4/ 0 Mbits)

Table 12. Low Power mode -Entr y/ Exi t

Parameter Description Min Max Unit

tCHML Low Power mode entry, P-CS# high level to P-Mode# Low level 0 ns

tMHCL1 Low Power mode(16/8/4 Mbits hold) exit to normal operatio n, P-Mode High

level to P-CS# Low level 30 ns

tMHCL2 Low Power Mode(0 Mbit data hold) exit to normal operation, P-Mode High

level to P-CS# Low level 200 us

Notes:

1. tMHCL1 is the time it takes to return to normal operation from Low Power Mode (data hold: 16 /8 /4

Mbits).

2. tMHCL2 is the time it takes to return to normal operation from Low Power Mode (0 Mbits data hold).

tMHCL1/tMHCL2

tCHML

Low Power Mode

(Part ia l Array Ref resh/ Z ero R e f resh)

P-Mode

P-CS#

Datasheet 29

8.0 Device Operation

8.1 Bus Operations

Bus oper ations fo r the Intel® Wir eless Flash Memory (W 18/W30 SCS P) family involve the

fol low ing chip enable and out put enable signals, respectively.

•CE#1 for Flash Die#1 and CE#2 for Flash Die#2

•OE#1 for Flash Die #1 and OE#2 for F l a sh Di e #2

All other cont rol signals are shar ed between the two flash die. T able 13 to Table 14 explain s the bus

operations of products across this SCS P family. Refer to the W18 and W30 datasheets (orde r

numbers 290701 a nd 290 702) f or single flash die SCSP bus ope rations.

Table 13. Flash Die#1 + Flash Die#2 Bus Operations

Device

Mode

RST#

CE#1

OE#1

WE#

ADV

VPP

WAIT

CE#2

OE#2

D[15:0]

Notes

Flash Die#1 Enabled

Sync Array Read H L L H L X Active H X Flash

DOUT 2,3,4

All Async /

Sync No n-Array

Read HLLHX XAsserted H X Flash

DOUT 1,3,4,5

Write H L H L X VPP1

VPP2 Asserted H X Flash

DIN 3,4,6

Output Disable H L H H X X Active X X Flash

High-Z 4

Standby H H X X X X High-Z X X Flash

High-Z 4

Reset LXXXX XHigh-Z X X Flash

High-Z 4

30 Datasheet

Flash Die#2 Enabled

Sync Array Read H H X H L X Active L L Flash

DOUT 2,3,4

All Async /

Sync Non-Array

Read HHXHX XAsserted L L Flash

DOUT 1,3,4,5

Write H H X L X VPP1

VPP2 Asserted L H Flash

DIN 3,4,6

Output Disable H X X H X X Active L H Flash

High-Z 4

Standby HXXXX XHigh-Z H X Flash

High-Z 4

Reset LXXXX XHigh-Z X X Flash

High-Z 4

Notes:

1.For a synch ronous rea d operati on, both die may be simul t aneo usly sel ected, but m ay not si mult aneousl y drive th e mem ory

bus. See Section 8.2, “Flash Command Definitions” on page 32 for details regarding Flash selection overlap.

2.WA IT is only acti ve during synchronous Flash reads. WAIT is driven if CE# is asserted. Refer to the Intel® Wireless Flas h

Memory (W18 and W30) datasheets (order numbers 290701 and 290702) for further information regarding WAIT

Signal.

3.For either Flash die, OE#1/OE#2 and WE# should never be assert ed simultaneous ly. If done so on a particular Flash die,

OE#1/OE#2 will override WE#.

4.L means VIL while H means VIH. X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for VPP.

5.Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].

6.Refer to W30 datasheet for valid DIN during Flash writes.

Table 14. Flas h (Single Die/Dual Die) + PSRAM Bus Operations

Device

Mode

RST#

CE#X

OE#X

WE#

ADV#

VPP

WAIT

P-CS#

P-Mode

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

Flash Die(#1 or #2) Enabled

Sync Array

Read HLLHL X Active

PSRAM must be in High-Z

Flash

DOUT 1,2,3,

4,6

All Async/

Sync Non-

array

Read HLLHX XAsserted Flash

DOUT 1,2,3,

4,6,7

Write H L H L L VPP1

VPP2 Asserted Flash

DIN 3,4,6,

Output

Disable HLHHX X Active

Any PSRAM mode allowed

Flash

High-Z 6

Standby HHXXX XHigh-Z Flash

High-Z 6

Reset LXXXX XHigh-Z Flash

High-Z 6

Device

Mode

RST#

CE#1

OE#1

WE#

ADV

VPP

WAIT

CE#2

OE#2

D[15:0]

Notes

Datasheet 31

8.2 Flash Command Definitions

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

290702) for in form a tion regar ding Fl a sh Command Defi nitions.

9.0 Flash Read Operations

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

290702) for informatio n regardin g flash read modes and op e rations.

10.0 Flash Program Operations

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

290702) for informatio n regardin g flas h progr a m oper a tions.

PSRAM Enabl ed

Read Flash must be in High-Z

Note 2

LHLHL

PSRAM

DOUT 1,5

Write L H H L L PSRAM

DIN 5

Output

Disable

Any flash mode allowed

LHHHX

PSRAM

High-Z 6

Standby H H X X X PSRAM

High-Z 6

Low

Power

Mode XLXXX

PSRAM

High-Z 6

Notes:

1.For asynchr onous read oper ation , all dies may be simult aneousl y select ed, but may not simultaneously drive the

memory bus. For synchronous burst-mode reads, only two die (one flash and the PSRAM) may be

simultaneously selected.

2. WA IT is only valid during sy nchronous flash r eads. Refer to the discrete datas heet for detail ed Wait functi onality.

3. CE#X is CE#1 for Flash Die#1, CE#2 for Flash Die#2. OE#X is OE#1 for Flash Die#1, OE#2 for Flash Die#2.

4.For either flash die, OE#X and WE# should never be asserted sim ult aneously. If done so on a particul ar flash die,

OE#X will override WE#.

5.For PSRAM, R-OE# and R-WE# should never be asserted simultaneously.

6.X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for VPP.

7.Flash CFI query and status register accesses use D[7:0] only, all other reads use D[15:0].

8.Refer to W30 datasheet for valid DIN during flash writes.

Tab le 14 . Flash (Single Die/Dual Die) + PSRAM Bu s Oper ation s

Device

Mode

RST#

CE#X

OE#X

WE#

ADV#

VPP

WAIT

P-CS#

P-Mode

R-OE#

R-WE#

R-UB#,

R-LB#

D[15:0]

Notes

32 Datasheet

11.0 Flash Erase Operations

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datasheets (o rder numbe r 290701 and

290702) for information regarding flash erase ope rations.

12.0 Flash Security Modes

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datasheets (o rder numbe r 290701 a nd

290702) for i nformation regarding fl a sh securit y modes a nd oper a tions.

13.0 Flash Read Configuratio n Register

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datasheets (o rder numbe r 290701 a nd

290702) for inf ormation regarding flas h Read Conf igura tion Regi ster (RCR) functions and

programming.

14.0 Flash Power Consumption

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datasheets (o rder numbe r 290701 a nd

290702) for information regarding flash power c onside rations and consumption.

Datasheet 33

Appendix A Write State Machine

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

2907 02) for the Write State Machine details.

Appendix B Common Flash Interface

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

2907 02) for the Common Flash Interface detail s.

Appendix C Flash Flowcharts

Refer to the Intel® Wireless Flash Memory (W18 and W30) Datashe e ts (order nu mber 290701 and

290702) for the flash flowchart de ta ils.

34 Datasheet

Appendix D Additional Information

Order Number Document

290701 Intel® Wireless Flash Memory (W18) Datasheet

290702 Intel® Wireless Flash Memory (W30) Datasheet

Notes:

1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International

customers should contact their local Intel or distribution sales office.

2. For the most current information on Intel ® Flash memory products, software and tools, visit our

website at http://developer.intel.com/design/flash.

Datasheet 35

Appendix E Ordering Information

E.1 Device Name Decoder

Figure 14 shows th e decod er for prod uct s in this SCSP fam ily with bo th f lash and RAM. Figure 15

sho ws the decoder for product s in this SC SP family with fla sh die only ( no RAM).

Figure 14. Decoder for Flash + RAM SCSP Device Name

F 3 3 W 0 Z D Q8D 3R

Package

Pi nout I ndi cator

Pr oduct Line Desi gnat or

Fl ash Densit y

Voltage

Pr oduct Family

R D = Leaded

PF = Lead- free

38F = S tacked- C S P Intel®

F lash Memory, Flash & RAM

0 = No die

W = Intel

Wi reless Flash Memory

0 = No Die Z = 3.0 V I/O, 1.8 V Core

Q= QUAD+ ballout

5 0

RAM Density

0 = No Di e

1 = 4 M b it

2 = 8 M b it

4 = 32 M bit

Parameter Location

B = Bottom Parameter

T = Top Parameter

Devi ce Details

0 = Original version of

the products:

W30 Speed = 20 ns Sync/

25ns Page/ 65 ns A sy nc

F lash P r ocess = 0. 13 µm

Flash #1

Flash #2

Flash #1

Flash #2

RAM #2

RAM #1

3 = 128 Mbit

5 = 64 Mb it

RAM = SRAM/PSRAM

D = Dual Parameter

Y = 1.8 V I/O, 1.8 V Core

36 Datasheet

Figure 15. Dec oder f or Flash- Onl y SCSP De vice Name

F 3 3 W 0 Y D Q8F 4P

Package

Pinout I ndicat or

Product L ine Designato r

Flash Densit y

VoltageProduct Family

RD = Leaded

PF = Lead-f r ee

48F = Intel

Flash Memory, Multiple

Flash- only Die

2 = 64 Mbit

0 = No Di e

W = Intel

Wireless memory

0 = No Di e Y = 1.8V core, 1. 8V I/ O

Z = 1.8 V core, 3. 0 V I/ O

Q = QUAD+ Ballout

0 0 0

Parameter Location

D = Bottom Parameter for Flash

Bank #1 (CE#1); Top Param et er

f or Flash Bank #2 (CE#2)

T = To p Par am eter

B = Bo t tom Par a m eter

Device Detai ls

0 = Or iginal vers ion of t his product

Flash #1

Flash #2

Flash Family 1/2

Flash #4

Flash #3

Flash Family 3/4

3 = 128 Mbit

pro

duc

Flash Process = 0. 13 µm

Size = 8 x 10 x 1.2 mm

W18 Speed = 14 ns Sync/

25ns Page/65 ns Async

Datasheet 37

E.2 Device Name List

Table 15, “W18 /30 SCSP Family Matrix” on page 38 shows the complete list of device names for

product s with double flash dies. Flash Die#1 is c onfig ured bo ttom para meter while Flash Die#2 is

configured top parameter.

Tab le 15 . W18/30 SC S P Famil y Matr ix

I/O

Voltage

(V) Flash RAM Package Size (mm) Part Number Notes

Size Ball Type

1.8 128W18+128W18 — 8x10x1.2 Lead-free SCSP QUAD+ PF48F3300W0YDQ0 1

3.0 128W30+128W30 64PSRAM 8x10x1.4 Leaded SCSP QUAD+ RD38F3350WWZDQ1 1

Notes:

1. D = A 2-Die stack device, where die#1 = Bottom Parameter and Die#2 = Top Parameter.