MOTOROLA CMOS LOGIC DATA 1
MC14581B
The MC14581B is a CMOS 4–bit ALU capable of providing 16 functions of
two Boolean variables and 16 binary arithmetic operations on two 14–bit
words. The level of the mode control input determines whether the output
function is logic or arithmetic. The desired logic function is selected by
applying the appropriate binary word to the select inputs (S0 thru S3) with
the mode control input high, while the desired arithmetic operation is
selected by applying a low voltage to the mode control input, the required
level to carry in, and the appropriate word to the select inputs. The word
inputs and function outputs can be operated with either active high or active
low data.
Carry propagate (P) and carry generate (G) outputs are provided to allow
a full look–ahead carry scheme for fast simultaneous carry generation for the
four bits in the package. Fast arithmetic operations on long words are
obtainable by using the MC14582B as a second order look ahead block. An
inverted ripple carry input (Cn) and a ripple carry output (Cn+4) are included
for ripple through operation.
When the device is in the subtract mode (LHHL), comparison of two 4–bit
words present at the A and B inputs is provided using the A = B output. It
assumes a high–level state when indicating equality. Also, when the ALU is
in the subtract mode the Cn+4 output can be used to indicate relative
magnitude as shown in this table:
Data
Level CnCn+4 Magnitude
Active
High H
L
H
L
H
H
L
L
A
v
B
A < B
A > B
A
w
B
Active
Low L
H
L
H
L
L
H
H
A
v
B
A < B
A > B
A
w
B
•Functional and Pinout Equivalent to 74181.
•Diode Protection on All Inputs
•All Outputs Buffered
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 623
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBDW SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 709
DW SUFFIX
SOIC
CASE 751E
PIN ASSIGNMENT
S0
S2
S3
A0
B0
MC
Cn
S1 B2
A2
B1
A1
VDD
P
Cn+4
G
5
4
3
2
1
10
9
8
7
6
14
15
16
17
18
19
20
13
11
12
21
22
23
24
F3
A = B
B3
A3
F2
VSS
F1
F0
MOTOROLA CMOS LOGIC DATAMC14581B
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
DD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 1.2
– 0.64
– 1.6
– 4.2
—
—
—
—
– 1.0
– 0.51
– 1.3
– 3.4
– 1.7
– 0.88
– 2.25
– 8.8
—
—
—
—
– 0.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.8 µA/kHz) f + IDD
IT = (3.7 µA/kHz) f + IDD
IT = (5.5 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.008.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA 3
MC14581B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Sum in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
tPHL 5.0
10
15
—
—
—
705
250
180
1410
500
360
ns
Sum in to Sum Out (Logic Mode)
tPLH, tPHL = (1.7 ns/pF) CL + 520 ns
tPLH, tPHL = (0.66 ns/pF) CL + 182 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
tPHL 5.0
10
15
—
—
—
605
215
180
1210
430
360
ns
Sum in to A = B
tPLH, tPHL = (1.7 ns/pF) CL + 870 ns
tPLH, tPHL = (0.66 ns/pF) CL + 297 ns
tPLH, tPHL = (0.5 ns/pF) CL + 220 ns
tPLH,
tPHL 5.0
10
15
—
—
—
955
330
245
1910
660
490
ns
Sum in to P or G
tPLH, tPHL = (1.7 ns/pF) CL + 400 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
tPHL 5.0
10
15
—
—
—
485
180
130
970
360
260
ns
Sum in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 530 ns
tPLH, tPHL = (0.66 ns/pF) CL + 187 ns
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns
tPLH 5.0
10
15
—
—
—
615
220
160
1230
440
360
ns
Carry in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 295 ns
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns
tPLH, tPHL = (0.5 ns/pF) CL + 80 ns
tPLH,
tPHL 5.0
10
15
—
—
—
380
145
105
760
290
210
ns
Carry in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
tPLH,
tPHL 5.0
10
15
—
—
—
305
120
85
610
240
170
ns
*The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
AC TEST SETUP REFERENCE TABLE
Test
AC Paths DC Data Inputs
Mode
Fig. 3
Waveform
Test
Inputs Outputs To VSS To VDD
Mode
Fig. 3
Waveform
Sumin to Sumout
Delay Time A0 Any F Remaining A’s
CnAll B’s Add #1
Sumin to P
Delay Time A0 P Remaining A’s
CnAll B’s Add #1
Sumin to G
Delay Time B0 G All A’s
CnRemaining B’s Add #1
Sumin to Cn+4
Delay Time B0 Cn+y All A’s
CnRemaining B’s Add #2
Cn to Sumout
Delay Time CnAny F All A’s All B’s Add #1
Cn to Cn+4
Delay Time CnCn+4 All A’s All B’s Add #1
Sumin to A = B
Delay Time A0 A = B All B’s
Remaining A’s CnSub #2
Sumin to Sumout
Delay Time
(Logic Mode) B0Any F All A’s M Exclusive
OR #2
MOTOROLA CMOS LOGIC DATAMC14581B
4
Figure 1. Typical Source Current Test Circuit Figure 2. Typical Sink Current Test Circuit
Figure 3. Switching Time Test Circuit and Waveforms
Figure 4. Dynamic Power Dissipation Test Circuit and Waveform
S0 S1 S2 S3
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
Cn+4
F0
F1
F2
F3
A = B
G
P
VDD Vout = VOH
IOH
EXTERNAL
POWER
SUPPLY
VSS
HIGH FOR
ALL OUTPUTS
EXCEPT Cn+4
VDD
S0 S1 S2 S3
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
Cn+4
F0
F1
F2
F3
A = B
G
P
VDD Vout = VOH
IOH
EXTERNAL
POWER
SUPPLY
VSS
HIGH FOR
ALL OUTPUTS
EXCEPT Cn+4
VDD
S0 S1 S2 S3
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
Cn+4
F0
F1
F2
F3
A = B
G
P
SEE AC TEST
SETUP
REFERENCE
TABLE FOR
CONNECTIONS
VDD
TPin
PULSE
GENERATOR
LOAD A TPout
50 pF
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
20 ns 20 ns VDD
0 V
VOH
VOL
VOH
VOL
TPin
#1
TPout
#2
TPout
90% 10%
10%
90%
10%
tTLH tPHL
tPLH
tTHL
tTHL
tPHL tTLH
tPLH
S0 S1 S2 S3
A0
A1
A2
A3
B0
B1
B2
B3
Cn
MC
Cn+4
F0
F1
F2
F3
A = B
G
P
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
LOAD A
PULSE
GENERATOR
TPin
DUTY CYCLE = 50%
VDD
LOAD A TPout
50 pF
20 ns 20 ns
90%
50% 10%
VDD
0 V
VARIABLE
WIDTH
TPin
MOTOROLA CMOS LOGIC DATA 5
MC14581B
BLOCK DIAGRAM
(ACTIVE LOW) BLOCK DIAGRAM
(ACTIVE HIGH)
29
A0
23 A1
21 A2
19 A3
1 B0
22 B1
20 B2
18 B3
7 Cn
8 MC
F0
WORD A
WORD B
CARRY IN
MODE CONTROL
10
F1 11
F2 13
F3
14
A = B 16
Cn+4 17
G15P
OUTPUT
FUNCTION
COMPARISON OUTPUT
RIPPLE CARRY OUTPUT
LOOK AHEAD
CARRY OUTPUTS
S0 S1 S2 S3
6
5
4
3
FUNCTION
SELECT
INPUTS VDD = PIN 24
VSS = PIN 12
29
A0
23 A1
21 A2
19 A3
1 B0
22 B1
20 B2
18 B3
7 Cn
8 MC
F0 10
F1 11
F2 13
F3
14
A = B 16
Cn+4 17
G15
P
S0 S1 S2 S3
6
5
4
3
TRUTH TABLE
Function Select Inputs/Outputs Active Low Inputs/Outputs Active High
S3 S2 S1 S0
Logic
Function
(MC = H)
Arithmetic*
Function
(MC = L, Cn = L)
Logic
Function
(MC = H)
Arithmetic*
Function
(MC = L, Cn = H)
L L L L A A minus 1 A A
L L L H AB AB minus 1 A + B A + B
L L H L A + B AB minus 1 AB A + B
L L H H Logic “1” minus 1 Logic “0” minus 1
L H L L A + B A plus (A + B) AB A plus AB
L H L H B AB plus (A + B) B (A + B) plus AB
L H H L A
ę
B A minus B minus 1 A
ę
B A minus B minus 1
L H H H A + B A + B AB AB minus 1
H L L L AB A plus (A + B) A + B A plus AB
H L L H A
ę
B A plus B A
ę
B A plus B
H L H L B AB plus (A + B) B (A + B) plus AB
H L H H A + B A + B AB AB minus 1
H H L L Logic “0” A plus A Logic “1” A plus A
H H L H AB AB plus A A + B (A + B) plus A
H H H L AB AB plus A A + B (A + B) plus A
H H H H A A A A minus 1
*Expressed as two’s complements. For arithmetic function with Cn in the opposite state, the resulting
function is as shown plus 1.
MOTOROLA CMOS LOGIC DATAMC14581B
6
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 709–02
ISSUE C
L SUFFIX
CERAMIC DIP PACKAGE
CASE 623–05
ISSUE M
NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D),
SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO
SEATING PLANE AND EACH OTHER.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A31.37 32.13 1.235 1.265
B13.72 14.22 0.540 0.560
C3.94 5.08 0.155 0.200
D0.36 0.56 0.014 0.022
F1.02 1.52 0.040 0.060
G2.54 BSC 0.100 BSC
H1.65 2.03 0.065 0.080
J0.20 0.38 0.008 0.015
K2.92 3.43 0.115 0.135
L15.24 BSC 0.600 BSC
M0 15 0 15
N0.51 1.02 0.020 0.040
_ _ _ _
1 12
1324
B
H
A
FD
G
K
SEATING
PLANE
N
C
MJ
L
NOTES:
1. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION (WHEN FORMED
PARALLEL).
1 12
24 13
B
A
SEATING
PLANE
F
D
GK
N
C
MJ
L
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A31.24 32.77 1.230 1.290
B12.70 15.49 0.500 0.610
C4.06 5.59 0.160 0.220
D0.41 0.51 0.016 0.020
F1.27 1.52 0.050 0.060
G2.54 BSC 0.100 BSC
J0.20 0.30 0.008 0.012
K3.18 4.06 0.125 0.160
L15.24 BSC 0.600 BSC
M0 15 0 15
N0.51 1.27 0.020 0.050
_ _ _ _
MOTOROLA CMOS LOGIC DATA 7
MC14581B
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751E–04
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P12X
D24X
12
1324
1
M
0.010 (0.25) B M
S
A
M
0.010 (0.25) B S
T
–T–
G
22X
SEATING
PLANE
K
C
RX 45
_
M
F
J
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A15.25 15.54 0.601 0.612
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.41 0.90 0.016 0.035
G1.27 BSC 0.050 BSC
J0.23 0.32 0.009 0.013
K0.13 0.29 0.005 0.011
M0 8 0 8
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
____
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MC14581B/D
*MC14581B/D*
◊
