CMX639P6 package discontinued CML Microcircuits COMMUNICATION SEMICONDUCTORS CMX639 Consumer / Commercial CVSD Digital Voice Codec D/639/3 February 2005 Provisional Issue Features Applications * * * 1.1 Single Chip Full Duplex CVSD codec * Integrated Input and Output Filters * Robust Coding for Wireless Links * Programmable Sampling Clocks * 3 and 4 bit Companding Algorithms Low Power/Small Size for Portable Devices * 1.9mA/2.75mA typ. @ 3.0V/5.0V * 3.0V to 5.5V Operation * Powersave Mode * * * Consumer and Business Handheld Devices Digital Voice Appliances * Spread Spectrum Wireless * Cordless Phones * Voice Recording and Storage * Delay Lines Time Domain Scramblers Multiplexers and Switches Brief Description The CMX639 is a Continuously Variable Slope Delta Modulation (CVSD) full duplex CODEC for use in consumer and commercial digital voice communication systems. With its robust and selectable coding algorithms, low cost, very low power, and small size, the CMX639 is ideal for use in a wide variety of consumer and business digital voice applications. Its completely integrated CODEC simplifies design and eliminates the costs, complexity and risk of external filters and software algorithms. 8kbps to 128kbps data/sampling clock rates are supported both via external clock signals or internally generated, programmable clocks. Internal data/sampling clocks are derived from an on-chip reference oscillator that uses an external clock crystal. An internal data/sampling clock output signal is provided to synchronize external circuits, if desired. Multiplexer applications are also well supported by the encoder output's three-state/high impedance enable feature. The CMX639 operates from 2.7V to 5.5V supplies and is available in the following packages: 24-pin TSSOP (CMX639E2), 16-pin SOIC (CMX639D4) and 22-pin PDIP (CMX639P6). (c) 2005 CML Microsystems Plc CMX639P6 package discontinued CVSD Codec CMX639 CONTENTS Page Section 1.0 Features and Applications ..................................................................... 1 1.1 Brief Description ..................................................................................... 1 1.2 Block Diagram ......................................................................................... 3 1.3 Signal List ................................................................................................ 4 1.4 External Components............................................................................. 6 1.5 General Description................................................................................ 7 1.6 Application Notes ................................................................................... 7 1.7 Performance Specification..................................................................... 8 1.7.1 Electrical Performance................................................................. 8 1.7.2 Packaging .................................................................................. 15 (c) CML Microsystems Plc 2 CMX639/3 CMX639P6 package discontinued CVSD Codec 1.2 CMX639 Block Diagram Figure 1 Block Diagram (c) CML Microsystems Plc 3 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 1.3 Signal List P6 22-pin PDIP E2 24-pin TSSOP D4 16-pin SOIC 1 1 1 2 2 3 2 Xtal output 3 4 4 5 3 N/C Encoder Data Clock input/ output 5 6 4 Encoder Output output 6 7 Not present 7 8 5 Data Enable 8 9 9 10 6 N/C VBIAS 10 11 7 Encoder Input input 11 12 13 12 13 14 8 VSS N/C Decoder Output power 14 15 Signal Name Xtal/Clock Type Description input Input to the clock oscillator inverter. A 1.024MHz Xtal input or externally derived clock is injected here. No Connection The 1.024 MHz output of the clock oscillator inverter. No Connection A logic I/O port. External encode clock input or internal data clock output. Clock frequency is dependent upon Clock Mode 1 and 2 inputs and Xtal frequency. Note: No internal pull-up is provided. See Table 3. The encoder digital output. This is a three-state output whose condition is set by the Data Enable and Powersave inputs. See Table 2. N/C 9 (c) CML Microsystems Plc Encoder Force Idle input When this pin is at a logical '0' the encoder is forced to an idle state and the encoder digital output is `0101...', a perfect idle pattern. When this pin is a logical '1' the encoder encodes as normal. Internal 1M pull-up. Data is made available at the encoder output pin by control of this input. See Encoder Output pin. Internal 1 M pull-up. No Connection Normally at VDD/2, this pin should be externally decoupled by capacitor C4. Internally pulled to VSS when Powersave is a logical '0'. input The analog signal input. Internally biased at VDD/2, this input requires an external coupling capacitor. The source impedance driving the coupling capacitor should be less than 1k. A lower driving source impedance will reduce encoder output channel noise levels. Negative Supply No Connection The recovered analog signal is output at this pin. It is the buffered output of a lowpass filter and requires external components. During `Powersave' this output is open circuit. No Connection output N/C 4 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 P6 22-pin PDIP E2 24-pin TSSOP D4 16-pin SOIC 15 16 10 16 17 18 17 19 11 Decoder Input input 18 20 12 Decoder Data Clock input/ output 19 21 13 Algorithm input 20 22 14 Clock Mode 2 input 21 23 15 Clock Mode 1 input 22 24 16 VDD power Signal Name Powersave Type Description Input A logic '0' at this pin puts most parts of the codec into a quiescent, non-operational state. When at a logical '1', the codec operates normally. Internal 1 M pull-up. No Connection A logic '0' at this pin gates a `0101...' pattern internally to the decoder so that the Decoder Output goes to VDD/2. When this pin is a logical '1' the decoder operates as normal. Internal 1M pull-up. N/C Not present (c) CML Microsystems Plc Decoder Force Idle input The received digital signal input. Internal 1 M pull-up. A logic I/O port. External decode clock input or internal data clock output. Clock frequency is dependent upon Clock Mode 1 and 2 inputs and Xtal frequency. Note: No internal pull-up is provided. See Table 3. A logic '1' at this pin sets this device for a 3-bit companding algorithm. A logical '0' sets a 4-bit companding algorithm. Internal 1 M pull-up. Clock rates refer to f = 1.024MHz Xtal/Clock input. During internal operation the data clock frequencies are available at these ports for external circuit synchronization. Independent or common data rate inputs to Encode and Decode data clock ports may be employed in the External Clocks mode. Internal 1M pull-ups. See Table 3. Positive Supply. A single 3.0V to 5.5V supply is required. This pin should be externally decoupled to VSS by capacitor C5. 5 CMX639/3 CMX639P6 package discontinued CVSD Codec 1.4 CMX639 External Components Figure 2 Recommended External Connections R1 Note 1 1M 10% C4 Note 4 1.0F 20% C1 Note 2 33pF 20% C5 Note 5 1.0F 20% C2 Note 2 33pF 20% X1 Note 6, 7 1.024MHz C3 Note 3 1.0F 20% Table 1 Recommended External Components Notes: 1. Oscillator inverter bias resister 2. Xtal circuit load capacitor 3. The drive source impedance connected to the coupling capacitor's input node, rather than the CMX639 ENCODER INPUT pin node, should be should be less than 1k. Output idle channel noise levels will improve with even lower source impedances driving the coupling capacitor's input node. 4. Bias decoupling capacitor 5. VDD decoupling capacitor 6. A 1.024MHz Xtal/Clock input will yield exactly 16kbps/32kbps/64kbps internally generated data clock rates 7. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, please consult your crystal manufacturer. (c) CML Microsystems Plc 6 CMX639/3 CMX639P6 package discontinued CVSD Codec 1.5 CMX639 General Description Data Enable Powersave 1 1 0 don't care 1 0 Encoder Output Enable High Z (open circuit) VSS Table 2 Encoder Output 0 Data/Sampling Clock Rate (CLOCK/XTAL = f = 1.024MHz) External Clocks External Clocks 0 1 Internally generated @ f/16 Internally generated @ 64kbps 1 0 Internally generated @ f/32 Internally generated @ 32kbps 1 1 Internally generated @ f/64 Internally generated @ 16kbps Clock Mode 1 Clock Mode 2 0 Example for f = 1.024MHz Table 3 Clock Modes and Pins 1.6 Application Notes Figure 3 System Configuration using the CMX639 (c) CML Microsystems Plc 7 CMX639/3 CMX639P6 package discontinued CVSD Codec 1.7 Performance Specification 1.7.1 Electrical Performance CMX639 1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -30 -20 Max. 7.0 VDD + 0.3 +30 +20 Units V V mA mA P6 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. Max. 800 10 +125 +85 Units mW mW/C C C E2 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. Max. 300 3.0 +125 +85 Units mW mW/C C C D4 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature Min. Max. 800 10 +125 +85 Units mW mW/C C C Max. 5.5 +85 2.048 Units V C MHz Supply (VDD - VSS) Voltage on any pin to VSS Current into or out of VDD and VSS pins Current into or out of any other pin -40 -40 -40 -40 -40 -40 1.7.1.2 Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Xtal Frequency (c) CML Microsystems Plc 8 Min. 2.7 -40 0.500 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: Xtal Frequency = 1.024 MHz, Sample Clock Rate = 32 kbps, Audio Test Frequency = 820 Hz, VDD = 3.0V to 5.5V, Tamb = - 40C to +85C, Audio Level 0dB ref (0dBm0) = 489mV rms. Static Values IDD (powersaved) IDD (enabled) @ VDD = 3.0V IDD (enabled) @ VDD = 5.0V Notes 6 6 6 Typ. 600 70% VDD 30% VDD 80% VDD 20% VDD 1 M k 100 Analog Output Impedance Insertion Loss (c) CML Microsystems Plc 3 9 4 0 k k 800 Three State Output Leakage A mA mA V V V V 300 4.0 2 Units 1.0 Digital Output Impedance Analog Input Impedance Max. 1.90 2.75 Input Logic `1' Input Logic `0' Output Logic `1' Output Logic `0' Digital Input Impedance Logic I/O pins Logic Input pins, Pull-up Resistor Min. A dB CMX639/3 CMX639P6 package discontinued CVSD Codec Dynamic Values Encoder: Analog Signal Input Levels VDD = 3.0V VDD = 5.0V Principal Integrator Frequency Encoder Passband Compand Time Constant Decoder: Analog Signal Output Levels VDD = 3.0V VDD = 5.0V Decoder Passband Encoder Decoder (Full Codec): Passband Stopband Stopband Attenuation Passband Gain Passband Ripple Output Noise (Input Short Circuit) Perfect Idle Channel Noise (Encode Forced) Group Delay Distortion (1000Hz - 2600Hz) CMX639 Notes 7 7 Min. Typ. -37 -33 Max. Units 6 10 dB dB Hz Hz ms 6 10 dB dB Hz 3400 10 160 3240 5 4 7 7 4 -37 -33 4 300 6 3200 8 -60 Hz kHz dB dB dB dBm0p 8, 9 5 -63 dBm0p 60 0 -3.0 3.0 450 s (600Hz - 2800Hz) 750 s (500Hz - 3000Hz) 1500 2.048 s MHz Xtal/Clock Frequency 10, 11 0.500 1.024 Notes: 1. All logic inputs except Encoder and Decoder Data clocks. 2. The source impedance driving the coupling capacitor should be less than 1k. A lower driving source impedance will reduce encoder output channel noise levels. 3. For an Encoder/Decoder combination. 4. See Figure 5. 5. Group Delay Distortion for the full codec is relative to the delay with an 820Hz, -20dB signal at the encoder input. 6. Not including any current drawn from the device pins by external circuits. 7. Recommended values. 8. dBm0p units are measured after the application of a psophometrically weighted filter that is commonly applied in voice communication applications per CCITT Recommendation G.223. 9. Forced idle encode/decode control not available on D4 (16-pin SOIC) package. (c) CML Microsystems Plc 10 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 10. Some applications may benefit from the use of an Xtal/Clock frequency other than 1.024MHz. Note: Codec time constants and filter response curves are effectively proportional to Xtal/Clock frequency and so will shift with the use of Xtal/Clock frequencies other than 1.024MHz. For example, the specified Encoder Decoder (Full Codec) passband of 300Hz min. to 3400Hz max. for a 1.024MHz Xtal/Clock will shift to 600Hz min. to 6800Hz max. when the device is operated from a 2.048MHz Xtal/Clock. For this reason, all CMX639 codecs involved in the same communications link should usually be operated from the same Xtal/Clock frequency. Example 1: A design saves the cost of a 1.024MHz Xtal or clock generator by making use of an already existing clock source of a frequency other than 1.024MHz. Example 2: Best noise performance is achieved when the CMX639 codec data clock is internally generated. If a codec bit rate other than 16kbps, 32kbps or 64kbps is desired then an Xtal/Clock different from 1.024MHz can be used to proportionately shift the available set of internally generated clock rates, as needed. Example 3: To increase the codec high frequency response and audio bandwidth a faster Xtal/Clock speed can be used. Other designs may prefer the proportionately higher codec bandwidths and data rates that can be supported with faster clock speeds. 11. In general, optimum codec performance is achieved when both encoder and decoder Xtal/Clock signals are synchronized. While this is practical in many telecom applications, it may not be so for others such as wireless data links. The CMX639 decoder can generally deliver best performance when its data clock is recovered/derived from the received data stream and applied as an external data clock to the decoder as per the decoder timing depicted in Figure 4. Nonetheless, some Xtal/Clock frequency and data rate combinations are better served by the use of internal clocks. Experimentation with each specific design may provide the best guidance for making this design choice. (c) CML Microsystems Plc 11 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 1.7.1.3 Operating Characteristics (continued) Timing Diagram ENCODER TIMING ENCODER CLOCK tCH DATA CLOCKED tCH tCL tIF t IR ENCODER DATA OUTPUT tPCO DECODER TIMING DECODER CLOCK DATA CLOCKED DECODER DATA INPUT tSU tH DATA TRUE TIME MULTIPLEXING FUNCTION ENCODER OUTPUT HIGH Z HIGH Z tDR tDF DATA ENABLE Figure 4 Serial Bus Timing For the following conditions unless otherwise specified: Xtal Frequency = 1.024 MHz, VDD = 3.0V to 5.0V, Tamb = - 40C to +85C. Serial Bus Timing (ref. Figure 4) Notes Min. Typ. Max. Units tCH Clock 1 pulse width 1.0 s tCL Clock 0 pulse width 1.0 s tIR Clock rise time tIF Clock fall time tSU Data set-up time tH Data hold time tSU +tH Data true time 1.5 s tPCO Clock to output delay time 750 ns tDR Data rise time 100 ns tDF Data fall time 100 ns (c) CML Microsystems Plc 0 100 ns 100 ns 450 600 12 ns ns CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 1.7.1.3 Operating Characteristics (continued) C odec G ain including encode and decode, (dB ) Typical Codec Performance Inp ut Level = -15d B m O D ata C locks = 3 2kbps X tal = 1.0 24 M H z 0 -1 0 -2 0 -3 0 -4 0 -5 0 -6 0 1 2 3 F requ ency (kH z) 5 4 6 Figure 5 Typical Frequency Response (32kbps) Input L eve l = -2 0dB 35 30 64kb/s S /N (dB ) 25 20 32kb/s 15 10 16kb/s 5 500 1000 1500 2000 2500 3000 3500 F re qu en cy (H z) Figure 6 Typical S/N Ratio with Input Frequency (c) CML Microsystems Plc 13 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 3 35 2 30 64 kbps S /N (dB ) Attenuation (dB) ref @ -15dBm O In put F re que ncy = 820H z R e f: 0dB Input Level = 489m Vrm s Inp ut F re quency = 82 0 H z 1 32 kbps 20 0 16 kbps -1 -40 -30 -20 -10 0 10 ref. 10 Input Level (dB m O ) -40 -30 -20 -10 0 Input L evel (dB ) Figure 7 Typical Variation of Gain with Input Level (32kbps) (c) CML Microsystems Plc Figure 8 Typical S/N Ratio with Input Level 14 CMX639/3 CMX639P6 package discontinued CVSD Codec 1.7.2 CMX639 Packaging Figure 9 P6 Mechanical Outline: Order as part no. CMX639P6 Figure 10 E2 Mechanical Outline: Order as part no. CMX639E2 (c) CML Microsystems Plc 15 CMX639/3 CMX639P6 package discontinued CVSD Codec CMX639 Figure 11 D4 Mechanical Outline: Order as part no. CMX639D4 Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed. www.cmlmicro.com For FAQs see: www.cmlmicro.com/products/faqs/ For a full data sheet listing see: www.cmlmicro.com/products/datasheets/download.htm For detailed application notes: www.cmlmicro.com/products/applications/ Oval Park, Langford, Maldon, Essex, CM9 6WG - England. 4800 Bethania Station Road, Winston-Salem, NC 27105 - USA. No 2 Kallang Pudding Road, #09 - 05/06 Mactech Industrial Building, Singapore 349307 No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. 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