1
8-lead SOIC
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
Features
•Serial Peripheral Interface (SPI) Compatible
•Supports SPI Modes 0 (0,0) and 3 (1,1)
•Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
•3 MHz Clock Rate
•64-byte Page Mode and Byte Write Operation
•Block Write Protection
– Protect 1/4, 1/2, or Entire Array
•Write Protect (WP) Pin and Write Disable Instructions for
Both Hardware and Software Data Protection
•Self-timed Write Cycle (5 ms Typical)
•High-reliability
– Endurance: 100,000 Write Cycles
– Data Retention: >200 Years
•Automotive Grade, Extended Temperature and Lead-Free Devices Available
•8-lead PDIP, 8-lead EIAJ SOIC, 8-lead and 16-lead JEDEC SOIC, 14-lead and 20-lead
TSSOP, and 8-lead Leadless Array Packages
Description
The AT25128/256 provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available in
space saving 8-lead PDIP (AT25128/256), 8-lead EIAJ SOIC (AT25128/256), 8-lead
and 16-lead JEDEC SOIC (AT25128), 14-lead TSSOP (AT25128), 20-lead TSSOP
(AT25128/256), and 8-lead Leadless Array (AT25256) packages. In addition, the entire
family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V) versions.
Table 1. Pin Configuration
Pin Name Function
CS Chip Select
SCK Serial Data Clock
SI Serial Data Input
SO Serial Data Output
GND Ground
VCC Power Supply
WP Write Protect
HOLD Suspends Serial
Input
NC No Connect
DC Don't Connect
Rev. 0872O–SEEPR–03/05
*Note: Pins 3, 4 and 17, 18 are internally connected for 14-lead TSSOP socket compatibility.
SPI Serial
EEPROMs
128K (16,384 x 8)
256K (32,768 x 8)
AT25128(1)
AT25256(2)
Notes: 1. This device is not rec-
ommended for new
designs. Please refer
to AT25128A.
2. This device is not rec-
ommended for new
designs. Please refer
to AT25256A.
20-lead TSSOP*
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
CS
SO
SO
NC
NC
WP
GND
DC
NC
NC
VCC
HOLD
HOLD
NC
NC
SCK
SI
DC
NC
8-lead PDIP
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
16-lead SOIC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CS
SO
NC
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
NC
SCK
SI
14-lead TSSOP
1
2
3
4
5
6
7
14
13
12
11
10
9
8
CS
SO
NC
NC
NC
WP
GND
VCC
HOLD
NC
NC
NC
SCK
SI
8-lead Leadless Array
Bottom View
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
CS
SO
WP
GND
2AT25128/256
0872O–SEEPR–03/05
The AT25128/256 is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All programming cycles are completely self-timed, and no separate Erase
cycle is required before Write.
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is pro-
vided via the WP pin to protect against inadvertent write attempts to the status register.
The HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Figure 1. Block Diagram
Absolute Maximum Ratings*
Operating Temperature..................................–55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature .....................................–65°C to +150°C
Voltage on Any Pin
with Respect to Ground ....................................–1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
16384/32768 x 8
3
AT25128/256
0872O–SEEPR–03/05
Note: 1. This parameter is characterized and is not 100% tested.
Note: 1. VIL and VIH max are reference only and are not tested.
Table 2. Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
COUT Output Capacitance (SO) 8 pF VOUT = 0V
CIN Input Capacitance (CS, SCK, SI, WP, HOLD)6pFV
IN = 0V
Table 3. DC Characteristics
Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.8V to +5.5V,
TAE = –40°C to +125°C, VCC = +1.8V to +5.5V(unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 5.5 V
VCC2 Supply Voltage 2.7 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V at 1 MHz, SO = Open, Read 2.0 3.0 mA
ICC2 Supply Current VCC = 5.0V at 2 MHz,
SO = Open, Read, Write 3.0 5.0 mA
ISB1 Standby Current VCC = 1.8V, CS = VCC 0.1 2.0 µA
ISB2 Standby Current VCC = 2.7V, CS = VCC 0.2 2.0 µA
ISB3 Standby Current VCC = 5.0V, CS = VCC 2.0 5.0 µA
IIL Input Leakage VIN = 0V to VCC –3.0 3.0 µA
IOL Output Leakage VIN = 0V to VCC, TAC = 0°C to 70°C –3.0 3.0 µA
VIL(1) Input Low-voltage –1.0 VCC x 0.3 V
VIH(1) Input High-voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low-voltage 4.5 ≤ VCC ≤ 5.5V IOL = 3.0 mA 0.4 V
VOH1 Output High-voltage IOH = –1.6 mA VCC - 0.8 V
VOL2 Output Low-voltage 1.8V ≤ VCC ≤ 3.6V IOL = 0.15 mA 0.2 V
VOH2 Output High-voltage IOH = –100 µA VCC - 0.2 V
4AT25128/256
0872O–SEEPR–03/05
Table 4. AC Characteristics
Applicable over recommended operating range from TAI = –40°C to + 85°C, TAE = –40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
fSCK SCK Clock Frequency
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
3.0
2.1
0.5
MHz
tRI Input Rise Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
tFI Input Fall Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
2
2
2
µs
tWH SCK High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
150
200
800
ns
tWL SCK Low Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
150
200
800
ns
tCS CS High Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
250
250
1000
ns
tCSS CS Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
250
1000
ns
tCSH CS Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
150
250
1000
ns
tSU Data In Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
30
50
100
ns
tH Data In Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
50
50
100
ns
tHD Hold Setup Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
100
400
ns
tCD Hold Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
200
300
400
ns
tVOutput Valid
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
150
200
800
ns
tHO Output Hold Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
ns
tLZ Hold to Output Low Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
0
0
0
100
200
300
ns
5
AT25128/256
0872O–SEEPR–03/05
Note: 1. This parameter is characterized and is not 100% tested. Contact Atmel for further information.
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the serial clock pin (SCK) is always an input, the AT25128/256
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25128/256 has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will
be received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25128/256, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25128/256 is selected when the CS pin is low. When the device
is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25128/256.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25128/256 in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
tHZ Hold to Output High Z
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
100
200
300
ns
tDIS Output Disable Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
200
250
1000
ns
tWC Write Cycle Time
4.5 – 5.5
2.7 – 5.5
1.8 – 5.5
5
10
10
ms
Endurance(1) 5.0V, 25°C, Page Mode 100K Write Cycles
Table 4. AC Characteristics (Continued)
Applicable over recommended operating range from TAI = –40°C to + 85°C, TAE = –40°C to +125°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Voltage Min Max Units
6AT25128/256
0872O–SEEPR–03/05
Figure 2. SPI Serial Interface
Functional
Description
The AT25128/256 is designed to interface directly with the synchronous serial periph-
eral interface (SPI) of the 6800 type series of microcontrollers.
The AT25128/256 utilizes an 8-bit instruction register. The list of instructions and their
operation codes are contained in Table 5. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
AT25128/256
Table 5. Instruction Set for the AT25128/256
Instruction Name Instruction Format Operation
WREN 0000 X110 Set Write Enable Latch
WRDI 0000 X100 Reset Write Enable Latch
RDSR 0000 X101 Read Status Register
WRSR 0000 X001 Write Status Register
READ 0000 X011 Read Data from Memory Array
WRITE 0000 X010 Write Data to Memory Array
7
AT25128/256
0872O–SEEPR–03/05
WRITE ENABLE (WREN): The device will power-up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The Ready/Busy and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection
employed. These bits are set by using the WRSR instruc-
tion
.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25128/256 is divided into four array segments.
Top quarter (1/4), top half (1/2), or all of the memory segments can be protected. Any of
the data within any selected segment will therefore be READ only. The block write pro-
tection levels and corresponding status register control bits are shown in Table 8.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 6. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
WPEN X X X BP1 BP0 WEN RDY
Table 7. Read Status Register Bit Definition
Bit Definition
Bit 0 (RDY) Bit 0 = “0” (RDY) indicates the device is READY.
Bit 0 = “1” indicates the write cycle is in progress.
Bit 1 (WEN) Bit 1 = “0” indicates the device is not WRITE ENABLED. Bit 1 = 1
indicates the device is WRITE ENABLED.
Bit 2 (BP0) See Table 8.
Bit 3 (BP1) See Table 8.
Bits 4 - 6 are “0”s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 9.
Bits 0 – 7 are “1”s during an internal write cycle.
Table 8. Block Write Protect Bits
Level
Status Register Bits Array Addresses Protected
BP1 BP0 AT25128 AT25256
0 0 0 None None
1(1/4) 0 1 3000 - 3FFF 6000 - 7FFF
2(1/2) 1 0 2000 - 3FFF 4000 - 7FFF
3(All) 1 1 0000 - 3FFF 0000 - 7FFF
8AT25128/256
0872O–SEEPR–03/05
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
READ SEQUENCE (READ): Reading the AT25128/256 via the SO pin requires the
following sequence. After the CS line is pulled low to select a device, the READ op-code
is transmitted via the SI line followed by the byte address to be read (see Table 10 on
page 9). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at
the specified address is then shifted out onto the SO line. If only one byte is to be read,
the CS line should be driven high after the data comes out. The read sequence can be
continued since the byte address is automatically incremented and data will continue to
be shifted out. When the highest address is reached, the address counter will roll over to
the lowest address allowing the entire memory to be read in one continuous read cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25128/256, two separate
instructions must be executed. First, the device must be write enabled via the WREN
instruction. Then a Write instruction may be executed. Also, the address of the memory
location(s) to be programmed must be outside the protected address field location
selected by the block write protection level. During an internal write cycle, all commands
will be ignored except the RDSR instruction.
A Write instruction requires the following sequence. After the CS line is pulled low to
select the device, the Write op-code is transmitted via the SI line followed by the byte
address and the data (D7 – D0) to be programmed (see Table 10 on page 9). Program-
ming will start after the CS pin is brought high. The low-to-high transition of the CS pin
must occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The Ready/Busy status of the device can be determined by initiating a Read Status
Register (RDSR) instruction. If Bit 0 = “1”, the write cycle is still in progress. If Bit 0 = “0”,
the write cycle has ended. Only the RDSR instruction is enabled during the write pro-
gramming cycle.
Table 9. WPEN Operation
WPEN WP WEN
Protected
Blocks
Unprotected
Blocks
Status
Register
0 X 0 Protected Protected Protected
0 X 1 Protected Writable Writable
1 Low 0 Protected Protected Protected
1 Low 1 Protected Writable Protected
X High 0 Protected Protected Protected
X High 1 Protected Writable Writable
9
AT25128/256
0872O–SEEPR–03/05
The AT25128/256 is capable of a 64-byte page write operation. After each byte of data
is received, the six-low order address bits are internally incremented by one; the high-
order bits of the address will remain constant. If more than 64 bytes of data are transmit-
ted, the address counter will roll over and the previously written data will be overwritten.
The AT25128/256 is automatically returned to the write disable state at the completion
of a write cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS fall-
ing edge is required to reinitiate the serial communication.
Timing Diagrams (for SPI Mode 0 (0, 0))
Figure 3. Synchronous Data Timing
Table 10. Address Key
Address AT25128 AT25256
ANA13 - A0A14 - A0
Don’t Care Bits A15 - A14 A15
SO
V
OH
V
OL
HI-Z HI-Z
t
V
VALID IN
SI
V
IH
V
IL
t
H
t
SU
t
DIS
SCK
V
IH
V
IL
t
WH
t
CSH
CS
V
IH
V
IL
t
CSS
t
CS
t
WL
t
HO
10 AT25128/256
0872O–SEEPR–03/05
Figure 4. WREN Timing
Figure 5. WRDI Timing
Figure 6. RDSR Timing
CS
SCK
01234567891011121314
SI INSTRUCTION
SO 76543210
DATA OUT
MSB
HIGH IMPEDANCE
15
11
AT25128/256
0872O–SEEPR–03/05
Figure 7. WRSR Timing
Figure 8. READ Timing
Figure 9. WRITE Timing
12 AT25128/256
0872O–SEEPR–03/05
Figure 10. HOLD Timing
SO
SCK
HOLD
tCD
tHD
tHZ
tLZ
tCD
tHD
CS
13
AT25128/256
0872O–SEEPR–03/05
Notes: 1. This device is not recommended for new designs. Please refer to AT25128A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
AT25128(1) Ordering Information
Ordering Code(2) Package Operation Range
AT25128-10PI-2.7
AT25128N-10SI-2.7
AT25128W-10SI-2.7
AT25128N1-10SI-2.7
AT25128T1-10TI-2.7
8P3
8S1
8S2
16S1
14A2
Industrial Temperature
(–40°C to 85°C)
AT25128-10PI-1.8
AT25128N-10SI-1.8
AT25128W-10SI-1.8
AT25128N1-10SI-1.8
AT25128T1-10TI-1.8
8P3
8S1
8S2
16S1
14A2
Industrial Temperature
(–40°C to 85°C)
AT25128N-10SJ-2.7
AT25128N-10SJ-1.8
8S1
8S1
Lead-Free/Industrial Temperature
(–40°C to 85°C)
AT25128N-10SE-2.7 8S1 High Grade/Extended Temperature
(–40°C to 125°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
16S1 16-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
14A2 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
–2.7 Low-voltage (2.7V to 5.5V)
–1.8 Low-voltage (1.8V to 5.5V)
14 AT25128/256
0872O–SEEPR–03/05
Notes: 1. This device is not recommended for new designs. Please refer to AT25256A.
2. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics
tables.
AT25256(1) Ordering Information
Ordering Code(2) Package Operation Range
AT25256-10PI-2.7
AT25256W-10SI-2.7
AT25256-10CI-2.7
AT25256T2-10TI-2.7
8P3
8S2
8CN3
20A2
Industrial Temperature
(–40°C to 85°C)
AT25256-10PI-1.8
AT25256W-10SI-1.8
AT25256-10CI-1.8
AT25256T2-10TI-1.8
8P3
8S2
8CN3
20A2
Industrial Temperature
(–40°C to 85°C)
AT25256W-10SJ-2.7
AT25256W-10SJ-1.8
8S2
8S2
Lead-Free/Industrial Temperature
(–40°C to 85°C)
AT25256W-10SE-2.7 8S2 High Grade/Extended Temperature
(–40°C to 125°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8CN3 8-lead, 0.230" Wide, Leadless Array Package (LAP)
20A2 20-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
–2.7 Low-voltage (2.7V to 5.5V)
–1.8 Low-voltage (1.8V to 5.5V)
15
AT25128/256
0872O–SEEPR–03/05
Packaging Information
8P3 – PDIP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
01/09/02
8P3B
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
COMMON DIMENSIONS
(Unit of Measure = inches)
SYMBOL MIN NOM MAX NOTE
D
D1
E
E1
e
L
b2
b
A2 A
1
N
eA
c
b3
4 PLCS
A
–
–
0.210 2
A2 0.115 0.130 0.195
b 0.014 0.018 0.022 5
b2 0.045 0.060 0.070 6
b3 0.030 0.039 0.045 6
c 0.008 0.010 0.014
D 0.355 0.365 0.400 3
D1 0.005
–
–
3
E 0.300 0.310 0.325 4
E1 0.240 0.250 0.280 3
e 0.100 BSC
eA 0.300 BSC 4
L 0.115 0.130 0.150 2
Top View
Side View
End View
16 AT25128/256
0872O–SEEPR–03/05
8S1 – JEDEC SOIC
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
Note:
10/7/03
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
Small Outline (JEDEC SOIC) 8S1 B
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
A 1.35 – 1.75
B 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.00
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
∅ 0° – 8°
∅
Top View
End View
Side View
eB
D
A
A1
N
E
1
C
E1
L
17
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8S2 – EIAJ SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
10/7/03
8S2C
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
∅
0° 8°
e 1.27 BSC 4
End View
Side View
eb
A
A1
D
E
N
1
C
E1
∅
L
Top View
18 AT25128/256
0872O–SEEPR–03/05
8CN3 – LAP
1150 E.Cheyenne Mtn Blvd.
Colorado Springs, CO 80906
TITLE DRAWING NO.
R
REV.
8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP) B
8CN3
11/8/04
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.94 1.04 1.14
A1 0.30 0.34 0.38
b 0.36 0.41 0.46 Note 1
D 5.89 5.99 6.09
E 4.83 4.93 5.03
e 1.27 BSC
e1 0.56 REF
L 0.62 0.67 0.72 Note 1
L1 0.92 0.97 1.02 Note 1
Note: 1. Metal Pad Dimensions.
2. All exposed metal area shall have the following finished platings.
Ni: 0.0005 to 0.015 mm
Au: 0.0005 to 0.001 mm
Pin1 Corner
Marked Pin1 Indentifier
0.10 mm
TYP
4
3
2
1
5
6
7
8
Top View
L
b
e
L1
e1
Side View
A1
A
Bottom View
E
D
19
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0872O–SEEPR–03/05
16S1 – JEDEC SOIC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
16S1
10/15/01
16S1, 16-lead, 0.150" Body,
Plastic Gull Wing Small Outline (SOIC ) A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in)
per side.
4. L is the length of terminal for soldering to a substrate.
5. The lead width B, as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024 in).
H
1
2
N
3
Top View
C
E
A
B
L
A2
e
D
A 1.35 – 1.75
B 0.33 – 0.51 5
C 0.19 – 0.25
D 9.80 – 10.00 2
E 3.80 – 4.00 3
e 1.27 BSC
H 5.80 – 6.20 4
L 0.40 – 1.27
Side View
End View
20 AT25128/256
0872O–SEEPR–03/05
14A2 – TSSOP
D 4.90 5.00 5.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
12/28/01
L1
A
L
DA2
E
E1
e
b
14A2,14-lead (4.4 x 5 mm Body), 0.65 Pitch,
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AB-1, for
additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate
burrs shall not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not
exceed 0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total
in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower
radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
14A2 A
Top View
Side View
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
21
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20A2 – TSSOP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
6/3/02
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
D 6.40 6.50 6.60 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
A – – 1.20
A2 0.80 1.00 1.05
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
20A2, 20-lead (4.4 x 6.5 mm Body), 0.65 pitch,
Thin Shrink Small Outline Package (TSSOP)
Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional
information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall
not exceed 0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed
0.25 mm (0.010 in) per side.
4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess
of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.
Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
20A2 C
L1
A
L
DA2
EE1
e
b
Top View
Side View
End View
Printed on recycled paper.
0872O–SEEPR–03/05
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