1. General description
The 74LVC1G80-Q100 provides a single positive-edge triggered D-type flip-flop.
Information on the dat a input is transferred to the Q ou tput on the LOW -to-HIGH tra nsition
of the clock pulse. The input pin D must be stable one set-up time prior to the
LOW-to-HIGH clock transition for predictable operation.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this
device in a mixed 3.3 Vand 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the outpu t, preventing the damaging ba ckflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC =3.0V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
Rev. 2 — 12 December 2016 Product data sheet
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 2 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lo wer left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVC1G80GW-Q100 40 C to +125 C TSSOP5 plastic thin shrink small outline package;
5 leads; body width 1.25 mm SOT353-1
74LVC1G80GV-Q100 40 C to +125 C SC-74A plastic surface-mounted package; 5 leads SOT753
Table 2. Marking codes
Type number Marking[1]
74LVC1G80GW-Q100 VT
74LVC1G80GV-Q100 V80
Fig 1. Logic symbol Fig 2. IEC logic symbol
PQD
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Fig 3. Logic diagra m
PQD
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© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 3 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
6. Pinning information
6.1 Pinning
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level.
= LOW-to-HIGH CP transition;
X = don’t care;
q = lower case letter indicates the state of referenced input, one set-up time prior to the LOW-to-HIGH CP transition.
Fig 4. Pin configuration SOT353-1 and SOT753
/9&*4
'
9&&
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3
*1' 4
DDD
Table 3. Pin description
Symbol Pin Description
D 1 data input
CP 2 clock pulse input
GND 3 ground (0 V)
Q4 data output
VCC 5 supply voltage
Table 4. Function table[1]
Input Output
CP D Q
LH
HL
LXq
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 4 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP5 and SC-74A packages: above 87.5 C the value of Ptot derates linearly with 4.0 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +6.5 V
IIK input clamping current VI < 0 V 50 - mA
VIinput voltage [1] 0.5 +6.5 V
IOK output clamping current VO > VCC or VO < 0 V - 50 mA
VOoutput voltage Active mode [1][2] 0.5 VCC + 0.5 V
Power-down mode [1][2] 0.5 +6.5 V
IOoutput current VO = 0 V to VCC -50 mA
ICC supply current - 100 mA
IGND ground current 100 - mA
Ptot total power dissipation Tamb = 40 C to +125 C[3] -250mW
Tstg storage temperature 65 +150 C
Table 6. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 1.65 - 5.5 V
VIinput voltage 0 - 5.5 V
VOoutput voltage Active mode 0 - VCC V
VCC = 0 V; Power-down mode 0 - 5.5 V
Tamb ambient temp erature 40 - +125 C
t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - - 20 ns/V
VCC = 2.7 V to 5.5 V - - 10 ns/V
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 5 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb =40 C to +85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC --V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
VOH HIGH-level output voltage VI=V
IH or VIL
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 1.2 - - V
IO=8mA; V
CC = 2.3 V 1.9 - - V
IO=12 mA; VCC = 2.7 V 2.2 - - V
IO=24 mA; VCC = 3.0 V 2.3 - - V
IO=32 mA; VCC = 4.5 V 3.8 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.45 V
IO=8mA; V
CC = 2.3 V - - 0.3 V
IO=12mA; V
CC = 2.7 V - - 0.4 V
IO=24mA; V
CC = 3.0 V - - 0.55 V
IO=32mA; V
CC = 4.5 V - - 0.55 V
IIinput leakage current VI= 5.5 V or G ND; VCC =0Vto5.5V - 0.1 1A
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - 0.1 2A
ICC supply current VI= 5.5 V o r GND;
VCC =1.65Vto5.5V; I
O=0A -0.14A
ICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC 0.6 V; IO=0A - 5 500 A
CIinput capacitance V CC = 3.3 V; VI = GND to VCC -5-pF
Tamb =40 C to +125 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 VCC --V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 VCC --V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 VCC V
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 6 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
[1] All typical values are measured at VCC = 3.3 V and Tamb =25C.
11. Dynamic characteristics
VOH HIGH-level output voltage VI=V
IH or VIL
IO=100 A; VCC = 1.65 V to 5.5 V VCC 0.1 - - V
IO=4mA; V
CC = 1.65 V 0.95 - - V
IO=8mA; V
CC = 2.3 V 1.7 - - V
IO=12 mA; VCC = 2.7 V 1.9 - - V
IO=24 mA; VCC = 3.0 V 2.0 - - V
IO=32 mA; VCC = 4.5 V 3.4 - - V
VOL LOW-level output voltage VI=V
IH or VIL
IO=100A; VCC = 1.65 V to 5.5 V - - 0.1 V
IO=4mA; V
CC = 1.65 V - - 0.70 V
IO=8mA; V
CC = 2.3 V - - 0.45 V
IO=12mA; V
CC = 2.7 V - - 0.60 V
IO=24mA; V
CC = 3.0 V - - 0.80 V
IO=32mA; V
CC = 4.5 V - - 0.80 V
IIinput leakage current VI= 5.5 V or G ND; VCC =0Vto5.5V - - 1A
IOFF power-off leakage current VCC = 0 V; VIor VO=5.5V - - 2A
ICC supply current VI= 5.5 V o r GND;
VCC =1.65Vto5.5V; I
O=0A --4A
ICC additional supply current per pin; VCC = 2.3 V to 5.5 V;
VI=V
CC 0.6 V; IO=0A - - 500 A
Table 7. Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
tpd propagation delay CP to Q; see Figure 5 [2]
VCC = 1.65 V to 1.95 V 1.0 3.4 9.9 1.0 13.0 ns
VCC = 2.3 V to 2.7 V 0.5 2.3 7 .0 0.5 9.0 ns
VCC = 2.7 V 0.5 2.5 6.0 0.5 8.0 ns
VCC = 3.0 V to 3.6 V 0.9 2.4 5 .0 0.9 6.5 ns
VCC = 4.5 V to 5.5 V 0.5 1.8 4.5 0.5 6.0 ns
tsu set-up time HIGH or LOW; D to CP;
see Figure 6 [3]
VCC = 1.65 V to 1.95 V 2.3 0.8 - 2.3 - ns
VCC = 2.3 V to 2.7 V 1.5 0.6 - 1.5 - ns
VCC = 2.7 V 1.5 0.5 - 1. 5 - ns
VCC = 3.0 V to 3.6 V 1.3 0.4 - 1.3 - ns
VCC = 4.5 V to 5.5 V 1.1 0.5 - 1.1 - ns
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 7 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.
[2] tpd is the same as tPLH and tPHL.
[3] tsu is the same as tsu(H) and tsu(L).
[4] CPD is used to determine the dynamic power dissipation (PDin W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
thhold time D to CP; see Figure 6
VCC = 1.65 V to 1.95 V 0 0.6 - 0 - ns
VCC = 2.3 V to 2.7 V 0 0.4 - 0 - ns
VCC = 2.7 V +0.5 0.2 - 0.5 - ns
VCC = 3.0 V to 3.6 V 0.9 0.2 - 0.9 - ns
VCC = 4.5 V to 5.5 V +0.5 0.1 - 0.5 - ns
tWpulse width CP HIGH or LOW;
see Figure 6
VCC = 1.65 V to 1.95 V 3.0 1.1 - 3.0 - ns
VCC = 2.3 V to 2.7 V 2.5 0.7 - 2.5 - ns
VCC = 2.7 V 2.5 0.6 - 2.5 - ns
VCC = 3.0 V to 3.6 V 2.5 0.6 - 2.5 - ns
VCC = 4.5 V to 5.5 V 2.0 0.5 - 2.0 - ns
fmax maximum
frequency CP; see Figure 6
VCC = 1.65 V to 1.95 V 160 300 - 160 - MHz
VCC = 2.3 V to 2.7 V 160 350 - 160 - MHz
VCC = 2.7 V 160 350 - 160 - MHz
VCC = 3.0 V to 3.6 V 160 350 - 160 - MHz
VCC = 4.5 V to 5.5 V 200 400 - 200 - MHz
CPD power dissipation
capacitance VI = GND to VCC;
VCC = 3.3 V [4] -17---pF
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7.
Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit
Min Typ[1] Max Min Max
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 8 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
12. Waveforms
Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
Fig 5. Clock (CP) to output (Q) propagation delay times
PQD
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9
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Measurement points are given in Table 9.
VOL and VOH are typical output voltage levels that occur with the output.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 6. Clock (CP) to output (Q) propagation delay times, clock pulse width, D to set-up times, the CP to D hold
times and maximum clock pu lse frequency
PQD
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90
90
90
9,
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9,
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92+
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4RXWSXW
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 9 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
Table 9. Measur ement points
Supply voltage Input Output
VCC VMVM
1.65 V to 1.95 V 0.5 VCC 0.5 VCC
2.3 V to 2.7 V 0.5 VCC 0.5 VCC
2.7V 1.5V 1.5V
3.0V to 3.6V 1.5V 1.5V
4.5 V to 5.5 V 0.5 VCC 0.5 VCC
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 7. Test circuit for measuring switching times
9(;7
9&&
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Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr=t
fCLRLtPLH, tPHL
1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen
2.3 V to 2.7 V VCC 2.0ns 30pF 500open
2.7V 2.7V 2.5ns 50pF 500open
3.0V to 3.6V 2.7V 2.5ns 50pF 500open
4.5 V to 5.5 V VCC 2.5ns 50pF 500open
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 10 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
13. Package outline
Fig 8. Package outline SOT353-1 (TSSOP5)
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© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 11 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
Fig 9. Package outline SOT753 (SC-74A)
5()(5(1&(6
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© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 12 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC1G80_Q100 v.2 20161212 Product data sheet - 74LVC1G80_Q100 v.1
Modifications: •Table 7: The maximum limits for leakage current and supply current have changed.
74LV C1G80_Q100 v.1 20120731 Product data sheet - -
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 13 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nexperia.com.
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Draft — The document is a draft version only. The content is still under
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representations or warranties as to the accuracy or completeness of
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Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local Nexperia sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
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customer have explicitly agreed otherwise in writing. In no event however,
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Limited warr a nty and liability — Information in this document is believed to
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Customers are responsible for the design and ope ration of their applications
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Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development .
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
© Nexperia B.V. 2017. All rights reserved
74LVC1G80_Q100 All information provided in this document is subject to legal disclaimers.
Product data sheet Rev. 2 — 12 December 2016 14 of 15
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
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may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
17. Contact information
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Nexperia 74LVC1G80-Q100
Single D-type flip-flop; positive-edge trigger
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
7 Functional description . . . . . . . . . . . . . . . . . . . 3
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
9 Recommended operating conditions. . . . . . . . 4
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 12
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 12
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 13
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
17 Contact information. . . . . . . . . . . . . . . . . . . . . 14
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
© Nexperia B.V. 2017. All rights reserved
For more information, please visit: http://www.nexperia.com
For sales office addresses, please send an email to: salesaddresses@nexperia.com
Date of release:
12 December 2016
