NCP6356BFCCT1G - ON SEMICONDUCTOR

August, 2016 − Rev. 1 1Publication Order Number:

NCP6356B/D

NCP6356B

Configurable 5.0 A ACOT

Step Down Converter

The NCP6356B is a synchronous ACOT (Adaptive Constant

On−time) buck converter optimized to supply the different sub

systems of portable applications powered by one cell Li−Ion or three

cell Alkaline/NiCd/NiMH batteries. The device is able to deliver up to

5.0 A, with programmable output voltage from 0.6 V to 1.4 V.

Operation at up to 2.4 MHz switching frequency allows the use of

small components. Synchronous rectification and automatic PFM

Pseudo−PWM (PPWM) transitions improve overall solution

efficiency. The NCP6356B is in a space saving, low profile

2.0 x 1.6 mm CSP−20 package.

Features

•Input Voltage Range from 2.5 V to 5.5 V: Battery and 5 V Rail

Powered Applications

•Programmable Output Voltage: 0.6 V to 1.4 V in 6.25 mV Steps

•Up to 2.4 MHz Switching Frequency with On Chip Oscillator

•Uses 330 nH Inductor and at least 22 mF Capacitors for Optimized

Footprint and Solution Thickness

•PFM/PPWM Operation for Optimum Efficiency

•Low 60 mA Quiescent Current

•I2C Control Interface with Interrupt and Dynamic Voltage Scaling

Support

•Enable / VSEL Pins, Power Good / Interrupt Signaling

•Thermal Protections and Temperature Management

•Transient Load Helper: Share the Same Rail with Another Rail

•Small 2.0 x 1.6 mm / 0.4 mm Pitch CSP Package

•These are Pb−Free Devices

Typical Applications

•Smartphones

•Webtablets

Figure 1. Typical Application Circuit

330 nH

22 uF

Processor

Core

NCP6356B

I@C

Thermal

Protection

Processor I@C

Control Interface

Operating

Mode

Control

Output

Monitoring

Voltage

Selection

Interrupt

Power Fail

DCDC

5.0 A

Supply Input

DCDC

Up to 2.4 MHz

Controller Sense

Enable Control

Input

4.7 uF

SDA

SCL

AGND

PGND

INTB

PGND

VSEL

Core

PVIN

PGND

D1 AVIN

22uF

WLCSP20

CASE 568AG

MARKING

DIAGRAM

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See detailed ordering and shipping information on page 31 o

this data sheet.

ORDERING INFORMATION

x = blank: production

= S: 0.95 V

= N: 1.20 V

= V: 1.00 V

= W: 0.80 V

A = Assembly Location

WL = Wafer Lot

Y = Year

WW = Work Week

G= Pb−Free Package

Pb−Free indicator, G or microdot (G),

may or may not be present

PVIN

AVIN

PVIN

PGND

INTB*

SCLEN

PVIN

PGNDPGND

SDA PGND

PG*

VSEL

PGND

AGND

321

PIN OUT

(Top View)

*Optional

6356Bx

AWLYWW

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Figure 2. Simplified Block Diagram

Core

Thermal

Protection

Output Voltage

Monitoring

Operating

Mode Control

Logic Control

Interrupt

I2C

Up to 2.4 MHz

DC−DC converter

Controller

Sense

AGND

VSEL

INTB

SCL

SDA

PGND

PVIN

5.0 A

DC−DC

ANALOG GROUND

ENABLE CONTROL INPUT

VOLTAGE SELECTION

INTERRUPT OUTPUT

(optional)

PROCESSOR I2C

CONTROL INTERFACE

POWER GOOD

(optional)

POWER INPUT

SWITCH NODE

POWER GROUND

FEEDBACK

AVIN

SUPPLY INPUT

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PVIN

AVIN

PVIN

PGND

INTB*

SCLEN

PVIN

PGNDPGND

SDA PGND

PG*

VSEL

PGND

AGND

321

Figure 3. Pin Out (Top View)

*Optional

PIN FUNCTION DESCRIPTION

Pin Name Type Description

REFERENCE

D1 AVIN Analog Input Analog Supply. This pin is the device analog and digital supply. Can be connected

directly to the VIN plane just next to the 4.7 mF PVIN capacitor or to a dedicated

1.0 mF ceramic capacitor. Must be equal to PVIN.

B4 AGND Analog Ground Analog Ground. Analog and digital modules ground. Must be connected to the

system ground.

CONTROL AND SERIAL INTERFACE

A2 EN Digital Input Enable Control. Active high will enable the part. There is an internal pull down

resistor on this pin.

A1 VSEL Digital Input Output voltage / Mode Selection. The level determines which of two programmable

configurations to utilize (operating mode / output voltage). There is an internal pull

down resistor on this pin; can be left unconnected if not used.

A3 SCL Digital Input I2C interface Clock line. There is an internal pull down resistor on this pin; can be left

unconnected if not used

B1 SDA Digital

Input/Output I2C interface Bi−directional Data line. There is an internal pull down resistor on this

pin; can be left unconnected if not used

B3 PGND

PG Digital Output

Analog Ground Power Good open drain output. Must be connected to the ground plane if not used.

B2 PGND

INTB Digital Output

Analog Ground Interrupt open drain output. Must be connected to the ground plane if not used.

DC to DC CONVERTER

D2, E1, E2 PVIN Power Input Switch Supply. These pins must be decoupled to ground by a 4.7 mF ceramic capa-

citor. It should be placed as close as possible to these pins. All pins must be used

with short thick connections. Must be equal to AVIN.

D3, D4,

E3, E4 SW Power Output Switch Node. These pins supply drive power to the inductor. Typical application uses

0.33 mH inductor; refer to application section for more information.

All pins must be used with short thick connections.

C1, C2,

C3, C4 PGND Power Ground Switch Ground. This pin is the power ground and carries the high switching current.

High quality ground must be provided to prevent noise spikes. To avoid high−density

current flow in a limited PCB track, a local ground plane that connects all PGND pins

together is recommended. Analog and power grounds should only be connected

together in one location with a trace.

A4 FB Analog Input Feedback Voltage input. Must be connected to the output capacitor positive termin-

al with a trace, not to a plane. This is the positive input to the error amplifier.

NCP6356B

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MAXIMUM RATINGS

Rating Symbol Value Unit

Analog and power pins: AVIN, PVIN, SW, INTB, FB (Note 1) VA−0.3 to +6.0 V

I2C pins: SDA, SCL VI2C−0.3 to +6.0 V

Digital pins: EN, VSEL

Input Voltage

Input Current VDG

IDG −0.3 to VA + 0.3 ≤ 6.0

10 V

Human Body Model (HBM) ESD Rating (Note 2) ESD HBM 2500 V

Charged Device Model (CDM) ESD Rating (Note 2) ESD CDM 1250 V

Latch Up Current: (Note 3)

Digital Pins

All Other Pins

ILU 10

100

Storage Temperature Range TSTG −65 to +150 °C

Maximum Junction Temperature TJMAX −40 to +150 °C

Moisture Sensitivity (Note 4) MSL Level 1

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be af fected.

1. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe

Operating parameters.

2. This device series contains ESD protection and passes the following ratings:

Human Body Model (HBM) ± 2.5 kV per JEDEC standard: JESD22−A114.

Charged Device Model (CDM) ± 1.25 V per JEDEC standard: JESD22−C101 Class IV

3. Latch up Current per JEDEC standard: JESD78 class II.

4. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.

OPERATING CONDITIONS

Symbol Parameter Conditions Min Typ Max Unit

AVIN, PVIN Power Supply AVIN = PVIN 2.5 5.5 V

TAAmbient Temperature Range −40 25 +85 °C

TJJunction Temperature Range (Note 6) −40 25 +125 °C

RqJA Thermal Resistance Junction to Ambient (Note 7) CSP−20 on Demo−board − 55 − °C/W

PDPower Dissipation Rating (Note 8) TA ≤ 85°C − 727 − mW

PDPower Dissipation Rating (Note 8) TA = 65°C − 1090 − mW

LInductor for DC to DC converter (Note 5) 0.26 0.33 0.56 mH

Co Output Capacitor for DC to DC Converter (Note 5) 15 − 150 mF

Cin Input Capacitor for DC to DC Converter (Note 5) 4.5 − − mF

Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond

the Recommended Operating Ranges limits may affect device reliability.

5. Including de−ratings (Refer to the Application Information section of this document for further details)

6. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.

7. The RqJA is dependent of the PCB heat dissipation. Board used to drive this data was a NCP6356BEVB board. It is a multilayer board with

1−once internal power and ground planes and 2−once copper traces on top and bottom of the board.

8. The maximum power dissipation (PD) is dependent by input voltage, maximum output current and external components selected.

RqJA +125 *TA

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ELECTRICAL CHARACTERISTICS (Note 9)

Min and Max Limits apply for TA = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.

Typical values are referenced to TA = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

SUPPLY CURRENT: PINS AVIN – PVINx

IQ−PPWM Operating quiescent current PPWM DCDC active in Forced PPWM, no load − 22 40 mA

IQ PFM Operating quiescent current PFM DCDC active in Auto mode

no load − minimal switching − 60 100 mA

ISLEEP Product sleep mode current EN high, DCDC off or

EN low and I2C pull up

VIN = 5.5 V

− 5 10 mA

IOFF Product in off mode EN, VSEL and Sleep_Mode low,

No I2C pull up

VIN = 5.5 V

− 0.8 3 mA

DC to DC CONVERTER

PVIN Input Voltage Range 2.5 − 5.5 V

IOUTMAX Maximum Output Current Ipeak[1..0] = 00 (Note 11) 3.5 − − A

Ipeak[1..0] = 01 (Note 11) 4.0 − −

Ipeak[1..0] = 10 (Note 11) 4.5 − −

Ipeak[1..0] = 11 (Note 11) 5.0 − −

DVOUT Output Voltage DC Error Forced PPWM mode, VIN range, No load −1.5 − 1.5 %

Forced PPWM mode, VIN range,

IOUT up to IOUTMAX (Note 11) −2 − 2

Auto mode, VIN range,

IOUT up to IOUTMAX (Note 11) −3 − 2

FSW Switching Frequency 2.16 2.40 2.64 MHz

RONHS P−Channel MOSFET On

Resistance From PVIN to SW

VIN = 5.0 V − 22 32 mW

RONLS N−Channel MOSFET On

Resistance From SW to PGND

VIN = 5.0 V − 12 18 mW

IPK Peak Inductor Current Open loop – Ipeak[1..0] = 00 (Note 11) 4.6 5.2 5.8 A

Open loop – Ipeak[1..0] = 01 (Note 11) 5.2 5.8 6.4

Open loop – Ipeak[1..0] = 10 (Note 11) 5.6 6.2 6.8

Open loop – Ipeak[1..0] = 11 6.2 6.8 7.4

DCLOAD Load Regulation IOUT from 0 A to IOUTMAX (Note 11)

Forced PPWM mode − 5 − mV

DCLINE Line Regulation 2.5 V ≤ VIN ≤ 5.5 V (Note 11)

Forced PPWM mode − 6 − mV

ACLOAD Transient Load Response tr = tf = 100 ns

Load step 1.5 A (Note 11) −±20 − mV

ACLINE Transient Line Response tr = tf = 10 ms

Line step 3.3 V / 3.9 V (Note 11) −±20 − mV

DMaximum Duty Cycle − 100 − %

tSTART Turn on time Time from EN transitions from Low to

High to 90% of Output Voltage

(DVS[1..0] = 00b)

− 100 130 ms

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

9. Refer to the Application Information section of this data sheet for more details.

10.Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels

to the VDD voltage to which the pull−up resistors RP are connected.

11.Guaranteed by design and characterized.

NCP6356B

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ELECTRICAL CHARACTERISTICS (Note 9)

Min and Max Limits apply for TA = −40°C to +85°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.

Typical values are referenced to TA = +25°C, AVIN = PVIN = 3.6 V and default configuration, unless otherwise specified.

Symbol UnitMaxTypMinConditionsParameter

DC to DC CONVERTER

RDISDCDC DCDC Active Output Discharge VOUT = 1.15 V − 12 25 W

EN, VSEL

VIH High input voltage 1.05 − − V

VIL Low input voltage − − 0.4 V

TFTR Digital input X Filter EN, VSEL rising and falling

DBN_Time = 01 (Note 11) 0.5 − 4.5 ms

IPD Digital input X Pull−Down

(input bias current) For EN and VSEL pins − 0.05 1.00 mA

PG (Optional)

VPGL Power Good Threshold Falling edge as a percentage of

nominal output voltage 86 90 94 %

VPGHYS Power Good Hysteresis 0 3 5 %

TRT Power Good Reaction Time for

DCDC Falling (Note 11)

Rising (Note 11) −

3.5 3.5

−−

14 ms

VPGL Power Good low output voltage IPG = 5 mA − − 0.2 V

PGLK Power Good leakage current 3.6 V at PG pin when power good valid − − 100 nA

VPGH Power Good high output voltage Open drain − − 5.5 V

INTB (Optional)

VINTBL INTB low output voltage IINT = 5 mA 0 − 0.2 V

VINTBH INTB high output voltage Open drain − − 5.5 V

INTBLK INTB leakage current 3.6 V at INTB pin when INTB valid − − 100 nA

I2C

VI2CIL SCL, SDA low input voltage SCL, SDA pin (Notes 10, 11) − − 0.4 V

VI2CIH SCL high input voltage SCL pin (Notes 10, 11) 1.6 − − V

SDA high input voltage SDA pin (Notes 10, 11) 1.2 − −

VI2COL SDA low output voltage ISINK = 3 mA (Note 11) − − 0.4 V

FSCL I2C clock frequency (Note 11) − − 3.4 MHz

TOTAL DEVICE

VUVLO Under Voltage Lockout VIN falling − − 2.5 V

VUVLOH Under Voltage Lockout Hysteresis VIN rising 60 − 200 mV

TSD Thermal Shut Down Protection − 150 − °C

TWARNING Warning Rising Edge − 135 − °C

TPWTH Pre − Warning Threshold I2C default value − 105 − °C

TSDH Thermal Shut Down Hysteresis − 30 − °C

TWARNINGH Thermal warning Hysteresis − 15 − °C

TPWTH HThermal pre−warning Hysteresis − 6 − °C

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

9. Refer to the Application Information section of this data sheet for more details.

10.Devices that use non−standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels

to the VDD voltage to which the pull−up resistors RP are connected.

11.Guaranteed by design and characterized.

NCP6356B

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TYPICAL OPERATING CHARACTERISTICS

AVIN = PVIN = 3.6 V, TJ = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 10 mF 0603

Figure 4. Efficiency vs. ILOAD and VIN

VOUT = 1.39375 V, SPM5030 Inductor Figure 5. Efficiency vs. ILOAD and Temperature

VOUT = 1.39375 V, SPM5030 Inductor

Figure 6. Efficiency vs. ILOAD and VIN

VOUT = 1.15 V, SPM5030 Inductor Figure 7. Efficiency vs. ILOAD and Temperature

VOUT = 1.15 V, SPM5030 Inductor

Figure 8. Efficiency vs. ILOAD and VIN

VOUT = 0.60 V, SPM5030 Inductor Figure 9. Efficiency vs. ILOAD and Temperature

VOUT = 0.60 V, SPM5030 Inductor

NCP6356B

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TYPICAL OPERATING CHARACTERISTICS

AVIN = PVIN = 3.6 V, TJ = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 10 mF 0603

Figure 10. Efficiency vs. ILOAD and VIN

VOUT = 1.15 V Figure 11. Efficiency vs. ILOAD and Temperature

VOUT = 1.15 V

Figure 12. VOUT Accuracy vs. ILOAD and VIN

VOUT = 1.15 V Figure 13. VOUT Accuracy vs. VIN and

Temperature, VOUT = 1.15 V

Figure 14. VOUT Accuracy vs. ILOAD and VIN

VOUT = 0.60 V Figure 15. VOUT Accuracy vs. ILOAD and VIN

VOUT = 1.39375 V

NCP6356B

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TYPICAL OPERATING CHARACTERISTICS

AVIN = PVIN = 3.6 V, TJ = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 10 mF 0603

Figure 16. HSS RON vs. VIN and Temperature Figure 17. LSS RON vs. VIN and Temperature

Figure 18. IOFF vs. VIN and Temperature Figure 19. ISLEEP vs. VIN and Temperature

Figure 20. IQ PFM vs. VIN and Temperature Figure 21. IQ PPWM vs. VIN and Temperature

NCP6356B

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TYPICAL OPERATING CHARACTERISTICS

AVIN = PVIN = 3.6 V, TJ = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 10 mF 0603

Figure 22. Switchover Point VOUT = 1.15 V Figure 23. Switchover Point VOUT = 1.4 V

Figure 24. Ripple Figure 25. Normal Power Up, VOUT = 1.15 V,

DVS[1..0] = 00

Figure 26. Transient Load 3.5 A to 5.0 A − VIN = 3.2 V

NCP6356B

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TYPICAL OPERATING CHARACTERISTICS

AVIN = PVIN = 3.6 V, TJ = +25°C, DCDC = 1.15 V, L = 0.33 mH DFE252012F – COUT = 2 x 22 mF 0603, CIN = 10 mF 0603

Figure 27. Transient Load 0.01 to 1.5 A

Transient Line 3.9 to 3.3 V − Auto Mode Figure 28. Transient Load 0.01 to 1.5 A

Transient Line 3.3 to 3.9 V − Auto Mode

Figure 29. Transient Load 1 to 2.5 A

Transient Line 3.9 to 3.3 V − Auto Mode Figure 30. Transient Load 1 to 2.5 A

Transient Line 3.3 to 3.9 V − Auto Mode

Figure 31. Transient Load 1 to 2.5 A during

Transient Line 3.9 − 3.3 V Auto Mode Figure 32. Transient Load 1 to 2.5 A during

Transient Line 3.3 to 3.9 V − Auto Mode

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DETAILED OPERATING DESCRIPTION

Detailed Description

The NCP6356B is voltage mode stand−alone DC to DC

converter optimized to supply different sub systems of

portable applications powered by one cell Li−Ion or three

cells Alkaline/NiCd/NiMh. It can deliver up to 5 A at a n I2C

selectable voltage ranging from 0.6 V to 1.40 V. The

switching frequency up to 2.4 MHz allows the use of small

output filter components. Power Good indicator and

Interrupt management are available. Operating modes,

configuration, and output power can be easily selected either

by using digital I/O pins or by programming a set of registers

using a n I 2C compatible interface capable of operation up to

3.4 MHz. Default I2C settings are factory programmable.

DC to DC Converter Operation

The converter integrates both high side and low side

(synchronous) switches. Neither external transistors nor

diodes are required for NCP6356B operation. Feedback and

compensation network are also fully integrated.

It uses the ACOT (Adaptive Constant On−Time) control

scheme and can operate in two different modes: PFM and

PPWM (Pseudo−PWM). The transition between modes can

occur automatically or the switcher can be placed in forced

PPWM mode by I2C programming (PPWMVSEL0 /

PPWMVSEL1 bits of COMMAND register).

PPWM (Pseudo Pulse Width Modulation) Operating Mode

In medium and high load conditions, NCP6356B operates

in PPWM mode to regulate the desired output voltage. In

this mode, the inductor current is in CCM (Continuous

Conduction Mode) and the ACOT guaranties a

pseudo−fixed frequency with 10% accuracy. The internal

N−MOSFET switch operates as a synchronous rectifier and

is driven complementary to the P−MOSFET switch.

PFM (Pulse Frequency Modulation) Operating Mode

In order to save power and improve efficiency at low

loads, the NCP6356B operates in PFM mode as the inductor

current drops into DCM (Discontinuous Conduction Mode).

The upper FET on−time is kept constant and the switching

frequency becomes proportional to the loading current. As

it does in PPWM mode, the internal N−MOSFET operates

as a synchronous rectifier after each P−MOSFET on−pulse

until there is no longer current in the coil.

When the load increases and the current in the inductor

become continuous again, the controller automatically turns

back to PPWM mode.

Forced PPWM

The NCP6356B can be programmed to only use PPWM

and the transition to PFM can be disabled if so desired,

thanks to the PPWMVSEL0 or PPWMVSEL1 I2C bits

(COMMAND register).

Output Stage

NCP6356B i s a 3 . 5 A to 5.0 A output current capable DC

to DC converter with both high side and low side

(synchronous) switches integrated.

Inductor Peak Current Limitation / Short Protection

During normal operation, p eak current l imitation monitors

and limits the inductor current by checking the current in the

P−MOSFET switch. When this current exceeds the Ipeak

threshold, the P−MOSFET is immediately opened.

To protect again excessive load or short circuit, the

number of consecutive Ipeak is counted. When the counter

reaches 16, the DCDC is powered down during about 2 ms

and the ISHORT interrupt is flagged. It will re−start

following the REARM bit in the LIMCONF register:

•If REARM = 0, then NCP6356B does not re−start

automatically, an EN pin toggle is required.

•If REARM = 1, NCP6356B re−starts automatically

after the 2 ms with register values set prior the fault

condition.

This current limitation is particularly useful to protect the

inductor. The peak current can be set by writing

IPEAK[1..0] bits in the LIMCONF register.

Table 1. IPEAK VALUES

IPEAK[1..0] Inductor Peak Current (A)

00 5.2 − for 3.5 output current

01 5.8 − for 4.0 output current

10 6.2 − for 4.5 output current

11 6.8 − for 5.0 output current

Output Voltage

The output voltage is set internally by an integrated

resistor bridge and no extra components are needed to set the

output voltage. Writing in the VoutVSEL0[6..0] bits of the

PROGVSEL0 register or VoutVSEL1[6..0] bits of the

PROGVSEL1 register will change the output voltage. The

output voltage level can be programmed by 6.26 mV steps

between 0.6 V to 1.39375 V. The VSEL pin and VSELGT

bit will determine which register between PROGVSEL0

and PROGVSEL1 will set the output voltage.

•If VSELGT = 1 AND VSEL=0 ³ Output voltage is set

by VoutVSEL0[6..0] bits (PROGVSEL0 register)

•Else ³ Output voltage is set by VoutVSEL1[6..0] bits

(PROGVSEL1 register)

Under Voltage Lock Out (UVLO)

The NCP6356B core does not operate for voltages below

the Under Voltage Lock Out (UVLO) level. Below the

UVLO threshold, all internal circuitry (both analog and

digital) is held in reset. The NCP6356B operation is

guaranteed down to UVLO as the battery voltage is

dropping off. To avoid erratic on / off behavior, a maximum

200 mV hysteresis is implemented. Restart is guaranteed at

2.7 V when the VBAT voltage is recovering or rising.

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Thermal Management

Thermal Shut Down (TSD)

The thermal capability of the NCP6356B can be exceeded

due to the step down converter output stage power level. A

thermal protection circuitry with associated interrupt is

therefore implemented to prevent the IC from damage. This

protection circuitry is only activated when the core is in

active mode (output voltage is turned on). During thermal

shut down, output voltage is turned of f. During thermal shut

down, output voltage is turned off.

During thermal shutdown, the output voltage is turned of f.

When the NCP6356B returns from thermal shutdown, it can

re−start in 2 different configurations depending on the

REARM bit in the LIMCONF register (refer to the register

description section):

If REARM = 0, the NCP6356B does not re−start after

TSD. To restart, an EN pin toggle is required. If REARM

= 1, the NCP6356B re−starts with register values set prior to

thermal shutdown.

The thermal shut down threshold is set at 150°C (typical)

and a 30°C hysteresis is implemented in order to avoid

erratic on / o ff behavior. After a typical 150°C thermal shut

down, the NCP6356B will resume to normal operation when

the die temperature cools to 120°C.

Thermal Warnings

In addition to the TSD, the die temperature monitoring

circuitry includes a thermal warning and thermal

pre−warning sensor and interrupts. These sensors can

inform the processor that the NCP6356B is close to its

thermal shutdown and preventive measures to cool down die

temperature can be taken by software.

The Warning threshold is set by hardware to 135°C

typical. The Pre−Warning threshold is set by default to

105°C but it can be changed by setting the TPWTH[1..0]

bits in the LIMCONF register.

Active Output Discharge

To make sure that no residual voltage remains in the power

supply rail when disabled, an active discharge path can

ground the NCP6356B output voltage. For maximum

flexibility, this feature can be easily disabled or enabled with

the DISCHG bit in the PGOOD register. By default the

discharge path is enabled and is activated during the first

100 ms after battery insertion.

Enabling

The EN pin controls the NCP6356B start up. EN pin Low

to High transition starts the power up sequencer . If E N i s l o w,

the DC to DC converter is turned off and device enters:

•Sleep Mode if Sleep_Mode I2C bit is high or VSEL is

high,

•Off Mode if Sleep_Mode I2C bit and VSEL are low.

When EN pin i s s et t o a h igh l evel, the D C t o D C converter c an

be e nabled / d isabled b y w riting t he ENVSEL0 or ENVSEL1

bit of the PROGVSEL0 and PROGVSEL1 registers:

•Enx I2C bit is high, the DC to DC converter is

activated.

•Enx I2C is low, the DC to DC converter is turned off

and the device enters in Sleep Mode.

A built in pull down resistor disables the device when this

pin is left unconnected or not driven. EN pin activity does

not generate any digital reset.

Power Up Sequence (PUS)

In order to power up the circuit, the input voltage AVIN

has to rise above the VUVLO threshold. This triggers the

internal core circuitry power up which is the “Wake Up

Time” (including “Bias Time”).

This delay is internal and cannot be bypassed. EN pin

transition within this delay corresponds to the “Initial power

up sequence” (IPUS):

POR

UVLO

AVIN

Wake up

Time

DELAY[2..0]

~80us 32us

VOUT

DVS ramp

Time

Init

Time

ÏÏÏÏÏ

Figure 33. Initial Power Up Sequence

In addition a user programmable delay will also take place

between the Wake Up Time and the Init time: The

DELAY[2..0] bits of the TIME register will set this user

programmable delay with a 2 ms resolution. With default

delay of 0 ms, the NCP6356B IPUS takes roughly 100 ms,

and the DC to DC converter output voltage will be ready

within 150 ms.

The power up output voltage is defined by the VSEL state.

NOTE: During the Wake Up time, the I2C interface is not

active. Any I2C request to the IC during this time period will

result in a NACK reply.

Normal, Quick and Fast Power Up Sequence

The previous description applies only when the EN

transitions during the internal core circuitry power up ( Wake

up and calibration time). Otherwise 3 different cases are

possible:

•Enabling the part by setting the EN pin from Off Mode

will result in “Normal power up sequence” (NPUS,

with DELAY;[2..0]).

•Enabling the part by setting the EN pin from Sleep

Mode will result in “Quick power up sequence”

(QPUS, with DELAY;[2..0]).

•Enabling the DC to DC converter, whereas EN is

already high, either by setting the ENVSEL0 or

ENVSEL1 bits or by VSEL pin transition will results in

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“Fast power up sequence” (FPUS, without

DELAY[2..0]).

Sleep mode is when VSEL is high and EN low, or when

Sleep_Mode I 2C bit is set and EN is low, or finally when DC

to DC converter is off and EN high.

POR

UVLO

DELAY[2..0] 32us

DVS ramp

Time

Init

Time

TFTR

60us

Bias

Time

AVIN

VOUT

Figure 34. Normal Power Up Sequence

POR

UVLO

DELAY[2..0] 32us

DVS ramp

Time

Init

Time

TFTR

10us

Bias

Time

AVIN

VOUT

Figure 35. Quick Power Up Sequence

Figure 36. Fast Power Up Sequence

POR

UVLO

AVIN

VSEL

32 us

VOUT

DVS ramp

Time

Init

Time

TFTR

In addition the delay set in DELAY[2..0] bits in TIME

(NPUS and QPUS).

The power up output voltage is defined by VSEL state.

DC to DC Converter Shut Down

When shutting down the device, no shut down sequence

is required. The output voltage is disabled and, depending on

the DISCHG bit state of the PGOOD register , the output may

be discharged.

DC to DC converter shutdown is initiated by either

grounding the EN pin (Hardware Shutdown) or, depending

on the VSEL internal signal level, by clearing the ENVSEL0

or ENVSEL1 bits (Software shutdown) in the PROGVSEL0

or PROGVSEL1 registers.

In hardware shutdown (EN = 0), the internal core is still

active and I2C accessible.

The internal core of the NCP6356B shuts down when

AVIN falls below UVLO

Dynamic Voltage Scaling (DVS)

The NCP6356B supports dynamic voltage scaling (DVS)

allowing the output voltage to be reprogrammed via I2C

commands and provides the different voltages required by

the processor. The change between set points is managed in

a smooth fashion without disturbing the operation of the

processor.

When programming a higher voltage, the output raises

with controlled dV/dt defined by DVS[1..0] bits in the TIME

voltage will decrease accordingly. The DVS step is fixed and

the speed is programmable.

The DVS sequence is automatically initiated by changing

the output voltage settings. There are two ways to change

these settings:

•Directly change the active setting register value

(VoutVSEL0[6..0] of the PROGVSEL0 register or

VoutVSEL1[6..0] of the PROGVSEL1 register) via an

I2C command

•Change the VSEL internal signal level by toggling the

VSEL pin.

The second method eliminates the I2C latency and is

therefore faster.

The DVS transition mode can be changed with the

DVSMODE bit in the COMMAND register:

•In forced PPWM mode when accurate output voltage

control is needed. Rise and fall time are controlled with

the DVS[1..0] bits.

Internal

Reference Output

Voltage

Figure 37. DVS in Forced PPWM Mode Diagram

•In Auto mode when the output voltage must not be

discharged. Rise time is controlled by the DVS[1..0],

and fall time depends on the load and cannot be faster

than the DVS[1..0] settings.

Internal

Reference

Output

Voltage

Figure 38. DVS in Auto Mode Diagram

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Digital IO Settings

VSEL Pin

By changing the VSEL pin levels, the user has a latency

free way to change the NCP6356B configuration: the

operating mode, the output voltage as well as the enable (see

Table 2).

Table 2. VSEL PIN PARAMETERS

Parameter VSEL

Pin Can Set REGISTER

VSEL = LOW REGISTER

VSEL = HIGH

ENABLE ENVSEL0

PROGVSEL0[7] ENVSEL1

PROGVSEL1[7]

VOUT VoutVSEL0[6..0] VoutVSEL1[6..0]

OPERATING MODE

(Auto / PPWM Forced) PWMVSEL0

COMMAND[7] PWMVSEL1

COMMAND[6]

VSEL pin action can be masked by writing 0 to the VSELGT

bit in the COMMAND register. In that case the I2C bit

corresponding to VSEL high will be taken into account.

EN Pin

The EN pin can be gated by writing the ENVSEL0 or

ENVSEL1 bits of the PROGVSEL0 and PROGVSEL1

registers, depending on which register is activated by the

VSEL internal signal.

Power Good Pin (Optional)

To indicate the output voltage level is established, a power

good signal is available.

The power good signal is low when the DC to DC

converter i s o f f . Once the output voltage reaches 95% of the

expected output level, the power good logic signal becomes

high and the open drain output becomes high impedance.

During a positive DVS sequence when the target voltage

is higher than the initial voltage, the Power Good logic

signal will be set low during the output voltage ramping an d

will transition to high once the output voltage reaches 95%

of the target voltage. When the target voltage is lower than

the initial voltage, the Power Good pin will remain at a high

level during the transition.

The Power Good signal during normal operation can be

disabled b y c learing t he P GDCDC b it i n t he P GOOD r egister .

The Power Good operation during DVS can be controlled

by setting / clearing the PGDVS bit in the PGOOD register.

DCDC_EN

32 us

min

DCDC

95%

90%

3.5−

14 us 3.5−

14 us

3.5us

Figure 39. Power Good Signal

Power Good Delay

In order to generate a Reset signal, a delay can be

programmed between when the output voltage gets 95% of

its final value and when the Power Good pin is released to

a high level.

Vout

Delay Programmed in

TOR[2:0]

Delay

Figure 40. Power Good Operation

Interrupt Pin (Optional)

The interrupt controller continuously monitors internal

interrupt sources, generating an interrupt signal when a

system status change is detected (dual edge monitoring).

Table 3. INTERRUPT SOURCES

Interrupt Name Description

TSD Thermal Shut Down

TWARN Thermal Warning

TPREW Thermal Pre Warning

UVLO Under Voltage Lock Out

IDCDC DC to DC converter Current Over /

below limit

ISHORT DC to DC converter Short−Circuit Protection

PG Power Good

Individual bits generating interrupts will be set to 1 in the

INT_ACK register (I2C read only registers), indicating the

interrupt source. INT_ACK register is automatically reset

by an I2C read. The INT_SEN register (read only register)

contains real time indicators of interrupt sources.

All interrupt sources can be masked by writing in register

INT_MSK. Masked sources will never generate an interrupt

request on the INTB pin.

The INTB pin is an open drain output. A non−masked

interrupt r equest w ill r esult i n t he I NTB p in b eing d riven l ow.

When the host reads the INT_ACK registers the INTB pi n

is released to high impedance and the interrupt register

INT_ACK is cleared.

Figure 41 is an example of an UVLO event of the INTB

pin with INT_SEN/INT_MSK/INT_ACK and an I2C read

access behavior.

readI@C access on INT_ACK read read read

INTB

ACK_UVLO

MSK_UVLO

SEN−UVLO

UVLO

Figure 41. Interrupt Operation Example

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Configurations

Default output voltages, enables, DCDC modes, current limit and other parameters can be factory programmed upon request.

Below are the pre−defined default configurations:

Table 4. NCP6356B CONFIGURATION

Configuration 5.0 A

NCP6356B 4.0 A

NCP6356BS 4.0 A

NCP6356BSN 5.0 A

NCP6356BV 5.0 A

NCP6356BW

Default I2C address

PID product identification

RID revision identification

FID feature identification

0x14

19h

Metal

00h

0x1C

19h

Metal

08h

0x1C

19h

Metal

09h

0x14

19h

Metal

04h

0x14

19h

Metal

05h

Default VOUT – VSEL=1 1.15 V 0.95 V 1.20 V 1.00 V 0.80 V

Default VOUT – VSEL=0 1.15 V 0.95 V 1.20 V 1.00 V 0.65 V

Default Enable – VSEL=1 ON ON ON ON ON

Default Enable – VSEL=0 ON ON ON ON ON

Default MODE – VSEL=1 Forced PPWM Auto mode Auto mode Forced PPWM Forced PPWM

Default MODE – VSEL=0 Auto mode Auto mode Auto mode Forced PPWM Forced PPWM

Default IPEAK 6.8 A 5.8 A 5.8 A 6.8 A 6.8 A

OPN NCP6356BFCCT

1G NCP6356BSFCC

T1G NCP6356BSNFC

CT1G NCP6356BVFCC

T1G NCP6356BWFC

CT1G

Marking 6356B 6356BS 6356BN 6356BV 6356BW

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I2C Compatible Interface

The NCP6356B can support a subset of the I2C protocol as detailed below.

I2C Communication Description

START IC ADDRESS 1

1àREAD

ACK DATA 1 ACK DATA n /ACK STOP

START ACK

IC ADDRESS 0

0àWRITE

DATA 1 ACK DATA n ACK

/ACK STOP

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

READ OUT FROM PAR

WRITE INSIDE PART

Figure 42. General Protocol Description

If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr (repeated start).

If PART Acknowledges, the ACK can be followed by another data or STOP or Sr

The first byte transmitted is the Chip address (with the LSB bit set to 1 for a read operation, or set to 0 for a W rite operation).

The following data will be:

•During a Write operation, the register address (@REG) is written in followed by the data. The writing process is

auto−incremental, so the first data will be written in @REG, the contents of @REG are incremented and the next data

byte is placed in the location pointed to by @REG + 1 …, etc.

•During a Read operation, the NCP6356B will output the data from the last register that has been accessed by the last

write operation. Like the writing process, the reading process is auto−incremental.

Read Sequence

The Master will first make a “Pseudo Write” transaction with no data to set the internal address register. Then, a stop then

start or a Repeated Start will initiate the read transaction from the register address the initial write transaction has pointed to:

STOP

IC ADDRESS 1

1à READ

ACK

START IC ADDRESS 0

0à

WRITE

START ACK DATA 1 DATA n

ACK /ACK STOP

SETS INTERNAL

VALUE REGISTER ADDRESS + (n−1)

n REGISTERS READ

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

Figure 43. Read Sequence

VALUE

The first WRITE sequence will set the internal pointer to the register that is selected. Then the read transaction will start at

the address the write transaction has initiated.

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Write Sequence

Write operation will be achieved by only one transaction. After chip address, the REG address has to be set, then following

data will be the data we want to write in REG, REG + 1, REG + 2, …, REG +n.

Write n Registers:

REG + (n−1) VALUE ACK STOP

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

START IC ADDRESS 0

0à

WRITE

ACK REGISTER REG0 ADDRESS ACK REG VALUE ACK

SETS INTERNAL

n REGISTERS WRITE

Figure 44. Write Sequence

Write then Read Sequence

With Stop Then Start

REG+ (n– 1) VALUE ACK STOP

FROM MCU to NCPxxxx

FROM NCPxxxx to MCU

IC ADDRESS 0

0à WRITE

ACK REGISTER REG0 ADDRESS ACK REG VALUE ACK

SETS INTERNAL

n REGISTERS WRITE

IC ADDRESS 1

1à READ

START ACK DATA 1 DATA kACK /ACK STOP

VALUE REGISTER ADDRESS + (n−1) +

k REGISTERS READ

START

Figure 45. Write Followed by Read Transaction

(k−1) VALUE

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I2C Address

The NCP6356B has 8 available I2C addresses selectable by factory settings (ADD0 to ADD7). Different address settings

can be generated upon request to ON Semiconductor. See Table 4 (NCP6356B Configuration) for the default I2C address.

Table 5. I2C ADDRESS

I2C Address Hex A7 A6 A5 A4 A3 A2 A1 A0

ADD0 W 0x20

R 0x21 0 0 1 0 0 0 0 R/W

Add 0x10 −

ADD1 W 0x28

R 0x29 0 0 1 0 1 0 0 R/W

Add 0x14 −

ADD2 W 0x30

R 0x31 0 0 1 1 0 0 0 R/W

Add 0x18 −

ADD3 W 0x38

R 0x39 0 0 1 1 1 0 0 R/W

Add 0x1C −

ADD4 W 0xC0

R 0xC1 1 1 0 0 0 0 0 R/W

Add 0x60 −

ADD5 W 0xC8

R 0xC9 1 1 0 0 1 0 0 R/W

Add 0x64 −

ADD6 W 0xD0

R 0xD1 1 1 0 1 0 0 0 R/W

Add 0x68 −

ADD7 W 0xD8

R 0xD9 1 1 0 1 1 0 0 R/W

Add 0x6C −

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The tables below describe the I2C registers.

Registers / bits Operations:

R Read only register

RC Read then Clear

RW Read and Write register

Reserved Address is reserved and register / bit is not physically designed

Spare Address is reserved and register / bit is physically designed

Table 6. I2C REGISTERS MAP CONFIGURATION (NCP6356B)

Add. Register Name Type Def. Function

00h INT_ACK RC 00h Interrupt register

01h INT_SEN R 00h Sense register (real time status)

02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim)

03h PID R 19h Product Identification

04h RID R Metal Revision Identification

05h FID R 00h Features Identification (trim)

06h to 0Fh − − − Reserved for future use

10h PROGVSEL1 RW D8h Output voltage settings and EN for VSEL pin = High (trim)

11h PROGVSEL0 RW D8h Output voltage settings and EN for VSEL pin = Low (trim)

12h PGOOD RW 10h Power good and active discharge settings (trim)

13h TIME RW 09h Enabling and DVS timings (trim)

14h COMMAND RW 43h Enabling and Operating mode Command register (trim)

15h − − − Reserved for future use

16h LIMCONF RW E3h Reset and limit configuration register (trim)

17h to 1Fh − − − Reserved for future use

20h to FFh − − − Reserved. Test Registers

Table 7. I2C REGISTERS MAP CONFIGURATION (NCP6356BS)

Add. Register Name Type Def. Function

00h INT_ACK RC 00h Interrupt register

01h INT_SEN R 00h Sense register (real time status)

02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim)

03h PID R 19h Product Identification

04h RID R Metal Revision Identification

05h FID R 08h Features Identification (trim)

06h to 0Fh − − − Reserved for future use

10h PROGVSEL1 RW B8h Output voltage settings and EN for VSEL pin = High (trim)

11h PROGVSEL0 RW B8h Output voltage settings and EN for VSEL pin = Low (trim)

12h PGOOD RW 10h Power good and active discharge settings (trim)

13h TIME RW 01h Enabling and DVS timings (trim)

14h COMMAND RW 03h Enabling and Operating mode Command register (trim)

15h − − − Reserved for future use

16h LIMCONF RW 63h Reset and limit configuration register (trim)

17h to 1Fh − − − Reserved for future use

20h to FFh − − − Reserved. Test Registers

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Table 8. I2C REGISTERS MAP CONFIGURATION (NCP6356BSN)

Add. Register Name Type Def. Function

00h INT_ACK RC 00h Interrupt register

01h INT_SEN R 00h Sense register (real time status)

02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim)

03h PID R 19h Product Identification

04h RID R Metal Revision Identification

05h FID R 09h Features Identification (trim)

06h to 0Fh − − − Reserved for future use

10h PROGVSEL1 RW E0h Output voltage settings and EN for VSEL pin = High (trim)

11h PROGVSEL0 RW E0h Output voltage settings and EN for VSEL pin = Low (trim)

12h PGOOD RW 10h Power good and active discharge settings (trim)

13h TIME RW 01h Enabling and DVS timings (trim)

14h COMMAND RW 03h Enabling and Operating mode Command register (trim)

15h − − − Reserved for future use

16h LIMCONF RW 63h Reset and limit configuration register (trim)

17h to 1Fh − − − Reserved for future use

20h to FFh − − − Reserved. Test Registers

Table 9. I2C REGISTERS MAP CONFIGURATION (NCP6356BV)

Add. Register Name Type Def. Function

00h INT_ACK RC 00h Interrupt register

01h INT_SEN R 00h Sense register (real time status)

02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim)

03h PID R 19h Product Identification

04h RID R Metal Revision Identification

05h FID R 04h Features Identification (trim)

06h to 0Fh − − − Reserved for future use

10h PROGVSEL1 RW C0h Output voltage settings and EN for VSEL pin = High (trim)

11h PROGVSEL0 RW C0h Output voltage settings and EN for VSEL pin = Low (trim)

12h PGOOD RW 10h Power good and active discharge settings (trim)

13h TIME RW 09h Enabling and DVS timings (trim)

14h COMMAND RW C3h Enabling and Operating mode Command register (trim)

15h − − − Reserved for future use

16h LIMCONF RW E3h Reset and limit configuration register (trim)

17h to 1Fh − − − Reserved for future use

20h to FFh − − − Reserved. Test Registers

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Table 10. I2C REGISTERS MAP CONFIGURATION (NCP6356BW)

Add. Register Name Type Def. Function

00h INT_ACK RC 00h Interrupt register

01h INT_SEN R 00h Sense register (real time status)

02h INT_MSK RW FFh Mask register to enable or disable interrupt sources (trim)

03h PID R 19h Product Identification

04h RID R Metal Revision Identification

05h FID R 05h Features Identification (trim)

06h to 0Fh − − − Reserved for future use

10h PROGVSEL1 RW A0h Output voltage settings and EN for VSEL pin = High (trim)

11h PROGVSEL0 RW 88h Output voltage settings and EN for VSEL pin = Low (trim)

12h PGOOD RW 10h Power good and active discharge settings (trim)

13h TIME RW 09h Enabling and DVS timings (trim)

14h COMMAND RW C3h Enabling and Operating mode Command register (trim)

15h − − − Reserved for future use

16h LIMCONF RW E3h Reset and limit configuration register (trim)

17h to 1Fh − − − Reserved for future use

20h to FFh − − − Reserved. Test Registers

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Registers Description

Table 11. INTERRUPT ACKNOWLEDGE REGISTER

Name: INTACK Address: 00h

Type: RC Default: 00000000b (00h)

Trigger: Dual Edge [D7..D0]

D7 D6 D5 D4 D3 D2 D1 D0

ACK_TSD ACK_TWARN ACK_TPREW Spare = 0 ACK_ISHORT ACK_UVLO ACK_IDCDC ACK_PG

Bit Bit Description

ACK_PG Power Good Sense Acknowledgement

0: Cleared

1: DCDC Power Good Event detected

ACK_IDCDC DCDC Over Current Sense Acknowledgement

0: Cleared

1: DCDC Over Current Event detected

ACK_UVLO Under Voltage Sense Acknowledgement

0: Cleared

1: Under Voltage Event detected

ACK_ISHORT DCDC Short−Circuit Protection Sense Acknowledgement

0: Cleared

1: DCDC Short circuit protection detected

ACK_TPREW Thermal Pre Warning Sense Acknowledgement

0: Cleared

1: Thermal Pre Warning Event detected

ACK_TWARN Thermal Warning Sense Acknowledgement

0: Cleared

1: Thermal Warning Event detected

ACK_TSD Thermal Shutdown Sense Acknowledgement

0: Cleared

1: Thermal Shutdown Event detected

Table 12. INTERRUPT SENSE REGISTER

Name: INTSEN Address: 01h

Type: R Default: 00000000b (00h)

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

SEN_TSD SEN_TWARN SEN_TPREW Spare = 0 SEN_ISHORT SEN_UVLO SEN_IDCDC SEN_PG

Bit Bit Description

SEN_PG Power Good Sense

0: DCDC Output Voltage below target

1: DCDC Output Voltage within nominal range

SEN_IDCDC DCDC over current sense

0: DCDC output current is below limit

1: DCDC output current is over limit

SEN_UVLO Under Voltage Sense

0: Input Voltage higher than UVLO threshold

1: Input Voltage lower than UVLO threshold

SEN_ISHORT DCDC Short−Circuit Protection Sense

0: Short−Circuit detected not detected

1: Short−Circuit not detected

SEN_TPREW Thermal Pre Warning Sense

0: Junction temperature below thermal pre−warning limit

1: Junction temperature over thermal pre−warning limit

SEN _TWARN Thermal Warning Sense

0: Junction temperature below thermal warning limit

1: Junction temperature over thermal warning limit

SEN _TSD Thermal Shutdown Sense

0: Junction temperature below thermal shutdown limit

1: Junction temperature over thermal shutdown limit

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Table 13. INTERRUPT MASK REGISTER

Name: INTMSK Address: 02h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

MSK_TSD MSK_TWARN MSK_TPREW Spare = 1 MSK_ISHORT MSK_UVLO MSK_IDCDC MASK_PG

Bit Bit Description

MSK_PG Power Good interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_IDCDC DCDC over current interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_UVLO Under Voltage interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_ISHORT DCDC Short−Circuit Protection source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_TPREW Thermal Pre Warning interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_TWARN Thermal Warning interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

MSK_TSD Thermal Shutdown interrupt source mask

0: Interrupt is Enabled

1: Interrupt is Masked

Table 14. PRODUCT ID REGISTER

Name: PID Address: 03h

Type: R Default: 00011001b (19h)

Trigger: N/A Reset on N/A

D7 D6 D5 D4 D3 D2 D1 D0

PID_7 PID_6 PID_5 PID_4 PID_3 PID_2 PID_1 PID_0

Table 15. REVISION ID REGISTER

Name: RID Address: 04h

Type: R Default: Metal

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

RID_7 RID_6 RID_5 RID_4 RID_3 RID_2 RID_1 RID_0

Bit Bit Description

RID[7..0] Revision Identification

0000000X: Prototype Silicon

00000010: Production

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Table 16. FEATURE ID REGISTER

Name: FID Address: 05h

Type: R Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

Spare Spare Spare Spare FID_3 FID_2 FID_1 FID_0

Bit Bit Description

FID[3..0] Feature Identification

See Table 4: NCP6356B Configuration

Table 17. DC TO DC VOLTAGE PROG (VSEL = 1) REGISTER

Name: PROGVSEL1 Address: 10h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

ENVSEL1 VoutVSEL1[6..0]

Bit Bit Description

VoutVSEL1[6..0] Sets the DC to DC converter output voltage when VSEL pin = 1 and VSEL pin function is enabled in register

COMMAND.D0, or when VSEL pin function is disabled in register COMMAND.D0

0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)

ENVSEL1 EN Pin Gating for VSEL internal signal = High

0: Disabled

1: Enabled

Table 18. DC TO DC VOLTAGE PROG (VSEL = 0) REGISTER

Name: PROGVSEL0 Address: 11h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

ENVSEL0 VoutVSEL0[6..0]

Bit Bit Description

VoutVSEL0[6..0] Sets the DC to DC converter output voltage when VSEL pin = 0 and VSEL pin function is enabled in register

COMMAND.D0

0000000b = 600 mV – 1111111b = 1393.75 mV (steps of 6.25 mV)

ENVSEL0 EN Pin Gating for VSEL internal signal = Low

0: Disabled

1: Enabled

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Table 19. POWER GOOD REGISTER

Name: PGOOD Address: 12h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

Spare = 0 Spare = 0 Spare = 0 DISCHG TOR[1..0] PGDVS PGDCDC

Bit Bit Description

PGDCDC Power Good Enabling

0 = Disabled

1 = Enabled

PGDVS Power Good Active On DVS

0 = Disabled

1 = Enabled

TOR[1..0] Time out Reset settings for Power Good

00 = 0 ms

01 = 8 ms

10 = 32 ms

11 = 64 ms

DISCHG Active discharge bit Enabling

0 = Discharge path disabled

1 = Discharge path enabled

Table 20. TIMING REGISTER

Name: TIME Address: 13h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

DELAY[2..0] DVS[1..0] Spare = 0 DBN_Time[1..0]

Bit Bit Description

DBN_Time[1..0] EN and VSEL debounce time

00 = No debounce

01 = 1−2 ms

10 = 2−3 ms

11 = 3−4 ms

DVS[1..0] DVS Speed

00 = 6.25 mV step / 0.333 ms

01 = 6.25 mV step / 0.666 ms

10 = 6.25 mV step / 1.333 ms

11 = 6.25 mV step / 2.666 ms

DELAY[2..0] Delay applied upon enabling (ms)

000b = 0 ms − 111b = 14 ms (Steps of 2 ms)

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Table 21. COMMAND REGISTER

Name: COMMAND Address: 14h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

PPWMVSEL0 PPWMVSEL1 DVSMODE Sleep_Mode Spare = 0 Spare = 0 Spare VSELGT

Bit Bit Description

VSELGT VSEL Pin Gating

0 = Disabled

1 = Enabled

Sleep_Mode Sleep mode

0 = Low Iq mode when EN and VSEL low

1 = Force product in sleep mode (when EN and VSEL are low)

DVSMODE DVS transition mode selection

0 = Auto

1 = Forced PPWM

PPWMVSEL1 Operating mode for MODE internal signal = High

0 = Auto

1 = Forced PPWM

PPWMVSEL0 Operating mode for MODE internal signal = Low

0 = Auto

1 = Forced PPWM

Table 22. LIMITS CONFIGURATION REGISTER

Name: LIMCONF Adress: 16h

Type: RW Default: See Register map

Trigger: N/A

D7 D6 D5 D4 D3 D2 D1 D0

IPEAK[1..0] TPWTH[1..0] Spare = 0 FORCERST RSTSTATUS REARM

Bit Bit Description

REARM Rearming of device after TSD / ISHORT

0: No re−arming after TSD / ISHORT

1: Re−arming active after TSD / ISHORT with no reset of I2C registers: new power−up sequence is initiated

with previously programmed I2C registers values

RSTSTATUS Reset Indicator Bit

0: Must be written to 0 after register reset

1: Default (loaded after Registers reset)

FORCERST Force Reset Bit

0: Default value. Self cleared to 0

1: Force reset of internal registers to default

TPWTH[1..0] Thermal pre−Warning threshold settings

00 = 83°C

01 = 94°C

10 = 105°C

11 = 116°C

IPEAK Inductor peak current settings

00 = 5.2 A (for 3.5 A output current)

01 = 5.8 A (for 4.0 A output current)

10 = 6.2 A (for 4.5 A output current)

11 = 6.8 A (for 5.0 A output current)

NCP6356B

www.onsemi.com

APPLICATION INFORMATION

Figure 46. Typical Application Schematic

330 nH

22 uF

Processor

Core

NCP6356B

I@C

Thermal

Protection

Processor I@C

Control Interface

Operating

Mode

Control

Output

Monitoring

Voltage

Selection

Interrupt

Power Fail

DCDC

5.0 A

Supply Input

DCDC

Up to 2 .4 MHz

Controller Sense

Enable Control

Input

4.7 uF

SDA

SCL

AGND

PGND

INTB

PGND

VSEL

Core

PVIN

PGND

D1 AVIN

22uF

Output Filter Considerations

The output filter introduces a double pole in the system at

a frequency of:

fLC +1

2@p@L@C

Ǹ(eq. 1)

The NCP6356B internal compensation network is

optimized for a typical output filter comprising a 330 nH

inductor and 47 mF capacitor as described in the basic

application schematic in Figure 46.

Voltage Sensing Considerations

In order to regulate the power supply rail, the NCP6356B

must sense its output voltage. The IC can support two

sensing methods:

•Normal sensing: The FB pin should be connected to the

output capacitor positive terminal (voltage to regulate).

•Remote sensing: The power supply rail sense should be

made close to the system powered by the NCP6356B.

The voltage to the system is more accurate, since the

PCB line impedance voltage drop is within the

regulation loop. In this case, we recommend connecting

the FB pin to the system decoupling capacitor positive

terminal.

Components Selection

Inductor Selection

The inductance of the inductor is chosen such that the

peak−to−peak ripple current IL_PP is approximately 20% to

50% of the maximum output current IOUT_MAX. This

provides the best trade−off between transient response and

output ripple. The inductance corresponding to a given

current ripple is:

L+ǒVIN *VOUTǓ@VOUT

VIN @fSW @IL_PP

(eq. 2)

The selected inductor must have a saturation current

rating higher than the maximum peak current which is

calculated by:

IL_MAX +IOUT_MAX )

IL_PP

2(eq. 3)

The inductor must also have a high enough current rating

to avoid self−heating. A low DCR is therefore preferred.

Refer to Table 23 for recommended inductors.

NCP6356B

www.onsemi.com

Table 23. INDUCTOR SELECTION

Supplier Part # Value

(mH) Size (mm)

(L x l x T) (mm) Saturation

Current Max (A) DCR Max at 255C

(mW)

Cyntec PIFE20161B−R33MS−11 0.33 2.0 x 1.6 x 1.2 4.0 33

Cyntec PIFE25201B−R33MS−11 0.33 2.5 x 2.0 x 1.2 5.2 17

Cyntec PIFE32251B−R33MS−11 0.33 3.2 x 2.5 x 1.2 6.5 14

TOKO DFE252012F−H−R33M 0.33 2.5 x 2.0 x 1.2 5.1 13

TOKO DFE201612E−H−R33M 0.33 2.0 x 1.6 x 1.2 4.8 21

TOKO FDSD0412−H−R33M 0.33 4.2 x 4.2 x 1.2 7.5 19

TDK VLS252012HBX−R33M 0.33 2.5 x 2.0 x 1.2 5.3 25

TDK SPM5030T−R35M 0.35 7.1 x 6.5 x 3.0 14.9 4

Output Capacitor Selection

The output capacitor selection is determined by output

voltage ripple and load transient response requirement. For

high transient load performance a high output capacitor

value must be used. For a given peak−to−peak ripple current

IL_PP in the inductor of the output filter, the output voltage

ripple across the output capacitor is the sum of three

components as shown below.

VOUT_PP [VOUT_PP(C) )VOUT_PP(ESR) )VOUT_PP(ESL),

(eq. 4)

With:

VOUT_PP(C) +

IL_PP

8@C@fSW ,(eq. 5)

VOUT_PP(ESR) +IL_PP @ESR (eq. 6)

VOUT_PP(ESL) +ESL

ESL )L@VIN (eq. 7)

Where the peak−to−peak ripple current is given by

IL_PP +ǒVIN *VOUTǓ@VOUT

VIN @fSW @L(eq. 8)

In applications with all ceramic output capacitors, the

main ripple component of the output ripple is VOUT_PP(C).

The minimum output capacitance can be calculated based on

a given output ripple requirement VOUT_PP in PPWM

operation mode.

CMIN +

IL_PP

8@VOUT_PP @fSW (eq. 9)

Input Capacitor Selection

One of the input capacitor selection requirements is the

input voltage ripple. To minimize the input voltage ripple

and get better decoupling at the input power supply rail, a

ceramic capacitor is recommended due to low ESR and ESL.

The minimum input capacitance with respect to the input

ripple voltage VIN_PP is

CIN_MIN +

IOUT_MAX @ǒD*D2Ǔ

VIN_PP @fSW (eq. 10)

where

D+VOUT

VIN (eq. 11)

In addition, the input capacitor must be able to absorb the

input current, which has a RMS value of

IIN_RMS +IOUT_MAX @D*D2

Ǹ(eq. 12)

The input capacitor also must be sufficient to protect the

device from over voltage spikes, and a 4.7 mF capacitor or

greater is required. The input capacitor should be located as

close as possible to the IC. All PGND pins must be

connected together to the ground terminal of the input cap

which then must be connected to the ground plane. All PVIN

pins must be connected together to the Vbat terminal of the

input cap which then connects to the Vbat plane.

Power Capability

The NCP6356B’s power capability is driven by the

difference in temperature between the junction (TJ) and

ambient (TA), the junction−to−ambient thermal resistance

(RqJA), and the on−chip power dissipation (PIC).

The on−chip power dissipation PIC can be determined as PIC

= PT − PL with the total power losses PT being

PT+VOUT IOUT ǒ1

h*1Ǔ(eq. 13)

where h is the efficiency and PL the simplified inductor

power losses PL = ILOAD2 x DCR.

Now the junction temperature TJ can easily be calculated

as TJ = RqJA x PIC + TA.

Please note that the TJ should stay within the recommended

operating conditions.

The R qJA is a function of the PCB layout (number of layers

and copper and PCB size). For example, the NCP6356B

mounted on the EVB has a RqJA about 55°C/W.

NCP6356B

www.onsemi.com

Layout Considerations

Electrical Rules

Good electrical layout is key to proper operation, high

efficiency, and noise reduction. Electrical layout guidelines

are:

•Use wide and short traces for power paths (such as

PVIN, VOUT, SW, and PGND) to reduce parasitic

inductance and high−frequency loop area. It is also

good for efficiency improvement.

•The device should be well decoupled by input capacitor

and the input loop area should be as small as possible to

reduce parasitic inductance, input voltage spike, and

noise emission.

•SW track should be wide and short to reduce losses and

noise radiation.

•It is recommended to have separated ground planes for

PGND and AGND and connect the two planes at one

point. Try to avoid overlap of input ground loop and

output ground loop to prevent noise impact on output

regulation.

•Arrange a “quiet” path for output voltage sense, and

make it surrounded by a ground plane.

Thermal Rules

Good PCB layout improves the thermal performance and

thus allows for high power dissipation even with a small IC

package. Thermal layout guidelines are:

•A four or more layers PCB board with solid ground

planes is preferred for better heat dissipation.

•Use multiple vias around the IC to connect the inner

ground layers to reduce thermal impedance.

•Use a large and thick copper area especially in the top

layer for good thermal conduction and radiation.

•Use two layers or more for the high current paths

(PVIN, PGND, SW) in order to split current into

different paths and limit PCB copper self−heating.

Component Placement

•Input capacitor placed as close as possible to the IC.

•PVIN directly connected to Cin input capacitor, and

then connected to the Vin plane. Local mini planes used

on the top layer (green) and the layer just below the top

layer (yellow) with laser vias.

•AVIN connected to the Vin plane just after the capacitor.

•AGND directly connected to the GND plane.

•PGND directly connected to Cin input capacitor, and

then connected to the GND plane: Local mini planes

used on the top layer (green) and the layer just below

the top layer (yellow) with laser vias.

•SW connected to the Lout inductor with local mini

planes used on the top layer (green) and the layer just

below the top layer (yellow) with laser vias.

(See Figures 47 and 48 for examples)

4.2 mm

S < 18.00 mm@

0603

4.7 uF

2.3 x 1.2 mm

0603

22 uF

2.3 x 1.2 mm

PIFE2016B

0.33 uH

2.0x1.6 mm

PVINAVIN

SWSW

PVIN

PGND

INTB

SCL

EN PVINPGND

PGNDSDA

PGND

VSEL

SWSWPGNDFB AGND

4.3 mm

Figure 47. Placement Recommendation

Figure 48. Demo Board Example

Legend:

Green: top layer planes and wires

Yellow: layer1 plane and wires (just below top layer)

Big grey circles: normal vias

Small gray circles: top to layer1 vias

NCP6356B

www.onsemi.com

ORDERING INFORMATION

Device Marking Configuration Package Shipping†

NCP6356BFCCT1G 6356B 5.0 A

1.15 V

WLCSP20 2.02 x 1.62 mm

(Pb–Free) 3000 / Tape & Reel

NCP6356BSFCCT1G 6356BS 4.0 A

0.95 V

NCP6356BSNFCCT1G 6356BN 4.0 A

1.20 V

NCP6356BVFCCT1G 6356BV 5.0 A

1.00 V

NCP6356BWFCCT1G 6356BW 5.0 A

0.80 V

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

Demo Board Available:

The NCP6356BGEVB/D evaluation board that configures the device in typical application to supply constant voltage.

NCP6356B

www.onsemi.com

PACKAGE DIMENSIONS

WLCSP20, 1.62x2.02

CASE 568AG

ISSUE D

SEATING

PLANE

0.10 C

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. COPLANARITY APPLIES TO THE SPHERICAL

CROWNS OF THE SOLDER BALLS.

DIM

AMIN MAX

−−−

MILLIMETERS

D1.62 BSC

b0.24 0.28

e0.40 BSC

0.60

ÈÈ

PIN A1

REFERENCE

A0.05 BC

0.03 C

0.05 C

20X b

0.10 C

0.17 0.23

2.02 BSC

0.25

20X

DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

0.40

0.10 C

2X TOP VIEW

SIDE VIEW

BOTTOM VIEW

NOTE 3

RECOMMENDED

PACKAGE

OUTLINE

123

PITCH

A2 0.33 0.39

e/2

DIE COAT

(OPTIONAL)

DETAIL A

A2A3

DET AIL A

A3 0.02 0.04

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