LT4256-1/LT4256-2
1
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APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U
The LT
®
4256-1/LT4256-2 are high voltage Hot Swap
TM
controllers that allow a board to be safely inserted and
removed from a live backplane. An internal driver drives an
external N-channel MOSFET switch to control supply
voltages ranging from 10.8V to 80V.
The LT4256-1/LT4256-2 features an adjustable analog
foldback current limit. If the supply remains in current limit
for more than a programmable time, the N-channel
MOSFET shuts off and the PWRGD output asserts low. The
LT4256-2 automatically restarts after a time-out delay.
The LT4256-1 latches off until the UV pin is cycled low.
The PWRGD output indicates when the output voltage
rises above a programmed level. An external resistor
string from V
CC
provides programmable undervoltage
protection.
The LT4256 can be used as an upgrade to LT1641 designs.
See Table 1 on page 14 for upgraded specifications.
The LT4256-1 and LT4256-2 are available in an 8-pin SO
package that is pin compatible with the LT1641.
■
Hot Board Insertion
■
Electronic Circuit Breaker/Power Bussing
■
Industrial High Side Switch/Circuit Breaker
■
24V/48V Industrial/Alarm Systems
■
Ideally Suited for 12V, 24V and 48V Distributed
Power Systems
■
48V Telecom Systems
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Allows Safe Board Insertion and Removal from a
Live Backplane
■
Controls Supply Voltage from 10.8V to 80V
■
Foldback Current Limiting
■
Overcurrent Fault Detection
■
Drives an External N-Channel MOSFET
■
Programmable Supply Voltage Power-Up Rate
■
Undervoltage Protection
■
Latch Off Operation Mode (LT4256-1)
■
Automatic Retry (LT4256-2)
■
Available in an 8-Pin SO Package
Positive High Voltage
Hot Swap Controllers
Hot Swap is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
4256 TA01
0.02Ω
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
VCC
GATE
FB
PWRGD
UV
TIMER GND
VIN
48V
GND
(SHORT PIN)
IRF530
CMPZ5241B
11V
8.06k
64.9k
100Ω
4.02k
10Ω36.5k
PWRGD
VOUT
48V
2A
27k
CL
33nF
0.1µF
10nF
SMAT70A
UV = 36V
PWRGD = 40V
48V, 2A Hot Swap Controller
PWRGD
50V/DIV
V
OUT
50V/DIV
INRUSH
CURRENT
500mA/DIV
V
IN
50V/DIV
2.5ms/DIV 4256 TA02
LT4256 Start-Up Behavior
C
L
= 225µF
LT4256-1/LT4256-2
2
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Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
(Note 1)
Supply Voltage (V
CC
) ................................ –0.3 to 100V
SENSE, PWRGD ....................................... – 0.3 to 100V
GATE (Note 2) ................................ –0.3V to V
CC
+ 10V
Maximum Input Current (GATE) ......................... 200µA
FB, UV ........................................................ – 0.3 to 44V
TIMER ..................................................... –0.3V to 4.3V
Maximum Input Current (TIMER) ....................... 100µA
Operating Temperature
LT4256C ................................................. 0°C to 70°C
LT4256I ............................................. –40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
ABSOLUTE AXI U RATI GS
W
WW
U
Consult LTC Marketing for parts specified with wider operating temperature ranges.
PACKAGE/ORDER I FOR ATIO
UUW
ORDER PART
NUMBER
S8 PART MARKING
42561
42561I
42562
42562I
LT4256-1CS8
LT4256-1IS8
LT4256-2CS8
LT4256-2IS8
T
JMAX
= 125°C, θ
JA
= 110°C/W
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Operating Voltage ●10.8 80 V
I
CC
Operating Current 1.8 3.9 mA
V
UVLH
Undervoltage Threshold V
CC
Low-to-High Transition ●3.96 4 4.04 V
V
UVHYS
Hysteresis 0.25 0.4 0.55 V
I
INUV
UV Input Current UV ≥ 1.2V –0.1 –1 µA
UV = 0V –1.5 –3 µA
V
UVRTH
Fault Latch Reset Threshold Voltage ●0.4 0.85 1.2 V
V
SENSETRIP
SENSE Pin Trip Voltage (V
CC
– V
SENSE
) FB = 0V ●5.5 14 22 mV
FB ≥ 2V ●45 55 65 mV
I
INSNS
SENSE Pin Input Current V
SENSE
= V
CC
40 70 µA
I
PU
GATE Pull-Up Current Charge Pump On, ∆V
GATE
= 7V ●–16 –32 –63 µA
I
PD
GATE Pull-Down Current Any Fault, V
GATE
= 3V 40 62 80 mA
∆V
GATE
External N-Channel Gate Drive (Note 2) V
GATE
– V
CC
, 10.8V ≤ V
CC
≤ 20V ●4.5 8.8 12.5 V
20V ≤ V
CC
≤ 80V ●10 11.6 12.8 V
V
FB
FB Voltage Threshold FB High-to-Low Transition ●3.95 3.99 4.03 V
FB Low-to-High Transition ●4.2 4.45 4.65 V
V
FBHYS
FB Hysteresis Voltage 0.3 0.45 0.6 V
V
OLPGD
PWRGD Output Low Voltage I
O
= 1.6mA 0.25 0.4 V
I
O
= 5mA 0.6 1 V
I
PWRGD
PWRGD Pin Leakage Current V
PWRGD
= 80V 0.1 1 µA
I
INFB
FB Input Current FB = 4.5V –0.1 –1 µA
I
TIMERPU
TIMER Pull-Up Current TIMER = 3V, During Fault ●– 63 – 105 –147 µA
I
TIMERPD
TIMER Pull-Down Current TIMER = 3V ●1.5 3 5 µA
V
THTIMER
TIMER Shut-Down Threshold C
TIMER
= 10nF ●4.3 4.65 5 V
D
TIMER
Duty Cycle (RETRY Mode) ●1.5 3 4.5 %
1
2
3
4
8
7
6
5
TOP VIEW
V
CC
SENSE
GATE
TIMER
UV
FB
PWRGD
GND
S8 PACKAGE
8-LEAD PLASTIC SO
LT4256-1/LT4256-2
3
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t
PHLUV
UV Low to GATE Low 1.7 3 µs
t
PLHUV
UV High to GATE High C
GATE
= 0 6 9 µs
t
PHLFB
FB Low to PWRGD Low 0.8 2 µs
t
PLHFB
FB High to PWRGD High 3.2 5 µs
t
PHLSENSE
(V
CC
– V
SENSE
) High to GATE Low V
CC
– V
SENSE
= 275mV 1 3 µs
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 48V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: An internal clamp limits the GATE pin to a minimum of 10V above
V
CC
. Driving this pin to a voltage beyond the clamp voltage may damage
the part.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ICC vs Temperature
PWRGD Thresholds
vs Temperature
PWRGD Output Voltage
vs IPWRGD
ICC vs VCC
UV Thresholds vs Temperature
SENSE Pin Regulation Voltage
vs Temperature
TEMPERATURE (°C)
–50
3.5
3.6
UV THRESHOLDS (V)
3.7
3.8
3.9
4.1
–25 02550
4256 G01
75 100
4.0
H-L THRESHOLD
L-H THRESHOLD
TEMPERATURE (°C)
10
SENSE PIN REGULATION VOLTAGE (mV)
15
20
48
58
4256 G02
53
FB = 0V
FB > 2V
–50 –25 0 255075100
V
CC
(V)
10
2.0
2.5
3.5
40 60
4256 G03
1.5
1.0
20 30 50 70 80
0.5
0
3.0
I
CC
(mA)
TEMPERATURE (°C)
0
ICC (mA)
0.5
1.0
1.5
2.5
4256 G04
2.0
VCC = 48V
–50 –25 0 255075100
TEMPERATURE (°C)
3.9
4.0
PWRGD THRESHOLDS (V)
4.1
4.2
4.3
4.5
4256 G05
4.4
H-L THRESHOLD
L-H THRESHOLD
–50 –25 0 255075100
IPWRGD (mA)
0
0
VPWRGD (V)
1
2
3
4
6
2468
4256 G06
10 12
5
Specifications are at TA = 25°C unless
otherwise noted.
LT4256-1/LT4256-2
4
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
GATE Pin Pull-Up Current
vs Temperature
GATE Pin Pull-Down Current
vs Temperature UV Pin Current vs UV Pin Voltage
VGATE – VCC Voltage
vs Temperature
TIMER Pin Currents
vs Temperature
VGATE – VCC Voltage
vs Temperature
TIMER Pin Currents vs VCC
Timer Shutdown Threshold
vs Temperature
TEMPERATURE (°C)
–40
GATE PIN PULL-UP CURRENT (µA)
–35
–30
–20
0
4256 G07
–10
–25
–5
–15
–50 –25 0 255075100
TEMPERATURE (°C)
56
GATE PIN PULL-DOWN CURRENT (mA)
57
58
60
63
4256 G08
62
59
61
–50 –25 0 255075100
VUV (V)
0
–1.4
IUV (µA)
–1.2
–0.8
–0.6
–0.4
20 30 40
0.4
4256 G09
–1.0
12 4350
–0.2
0
0.2
TEMPERATURE (°C)
0
VGATE – VCC VOLTAGE (V)
6
8
4
2
14
12
4256 G10
10
VCC = 10.8V
VCC = 12V
VCC = 18V
–50 –25 0 25 50 75 100
TEMPERATURE (°C)
10.0
VGATE – VCC VOLTAGE (V)
10.5
11.0
12.0
14.0
4256 G11
13.0
13.5
11.5
12.5
VCC = 80V VCC = 48V
VCC = 20V
–50 –25 0 25 50 75 100
V
CC
(V)
10
I
TIMER
(µA)
0
2.5
5.0
40 60
4256 G13
–80
–100
20 30 50 70 80
–120
–140
PULL-UP CURRENT
PULL-DOWN CURRENT
TEMPERATURE (°C)
0
TIMER SHUTDOWN THRESHOLD (V)
4.2
4.4
4.8
5.4
4256 G14
5.2
4.6
5.0
–50 –25 0 25 50 75 100
Specifications are at TA = 25°C unless
otherwise noted.
TEMPERATURE (°C)
–50
–140
ITIMER (µA)
–120
–100
–80
0
10
–25 02550
4256 G12
75 100
5PULL-DOWN CURRENT
PULL-UP CURRENT
LT4256-1/LT4256-2
5
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TYPICAL PERFOR A CE CHARACTERISTICS
UW
FB Pin Current vs FB Pin Voltage
Gate Pull-Down Capability vs VCC
Below Minimum Operating Voltage
V
FB
(V)
0
–0.4
I
FB
(µA)
–0.3
–0.2
–0.1
0
0.1
0.2
10 20 30 40
4256 G15
50
VCC (V)
0
0
IGATE (mA )
10
20
30
40
60
2468
4256 G16
10 12
50
Specifications are at TA = 25°C unless
otherwise noted.
LT4256-1/LT4256-2
6
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PI FU CTIO S
UUU
UV (Pin 1): Undervoltage Sense. UV is an input that
enables the output voltage. When UV is driven above 4V,
GATE will start charging and the output turns on. When
UV goes below 3.6V, GATE discharges and the output
shuts off.
Pulsing UV low for a minimum of 5µs after a current limit
fault cycle resets the fault latch (LT4256-1) and allows the
part to turn back on. This command is only accepted after
TIMER has discharged below 0.65V. To disable UV sens-
ing, connect UV to a voltage beween 5V and 44V.
FB (Pin 2): Power Good Comparator Input. FB monitors
the output voltage through an external resistive divider.
When the voltage on FB is lower than the high-to-low
threshold of 3.99V, PWRGD is pulled low and released
when FB is pulled above the 4.45V low-to-high threshold.
The voltage present on FB affects foldback current limit
(see Figure 7 and related discussion).
PWRGD (Pin 3): Power Good Output. PWRGD is pulled
low whenever the voltage on FB falls below the 3.99V high-
to-low threshold voltage. It goes into a high impedance
state when the voltage on FB exceeds the low-to-high
threshold voltage. An external pull-up resistor can pull
PWRGD to a voltage higher or lower than V
CC
.
GND (Pin 4): Device Ground. This pin must be tied to a
ground plane for best performance.
TIMER (Pin 5): Timing Input. An external timing capacitor
from TIMER to GND programs the maximum time the part
is allowed to remain in current limit. When the part goes
into current limit, a 105µA pull-up current source starts to
charge the timing capacitor. When the voltage on TIMER
reaches 4.65V (typ), GATE pulls low; the TIMER pull-up
current will be turned off and the capacitor is discharged
by a 3µA pull-down current. When TIMER falls below 0.65V
(typ), GATE turns on again for the LT4256-2. UV must be
cycled low after TIMER has discharged below 0.65V (typ)
to reset the LT4256-1. If UV is not cycled low (LT4256-1),
GATE remains latched off and TIMER is discharged to near
GND. Under an output short-circuit condition, the
LT4256-2 cycles on and off with a 3% duty cycle.
GATE (Pin 6): High Side Gate Drive for the External N-
Channel MOSFET. An internal charge pump guarantees at
least 10V of gate drive for V
CC
supply voltages above 20V
and 4.5V of gate drive for V
CC
supply voltages between
10.8V and 20V. The rising slope of the voltage on GATE is
set by an external capacitor connected from GATE to GND
and an internal 32µA pull-up current source from the
charge pump output.
If the current limit is reached, the GATE voltage is adjusted
to maintain a constant voltage across the sense resistor
while the timing capacitor starts to charge. If the TIMER
voltage ever exceeds 4.65V, GATE is pulled low.
GATE is also pulled to GND whenever UV is pulled low, the
V
CC
supply voltage drops below the externally programmed
undervoltage threshold, or V
CC
drops below the internal
UVLO threshold (9.8V).
GATE is clamped internally to a maximum voltage of 11.6V
(typ) above V
CC
under normal operating conditions. Driv-
ing this pin beyond the clamp voltage may damage the
part. A Zener diode is needed between the gate and source
of the external MOSFET to protect its gate oxide under
instantaneous short-circuit conditions. See Applications
Information.
SENSE (Pin 7): Current Limit Sense Input. A sense
resistor is placed in the supply path between VCC and
SENSE. The current limit circuit regulates the voltage
across the sense resistor (VCC – SENSE) to 55mV while in
current limit when FB is 2V or higher. If FB drops below
2V, the regulated voltage across the sense resistor de-
creases linearly to 14mV when FB is 0V.
To defeat current limit, connect SENSE to V
CC
.
V
CC
(Pin 8): Input Supply Voltage. The positive supply
input ranges from 10.8V to 80V for normal operation.
I
CC
is typically 1.8mA. An internal circuit disables the
LT4256-1/LT4256-2 for inputs less than 9.8V (typ).
LT4256-1/LT4256-2
7
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BLOCK DIAGRA
W
+
–
–
+
–
+
108µA
V
P
V
P
LOGIC
2V
14mV ~ 55mV
9.8V 4V
V
CC
INTERNAL
UV
TIMER LOW
TIMER HIGH
GND
0.65V
4.65V
–
+
–
+
3.99V3.99V
PWRGD
TIMER
4256 BD
V
CC
SENSE
V
P
GEN
FB
3µA
UV
GATE
+
–
+
–
CHARGE
PUMP
AND
GATE
DRIVER
REF GEN
8 7
6
3
5
4
CURRENT
LIMIT
FOLDBACK
2
1
UV
LT4256-1/LT4256-2
8
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TEST CIRCUIT
TI I G DIAGRA S
WUW
Figure 2. UV to GATE Timing Figure 3. VOUT to PWRGD Timing
Figure 4. SENSE to GATE Timing
Figure 1
VCC
GATE
SENSE
TIMER
PWRGD
FB
UV
48V
48k
GND
4256 F01
100pF
+–
UV
4256 F02
GATE V
OUT
+2V
t
PLHUV
4V
V
OUT
+2V
t
PHLUV
3.6V
V
CC
– SENSE
4256 F04
GATE
V
CC
t
PHLSENSE
55mV
APPLICATIO S I FOR ATIO
WUUU
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors on the boards draw high peak
currents from the backplane power bus as they charge.
The transient currents can permanently damage the con-
nector pins and glitch the system supply, causing other
boards in the system to reset.
The LT4256-1/LT4256-2 are designed to turn on a board’s
supply voltage in a controlled manner, allowing the board
to be safely inserted or removed from a live backplane. The
device also provides undervoltage as well as overcurrent
protection while a power good output signal indicates
when the output supply voltage is ready with a high output.
Power-Up Sequence
An external N-channel MOSFET pass transistor (Q1) is
placed in the power path to control the power up of the
supply voltage (Figure 5). Resistor R5 provides current
detection and capacitor C1 controls the GATE slew rate.
Resistor R7 compensates the current control loop while
R6 prevents high frequency oscillations in Q1.
FB
4256 F03
PWRGD 1V
tPLHFB
4.45V
1V
tPHLFB
3.99V
LT4256-1/LT4256-2
9
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APPLICATIO S I FOR ATIO
WUUU
Figure 5. 1600mA, 48V Application
Figure 6. Start-Up Waveforms
When the power pins first make contact, transistor Q1 is
held off. If the voltage on V
CC
is above the externally
programmed undervoltage threshold, V
CC
is above 9.8V,
and the voltage on TIMER is less than 4.65V (typ), transis-
tor Q1 will be turned on (Figure 6). The voltage on GATE
rises with a slope equal to 32µA/C1 and the supply inrush
current is set at:
I
INRUSH
= C
L
• 32µA/C1 (1)
where C
L
is the total load capacitance.
To reduce inrush current, increase C1 or decrease load
capacitance. If the voltage across the current sense resis-
tor R5 reaches V
SENSETRIP
, the inrush current will be
limited by the internal current limit circuitry. The voltage
on GATE is adjusted to maintain a constant voltage across
the sense resistor and TIMER begins to charge.
When the FB voltage goes above the low-to-high V
FB
threshold, PWRGD goes high.
Undervoltage Detection
The LT4256-1/LT4256-2 uses UV to monitor the V
CC
voltage to determine when it is safe to turn on the load and
allow the user the greatest flexibility for setting the thresh-
old. Any time that UV goes below 3.6V, GATE will be pulled
low until UV goes above 4V again.
The UV threshold should never be set below the internal
UVLO threshold (9.8V typically) because the benefit of
UV’s hysteresis will be lost, making the LT4256-1/
4256 F05
R5
0.025Ω
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER GND
V
IN
48V
GND
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10Ω
R8
36.5k
PWRGD
V
OUT
48V
1.6A
R4
27k
C
L
C2
33nF
C3
0.1µFC1
10nF
D2
SMAT70A
UV = 36V
PWRGD = 40V
+
LT4256-2 more susceptible to noise (V
CC
must be at least
9.8V when UV is at its 3.6V threshold). UV is filtered with
C3 to prevent noise spikes and capacitively coupled glitches
from shutting down the LT4256-1/LT4256-2 output
erroneously.
To calculate the UV threshold, use the following equations:
RRV
V
kRR k
VR
R
THUVLH
THUVLH
12 41
20 1 2 200
36 1 1
2
=−
⎛
⎝
⎜⎞
⎠
⎟
Ω≤ +≤Ω
=+
⎛
⎝
⎜⎞
⎠
⎟
(2)
(3)
(4).
where V
THUVLH
is the desired UV threshold voltage when
V
CC
is rising (L-H), etc.
I
OUT
500mA/DIV
V
OUT
50V/DIV
5ms/DIV
4256 F06
PWRGD
50V/DIV
GATE
50V/DIV C
L
= 125µF
LT4256-1/LT4256-2
10
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APPLICATIO S I FOR ATIO
WUUU
Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 8. Response Time to Overcurrent
Figure 11 shows how the LT4256-1/LT4256-2 are com-
manded to shut off with a logic signal. This is accom-
plished by pulling the gate of the open-drain MOSFET, Q2,
(tied to the UV pin) high.
Short-Circuit Protection
The LT4256-1/LT4256-2 features a programmable foldback
current limit with an electronic circuit breaker that protects
against short circuits or excessive load currents. The
current limit is set by placing a sense resistor (R5)
between V
CC
and SENSE. The current limit threshold is
calculated as:
I
LIMIT
= 55mV/R5 (5)
where R5 is the sense resistor.
To limit excessive power dissipation in the pass transistor
and to reduce voltage spikes on the input supply during
short-circuit conditions at the output, the current folds
back as a function of the output voltage, which is sensed
internally on FB.
If the LT4256-1/LT4256-2 go into current limit when the
voltage on FB is 0V, the current limit circuit drives the
GATE pin to force a constant 14mV drop across the sense
resistor. As the output at FB increases, the voltage across
the sense resistor increases until the FB pin reaches 2V, at
which point the voltage across the sense resistor is held
constant at 55mV (see Figure 7).
For a 0.025Ω sense resistor, the current limit is set at
2200mA and folds back to 560mA when the output is
shorted to ground. Thus, MOSFET peak power dissipation
under short-circuit conditions is reduced from 105.6W to
26.5W. See the Layout Considerations section for impor-
tant information about board layout to minimize current
limit threshold error.
The LT4256-1/LT4256-2 also features a variable
overcurrent response time. The time required for the part
to regulate the GATE voltage is a function of the voltage
across the sense resistor connected between V
CC
and
SENSE. This helps to eliminate sensitivity to current
spikes and transients that might otherwise unnecessarily
trigger a current limit response and increase MOSFET
dissipation. Figure 8 shows the response time as a func-
tion of the overdrive at SENSE.
TIMER
TIMER provides a method for programming the maximum
time the part is allowed to operate in current limit. When
the current limit circuitry is not active, the TIMER pin is
pulled to GND by a 3µA current source. When the current
limit circuitry becomes active, a 108µA pull-up current
source is connected to TIMER and the voltage will rise with
a slope equal to 105µA/C
TIMER
as long as the circuitry
stays active. Once the desired maximum current limit time
is known, the capacitor value is:
C nF t ms C A
Vt[] •[ ]; .•==
µ
25 105
465 (6)
14mV
0V 2V FB
4256 F07
55mV
V
CC
– V
SENSE
50 100 150 200 4256 F08
12
10
8
6
4
2
RESPONSE TIME (µs)
V
CC
– V
SENSE
(mV)
0
LT4256-1/LT4256-2
11
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When the TIMER pin reaches 4.65V (typ), the internal fault
latch is set causing GATE to be pulled low and TIMER to be
discharged to GND by the 3µA current source. The part is
not allowed to turn on again until the voltage on TIMER
falls below 0.65V (typ).
TIMER must never be pulled high by a low impedance
because whenever TIMER rises above the upper threshold
(typically 4.65V) the pin characteristics change from a
high impedance current source to a low impedance.
Whenever GATE is commanded off by any fault condition,
it is discharged rapidly, turning off the external MOSFET.
The waveform in Figure 9 shows how the output latches off
following a current fault (LT4256-1). The drop across the
sense resistor is held at 55mV as the timer ramps up. Once
TIMER reaches its shutdown threshold (4.65V typically),
the circuit latches off.
The LT4256-1 latches off after a current limit fault. After
the LT4256-1 latches off, the part may be commanded to
start back up. This is accomplished by cycling UV to
ground and then back high (this command can only be
accepted after TIMER discharges back below the 0.65V
typical threshold, to prevent overheating transistor Q1).
Automatic Restart
The LT4256-2 will automatically restart after an overcurrent
fault. These waveforms are shown in Figure 10.
The LT4256-2 functionality is as follows: When an
overcurrent condition occurs, the GATE pin is servoed to
maintain a constant voltage across the sense resistor, and
the capacitor C2 at the TIMER pin will begin to charge.
When the voltage at the TIMER pin reaches 4.65V (typ),
the GATE pin is pulled low. When the voltage at the TIMER
pin ramps back down to 0.65V (typ), the LT4256-2 turns
on again. If the short-circuit condition at the output still
exists, the cycle will repeat itself indefinitely. The duty
cycle under short-circuit conditions is 3% which prevents
Q1 from overheating.
Figure 9. LT4256-1 Current Limit Waveforms Figure 10. LT4256-2 Current Limit Waveforms
10ms/DIV
4256 F09
IOUT
500mA/DIV
VOUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
I
OUT
500mA/DIV
V
OUT
50V/DIV
TIMER
5V/DIV
GATE
50V/DIV
10ms/DIV
4256 F10
LT4256-1/LT4256-2
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Figure 12. Active Low Enable PWRGD Application
4256 F11
R5
100mΩ
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
VCC
GATE
FB
PWRGD
UV
TIMER GND
VIN
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R6
10Ω
VOUT
VLOGIC
R4
27k
R8
36.5k
CL
R10
27k
C2
33nF
C3
0.1µFC1
10nF
R9
4.02k
Q2
2N3904
PWRGD
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Power Good Detection
The LT4256-1/LT4256-2 includes a comparator for moni-
toring the output voltage. The output voltage is sensed
through the FB pin via an external resistor string. The
comparator’s output (PWRGD) is an open collector ca-
pable of operating from a pull-up as high as 80V.
PWRGD can be used to directly enable/disable a power
module with an active high enable input. Figure 12 shows
how to use PWRGD to control an active low enable input
power module. Signal inversion is accomplished by tran-
sistor Q2 and R10.
4256 F07
R5
0.010Ω
LT4256-1/
LT4256-2
SENSE
6
3
4
78
1
5
V
CC
GATE
FB 2
PWRGD
UV
TIMER GND
V
IN
48V
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
Q2
VN2222
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
V
OUT
48V
4A
R4
51k
C
L
C2
33nF
C3
0.01µF
OFF SIGNAL
FROM MPU
C1
10nF
GND
D2
SMAT70A
UV = 36V
PWRGD = 40V
Figure 11. How to Use a Logic Signal to Control LT4256 Turn-On/-Off
The thresholds for the FB pin are 4.45V (low to high) and
3.99V (high to low). To calculate the PWRGD thresholds,
use the following equations:
RV
kRR k
V
8= V• R9, high to low (7)
(8a)
= 4.45V 1+ R8
R9 , low to high (8b)
THPWRGD
THPWRGD
399 1
20 8 9 200
.–
⎛
⎝
⎜⎞
⎠
⎟
Ω≤ +≤Ω
⎛
⎝
⎜⎞
⎠
⎟
LT4256-1/LT4256-2
13
425612fa
Figure 13. ∆VGATE vs VCC
Supply Transient Protection
The LT4256-1/LT4256-2 is 100% tested and guaranteed
to be safe from damage with supply voltages up to 80V.
However, voltage transients above 100V may cause per-
manent damage. During a short-circuit condition, the
large change in currents flowing through the power supply
traces can cause inductive voltage transients which could
exceed 100V. To minimize the voltage transients, the
power trace parasitic inductance should be minimized by
using wider traces or heavier trace plating and a 0.1µF
bypass capacitor should be placed between V
CC
and GND.
A surge suppressor, as shown in the application diagrams,
(Transzorb) at the input can also prevent damage from
voltage transients.
GATE Pin
A curve of gate drive vs V
CC
is shown in Figure 13. GATE
is clamped to a maximum voltage of 12.8V above V
CC
. This
clamp is designed to sink the internal charge pump cur-
rent. An external Zener diode must be used as shown in all
applications. At a minimum input supply voltage of 12V,
the minimum gate drive voltage is 4.5V. When the input
supply voltage is higher than 20V, the gate drive voltage is
at least 10V and a standard threshold MOSFET can be
used. In applications from 12V to 15V range, a logic level
MOSFET must be used.
In some applications it may be possible for the V
OUT
pin to
ring below ground (due to the parasitic trace inductance).
V
CC
(V)
10
∆V
GATE
(V)
8
9
10
4256 F13
7
6
520 30 70605040 80
12
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Higher current applications, especially where the output
load is physically far away from the LT4256-1/LT4256-2
will be more susceptible to these transients. This is normal
and the LT4256-1/LT4256-2 have been designed to allow
for some ringing below ground. However, if the applica-
tion is such that V
OUT
can ring more than 10V below
ground, damage may occur to the LT4256-1 and an
external diode from ground (anode) to V
OUT
(cathode)
must be added to the circuit as shown in Figure 14 (it is
critical that the reverse breakdown voltage of the diode be
higher than the highest expected V
CC
voltage). A capacitor
placed from ground to V
OUT
directly at the LT4256-1/
LT4256-2 can help reduce the amount of ringing on V
OUT
but it may not be enough for some applications.
During a fault condition, the LT4256-1/LT4256-2 pulls
down on GATE with a switch capable of sinking about
60mA. Once GATE drops below the output voltage by a
diode forward voltage, the external Zener will forward bias
and V
OUT
will also be discharged to GND. In addition to the
GATE capacitance, the output capacitance will be dis-
charged through the LT4256-1/LT4256-2.
In applications utilizing very large external N-channel
MOSFETs, the possibility exists for the MOSFET to turn on
when initially inserted into a live backplane (before the
LT4256-1/LT4256-2 becomes active and pulls down on
GATE). This is due to the drain to gate capacitance forcing
current into R7 and C1 when the drain voltage steps up
from ground to V
IN
with an extremely fast rise time. To
alleviate this situation, a diode, D3, should be put
across R7 with the cathode connected to C1 as shown in
Figure 15.
LT4256-1/LT4256-2
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Figure 14. Negative Output Voltage Protection Diode Application
4256 F14
R5
0.033Ω
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER GND
V
IN
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
V
OUT
R4
27k
C
L
100µF
C2
33nF
C3
0.1µFC1
10nF
GND
D2
SMAT70A
D3
MRA4003T3
UV = 36V
PWRGD = 40V
Notes on Using the LT4256 in LT1641 Applications
Even though the LT4256 and LT1641 have the same
pinout, several changes were made to improve overall
system accuracy and increase noise immunity. These
changes are spelled out in Table 1 and must be accounted
for if using the LT4256 in an LT1641 application.
Layout Considerations
To achieve accurate current sensing, a Kelvin connection
to the current sense resistor (R5 in typical application
circuit) is recommended. The minimum trace width for
1oz copper foil is 0.02" per amp to make sure the trace
stays at a reasonable temperature. 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530µΩ/❏. Small resistances can
cause large errors in high current applications. Noise
immunity will be improved significantly by locating resis-
tor dividers close to the pins with short V
CC
and GND
traces. A 0.1µF decoupling capacitor from UV to GND is
also required.
Table 1. Differences Between LT1641 and LT4256
SPECIFICATION LT1641 LT4256 COMMENTS
UV Threshold 1.313V 4V Higher 1% Reference for Better Noise Immunity and System Accuracy
FB Threshold 1.233V 3.99V Higher 1% Reference for Better Noise Immunity and System Accuracy
TIMER Current ±70% ±40% More Accurate TIMEOUT
TIMER Shutdown V 1.233V 4.65V Higher Trip Voltage for Better Noise Immunity
GATE I
PU
10µA30µA Higher Current to Accommodate Higher Leakage MOSFETs or Parallel Devices
GATE Resistor 1kΩ100ΩDifferent Compensation for Current Limit Loop
Foldback I
LIM
12mV 14mV Slightly Different Current Limit Trip Point
I
LIM
Threshold 47mV 55mV Slightly Different Current Limit Trip Point
Fault Latch Reset 1.233V 0.85V Better Noise Immunity
Threshold Voltage
LT4256-1/LT4256-2
15
425612fa
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
.016 – .050
(0.406 – 1.270)
.010 – .020
(0.254 – 0.508)× 45°
0°– 8° TYP
.008 – .010
(0.203 – 0.254)
SO8 0303
.053 – .069
(1.346 – 1.752)
.014 – .019
(0.355 – 0.483)
TYP
.004 – .010
(0.101 – 0.254)
.050
(1.270)
BSC
1234
.150 – .157
(3.810 – 3.988)
NOTE 3
8765
.189 – .197
(4.801 – 5.004)
NOTE 3
.228 – .244
(5.791 – 6.197)
.245
MIN .160 ±.005
RECOMMENDED SOLDER PAD LAYOUT
.045 ±.005
.050 BSC
.030 ±.005
TYP
INCHES
(MILLIMETERS)
NOTE:
1. DIMENSIONS IN
2. DRAWING NOT TO SCALE
3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LT4256-1/LT4256-2
16
425612fa
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
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© LINEAR TECHNOLOGY CORPORATION 2004
LT/LWI/LT 0705 REV A • PRINTED IN USA
APPLICATIO S I FOR ATIO
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Figure 15. High dV/dT MOSFET Turn-On Protection Circuit
4256 TA03
R5
0.033Ω
LT4256-1/
LT4256-2
SENSE
6
2
3
4
87
1
5
V
CC
GATE
FB
PWRGD
UV
TIMER GND
V
IN
(SHORT PIN)
Q1
IRF530
D1
CMPZ5241B
11V
R2
8.06k
R1
64.9k
R7
100Ω
R9
4.02k
R6
10ΩR8
36.5k
V
OUT
R4
27k
C
L
100µF
C2
33nF
C3
0.1µF
C1
10nF
GND
D2
SMAT70A
D3
1N4148W
UV = 36V
PWRGD = 40V
