AL5DS9xx9V Data Sheets 3.3V Synchronous Dual-Port SRAM AL5DS9349V/59V/69V/79V/89V 4K/8K/16K/32K/64K x 18 AL5DS9269V/79V/89V 16K/32K/64K x 16 AL5DS9149V/59V/69V/79V/89V/99V 4K/8K/16K/32K/64K/128K x 9 AL5DS9069V/79V/89V/99V 16K/32K/64K/128K x 8 Preliminary AL5DS9xx9V Amendments (Since January 4, 2002) 02.01.04 Preliminary version 0.1 02.01.10 Preliminary version 0.2: (1) Modifies truth table and note descriptions in paragraph 7 (2) Modifies Absolute Maximum Ratings in paragraph 8.1 (3) Modifies CIN and COUT DC characteristics in paragraph 8.3 (4) Modifies Bank Select Pipelined Read and Counter Rest in Pipelined Mode timing diagrams Preliminary version 0.3: (1) Modifies features in paragraph 2 (2) Modifies ordering information in paragraph 4.1 (3) Modifies AC characteristics in paragraph 8.5 Preliminary version 0.4: (1) Modifies marking information in paragraphs 4 and 6 (2) Modifies the font type in paragraphs 6 and 9 02.04.09 02.05.07 THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 2 AL5DS9xx9V AL5DS9XX9V 3.3V Synchronous Dual-Port SRAM Contents: 1 General Description ...............................................................................................4 2 Features ..................................................................................................................4 3 Applications ............................................................................................................5 4 Chip Information....................................................................................................5 4.1 Marking Information.............................................................................................................5 4.2 Ordering Information............................................................................................................5 5 Function Block Diagram .......................................................................................7 6 Pin-out Diagram.....................................................................................................8 7 Pin Definition and Description............................................................................14 8 Electrical Characteristics.....................................................................................16 8.1 Absolute Maximum Ratings................................................................................................16 8.2 Recommended Operating Conditions ................................................................................16 8.3 DC Characteristics ...............................................................................................................16 8.4 AC Test Loads ......................................................................................................................17 8.5 AC Characteristics ...............................................................................................................18 9 Timing Diagrams .................................................................................................20 10 Mechanical Drawing............................................................................................26 (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 3 AL5DS9xx9V 1 General Description A Dual-port RAM is a static RAM with a dual-ported cell. There are separate address, data and control signals for each port to access a common SRAM array. A dual-port RAM is generally classified with FIFOs as a "specialty" memory. They are most used in communications that include the exchange of data between processors, processes, and systems. Each port contains an internal counter for fast memory access applications. The initial address of internal counter is loaded with the port's Address Strobe (/ADS). Also provided the Counter Enable (/CNTEN) to increment the internal counter on each Low to High transition of that port's clock signal. The counter can address the entire memory array and will loop back to start (address 0). The internal counter will be reset to zero while asserting Counter Reset (/CNTRST). The AL5DS9xx9V series are high speed 3.3V synchronous CMOS dual-ported SRAM. The AL5DS9349V/59V/69V/79V/89V are configured as 4K/8K/16K/32K/64K x 18-bit, AL5DS9269V/79V/89V as 16K/32K/64K x 16-bit, AL5DS9149V/59V/69V/79V/89V/99V as 4K/8K/16K/32K/64K/128K x 9-bit, and AL5DS9069V/79V/89V/99V as 16K/32K/64K/128 x 8-bit. All these parts support both Pipelined and Flow-Through modes that are selected via the Pipe/FT pin. In the Pipelined mode, there are required two cycles to reactivate the data outputs. The AL5DS9xx9V series feature dual Chip Enables that allow simple depth and width expansion without external control logic. All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages. AL5DS9269V/79V/89V and AL5DS9379V/89V are also available in 128-pin TQFP packages. 2 Features z True dual ported memory cells z 18 Flow-Through/Pipelined devices: -- 4K/8K/16K/32K/64K x 18-bit organization (AL5DS9349V/59V/69V/79V/89V) -- 16K/32K/64K x 16-bit organization (AL5DS9269V/79V/89V) -- 4K/8K/16K/32K/64K/128K x 9-bit organization (AL5DS9149V/59V/69V/79V/89V/99V) -- 16K/32K/64K/128K x 8-bit organization (AL5DS9069V/79V/89V/99V) z Supports byte write/read for 16/18 bit devices z Separate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices) z 3 modes supported: -Pipelined -Flow-Through -Burst z Counter enable and reset z Fast 100-MHz operation on both ports in Pipelined output mode z Supports depth and width expansion z 0.25-micron CMOS for optimum speed/power z High speed clock to data access z 3.3V low operating power z Pin-compatible and functionally equivalent to IDT or Cypress z Available in 100 or 128 pin TQFP (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 4 AL5DS9xx9V 3 Applications z z z z z z z z z z z z z z Cellular Base Stations Cellular Phones Multi-protocol Routers LAN/WAN Switches PBXs RAIDs (Storage Networks) Set-top Boxes Audio/Video Editing Graphics Accelerators Satellite Encoders Cable Modems Flight Simulators High-end Printing Servers Ultrasound Imaging 4 Chip Information 4.1 Marking Information AL5DS9XX9V Part Number: XX = 06, 07, 08, 09, 14, 15, 16, 17, 18, 19, 26, 27, 28, 34, 35, 36, 37, 38 X-xxx-XXyyy Package: XXyyy= PF128: 128-pin TQFP PF100: 100-pin TQFP Speed Grade: xxx = 100, 83 Version Number: X = A, B, C.. XXXXXX.X Lot Number XXXX Date Code 4.2 Ordering Information Two packages are available for AL5DS9xx9V series Synchronous Dual-Port SRAM. Part number AL5DS9069V (A-100-PF100) AL5DS9069V (A-83-PF100) AL5DS9079V (A-100-PF100) AL5DS9079V (A-83-PF100) AL5DS9089V (A-100-PF100) AL5DS9089V (A-83-PF100) AL5DS9099V (A-100-PF100) AL5DS9099V (A-83-PF100) AL5DS9149V (A-100-PF100) Speed (MHz) 100 83 100 83 100 83 100 83 100 Package 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP (c)2002-Copyright by AverLogic Technologies, Corp. Power Supply 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% Word Length 16K 16K 32K 32K 64K 64K 128K 128K 4K Preliminary Version 0.4 Bus Width 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 8 bits 9 bits 5 AL5DS9xx9V Part number AL5DS9149V (A-83-PF100) AL5DS9159V (A-100-PF100) AL5DS9159V (A-83-PF100) AL5DS9169V (A-100-PF100) AL5DS9169V (A-83-PF100) AL5DS9179V (A-100-PF100) AL5DS9179V (A-83-PF100) AL5DS9189V (A-100-PF100) AL5DS9189V (A-83-PF100) AL5DS9199V (A-100-PF100) AL5DS9199V (A-83-PF100) AL5DS9269V (A-100-PF100) AL5DS9269V (A-83-PF100) AL5DS9279V (A-100-PF100) AL5DS9279V (A-83-PF100) AL5DS9289V (A-100-PF100) AL5DS9289V (A-83-PF100) AL5DS9269V (A-100-PF128) AL5DS9269V (A-83-PF128) AL5DS9279V (A-100-PF128) AL5DS9279V (A-83-PF128) AL5DS9289V (A-100-PF128) AL5DS9289V (A-83-PF128) AL5DS9349V (A-100-PF100) AL5DS9349V (A-83-PF100) AL5DS9359V (A-100-PF100) AL5DS9359V (A-83-PF100) AL5DS9369V (A-100-PF100) AL5DS9369V (A-83-PF100) AL5DS9379V (A-100-PF100) AL5DS9379V (A-83-PF100) AL5DS9389V (A-100-PF100) AL5DS9389V (A-83-PF100) AL5DS9379V (A-100-PF128) AL5DS9379V (A-83-PF128) AL5DS9389V (A-100-PF128) AL5DS9389V (A-83-PF128) Speed (MHz) 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 100 83 Package 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 100 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP 128 pin TQFP (c)2002-Copyright by AverLogic Technologies, Corp. Power Supply 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% 3.3V10% Word Length 4K 8K 8K 16K 16K 32K 32K 64K 64K 128K 128K 16K 16K 32K 32K 64K 64K 16K 16K 32K 32K 64K 64K 4K 4K 8K 8K 16K 16K 32K 32K 64K 64K 32K 32K 64K 64K Preliminary Version 0.4 Bus Width 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 9 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 18 bits 6 AL5DS9xx9V 5 Function Block Diagram PIPE/FTL CE1L CE0L R/WL LBL UBL OEL I/O8/9L~15/17L I/O0L~7/8L PIPE/FTR Left I/O Control Right I/O Control 8/9 8/9 8/9 8/9 CE1R CE0R R/WR LBR UBR OER I/O8/9R~15/17R I/O0R~7/8R CLKL A0L~16L ADSL CNTENL CNTRSTL CLKR 12~17 Left Address Control True Dual-Ported SRAM Right Address Control 12~17 A0R~16R ADSR CNTENR CNTRSTR Note 1: LBR and UBR are for 16/18 bit devices only. Note 2: I/O0~7 for 8/16 bit devices, I/O0~8 for 9/18 bit devices, I/O8~15 for 16 bit devices, and I/O9~17 for 18 bit devices. Note 3: A0~11 for 4K, A0~12 for 8K, A0~13 for 16K, A0~14 for 32K, A0~15 for 64K, and A0~16 for 128K devices (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 7 AL5DS9xx9V 6 Pin-out Diagram 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 A10R A11R A12R A13R A14R A15R[NC] NC NC LBR UBR CE0R CE1R CNTRSTR VCC GND R/WR OER PIPE/FTR GND I/O17R I/O16R I/O15R I/O14R VCC VCC I/O13R 128 pin 14mm*20mm*1.4mm TQFP package-1: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128-Pin TQFP (Top View) AL5DS9389V(A-100-PF128): 64K * 18 AL5DS9389V(A-83-PF128): 64K * 18 AL5DS9379V(A-100-PF128): 32K * 18 AL5DS9379V(A-83-PF128): 32K * 18 (Note: Pins 44 and 123 are NC for AL5DS9379V) 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 I/O12R I/O11R GND NC I/O10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R GND I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L I/O10L NC VCC I/O11L I/O12L A10L A11L A12L A13L A14L [NC]A15L NC NC LBL UBL CE0L CE1L CNTRSTL VCC GND R/WL OEL PIPE/FTL GND I/O17L I/O16L I/O15L I/O14L VCC GND I/O13L 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VCC ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 8 AL5DS9xx9V 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 A10R A11R A12R A13R A14R[NC] A15R[NC] NC NC LBR UBR CE0R CE1R CNTRSTR VCC GND R/WR OER PIPE/FTR GND I/O15R I/O14R I/O13R I/O12R VCC VCC I/O11R 128 pin 14mm*20mm*1.4mm TQFP package-2: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 128-Pin TQFP (Top View) AL5DS9289V(A-100-PF128): 64K * 16 AL5DS9289V(A-83-PF128): 64K * 16 AL5DS9279V(A-100-PF128): 32K * 16 AL5DS9279V(A-83-PF128): 32K * 16 AL5DS9269V(A-100-PF128): 16K * 16 AL5DS9269V(A-83-PF128): 16K * 16 Note 1: pins 44 and 123 are NC for AL5DS9279V/69V Note 2: pins 43 and 124 are NC for AL5DS9269V I/O10R I/O9R GND NC I/O8R NC NC I/O7R VCC I/O6R I/O5R I/O4R GND I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VCC NC NC I/O8L NC VCC I/O9L I/O10L (c)2002-Copyright by AverLogic Technologies, Corp. I/O11L I/O15L I/O14L I/O13L I/O12L VCC GND A10L A11L A12L A13L [NC]A14L [NC]A15L NC NC LBL UBL CE0L CE1L CNTRSTL VCC GND R/WL OEL PIPE/FTL GND 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VCC ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC Preliminary Version 0.4 9 AL5DS9xx9V 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND GND ADSR CLKL CNTENR A0R A1R A2R A3R A4R A5R A6R A7R 100 pin 14mm*14mm*1.4mm TQFP package-1: A9L A10L A11L [NC]A12L [NC]A13L [NC]A14L [NC]A15L LBL UBL CE0L CE1L CNTRSTL R/WL OEL VCC PIPE/FTL I/O17L I/O16L 100-Pin TQFP (Top View) AL5DS9389V(A-100-PF100): 64K * 18 AL5DS9389V(A-83-PF100): 64K * 18 AL5DS9379V(A-100-PF100): 32K * 18 AL5DS9379V(A-83-PF100): 32K * 18 AL5DS9369V(A-100-PF100): 16K * 18 AL5DS9369V(A-83-PF100): 16K * 18 AL5DS9359V(A-100-PF100): 8K * 18 AL5DS9359V(A-83-PF100): 8K * 18 AL5DS9349V(A-100-PF100): 4K * 18 AL5DS9349V(A-83-PF100): 4K * 18 Note 1: pins 7 and 68 are NC for AL5DS9379V/69V/59V/49V Note 2: pins 6 and 69 are NC for AL5DS9369V/59V/49V Note 3: pins 5 and 70 are NC for AL5DS9359V/49V Note 4: pins 4 and 71 are NC for AL5DS9349V 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A8R A9R A10R A11R A12R[NC] A13R[NC] A14R[NC] A15R[NC] LBR UBR CE0R CE1R CNTRSTR R/WR GND OER PIPE/FTR I/O17R GND I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R I/O10R 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 10 AL5DS9xx9V A8R 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKL CNTENR A0R A1R A2R A3R A4R A5R A6R A7R 100 pin 14mm*14mm*1.4mm TQFP package-2: A9L A10L A11L A12L A13L [NC]A14L [NC]A15L NC NC LBL 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 I/O10R Preliminary Version 0.4 11 100-Pin TQFP (Top View) AL5DS9289V(A-100-PF100): 64K * 16 AL5DS9289V(A-83-PF100): 64K * 16 AL5DS9279V(A-100-PF100): 32K * 16 AL5DS9279V(A-83-PF100): 32K * 16 AL5DS9269V(A-100-PF100): 16K * 16 AL5DS9269V(A-83-PF100): 16K * 16 Note 1: pins 7 and 69 are NC for AL5DS9279V/69V Note 2: pins 6 and 70 are NC for AL5DS9269V A9R A10R A11R A12R A13R A14R[NC] A15R[NC] NC NC LBR UBR CE0R CE1R CNTRSTR GND R/WR OER PIPE/FTR GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O9L I/O8L VCC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VCC I/O7R I/O8R I/O9R NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBL CE0L CE1L CNTRSTL VCC R/WL OEL PIPE/FTL GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 (c)2002-Copyright by AverLogic Technologies, Corp. AL5DS9xx9V 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND GND ADSR CLKL CNTENR A0R A1R A2R A3R A4R A5R A6R NC 100 pin 14mm*14mm*1.4mm TQFP package-3: NC NC A7L A8L A9L A10L A11L [NC]A12L [NC]A13L [NC]A14L [NC]A15L [NC]A16L VCC NC NC NC NC A7R A8R A9R A10R A11R A12R[NC] A13R[NC] A14R[NC] A15R[NC] A16R[NC] GND NC NC NC NC CE0R CE1R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND NC Preliminary Version 0.4 12 100-Pin TQFP (Top View) AL5DS9199V(A-100-PF100): 128K * 9 AL5DS9199V(A-83-PF100): 128K * 9 AL5DS9189V(A-100-PF100): 64K * 9 AL5DS9189V(A-83-PF100): 64K * 9 AL5DS9179V(A-100-PF100): 32K * 9 AL5DS9179V(A-83-PF100): 32K * 9 AL5DS9169V(A-100-PF100): 16K * 9 AL5DS9169V(A-83-PF100): 16K * 9 AL5DS9159V(A-100-PF100): 8K * 9 AL5DS9159V(A-83-PF100): 8K * 9 AL5DS9149V(A-100-PF100): 4K * 9 AL5DS9149V(A-83-PF100): 4K * 9 Note 1: pins 12 and 64 are NC for AL5DS9189V/79V/69V/59V/49V Note 2: pins 11 and 65 are NC for AL5DS9179V/69V/59V/49V Note 3: pins 10 and 66 are NC for AL5DS9169V/59V/49V Note 4: pins 9 and 67 are NC for AL5DS9159V/49V Note 5: pins 8 and 68 are NC for AL5DS9149V CNTRSTR R/WR OER PIPE/FTR (c)2002-Copyright by AverLogic Technologies, Corp. I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R NC NC GND I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L VCC GND I/O0R I/O1R I/O2R VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC CE0L CE1L CNTRSTL R/WL OEL PIPE/FTL NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AL5DS9xx9V 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND ADSR CLKL CNTENR A0R A1R A2R A3R A4R A5R A6R NC NC 100 pin 14mm*14mm*1.4mm TQFP package-4: NC NC A7L A8L A9L A10L A11L A12L A13L [NC]A14L [NC]A15L [NC]A16L VCC NC NC NC NC A7R A8R A9R A10R A11R A12R A13R A14R[NC] A15R[NC] A16R[NC] GND NC NC NC NC CE0R CE1R 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND NC Preliminary Version 0.4 13 100-Pin TQFP (Top View) AL5DS9099V(A-100-PF100): 128K * 8 AL5DS9099V(A-83-PF100): 128K * 8 AL5DS9089V(A-100-PF100): 64K * 8 AL5DS9089V(A-83-PF100): 64K * 8 AL5DS9079V(A-100-PF100): 32K * 8 AL5DS9079V(A-83-PF100): 32K * 8 AL5DS9069V(A-100-PF100): 16K * 8 AL5DS9069V(A-83-PF100): 16K * 8 Note 1: pins 12 and 64 are NC for AL5DS9089V/79V/69V Note 2: pins 11 and 65 are NC for AL5DS9079V/69V Note 3: pins 10 and 66 are NC for AL5DS9069V CNTRSTR R/WR OER PIPE/FTR (c)2002-Copyright by AverLogic Technologies, Corp. I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L VCC GND I/O0R I/O1R I/O2R VCC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC CE0L CE1L CNTRSTL R/WL OEL PIPE/FTL NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AL5DS9xx9V 7 Pin Definition and Description The pin-out definitions are described as follows: Left Port Right Port A0L~A16L /ADSL A0R~A16R /ADSR I/O type I I /CNTENL /CNTENR I /CNTRSTL /CNTRSTR I /CE0L, CE1L /CE0R, CE1R I CLKL I/O0L~I/O17L /LBL CLKR I/O0R~I/O17R /LBR I I/O I /UBL /UBR I /OEL R/WL /OER R/WR I I PIPE/FTL PIPE/FTR I Description Address bus. Address Strobe. Low active. Asserting this signal LOW while using an external address to access the port. /ADS is only dependent of /CNTRST control signal. Counter Enable. Low active. The internal address counter increments one on each rising edge of CLK when counter enable, regardless of Chip Enable and Lower Byte or Upper Byte Selects. Counter Reset. Low active. Reset the internal address counter to zero. This signal is independent of all other control signals. Chip Enable. Low active for Chip Enable 0 and High active for Chip Enable 1. Clock input. Data bus. Lower Byte Select. Low active. Enable the read and write operations to the lower byte (I/O0-I/O8 for 18 bit devices, I/O0-I/O7 for 16 bit devices) while asserting this signal Low. Not available for 8/9 bit devices. Upper Byte Select. Low active. Enable the read and write operations to the upper byte (I/O9-I/O17 for 18 bit devices, I/O8-I/O15 for 16 bit devices) while asserting this signal Low. Not available for 8/9 bit devices. Output Enable. Low active. Asynchronous input signal. Read/Write Enable. High active for read operations and Low active for write operations. Pipelined and Flow-Through Mode Select. High active for Pipelined mode and Low active for Flow-Through mode. No connection NC Digital Power VCC DP Digital power GND DP Digital ground Note: For I/O type, I, O, and DP indicate input, output, and digital power respectively. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 14 AL5DS9xx9V For 18 or 16 bit devices, the truth table of read/write and enable control is as follows: /CE0 X L L L L L L X H X CE1 CLK R/W /UB /LB X X X X X H H H L H H L H H H L L H L H L H L L H H L L L X X H H X X X X L X X X /OE H L L L X X X X X X Upper byte High-Z High-Z Data output Data output High-Z Data input Data input High-Z High-Z High-Z Lower byte High-Z Data output High-Z Data output Data input High-Z Data input High-Z High-Z High-Z Note Outputs disabled Read Lower byte only Read Upper byte only Read both bytes Write to Lower byte Write to Upper byte Write to both bytes Both bytes disabled Chip disabled (Note 2) Chip disabled (Note 2) Note 1: H, L, X, and denote VIH, VIL, Don't Care and Rising-Edge Trigger, respectively. Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state. For 9 or 8 bit devices, the truth table of read/write and enable control is as follows: /CE0 CE1 CLK R/W /OE Data I/O Note X X X X H High-Z Outputs disabled L H H L Data output Read operation L H L X Data input Write operation H X X X High-Z Chip disabled (Note 2) X L X X High-Z Chip disabled (Note 2) Note 1: H, L, X, and denote VIH, VIL, Don't Care and Rising-Edge Trigger, respectively. Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state. The truth table of address counter control is as follows: /CNTRST /ADS /CNTEN CLK Address Previous Internal Data I/O Note input address address L X X X X 0 Q0 Reset internal address counter to 0 H L X An X An Qn Load external address into internal address counter H H L X AP AP+1 QP+1 Enable internal address counter H H H X AP AP QP Disable internal address counter Note 1: H, L, X, and denote VIH, VIL, Don't Care and Rising-Edge Trigger, respectively. Note 2: Assume /CE0, /UB, /LB, and /OE = VIL, CE1 and R/W = VIH. Note 3: Data I/O is configured in Flow-Through mode. For Pipelined mode, the data output will be delayed by one cycle. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 15 AL5DS9xx9V 8 Electrical Characteristics 8.1 Absolute Maximum Ratings (Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.) Parameter VCC Supply Voltage VP Input Pin Voltage IO Output Current TAMB Ambient Op. Temperature Tstg Storage Temperature TVSOL Vapor Phase Soldering Temperature (15 Sec.) 3.3V Rating Unit -0.3 ~ +3.8 V -0.3 ~ +(VCC+0.3) V -20 ~ +20 mA 0 ~ +85 C -40 ~ +125 C 220 C 8.2 Recommended Operating Conditions 3.3V Rating Parameter Unit Min. Typical Max. +3.0 +3.3 +3.6 V VCC Supply Voltage VIH High Level Input Voltage 0.7 VCC VCC V VIL Low Level Input Voltage 0 0.3 VCC V TAMB Ambient Op. Temperature 0 +70 C 8.3 DC Characteristics (VCC = 3.3V, GND=0V. TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested) 3.3V Rating Parameter Unit Min. Typical Max. - VCC V 0.3 VCC V VIH Hi-level Input Voltage 0.7 VCC VIL Lo-level Input Voltage 0 VOH Hi-level Output Voltage (VCC = Min., IOH = -4 mA) 2.4 - VCC V VOL Lo-level Output Voltage (VCC = Min., IOH = +4 mA) - - +0.4 V (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 16 AL5DS9xx9V 3.3V Rating Parameter Min. Typical Unit Max. CIN Input Capacitance at VCC=3.3V, TA=25C and f=1MHz 10 pF COUT Output Capacitance at VCC=3.3V, TA=25C and f=1MHz 10 pF ILI Input Leakage Current (VCC = 3.6V, VIN = 0V~ VCC) +5 A ILO Output Leakage Current (CE1 = VIL, VOUT = 0V~ VCC) +5 A IOZ 3-state Current (/OE = VIH) TBD ICC Operating Current (VCC = Max., IOUT = 0 mA, outputs disabled) TBD TBD mA ISB1 Standby Current (Both ports are TTL level inputs) TBD TBD mA ISB2 Standby Current (One port is TTL level inputs) TBD TBD mA ISB3 Standby Current (Both ports are CMOS level inputs) TBD TBD mA ISB4 Standby Current (One port is CMOS level inputs) TBD TBD mA A 8.4 AC Test Loads 8.4.1 Normal Load (Load 1) 3.3V 590 I/OOUT 435 30pF 8.4.2 3-State Load (Load 2) 3.3V 590 I/OOUT 435 (c)2002-Copyright by AverLogic Technologies, Corp. 5pF Preliminary Version 0.4 17 AL5DS9xx9V 8.5 AC Characteristics (VCC = 3.3V, GND=0V, TAMB = 0 to 70C; Some parameters are guaranteed by design only, not production tested) 3.3V Rating Parameter -100 Min Unit -83 Max Min Max Address Control tADDRS Setup time for Address 3.5 4 ns tADDRH Hold time for Address 0 0 ns tINr Rising time for all control inputs 3 3 ns tINf Falling time for all control inputs 3 3 ns tADSS Setup time for /ADS 3.5 4 ns tADSH Hold time for /ADS 0 0 ns tCENS Setup time for /CNTEN 3.5 4.5 ns tCENH Hold time for /CNTEN 0 0 ns tCRSTS Setup time for /CNTRST 3.5 4 ns tCRSTH Hold time for /CNTRST 0 0 ns I/O Control tINr Rising time for all control inputs 3 3 ns tINf Falling time for all control inputs 3 3 ns tCES Setup time for Chip Enable 3.5 4 ns tCEH Hold time for Chip Enable 0 0 ns tRWS Setup time for R/W 3.5 4 ns tRWH Hold time for R/W 0 0 ns tBS Setup time for /UB and /LB (not for 8/9 bit devices) 3.5 4 ns tBH Hold time for /UB and /LB (not for 8/9 bit devices) 0 0 ns tDAIS Setup time for input data 3.5 4 ns tDAIH Hold time for input data 0 0 ns tOE Output Enable to data valid tOELZ Output Enable to Low Z [1] (c)2002-Copyright by AverLogic Technologies, Corp. 8 2 9 2 Preliminary Version 0.4 ns ns 18 AL5DS9xx9V 3.3V Rating Parameter -100 Unit -83 Min Max Min Max 1 7 1 7 ns tOEHZ Output Enable to High Z [1] tCDFT Clock to data valid of Flow-Through 15 18 ns tCDPIPE Clock to data valid of Pipelined 6.5 7.5 ns tCKLZ Clock High to Low Z [1] 2 tCKHZ Clock High to High Z [1] 2 tDAOH Data output hold time after Clock High 2 tCWDD Write port Clock High to Read data delay 2 9 2 ns 9 ns 2 ns 28 30 ns 53 45 MHz Clock fFT Frequency of Flow-Through tFT Clock cycle time of Flow-Through 19 FT Duty Factor for Flow-Through (tFTH * fFT) 40 fPIPE Frequency of Pipelined tPIPE Clock cycle time of Pipelined 10 PIPE Duty Factor for Pipelined (tPIPEH * fPIPE) 40 tr Rising time for Clock tf tCCS 22 60 40 100 ns 60 % 83 MHz 12 60 40 ns 60 % 3 3 ns Falling time for Clock 3 3 ns Setup time for Clock to Clock 9 10 ns Note 1: These parameters that use 3-State load (load 2) as test conditions are guaranteed by design only. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 19 AL5DS9xx9V 9 Timing Diagrams t t CLK t f FT r t t FTL t FTH INr CE0 t INf t t t t CES CE1 t t CES t UB, LB INf CEH t t INr INr BH t R/W t t t BS BS RWH t t ADDRS t INr ADDRH A BH INf t RWS Address CEH t A X INf A Y t A Z n t CDFT t DAOH DATA I/O Q CKHZ Q X Q Y Z t CKLZ t OEHZ t OELZ OE t Note 1: PIPE/FT and ADS=VIL, CNTEN and CNTRST = VIH Note 2: UB and LB are only available for 16/18 bit devices. OE Read Cycle for Flow-Through Mode t t CLK t t t f PIPE r PIPEL PIPEH CE0 t t CES CE1 t CES UB, LB CEH t t t t BS R/W RWS t BH RWH t ADDRS ADDRH A A X A Y DAOH Q ency n t CDPIPE 1 Lat A Z t DATA I/O t BS BH t Address CEH t Q X t Q Y t CKLZ OEHZ Z t OELZ OE Note 1: ADS=VIL, PIPE/FT , CNTEN and CNTRST = VIH Note 2: QZ would be disabled if UB and/or LB was High. UB and LB are only for 16/18 bit devices. t OE Read Cycle for Pipelined Mode (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 20 AL5DS9xx9V CLKL t R/WL t RWS RWH t t ADDRS ADDRH AddressL No Match Match t t DAIS DATA-InL DAIH Valid t CCS CLKR t CWDD R/WR t RWS t RWH t t ADDRS t ADDRH AddressR CDFT No Match Match t t t CDFT DAOH DAOH DATA-OutR Valid Valid Note1: If TCCS > maximum specified, then data is not valid until TCCS+TCDFT and ignores TCWDD. Note2: OER, CE0 , UB, LB, PIPE/FT and ADS=VIL, OEL, CE1, CNTEN and CNTRST = VIH Left Port Write to Flow-Through Right Port Read t t CLK t t t f PIPE r PIPEL PIPEH t CE0(A) CES t CEH t t CES t CEH t ADDRS ADDRH Address(A) A A X A Y t CDPIPE A Z n t DAOH t CDPIPE DATA I/O(A) Q X t t Q Z CKLZ CKHZ CE0(B) t CES t Address(B) t t t CES CEH CEH t ADDRS ADDRH A X A A Y A Z t n t CDPIPE CKHZ DATA I/O(B) Q Y t CKLZ Note 1: UB, LB, OE and ADS=VIL, CE1(A), CE1(B), R/W, PIPE/FT, CNTEN and CNTRST = VIH Note 2: Each bank consists of one AverLogic dual port SRAM for this waveform. Address(A) = Address(B) Bank Select Pipelined Read (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 21 AL5DS9xx9V t t CLK t t t t f PIPE r PIPEL PIPEH RWH t t RWH RWS R/W t RWS t t ADDRS ADDRH Address A A n A n+1 A n+2 A n+3 n+4 t DAIS DAIH D DATAIN A n+2 t n+2 t t CDPIPE t t CKHZ CDPIPE Q DATAOUT CKLZ Q n Read No Operation Write n+3 Read Note 1: CE0, UB, LB and ADS=VIL, CE1, PIPE/FT , CNTEN and CNTRST = VIH Note 2: Output state is determined by the previous cycle control signals. Note 3: Data in memory at the selected address should be re-written to ensure data integrity during No Operation cycle. Pipelined Read-to-Write-to-Read Mode (OE = VIL) t t t r f PIPE CLK t t t PIPEL PIPEH RWH t RWS R/W t RWH t RWS t t ADDRS Address ADDRH A A n A n+1 t DAIS t t A n+4 n+5 DAIH D n+2 A n+3 t DAIS DAIH D DATAIN A n+2 n+3 t CDPIPE t DATAOUT t CDPIPE CKLZ Q Q n t n+4 OEHZ OE t INr t INf Read Write Read Note 1: CE0, UB, LB and ADS=VIL, CE1, PIPE/FT , CNTEN and CNTRST = VIH Note 2: Output state is determined by the previous cycle control signals. Pipelined Read-to-Write-to-Read Mode (OE controlled) (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 22 AL5DS9xx9V t t r f FT CLK t t t t FTL FTH RWH t t RWH RWS R/W t RWS t t ADDRS ADDRH Address A A n A n+1 A n+2 t D n+2 t CDFT CDFT t CKHZ Q DATAOUT Q n n+4 DAIH DATAIN t A n+3 t DAIS t A n+2 t CDFT CDFT Q n+1 n+3 t t t CKLZ DAOH Read No Operation DAOH Write Read Note 1: CE0, UB, LB, PIPE/FT, and ADS=VIL, CE1, CNTEN and CNTRST = VIH Note 2: Output state is determined by the previous cycle control signals. Note 3: Data in memory at the selected address should be re-written to ensure data integrity during No Operation cycle. Flow-Through Read-to-Write-to-Read Mode (OE = VIL) t t r f FT CLK t t t t FTL FTH RWH t RWS R/W t RWH t RWS t t ADDRS Address ADDRH A A n A n+1 t DAIS t t CDFT DATAOUT Q t t A n+3 A n+4 DAIH D n+2 n+3 t DAOH t CDFT CDFT Q n t n+5 t DAIS DAIH D DATAIN A n+2 t t CKLZ OEHZ n+4 DAOH t OE OE t INr t INf Read Write Read Note 1: CE0, UB, LB, PIPE/FT and ADS=VIL, CE1, CNTEN and CNTRST = VIH Note 2: Output state is determined by the previous cycle control signals. Flow-Through Read-to-Write-to-Read Mode (OE controlled) (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 23 AL5DS9xx9V t t CLK t t t f PIPE t r PIPEL PIPEH t ADDRS ADDRH Address A n t t ADSH ADSS ADS t ADSS t ADSH t CENH t CENS CNTEN t t CENH CENS t CDPIPE Q DATAOUT Q y Q x Q n t Read External Address Q n+1 DAOH Counter Hold Read with Counter Q n+2 n+3 Read with Counter Note 1: CE0, UB, LB and OE=VIL, CE1, PIPE/FT , R/W and CNTRST = VIH Pipelined Read with Internal Address Counter Enable t t CLK t t t f FT t r FTL FTH t ADDRS ADDRH Address A n t t ADSH ADSS ADS t ADSS t ADSH t CENH t CENS CNTEN t t CENH CENS t CDFT DATAOUT Q Q x t DAOH n Read External Address Q n+1 Read with Counter Q Q n+2 Counter Hold n+3 Q n+4 Read with Counter Note 1: CE0, UB, LB, PIPE/FT and OE=VIL, CE1, R/W and CNTRST = VIH Flow-Through Read with Internal Address Counter Enable (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 24 AL5DS9xx9V t t CLK t t t f FT t r FTL FTH t ADDRS ADDRH Address A n t t ADSH ADSS ADS t ADSS t ADSH t CENH t CENS CNTEN t t CENH CENS Internal Address A A n+1 A n+2 A n+3 n+4 t t DAIH DAIS DATAIN A n D D n D n+1 Write External Address D n+2 D D n+3 n+2 Counter Hold Write with Counter D n+4 n+5 Write with Counter Note 1: CE0, UB, LB, and R/W =VIL, OE, CE1, and CNTRST = VIH Note 2: Pipelined mode is the same as Flow-Through mode. Pipelined/Flow-Through Write with Internal Address Counter Enable CLK t t PIPEL t PIPEH t f t r t PIPE t ADDRS ADDRH Address A t RWH t R/W n+1 t RWH t RWS A n RWS ADS t ADSS t t ADSH t ADSS t ADSH CENH CNTEN t t CRSTS t t CENS t CENH CENS CRSTH CNTRST Internal Address A 1 0 X t DAIS DATAIN t A A n n+1 DAIH D 0 Q DATAOUT Write with Counter Reset Write Address 0 Read Address 0 Read Address 1 Q 0 1 Read Address n Note 1: CE0, UB, LB and OE =VIL, CE1 and PIPE/FT = VIH Note 2: There exists no dead cycle during counter reset. Q Read Address n+1 Counter Reset in Pipelined Mode (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 25 n AL5DS9xx9V 10 Mechanical Drawing 128 PIN 14mm*20mm*1.4mm TQFP: MILLIMETER INCH MIN. NOM. MAX. MIN. NOM. MAX. 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BSC. 0.020 BSC. e 18.50 0.728 D2 12.50 0.492 E2 TOLERANCES OF FORM AND POSITION 0.20 0.008 aaa 0.20 0.008 bbb 0.08 0.003 ccc 0.08 0.003 ddd SYMBOL NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 26 AL5DS9xx9V 100 PIN 14mm*14mm*1.4mm TQFP: MILLIMETER INCH MIN. NOM. MAX. MIN. NOM. MAX. 0.17 0.20 0.27 0.007 0.008 0.011 b 0.50 BSC. 0.020 BSC. e 12.00 0.472 D2 12.00 0.472 E2 TOLERANCES OF FORM AND POSITION 0.20 0.008 aaa 0.20 0.008 bbb 0.08 0.003 ccc 0.08 0.003 ddd SYMBOL NOTES: 1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages. (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 27 AL5DS9xx9V CONTACT INFORMATION Averlogic Technologies Corp. 4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan Tel: +886 2-27915050 Fax: +886 2-27912132 E-mail: sales@averlogic.com.tw URL: http://www.averlogic.com.tw Averlogic Technologies, Inc. 90 Great Oaks Blvd. #204, San Jose, CA 95119,U.S.A. Tel: 1 408 361-0400 Fax: 1 408 361-0404 E-mail: sales@averlogic.com URL: http://www.averlogic.com (c)2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 28