AL5DS9xx9V Data Sheets
3.3V Synchronous Dual-Port SRAM
AL5DS9349V/59V/69V/79V/89V
4K/8K/16K/32K/64K x 18
AL5DS9269V/79V/89V
16K/32K/64K x 16
AL5DS9149V/59V/69V/79V/89V/99V
4K/8K/16K/32K/64K/128K x 9
AL5DS9069V/79V/89V/99V
16K/32K/64K/128K x 8
Preliminary
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 2
Amendments (Since January 4, 2002)
02.01.04 Preliminary version 0.1
02.01.10 Preliminary version 0.2:
(1) Modifies truth table and note descriptions in paragraph 7
(2) Modifies Absolute Maximum Ratings in paragraph 8.1
(3) Modifies CIN and COUT DC characteristics in paragraph 8.3
(4) Modifies Bank Select Pipelined Read and Counter Rest in Pipelined Mode timing
diagrams
02.04.09 Preliminary version 0.3:
(1) Modifies features in paragraph 2
(2) Modifies ordering information in paragraph 4.1
(3) Modifies AC characteristics in paragraph 8.5
02.05.07 Preliminary version 0.4:
(1) Modifies marking information in paragraphs 4 and 6
(2) Modifies the font type in paragraphs 6 and 9
THE INFORMATION CONTAINED HEREIN IS SUBJECT TO CHANGE WIHOUT NOTICE.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 3
AL5DS9XX9V 3.3V Synchronous Dual-Port SRAM
Contents:
1 General Description ...............................................................................................4
2 Features ..................................................................................................................4
3 Applications ............................................................................................................5
4 Chip Information....................................................................................................5
4.1 Marking Information.............................................................................................................5
4.2 Ordering Information............................................................................................................5
5 Function Block Diagram .......................................................................................7
6 Pin-out Diagram.....................................................................................................8
7 Pin Definition and Description............................................................................14
8 Electrical Characteristics.....................................................................................16
8.1 Absolute Maximum Ratings................................................................................................16
8.2 Recommended Operating Conditions ................................................................................16
8.3 DC Characteristics ...............................................................................................................16
8.4 AC Test Loads ......................................................................................................................17
8.5 AC Characteristics ...............................................................................................................18
9 Timing Diagrams .................................................................................................20
10 Mechanical Drawing............................................................................................26
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 4
1 General Description
A Dual-port RAM is a static RAM with a dual-ported cell. There are separate address, data and
control signals for each port to access a common SRAM array. A dual-port RAM is generally
classified with FIFOs as a “specialty” memory. They are most used in communications that include
the exchange of data between processors, processes, and systems.
Each port contains an internal counter for fast memory access applications. The initial address of
internal counter is loaded with the port’s Address Strobe (/ADS). Also provided the Counter Enable
(/CNTEN) to increment the internal counter on each Low to High transition of that port’s clock
signal. The counter can address the entire memory array and will loop back to start (address 0). The
internal counter will be reset to zero while asserting Counter Reset (/CNTRST).
The AL5DS9xx9V series are high speed 3.3V synchronous CMOS dual-ported SRAM. The
AL5DS9349V/59V/69V/79V/89V are configured as 4K/8K/16K/32K/64K x 18-bit,
AL5DS9269V/79V/89V as 16K/32K/64K x 16-bit, AL5DS9149V/59V/69V/79V/89V/99V as
4K/8K/16K/32K/64K/128K x 9-bit, and AL5DS9069V/79V/89V/99V as 16K/32K/64K/128 x 8-bit.
All these parts support both Pipelined and Flow-Through modes that are selected via the Pipe/FT
pin. In the Pipelined mode, there are required two cycles to reactivate the data outputs. The
AL5DS9xx9V series feature dual Chip Enables that allow simple depth and width expansion
without external control logic.
All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.
AL5DS9269V/79V/89V and AL5DS9379V/89V are also available in 128-pin TQFP packages.
2 Features
zTrue dual ported memory cells
z18 Flow-Through/Pipelined devices:
-- 4K/8K/16K/32K/64K x 18-bit organization (AL5DS9349V/59V/69V/79V/89V)
-- 16K/32K/64K x 16-bit organization (AL5DS9269V/79V/89V)
-- 4K/8K/16K/32K/64K/128K x 9-bit organization (AL5DS9149V/59V/69V/79V/89V/99V)
-- 16K/32K/64K/128K x 8-bit organization (AL5DS9069V/79V/89V/99V)
zSupports byte write/read for 16/18 bit devices
zSeparate upper-byte and lower-byte controls for bus matching (only for 16/18 bit devices)
z3 modes supported:
-Pipelined
-Flow-Through
-Burst
zCounter enable and reset
zFast 100-MHz operation on both ports in Pipelined output mode
zSupports depth and width expansion
z0.25-micron CMOS for optimum speed/power
zHigh speed clock to data access
z3.3V low operating power
zPin-compatible and functionally equivalent to IDT or Cypress
zAvailable in 100 or 128 pin TQFP
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 5
3 Applications
zCellular Base Stations
zCellular Phones
zMulti-protocol Routers
zLAN/WAN Switches
zPBXs
zRAIDs (Storage Networks)
zSet-top Boxes
zAudio/Video Editing
zGraphics Accelerators
zSatellite Encoders
zCable Modems
zFlight Simulators
zHigh-end Printing Servers
zUltrasound Imaging
4 Chip Information
4.1 Marking Information
AL5DS9XX9V
X-xxx-XXyyy
XXXX
XXXXXX.X
Part Number: XX = 06, 07, 08, 09, 14, 15, 16,
17, 18, 19, 26, 27, 28, 34, 35, 36, 37, 38
Package: XXyyy=
PF128: 128-pin TQFP
PF100: 100-pin TQFP
Speed Grade: xxx = 100, 83
Version Number: X = A, B, C..
Lot Number
Date Code
4.2 Ordering Information
Two packages are available for AL5DS9xx9V series Synchronous Dual-Port SRAM.
Part number Speed
(MHz)
Package Power
Supply
Word
Length
Bus
Width
AL5DS9069V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 16K 8 bits
AL5DS9069V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 16K 8 bits
AL5DS9079V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 32K 8 bits
AL5DS9079V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 32K 8 bits
AL5DS9089V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 64K 8 bits
AL5DS9089V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 64K 8 bits
AL5DS9099V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 128K 8 bits
AL5DS9099V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 128K 8 bits
AL5DS9149V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 4K 9 bits
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 6
Part number Speed
(MHz)
Package Power
Supply
Word
Length
Bus
Width
AL5DS9149V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 4K 9 bits
AL5DS9159V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 8K 9 bits
AL5DS9159V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 8K 9 bits
AL5DS9169V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 16K 9 bits
AL5DS9169V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 16K 9 bits
AL5DS9179V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 32K 9 bits
AL5DS9179V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 32K 9 bits
AL5DS9189V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 64K 9 bits
AL5DS9189V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 64K 9 bits
AL5DS9199V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 128K 9 bits
AL5DS9199V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 128K 9 bits
AL5DS9269V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 16K 16 bits
AL5DS9269V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 16K 16 bits
AL5DS9279V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 32K 16 bits
AL5DS9279V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 32K 16 bits
AL5DS9289V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 64K 16 bits
AL5DS9289V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 64K 16 bits
AL5DS9269V (A-100-PF128) 100 128 pin TQFP 3.3V±10% 16K 16 bits
AL5DS9269V (A-83-PF128) 83 128 pin TQFP 3.3V±10% 16K 16 bits
AL5DS9279V (A-100-PF128) 100 128 pin TQFP 3.3V±10% 32K 16 bits
AL5DS9279V (A-83-PF128) 83 128 pin TQFP 3.3V±10% 32K 16 bits
AL5DS9289V (A-100-PF128) 100 128 pin TQFP 3.3V±10% 64K 16 bits
AL5DS9289V (A-83-PF128) 83 128 pin TQFP 3.3V±10% 64K 16 bits
AL5DS9349V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 4K 18 bits
AL5DS9349V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 4K 18 bits
AL5DS9359V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 8K 18 bits
AL5DS9359V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 8K 18 bits
AL5DS9369V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 16K 18 bits
AL5DS9369V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 16K 18 bits
AL5DS9379V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 32K 18 bits
AL5DS9379V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 32K 18 bits
AL5DS9389V (A-100-PF100) 100 100 pin TQFP 3.3V±10% 64K 18 bits
AL5DS9389V (A-83-PF100) 83 100 pin TQFP 3.3V±10% 64K 18 bits
AL5DS9379V (A-100-PF128) 100 128 pin TQFP 3.3V±10% 32K 18 bits
AL5DS9379V (A-83-PF128) 83 128 pin TQFP 3.3V±10% 32K 18 bits
AL5DS9389V (A-100-PF128) 100 128 pin TQFP 3.3V±10% 64K 18 bits
AL5DS9389V (A-83-PF128) 83 128 pin TQFP 3.3V±10% 64K 18 bits
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 7
5 Function Block Diagram
True Dual-Ported SRAM
Left
Address
Control
Right
Address
Control
Left I/O
Control
Right I/O
Control
ADSL
CNTENL
CNTRSTL
CLKL
12~17
A0L~16L
ADSR
CNTENR
CNTRSTR
CLKR
12~17 A0R~16R
8/9
8/9
I/O0R~7/8R
I/O8/9R~15/17R
R/WR
LBR
UBR
OER
CE1R
CE0R
PIPE/FTR
8/9
8/9
I/O0L~7/8L
I/O8/9L~15/17L
R/WL
LBL
UBL
OEL
CE1L
CE0L
PIPE/FTL
Note 1: LBR and UBR are for 16/18 bit devices only.
Note 2: I/O0~7 for 8/16 bit devices, I/O0~8 for 9/18 bit devices, I/O8~15 for 16 bit devices, and I/O9~17 for 18 bit devices.
Note 3: A0~11 for 4K, A0~12 for 8K, A0~13 for 16K, A0~14 for 32K, A0~15 for 64K, and A0~16 for 128K devices
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 8
6 Pin-out Diagram
128 pin 14mm*20mm*1.4mm TQFP package-1:
1
11
10
9
8
7
6
5
4
3
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
38
37
36
35
34
33
32
92
93
94
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
65
66
67
68
69
70
71
39
40
44
43
42
41
50
54
53
52
51
60
63
62
61
64
55
59
58
57
56
45
49
48
47
46
100
101
102
95
96
97
98
99
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
128-Pin TQFP (Top View)
AL5DS9389V(A-100-PF128): 64K * 18
AL5DS9389V(A-83-PF128): 64K * 18
AL5DS9379V(A-100-PF128): 32K * 18
AL5DS9379V(A-83-PF128): 32K * 18
(Note: Pins 44 and 123 are NC for AL5DS9379V)
I/O13R
VCC
VCC
VCC
I/O15R
I/O14R
I/O17R
I/O16R
PIPE/FTR
GND
GND
OER
R/WR
LBR
UBR
CE0R
CE1R
CNTRSTR
NC
NC
A10R
A15R[NC]
A14R
A13R
A12R
A11R
NC
NC
NC
A9R
NC
NC
NC
NC
NC
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
GND
VCC
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O12R
NC
NC
GND
I/O11R
GND
VCC
I/O10R
I/O9R
I/O8R
I/O7R
I/O6R
I/O5R
I/O4R
VCC
GND
I/O3R
I/O2R
I/O1R
I/O0R
VCC
GND
GND
VCC
VCC
I/O0L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O7L
I/O9L
I/O8L
I/O10L
I/O12L
I/O11L
A10L
[NC]A15L
A14L
A13L
A12L
A11L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
GND
VCC
R/WL
OEL
PIPE/FTL
GND
GND
VCC
I/O17L
I/O16L
I/O15L
I/O14L
I/O13L
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 9
128 pin 14mm*20mm*1.4mm TQFP package-2:
1
11
10
9
8
7
6
5
4
3
2
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
38
37
36
35
34
33
32
92
93
94
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
65
66
67
68
69
70
71
39
40
44
43
42
41
50
54
53
52
51
60
63
62
61
64
55
59
58
57
56
45
49
48
47
46
100
101
102
95
96
97
98
99
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
128-Pin TQFP (Top View)
AL5DS9289V(A-100-PF128): 64K * 16
AL5DS9289V(A-83-PF128): 64K * 16
AL5DS9279V(A-100-PF128): 32K * 16
AL5DS9279V(A-83-PF128): 32K * 16
AL5DS9269V(A-100-PF128): 16K * 16
AL5DS9269V(A-83-PF128): 16K * 16
Note 1: pins 44 and 123 are NC for AL5DS9279V/69V
Note 2: pins 43 and 124 are NC for AL5DS9269V
A10L
[NC]A15L
[NC]A14L
A13L
A12L
A11L
NC
NC
LBL
UBL
CE0L
CE1L
CNTRSTL
GND
VCC
R/WL
OEL
PIPE/FTL
GND
GND
VCC
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
NC
NC
NC
A9R
NC
NC
NC
NC
NC
A8R
A7R
A6R
A5R
A4R
A3R
A2R
A1R
A0R
NC
CNTENR
CLKR
ADSR
GND
VCC
ADSL
CLKL
CNTENL
NC
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
I/O13R
VCC
VCC
VCC
I/O15R
I/O14R
I/O12R
I/O11R
PIPE/FTR
GND
GND
OER
R/WR
LBR
UBR
CE0R
CE1R
CNTRSTR
NC
NC
A10R
A15R[NC]
A14R[NC]
A13R
A12R
A11R
NC
NC
GND
GND
VCC
I/O10R
I/O9R
I/O8R
I/O7R
I/O6R
I/O5R
I/O4R
VCC
GND
I/O3R
I/O2R
I/O1R
I/O0R
VCC
GND
GND
VCC
VCC
I/O0L
I/O6L
I/O5L
I/O4L
I/O3L
I/O2L
I/O1L
I/O7L
I/O9L
I/O8L
I/O10L
NC
NC
NC
NC
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 10
100 pin 14mm*14mm*1.4mm TQFP package-1:
100-Pin TQFP (Top View)
AL5DS9389V(A-100-PF100): 64K * 18
AL5DS9389V(A-83-PF100): 64K * 18
AL5DS9379V(A-100-PF100): 32K * 18
AL5DS9379V(A-83-PF100): 32K * 18
AL5DS9369V(A-100-PF100): 16K * 18
AL5DS9369V(A-83-PF100): 16K * 18
AL5DS9359V(A-100-PF100): 8K * 18
AL5DS9359V(A-83-PF100): 8K * 18
AL5DS9349V(A-100-PF100): 4K * 18
AL5DS9349V(A-83-PF100): 4K * 18
Note 1: pins 7 and 68 are NC for AL5DS9379V/69V/59V/49V
Note 2: pins 6 and 69 are NC for AL5DS9369V/59V/49V
Note 3: pins 5 and 70 are NC for AL5DS9359V/49V
Note 4: pins 4 and 71 are NC for AL5DS9349V
A9L
A10L
A11L
[NC]A12L
[NC]A13L
[NC]A14L
GND
I/O16L
LBL
UBL
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
I/O17L
[NC]A15L
I/O14L
I/O15L
I/O12L
I/O13L
I/O10L
I/O11L
GND
GND
I/O11R
PIPE/FTR
OER
R/WR
I/O16R
I/O15R
I/O14R
I/O13R
I/O12R
I/O17R
LBR
UBR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A14R[NC]
A8R
GND
GND
A8L
A3L
A4L
A5L
A6L
A7L
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKL
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
A7R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
I/O9R
I/O8R
I/O10R
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
A13R[NC]
A15R[NC]
A12R[NC]
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 11
100 pin 14mm*14mm*1.4mm TQFP package-2:
100-Pin TQFP (Top View)
AL5DS9289V(A-100-PF100): 64K * 16
AL5DS9289V(A-83-PF100): 64K * 16
AL5DS9279V(A-100-PF100): 32K * 16
AL5DS9279V(A-83-PF100): 32K * 16
AL5DS9269V(A-100-PF100): 16K * 16
AL5DS9269V(A-83-PF100): 16K * 16
Note 1: pins 7 and 69 are NC for AL5DS9279V/69V
Note 2: pins 6 and 70 are NC for AL5DS9269V
A9L
A10L
A11L
A12L
A13L
[NC]A14L
GND
LBL
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
[NC]A15L
I/O14L
I/O15L
I/O12L
I/O13L
I/O10L
I/O11L
GND
GND
I/O11R
PIPE/FTR
OER
R/WR
I/O15R
I/O14R
I/O13R
I/O12R
LBR
UBR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R
A13R
A14R[NC]
GND
A8L
A3L
A4L
A5L
A6L
A7L
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKL
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
A7R
GND
GND
VCC
I/O9L
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
I/O9R
I/O8R
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
LBL
NC
I/O10R
NC
NC
A8R
A15R[NC]
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 12
100 pin 14mm*14mm*1.4mm TQFP package-3:
100-Pin TQFP (Top View)
AL5DS9199V(A-100-PF100): 128K * 9
AL5DS9199V(A-83-PF100): 128K * 9
AL5DS9189V(A-100-PF100): 64K * 9
AL5DS9189V(A-83-PF100): 64K * 9
AL5DS9179V(A-100-PF100): 32K * 9
AL5DS9179V(A-83-PF100): 32K * 9
AL5DS9169V(A-100-PF100): 16K * 9
AL5DS9169V(A-83-PF100): 16K * 9
AL5DS9159V(A-100-PF100): 8K * 9
AL5DS9159V(A-83-PF100): 8K * 9
AL5DS9149V(A-100-PF100): 4K * 9
AL5DS9149V(A-83-PF100): 4K * 9
Note 1: pins 12 and 64 are NC for AL5DS9189V/79V/69V/59V/49V
Note 2: pins 11 and 65 are NC for AL5DS9179V/69V/59V/49V
Note 3: pins 10 and 66 are NC for AL5DS9169V/59V/49V
Note 4: pins 9 and 67 are NC for AL5DS9159V/49V
Note 5: pins 8 and 68 are NC for AL5DS9149V
NC
A7L
A8L
[NC]A12L
[NC]A13L
[NC]A14L
NC
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
[NC]A15L
GND
GND
PIPE/FTR
OER
R/WR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R[NC]
A13R[NC]
GND
NC
A3L
A4L
A5L
A6L
NC
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKL
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
GND
GND
VCC
GND
I/O8L
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
NC
I/O8R
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
NC
NC
NC
GND
N
C
NC
NC
NC
NC
[NC]A16L
A9L
A10L
A11L
NC
NC
NC
NC
NC
A8R
A7R
A14R[NC]
A15R[NC]
A16R[NC]
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 13
100 pin 14mm*14mm*1.4mm TQFP package-4:
100-Pin TQFP (Top View)
AL5DS9099V(A-100-PF100): 128K * 8
AL5DS9099V(A-83-PF100): 128K * 8
AL5DS9089V(A-100-PF100): 64K * 8
AL5DS9089V(A-83-PF100): 64K * 8
AL5DS9079V(A-100-PF100): 32K * 8
AL5DS9079V(A-83-PF100): 32K * 8
AL5DS9069V(A-100-PF100): 16K * 8
AL5DS9069V(A-83-PF100): 16K * 8
Note 1: pins 12 and 64 are NC for AL5DS9089V/79V/69V
Note 2: pins 11 and 65 are NC for AL5DS9079V/69V
Note 3: pins 10 and 66 are NC for AL5DS9069V
NC
A7L
A8L
A12L
A13L
[NC]A14L
NC
NC
CE0L
CE1L
CNTRSTL
VCC
R/WL
OEL
PIPE/FTL
[NC]A15L
GND
GND
PIPE/FTR
OER
R/WR
CE0R
CE1R
CNTRSTR
A9R
A10R
A11R
A12R
A13R
GND
NC
A3L
A4L
A5L
A6L
NC
A0L
A1L
A2L
ADSL
CLKL
CNTENL
ADSR
CLKL
CNTENR
A0R
A3R
A4R
A5R
A1R
A2R
A6R
GND
GND
VCC
GND
NC
I/O7L
I/O6L
I/O3L
I/O2L
I/O1L
I/O0L
I/O5L
I/O4L
VCC
I/O1R
I/O0R
I/O3R
I/O2R
I/O5R
I/O4R
I/O7R
I/O6R
NC
NC
NC
72
73
74
75
68
69
70
71
64
65
66
67
60
61
62
63
56
57
58
59
52
53
54
55
51
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
11
10
9
8
7
6
5
4
3
2
25
24
23
22
21
20
19
18
17
16
15
14
13
12
39
40
44
43
42
41
50
45
49
48
47
46
26
27
31
30
29
28
37
32
36
35
34
33
38
NC
NC
NC
NC
N
C
NC
NC
NC
NC
[NC]A16L
A9L
A10L
A11L
NC
NC
NC
NC
NC
A8R
A7R
A14R[NC]
A15R[NC]
A16R[NC]
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 14
7 Pin Definition and Description
The pin-out definitions are described as follows:
Left Port Right Port I/O
type
Description
A0L~A16L A
0R~A16R I Address bus.
/ADSL /ADSR I Address Strobe. Low active. Asserting this signal LOW
while using an external address to access the port. /ADS
is only dependent of /CNTRST control signal.
/CNTENL /CNTENR I Counter Enable. Low active. The internal address counter
increments one on each rising edge of CLK when counter
enable, regardless of Chip Enable and Lower Byte or
Upper Byte Selects.
/CNTRSTL /CNTRSTR I Counter Reset. Low active. Reset the internal address
counter to zero. This signal is independent of all other
control signals.
/CE0L, CE1L /CE0R, CE1R I Chip Enable. Low active for Chip Enable 0 and High
active for Chip Enable 1.
CLKL CLKR I Clock input.
I/O0L~I/O17L I/O0R~I/O17R I/O Data bus.
/LBL /LBR I Lower Byte Select. Low active. Enable the read and write
operations to the lower byte (I/O0-I/O8 for 18 bit devices,
I/O0-I/O7 for 16 bit devices) while asserting this signal
Low. Not available for 8/9 bit devices.
/UBL /UBR I Upper Byte Select. Low active. Enable the read and write
operations to the upper byte (I/O9-I/O17 for 18 bit devices,
I/O8-I/O15 for 16 bit devices) while asserting this signal
Low. Not available for 8/9 bit devices.
/OEL /OER I Output Enable. Low active. Asynchronous input signal.
R/WL R/WR I Read/Write Enable. High active for read operations and
Low active for write operations.
PIPE/FTL PIPE/FTR I Pipelined and Flow-Through Mode Select. High active for
Pipelined mode and Low active for Flow-Through mode.
NC - No connection
Digital Power
VCC DP Digital power
GND DP Digital ground
Note: For I/O type, I, O, and DP indicate input, output, and digital power respectively.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 15
For 18 or 16 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /UB /LB /OE Upper byte Lower byte Note
X X X X X X H High-Z High-Z Outputs disabled
L H ↑H H L L High-Z Data output Read Lower byte only
L H ↑H L H L Data output High-Z Read Upper byte only
L H ↑H L L L Data output Data output Read both bytes
L H ↑L H L X High-Z Data input Write to Lower byte
L H ↑L L H X Data input High-Z Write to Upper byte
L H ↑L L L X Data input Data input Write to both bytes
X X ↑X H H X High-Z High-Z Both bytes disabled
H X ↑X X X X High-Z High-Z Chip disabled (Note 2)
X L ↑X X X X High-Z High-Z Chip disabled (Note 2)
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state.
For 9 or 8 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /OE Data I/O Note
X X X X H High-Z Outputs disabled
L H ↑H L Data output Read operation
L H ↑L X Data input Write operation
H X ↑X X High-Z Chip disabled (Note 2)
X L ↑X X High-Z Chip disabled (Note 2)
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state.
The truth table of address counter control is as follows:
/CNTRST /ADS /CNTEN CLK Address
input
Previous
address
Internal
address
Data I/O Note
L X X
↑X X 0 Q0 Reset internal address
counter to 0
H L X
↑An X An Q
n Load external address into
internal address counter
H H L
↑X AP A
P+1 Q
P+1 Enable internal address
counter
H H H
↑X AP A
P Q
P Disable internal address
counter
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: Assume /CE0, /UB, /LB, and /OE = VIL, CE1 and R/W = VIH.
Note 3: Data I/O is configured in Flow-Through mode. For Pipelined mode, the data output will be
delayed by one cycle.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 16
8 Electrical Characteristics
8.1 Absolute Maximum Ratings
(Excessive ratings are harmful to the lifetime. Only for user guidelines, not tested.)
Parameter 3.3V Rating Unit
VCC Supply Voltage -0.3 ~ +3.8 V
VP Input Pin Voltage -0.3 ~ +(VCC+0.3) V
IO Output Current -20 ~ +20 mA
TAMB Ambient Op. Temperature 0 ~ +85 °C
Tstg Storage Temperature -40 ~ +125 °C
TVSOL Vapor Phase Soldering
Temperature (15 Sec.)
220 °C
8.2 Recommended Operating Conditions
3.3V Rating
Parameter
Min. Typical Max.
Unit
VCC Supply Voltage +3.0 +3.3 +3.6 V
VIH High Level Input Voltage 0.7 VCC V
CC V
VIL Low Level Input Voltage 0 0.3 VCC V
TAMB Ambient Op. Temperature 0 +70 °C
8.3 DC Characteristics
(VCC = 3.3V, GND=0V. TAMB = 0 to 70°C; Some parameters are guaranteed by design only,
not production tested)
3.3V Rating
Parameter
Min. Typical Max.
Unit
VIH Hi-level Input Voltage 0.7 VCC - VCC V
VIL Lo-level Input Voltage 0 0.3 VCC V
VOH Hi-level Output Voltage (VCC =
Min., IOH = -4 mA)
2.4 - VCC V
VOL Lo-level Output Voltage (VCC =
Min., IOH = +4 mA)
- - +0.4 V
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 17
3.3V Rating
Parameter
Min. Typical Max.
Unit
CIN Input Capacitance at VCC=3.3V,
TA=25°C and f=1MHz
10 pF
COUT Output Capacitance at VCC=3.3V,
TA=25°C and f=1MHz
10 pF
ILI Input Leakage Current (VCC =
3.6V, VIN = 0V~ VCC)
+5
µA
ILO Output Leakage Current (CE1 =
VIL, VOUT = 0V~ VCC)
+5
µA
IOZ 3-state Current (/OE = VIH) TBD
µA
ICC Operating Current (VCC = Max.,
IOUT = 0 mA, outputs disabled)
TBD TBD mA
ISB1 Standby Current (Both ports are
TTL level inputs)
TBD TBD mA
ISB2 Standby Current (One port is TTL
level inputs)
TBD TBD mA
ISB3 Standby Current (Both ports are
CMOS level inputs)
TBD TBD mA
ISB4 Standby Current (One port is
CMOS level inputs)
TBD TBD mA
8.4 AC Test Loads
8.4.1 Normal Load (Load 1)
I/OOUT
590Ω
435Ω30pF
3.3V
8.4.2 3-State Load (Load 2)
I/OOUT
590Ω
435Ω5pF
3.3V
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 18
8.5 AC Characteristics
(VCC = 3.3V, GND=0V, TAMB = 0 to 70°C; Some parameters are guaranteed by design only, not
production tested)
3.3V Rating
-100 -83 Parameter
Min Max Min Max
Unit
Address Control
tADDRS Setup time for Address 3.5 4 ns
tADDRH Hold time for Address 0 0 ns
tINr Rising time for all control inputs 3 3 ns
tINf Falling time for all control inputs 3 3 ns
tADSS Setup time for /ADS 3.5 4 ns
tADSH Hold time for /ADS 0 0 ns
tCENS Setup time for /CNTEN 3.5 4.5 ns
tCENH Hold time for /CNTEN 0 0 ns
tCRSTS Setup time for /CNTRST 3.5 4 ns
tCRSTH Hold time for /CNTRST 0 0 ns
I/O Control
tINr Rising time for all control inputs 3 3 ns
tINf Falling time for all control inputs 3 3 ns
tCES Setup time for Chip Enable 3.5 4 ns
tCEH Hold time for Chip Enable 0 0 ns
tRWS Setup time for R/W 3.5 4 ns
tRWH Hold time for R/W 0 0 ns
tBS
Setup time for /UB and /LB (not for 8/9 bit
devices) 3.5 4 ns
tBH
Hold time for /UB and /LB (not for 8/9 bit
devices) 0 0 ns
tDAIS Setup time for input data 3.5 4 ns
tDAIH Hold time for input data 0 0 ns
tOE Output Enable to data valid 8 9 ns
tOELZ Output Enable to Low Z [1] 2 2 ns
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 19
3.3V Rating
-100 -83 Parameter
Min Max Min Max
Unit
tOEHZ Output Enable to High Z [1] 1 7 1 7 ns
tCDFT Clock to data valid of Flow-Through 15 18 ns
tCDPIPE Clock to data valid of Pipelined 6.5 7.5 ns
tCKLZ Clock High to Low Z [1] 2 2 ns
tCKHZ Clock High to High Z [1] 2 9 2 9 ns
tDAOH Data output hold time after Clock High 2 2 ns
tCWDD Write port Clock High to Read data delay 28 30 ns
Clock
fFT Frequency of Flow-Through 53 45 MHz
tFT Clock cycle time of Flow-Through 19 22 ns
δFT Duty Factor for Flow-Through (tFTH * fFT) 40 60 40 60 %
fPIPE Frequency of Pipelined 100 83 MHz
tPIPE Clock cycle time of Pipelined 10 12 ns
δPIPE Duty Factor for Pipelined (tPIPEH * fPIPE) 40 60 40 60 %
tr Rising time for Clock 3 3 ns
tf Falling time for Clock 3 3 ns
tCCS Setup time for Clock to Clock 9 10 ns
Note 1: These parameters that use 3-State load (load 2) as test conditions are guaranteed by
design only.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 20
9 Timing Diagrams
tCDFT
OE
tCKLZ
CE0
CE1
UB, LB
R/W
AXAYAZAn
Address
tADDRS tADDRH
QXQYQZ
DATA I/O
tDAOH tCKHZ
tOE
tOEHZ tOELZ
tCES tCEH
tBS tBH
tRWS tRWH
tCES tCEH
tBS tBH
CLK tFTH
tFTL
tFT
Read Cycle for Flow-Through Mode
Note 1: PIPE/FT and ADS=VIL, CNTEN and CNTRST = VIH
Note 2: UB and LB are only available for 16/18 bit devices.
tftr
tINr tINf
tINr
tINf
tINr
tINf
tINr
tINf
Read Cycle for Pipelined Mode
tCDPIPE
OE
CE0
CE1
UB, LB
R/W
AXAYAZAn
Address
tADDRS tADDRH
QXQYQZ
DATA I/O
tDAOH
tOE
tOEHZ tOELZ
tCES tCEH
tBS tBH
tRWS tRWH
tCES tCEH
tBS tBH
CLK tPIPEH
tPIPEL
tPIPE tftr
tCKLZ
1Latency
Note 1: ADS=VIL, PIPE/FT , CNTEN and CNTRST = VIH
Note 2: QZ would be disabled if UB and/or LB was High. UB and LB are only for 16/18 bit devices.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 21
Left Port Write to Flow-Through Right Port Read
R/WLtRWS tRWH
CLKL
No
Match
AddressL
DATA-InL
Match
tADDRS tADDRH
Valid
tDAIS tDAIH
CLKR
tCCS
tCWDD
tCDFT
R/WR
AddressR
DATA-OutR
tRWS tRWH
Match
tADDRS tADDRH
tDAOH
Valid
No
Match
tDAOH
Valid
tCDFT
Note1: If TCCS > maximum specified, then data is not valid until TCCS+TCDFT and ignores TCWDD.
Note2: OER, CE0, UB, LB, PIPE/FT and ADS=VIL, OEL, CE1, CNTEN and CNTRST = VIH
Bank Select Pipelined Read
tCEH
CLK tPIPEH
tPIPEL
tPIPE tftr
tCES
tCES tCEH
AXAYAn
tADDRS tADDRH
QY
tCKHZ
AXAYAn
Address(A)
tADDRS tADDRH
DATA I/O(A)
tCDPIPE
tCKHZ
QX
CE0(A)
tDAOH
QZ
tCKLZ
tCDPIPE
CE0(B)
Address(B)
DATA I/O(B)
tCEH
tCES
tCEH
tCES
tCKLZ
tCDPIPE
Note 1: UB, LB, OE and ADS=VIL, CE1(A), CE1(B), R/W, PIPE/FT, CNTEN and CNTRST = VIH
Note 2: Each bank consists of one AverLogic dual port SRAM for this waveform. Address(A) = Address(B)
AZ
AZ
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 22
Pipelined Read-to-Write-to-Read Mode (OE = VIL)
Note 1: CE0, UB, LB and ADS=VIL, CE1, PIPE/FT , CNTEN and CNTRST = VIH
Note 2: Output state is determined by the previous cycle control signals.
Note 3: Data in memory at the selected address should be re-written to ensure data integrity during No Operation cycle.
R/W
AnAn+1 An+2
Address
tADDRS tADDRH
tRWS
tRWH
CLK tPIPEH
tPIPEL
tPIPE tftr
An+2
tRWS tRWH
An+3 An+4
DATAIN
tDAIS
QnQn+3
DATAOUT
tCKLZ
Dn+2
tDAIH
tCDPIPE tCKHZ
tCDPIPE
No Operation WriteRead Read
Pipelined Read-to-Write-to-Read Mode (OE controlled)
Note 1: CE0, UB, LB and ADS=VIL, CE1, PIPE/FT , CNTEN and CNTRST = VIH
Note 2: Output state is determined by the previous cycle control signals.
R/W
AnAn+1 An+2
Address
tADDRS tADDRH
tRWS
tRWH
CLK tPIPEH
tPIPEL
tPIPE tftr
An+3
tRWS tRWH
An+4 An+5
DATAIN
QnQn+4
DATAOUT
tCKLZ
Dn+3
tCDPIPE
tOEHZ
tCDPIPE
Dn+2
tDAIS tDAIH
tDAIS tDAIH
WriteRead Read
OE
tINr tINf
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 23
Flow-Through Read-to-Write-to-Read Mode (OE = VIL)
Note 1: CE0, UB, LB, PIPE/FT, and ADS=VIL, CE1, CNTEN and CNTRST = VIH
Note 2: Output state is determined by the previous cycle control signals.
Note 3: Data in memory at the selected address should be re-written to ensure data integrity during No Operation cycle.
R/W
AnAn+1 An+2
Address
tADDRS tADDRH
tRWS
tRWH
CLK tFTH
tFTL
tFT tftr
An+2
tRWS tRWH
An+3 An+4
DATAIN
tDAIS
Qn+3
DATAOUT
tCKLZ
Dn+2
tDAIH
tCDFT tCKHZ tCDFT
No Operation WriteRead Read
Qn
tDAOH
tCDFT
Qn+1
tDAOH
tCDFT
Flow-Through Read-to-Write-to-Read Mode (OE controlled)
Note 1: CE0, UB, LB, PIPE/FT and ADS=VIL, CE1, CNTEN and CNTRST = VIH
Note 2: Output state is determined by the previous cycle control signals.
R/W
AnAn+1 An+2
Address
tADDRS tADDRH
tRWS
tRWH
CLK tFTH
tFTL
tFT tftr
An+3
tRWS tRWH
An+4 An+5
DATAIN
QnQn+4
DATAOUT
tCKLZ
Dn+3
tCDFT
tOEHZ
tCDFT
Dn+2
tDAIS tDAIH
tDAIS tDAIH
WriteRead Read
OE
tINr
tDAOH
tINf
tCDFT
tOE
tDAOH
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 24
Pipelined Read with Internal Address Counter Enable
Note 1: CE0, UB, LB and OE=VIL, CE1, PIPE/FT , R/W and CNTRST = VIH
An
Address
tADDRS tADDRH
CLK tPIPEH
tPIPEL
tPIPE tftr
QyQn+3
DATAOUT
tADSH
tCDPIPE
tDAOH
Read with Counter Counter
Hold
Read
External
Address
Read with
Counter
ADS
tADSS
tADSH
tADSS
CNTEN tCENS
tCENH
tCENS
tCENH
QxQnQn+1 Qn+2
Flow-Through Read with Internal Address Counter Enable
Note 1: CE0, UB, LB, PIPE/FT and OE=VIL, CE1, R/W and CNTRST = VIH
An
Address
tADDRS tADDRH
CLK tFTH
tFTL
tFT tftr
QxQn+4
DATAOUT
tADSH
tCDFT
tDAOH
Read with Counter Counter
Hold
Read
External
Address
Read with
Counter
ADS
tADSS
tADSH
tADSS
CNTEN tCENS
tCENH
tCENS
tCENH
QnQn+1 Qn+2 Qn+3
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 25
Pipelined/Flow-Through Write with Internal Address Counter Enable
Note 1: CE0, UB, LB, and R/W =VIL, OE, CE1, and CNTRST = VIH
Note 2: Pipelined mode is the same as Flow-Through mode.
An
Address
tADDRS tADDRH
CLK tFTH
tFTL
tFT tftr
tADSH
ADS
tADSS
tADSH
tADSS
CNTEN tCENS
tCENH
tCENS
tCENH
tDAIS
Write with Counter Counter
Hold
Write
External
Address
Write with
Counter
Dn+5
DATAIN
tDAIH
DnDn+1 Dn+2 Dn+4
An+4
Internal
Address AnAn+1 An+2 An+3
Dn+2 Dn+3
Counter Reset in Pipelined Mode
Note 1: CE0, UB, LB and OE =VIL, CE1 and PIPE/FT = VIH
Note 2: There exists no dead cycle during counter reset.
tADSH
ADS
tADSS tADSH
tADSS
tCENH
An+1
Internal
Address AX01 An
Qn
DATAOUT Q1
Q0
DATAIN D0
tDAIS tDAIH
tADDRS tADDRH
CLK tPIPEH
tPIPEL tftr
Address AnAn+1
tPIPE
tCRSTS
CNTEN tCENS tCENS
tCENH
CNTRST
tCRSTH
R/W
Write with
Counter Reset
Write
Address 0
Read
Address 0
Read
Address 1
Read
Address n
Read
Address
n+1
tRWH
tRWS
tRWH
tRWS
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 26
10 Mechanical Drawing
128 PIN 14mm*20mm*1.4mm TQFP:
MILLIMETER INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
b0.17 0.20 0.27 0.007 0.008 0.011
e0.50 BSC. 0.020 BSC.
D2 18.50 0.728
E2 12.50 0.492
TOLERANCES OF FORM AND POSITION
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be
located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead
is 0.07mm for 0.4mm and 0.5mm pitch packages.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 27
100 PIN 14mm*14mm*1.4mm TQFP:
MILLIMETER INCH
SYMBOL
MIN. NOM. MAX. MIN. NOM. MAX.
b0.17 0.20 0.27 0.007 0.008 0.011
e0.50 BSC. 0.020 BSC.
D2 12.00 0.472
E2 12.00 0.472
TOLERANCES OF FORM AND POSITION
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
NOTES:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per
side. D1 and E1 are maximum plastic body size dimensions including mold mismatch.
2. Dimension b does not include dambar protrusion. Allowance dambar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be
located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead
is 0.07mm for 0.4mm and 0.5mm pitch packages.
AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 28
CONTACT INFORMATION
Averlogic Technologies Corp.
4F, No. 514, Sec. 2, Cheng Kung Rd., Nei-Hu Dist., Taipei, Taiwan
Tel: +886 2-27915050
Fax: +886 2-27912132
E-mail: sales@averlogic.com.tw
URL: http://www.averlogic.com.tw
Averlogic Technologies, Inc.
90 Great Oaks Blvd. #204, San Jose, CA 95119,U.S.A.
Tel: 1 408 361-0400
Fax: 1 408 361-0404
E-mail: sales@averlogic.com
URL: http://www.averlogic.com
