AL5DS9xx9V
©2002-Copyright by AverLogic Technologies, Corp. Preliminary Version 0.4 15
For 18 or 16 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /UB /LB /OE Upper byte Lower byte Note
X X X X X X H High-Z High-Z Outputs disabled
L H ↑H H L L High-Z Data output Read Lower byte only
L H ↑H L H L Data output High-Z Read Upper byte only
L H ↑H L L L Data output Data output Read both bytes
L H ↑L H L X High-Z Data input Write to Lower byte
L H ↑L L H X Data input High-Z Write to Upper byte
L H ↑L L L X Data input Data input Write to both bytes
X X ↑X H H X High-Z High-Z Both bytes disabled
H X ↑X X X X High-Z High-Z Chip disabled (Note 2)
X L ↑X X X X High-Z High-Z Chip disabled (Note 2)
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state.
For 9 or 8 bit devices, the truth table of read/write and enable control is as follows:
/CE0 CE1 CLK R/W /OE Data I/O Note
X X X X H High-Z Outputs disabled
L H ↑H L Data output Read operation
L H ↑L X Data input Write operation
H X ↑X X High-Z Chip disabled (Note 2)
X L ↑X X High-Z Chip disabled (Note 2)
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: For Pipelined mode, chip is disabled in the following clock cycle if /CE changes state.
The truth table of address counter control is as follows:
/CNTRST /ADS /CNTEN CLK Address
input
Previous
address
Internal
address
Data I/O Note
L X X
↑X X 0 Q0 Reset internal address
counter to 0
H L X
↑An X An Q
n Load external address into
internal address counter
H H L
↑X AP A
P+1 Q
P+1 Enable internal address
counter
H H H
↑X AP A
P Q
P Disable internal address
counter
Note 1: H, L, X, and ↑ denote VIH, VIL, Don’t Care and Rising-Edge Trigger, respectively.
Note 2: Assume /CE0, /UB, /LB, and /OE = VIL, CE1 and R/W = VIH.
Note 3: Data I/O is configured in Flow-Through mode. For Pipelined mode, the data output will be
delayed by one cycle.