Circuit Systems, Inc. rR Integrated i a 7 ICS5340 GENDAC 16-Bit Integrated Clock-LUT-DAC General Description The ICS5340 GENDAC is a combination of dual pro- grammable clock generators, a 256 x 18-bit RAM, anda triple 8-bit video DAC. The GENDAC supports 8-bit pseudo color applications, as well as 15-bit, 16-bit and 24- bit True Color bypass for high speed, direct access to the DACs. The RAM makes it possible to display 256 colors selected froma possible 262, 144 colors. The dual clock generators use Phase Locked Loop (PLL) technology to provide programmable frequencies for use in the graphics sub- system. The video clock contains 8 frequencies, 6 of which are programmable by the user. The memory clock has two programmable frequency locations. The three 8-bit DACs on the ICS5340 are capable of driving singly or doubly-terminated 75Q loads to nomi- nal 0 - 0.7 volts at pixel rates up to 135 MHz. Differential and integral linearity errors are less than 1 LSB over full temperature and V,p ranges. Monotonicity is guaran- teed by design. On-chip pixel mask register allows displayed colors to be changed in a single write cycle rather than by modifying the color palette. ICS is the world leader in all aspects of frequency (clock) generation for graphics, using patented techniques to produce low jitter video timing. Block Diagram Features Triple video DAC, dual clock generator, and a color palette e 24, 16, 15, or 8-bit pseudo color pixel mode supports True Color, Hi-Color, and VGA modes * High speed 256 x 18 color palette (135 MHz) with bypass mode and 8-bit DACs Two fixed, six programmable video (pixel) clock frequencies (CLKO) Two programmable memory (controller) clock frequency (CLK1) DAC power down in blanking mode * Anti-sparkle circuitry On-chip loop filters reduce external components * Standard CPU interface * Single external crystal (typically 14.318 MHz) Monitor Sense * Internal voltage reference * 135 MHz (-3), 110 MHz (-2) & 80 MHz (-1) versions Very low clock jitter e Latched frequency control pin PCLK TY COMPARE SENSE* \\ TRIPLE > RED PO-P15. KN _ A BUF COLOR LaTCHL a) 6:8 617 > GREEN PALETTE DAS le BLUE 256 X 18 BIT A RSET 1 VREF DO-D7 PCLK WR* > P - INTERFACE Rp pP - IN C RSO-2 er STROBE 4 2x > BLANK* CTL cS0 - CS0/2 >| SPLL ra PARAMETER > cLKO XIN XTALH] [ae ciKo PL Osc xOUT <1 TN eee L____/ PARAMETE } CLKI CLK 1PLL H-63ICS5340 GENDAC M Pin Configuration vs 22M oa ZERERRABBBASHEE RS OO OOOO fo cenomwmmnn ge eesegs N/C [10 oH N/C n/c Qu 59F] N/C N/C [12 58-7 P12 WR* 713 5779 Pl RS2_ 7] 14 56] P10 RS] G15 55(7] Po RSO [] 16 5417] Ps CvDD (417 GENDAC II 33,7) P7 XIN U8 1CS5340 5217] P6 XOUT []19 51 5 DVDD CGND [J 20 500 Ps CLK1 [J 21 491] AGND CGND [J 22 48[] Ps N/C (723 4717] P3 N/C [24 461] P2 N/C f 25 45 Nc nic C26 440] Nic RAASZRRZASRRRRSSEGVS QOOUOU UU uo Cr nN im G Green's a oO &#& Pin Description (68 pin PLCC) K-10 Symbol Pin # Type Description D7 - DO 68, 1-7 /O System data bus I/O. These bidirectional Data I/O lines are used by the host microprocessor to write (using active low WR*) information into, and read (using active low RD*) information from the six internal registers (Pixel Address, Color Value, Pixel Mask, PLL Address, PLL Parameter, and Command). During the write cycle, the rising edge of WR* latches the data into the selected register (set by the status of the three RS pins). The rising edge of RD* determines the end of the read cycle. When RD* is a logical high, the Data I/O lines no longer contain information from the selected register and will go into a tri-state mode. RD* 8 Input RAM/PLL Read Enable, active low. This is the READ bus control signal. When active, any information present on the internal data bus is available on the Data I/O lines, D0-D7. WR* 13 Input RAM/PLL Write Enable, active low. This signal controls the timing of the write operation on the microprocessor interface inputs, DO-D7. RS2 14 Input Register Address Select 0. These inputs control the selection of one of the RS1 15 Input six internal registers. They are sampled on the falling edge of the active RSO 16 Input enable signal (RD* or WR*). CVDD 17 - Crystal oscillator and CLKO power supply connect to AVDD. XIN 18 Input Crystal input. A 14.318 MHz crystal should be connected to this pin. XOUT 19 Output Crystal output. A 14.318 MHz crystal should be connected to this pin. CGND 20 - VSS for CLKO. Connect to ground. H-64ICS5340 GENDAC Pin Description (continued) Symbol Pin # Type Description CLK1 21 Qutput Memory clock output. Used to time the video memory. CGND 22 - VSS for CLK1. Connect to ground. CLKO 28 Output Video clock output. Provides a CMOS level pixel or dot clock frequency to the graphics controller. The output frequency is determined by the values of the PLL registers. CVDD 29 - CLKI Power Supply. Connect to AVDD. CSO 30 Input Clock select 0. The status of CS0-2 determine which frequency is selected on the CLKO (video) output. Latched by STB. CS1 31 Input Clock select 1. The status of CSQ-2 determine which frequency is selected on the CLKO (video) output. Latched by STB. CS2 32 Input Clock select 2. The status of CS0-2 determine which frequency is selected on the CLKO (video) output. Latched by STB. VREF 33 1/0 Internal Reference Voltage. Normally connects to a 0.1 cap to ground. To use an external Vret, connect a 1.235V reference to this pin. RSET 34 Input Resistor Set. This pin is used to set the current level in the analog outputs. It is usually connected through a 140Q, 1% resistor to ground. SENSE* 35 Output Monitor Sense, active low. This pin is low when any of the red, green, or blue outputs have exceeded 335mV. The chip has on-board compara- tors and an internal 335mV voltage reference. This is used to detect monitor type. AVDD 37 - DAC power supply. Connect to AVDD. BLUE 36 Output Color Signals. These three signals are the DACs analog outputs. Each GREEN 38 Output DAC is composed of several current sources. The outputs of each of the RED 39 Output sources are added together according to the applied binary value. These outputs are typically used to drive a CRT monitor. STROBE 40 Input Latches the input clock select signals CSO - CS2. PO- P15 41-42 Input Pixel Address Lines. This byte-wide information is latched by the rising 46-48, 50 edge of PCLK when using the Color Palette, and is masked by the Pixel Mask register. These values are used to specify the RAM word address in the default mode (accessing RAM). In the Hi-Color XGA, and True Color modes, they represent color data for the DACs. These inputs should be grounded if they are not used. AGND 49 - DAC Ground. Connect to ground. DVDD 51 - Digital power supply. PCLK 65 Input Pixel Clock. The rising edge of PCLK controls the latching of the Pixel 52-58, Address and BLANK* inputs. This clock also controls the progress of 62-64 these values through the three-stage pipeline of the Color Palette RAM, DAC, and outputs. BLANK* 66 Input Composite BLANK* Signal, active low. When BLANK is asserted, the outputs of the DACs are zero and the screen becomes black. The DACs are automatically powered down to save current during blanking. The color palette may still be updated through D0-D7 during blanking. DGND 67 - Digital Ground. Connect to ground. H-65la bia id ICS5340 GENDAC Internal Registers RS2| RS1 RSO Register Name Description (all registers can be written to and read from) Pixel Address WRITE Pixel Address READ There is a single Pixel Address register within the GENDAC. This register can be accessed through either register address 0,0,0 or register address 0,1,1. A read from address 0,0,0 is identical to a read from address 0,1,1. Writing a value to address 0,0,0 performs the following operations: a) Specifies an address within the color palette RAM. b) Initializes the Color Value register. Writing a value to address 0,1,1 performs the following operations: a) Specifies an address within the color palette RAM. b) Loads the Color Value register with the contents of the location in the addressed RAM palette and then increments the Pixel Address register. Writing to this 8-bit register is performed prior to writing one or more color values to the color palette RAM. Writing to this 8-bit register is performed prior to reading one or more color values from the color palette RAM. Color Value The 18-bit Color Value register acts as a buffer between the microprocessor interface and the color palette. Using a three bytes transfer sequence allows a value to be read from or written to this register. When a byte is read, the color value is contained in the least significant 6 bits , DO-D5 (the most significant 2 bits are set to zero). When writing a byte, the same 6 bits are used, When reading or writing, data is transferred in the same order - the red byte first, then green, then blue. Each transfer between the Color Value register and the color palette replaces the normal pixel mapping operations of the GENDAC for a single pixel. After writing three definitions to this register, its contents are written to the location in the color palette RAM specified by the Pixel Address register, and the Pixel Address register increments. After reading three definitions from this register, the contents of the location in the color palette RAM specified by the Pixel Address registers are copied into the Color Value register, and the Pixel Address register increments. Pixel Mask The 8-bit Pixel Mask register can be used to mask selected bits of the Pixel Address value applied to the Pixel Address inputs (PO-P7). A one in a position in the mask register leaves the corresponding bit in the Pixel Address unaltered, while a zero sets that bit to zero. The Pixel Mask register does not affect the Pixel Address generated by the microprocessor interface when the palette RAM is being accessed. H-66ICS5340 GENDAC Internal Registers (continued) RS2 | RS1 | RSO Register Description Name (all registers can be written to and read from) 1 0 0 PLL Address | Writing to this 8-bit register is performed prior to writing one or more WRITE PLL programming values to the PLL Parameter register. 1 1 1 PLL Address | Writing to this 8-bit register is performed prior to reading one or more READ PLL programming values from the PLL Parameter register. 1 ] 0 Command This 8-bit register selects the color mode, for instance 8-bit Pseudo Color, Hi- Color , True Color, or XGA, and DAC power down. The registers are reset to pseudo color mode on power up. 1 0 1 PLL There are sixteen parameter registers as indexed by PLL Address Write/ Parameter Read registers. Parameter registers 00-0D and OF are two bytes long and 0E* is one byte long. This register set contains one control register. The bits of this register include clock select and enable functions, the rest contain PLL frequency parameters. After writing the start index address in the PLL address register, these registers can be accessed in successive two (or one) bytes. The address register auto increments after one or two bytes to access the entire register set. H-67ICS5340 GENDAC Absolute Maximum Ratings Power Supply Voltage 0.00... cece cece teeeeeeeeteees 7V_ DC Digital Output Current ......0. eee 25 mA Voltage on any other pin ......GND-0.5V to Vpp + 0.5V Analog Output Current ...0.....0 cc cesececeeeneseeeene 45 mA Temperature under bias... 40C to 85C Reference Current 0.0.0... cceseceseeseeseeeeseeesteneneees -15 mA Storage Temperature 00.0... 65Cto 150C - Power Dissipation... cece eeseseeeeeeneaeeeesneeees 1O0W Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics Symbol | Parameter Conditions Min Max Units DC CHARACTERISTICS (note: J) Vop Positive supply voltage 4.75 5.25 Vv Vig Input logic 1 voltage 2.0 Vopp + 0.5 Vv Vin Input logic 0 voltage -0.5 0.8 Vv leEF Reference current ~7.0 -10 mA Veer Reference voltage 1.10 1.35 Vv lin Digital input current Vop = Max, +10 HA GND Vin S$ Vpp loz Off-state digital output current Vpp = max, +50 HA GND Vin Vop lop Average power supply current Ig = max, 250 mA Digital outputs unloaded Ibacorr DACs in power down mode No palette access 50 mA Vous Sense logic 1 Ip = .4mA 2.4 Vv Vous Sense logic 0 lb=.4mA 0.4 Vv Vouc Clock logic 1 I, = TBD 2.4 Vv Voc Clock logic 0 I, = TBD 0.4 Vv Vou logic 1 Ig =-3.2mA, note K 24 Vv Vor logic 0 Ip = 3.2mA, note K 0.4 Vv ICLK,+ Input Clock Rise Time TIL levels 15 ns ICLK Input Clock Fall Time TTL levels 15 ns Fp Frequency Change of CLKO and With respect to CLK1 over supply and temperature | typical frequency 0.05 % H-68ICS5340 GENDAC Electrical Characteristics (continued) Symbol Parameter Conditions Min Max Units DAC CHARACTERISTICS (note: J) Vo (max) | Maximum output voltage Ip $10mA 1.5 Vv Ig (max) | Maximum output current Vo $1V 21 mA Full scale error note A, B +5 % DAC to DAC correlation note B +2 % Integral Linearity, 6-bit note B 40.5 LSB Integral Linearity, 83-bit note B + LSB Full scale settling time*, 6-bit note C 28 ns Full scale settling time*, 8-bit note C 20 ns Rise time (10% to 90%)* note C 6 ns Glitch energy* note C 200 pVsec * Characterized values only Symbol Parameter Conditions Min Max Units PLL AC CHARACTERISTICS fy Clock 0 operating range* 25 135 MHz fy Clock 1 operating range* 25 135 MHz t. Output clocks rise time* 25 pf load, TTL levels 3 ns t. Output clocks fall time* 25 pf load, TTL levels 3 ns di Duty Cycle* 40/60 60/40 %o iis Jitter, one sigma* 130 ps ps jabs Jitter, absolute* -300 ps 300 ps ps bref Input reference frequency* Typically 14.318 MHz 5 25 MHz H-69ICS5340 GENDAC AC Electrical Characteristics (note: J) 80 MHz 110 MHz 135 MHz Symbol| Parameter Condition | Min | Max Min | Max| Min | Max | Units toHcH PCLK period 12.5 9.09 74 ns Atcucy | PCLK jitter note D 2.5 42.5 % tercH PCLK width low 5 3.6 3 ns terct PCLK width high 5 3.6 3 ns tpvcH Pixel word setup time note E 3 3 2 ns toupx Pixel word hold time note E 3 2 1 ns taycr BLANK* setup time note E 3 3 2 ns torpx BLANK* hold time note E 3 2 1 ns topav PCLK to valid DAC output note F 20 20 20 ns Atcpav Differential output delay note G 2 2 2 ns. twLwH WR* pulse width low 50 50 50 ns teLRH RD* pulse width low 50 50 50 ns tovwe Register select setup time Write cycle 10 10 10 ns toyer Register select setup time Read cycle 10 10 10 ns twrsx Register select hold time Write cycle} 10 10 10 ns tersx Register select hold time Read cycle 10 10 10 ns tovwH WR* data setup time 10 10 10 ns twHpx WR* data hold time 10 10 10 ns trtox Output turn-on delay 5 5 5 ns trrov RD* enable access time 40 40 40 ns trHox Output hold time 5 5 5 ns trHoz Output turn-off delay note H 20 20 20 ns twaHwit Successive write interval notel 4 (tere) 4 (torcH) 4 (topcy) cycle twurti WR* followed by read interval notel BA (topics) 4 (topcH) 4 (toyceD) cycle teHRLI Successive read interval notel K (topcqy) 4 (tocH) 4 (topcy) cycle teHWLt RD* followed by write interval notel H (tec) 4 (terce) 4 (toyce) cycle twHwL2 WR after color write notel # (tepe})) 4 (torcey) 4 (tocH) cycle twuri2 RD* after color write notel #4 (topic) 4 (torce) 4 (tency) cycle terete RD after color read notel [8 (tepcey) 8 (terce) 8 (tec) cycle terwi2 WR* after color read notel [8 (tere) 8 (toric) 8 (tercH) cycle twuris RD* after read address write notel 8 (tere 8 (toricH) 8 (tence) cycle tsop SENSE* output delay 1 1 1 [is H-70ICS5340 GENDAC NOTES: A. Full scale error is derived from design equation {FS Loup) Ry - 2.1 ep) R,1/12.1 ger) Rp) 100% Verack cever=OV F.S.Loyy = Actual full scale measured output B. R= 37.5Q, Ipeg = - 8.88MA C. 2,= 37.5Q + 30 pF, Ipgg = - 8.88MA D. This parameter is the allowed Pixel Clock frequency variation. It does not permit the Pixel Clock period to vary outside the minimum values for Pixel Clock (toyi,;) period. E. Itis required that the color palettes pixel address be a valid logic level with the appropriate setup and hold times at each rising edge of Per, (this requirement includes the blanking period). F. Theoutput delay is measured from the 50% point of the rising edge of CLOCK to the valid analog output. A valid analog output is defined when the analog signal is halfway between its successive values. G. This applies to different analog outputs on the same device. H. Measured at + 200 mV from steady state output voltage. 1. This parameter allows synchronization between operations on the microprocessor interface and the pixel stream being processed by the color palette. J. The following specifications apply for Vj) = +5V+ 0.5V, GND=0. Operating Temperature = 0C to 70C. K. Except for SENSE pin. AC Test Conditions Input pulse levels........... esses seneetececernees Vppto3V Input rise and fall times (10% to 90%) Digital input timing reference level Digital output timing reference level........0.8V and 2.4V Capacitance C, Digital input............... 7 PF Cy Digital output ve Cog Analog OUtPUL... ce ceseseccsecssstecscanessseerssaessseressasee 10pF 2002 1.4V vO ro 50 pF (including scope and jig) DIGITAL OUTPUT LOAD General Operation The ICS5340 GENDAC is intended for use as the analog output stage of raster scan video systems. It contains a high-speed Random Access Memory of 256 x 18-bit words, three6/8-bit high-speed DACs,a microprocessor/ graphic controller interface, a pixel word mask, on-chip compara- tors, and two user programmable frequency generators. Anexternally generated BLANK* signal can be applied to pin 66 of the ICS5340. This signal acts on all three of the analog outputs. The BLANK* signal is delayed internally so that it appears with the correct relationship to the pixel bit stream at the analog outputs. A pixel word mask is included to allow the incoming pixel address to be masked. This permits rapid changes to the effective contents of the color palette RAM to facilitate such operations as animation and flashing objects. Operations on the contents of the mask register can also be totally asynchronous to the pixel stream. The [CS55340 also includes dual PLL frequency generators providing a video clock (CLKO) and a memory clock (CLK1), both generated froma single 14.318 MHz crystal. There are eight selectable CLKO frequencies. Six are programmable, and two are fixed. There are two select- able and programmable CLK] frequencies (fA, fB). De- fault values (Table 1 and Table 2) are loaded into the appropriate registers on power up. Video Path The GENDAC supports nine different video modes and is determined by bits 4-7 of the command register. The default mode is the 8-bit Pseudo Color mode. The other modes are the bypass 15-bit, 16-bit and 24 bit True Color modes in 8-bit and 16-bit interface, and the 16-bit Pseudo Color (2:1) mode with 2X Clock. . The 16-bit True Color has sparse and packed modes. H-71ICS5340 GENDAC Pseudo Color 8-bit Interface In this mode, Pixel Address, P0-P7 and BLANK* inputs are sampled on the rising edge of the clock (PCLK) and any change appears at the analog outputs after three succeeding rising edges of the PCLK. The DAC outputs depends on the data in the color palette RAM. 16-bit Interface In this mode, Pixel Address, P0-P15 and BLANK* inputs are sampled on the rising edge of the clock (PCLK) and any change appears at the analog outputs after three succeeding rising edges of the 2 x ICLK. The DAC outputs depends on the data in the color palette RAM. Bypass Mode The GENDAC supports seven different bypass modes : three for byte transfers and four for word transfers. In these modes, the address pins PO-P15 represent Color Data that is applied directly to the DAC . The internal look-up table RAM is ignored. During byte transfers, the P8-P15 inputs are Don't Care. Data is always latched on the rising edge of PCLK. Byte or Word framing is inter- nally synchronized with the rising edge of BLANK*. Dac Outputs The outputs of the DACs are designed to be capable of producing 0.7 volt peak white amplitude with an Ipg,y of 8.88 mA when driving a doubly terminated 75Q load. This corresponds to an effective DAC output load (Regrecrive) Of 37.5Q. The formula for calculating [per with various peak white voltage/output loading combinations is given below: VogaK WHITE 2.1 x Reerective Teer = Note that for all values of Ipg- and output loading: Vetack LeveL = 9 The reference current Ipp, is determined by the reference voltage Vee, and the value of the resistor connected to Reger pin. Veer can be the internal band gap reference voltage or can be overridden by an external voltage. In both cases Iper =Vegp/Repy - 4 4 yj 7 REF (EXT) Phe Figure 4 - DAC Set up The BLANK* input to the GENDAC acts onall three of the DAC outputs. When the BLANK* input is low, the DACs are powered down. The connection between the DAC outputs of the ICS5340 and the RGB inputs of the monitor should be regarded as a transmission line. Impedance changes along the trans- mission line will result in the reflection of part of the video signal back along the transmission line. These reflections may result in a degradation of the picture displayed by the monitor. RF techniques should be observed to ensure good fidel- ity. The PCB trace connecting the GENDAC to the off- board connector should be sized to form a transmission line of the correct impedance. Correctly matched RF connectors should be used for connection from the PCB to the coaxial cable leading to the monitor and from the cable to the monitor. There are two recommended methods of DAC termina- tion: double termination and buffered signal. Each is described below with its relative merits: Double Termination (Figure 1) For this termination scheme, a load resistor is placed at both the DAC output and the monitor input. The resistor values should be equal to the characteristic impedance of the line. Double termination of the DAC output allows both ends of the transmission line between the DAC H-72ICS5340 GENDAC outputs and the monitor inputs to be correctly matched. The result should be an ideal reflection free system. This arrangement is relatively tolerant to variations in transmission line impedance (e.g. a mismatched connector) since no reflections occur from either end of the line. A doubly terminated DAC output will rise faster than any singly terminated output because the rise time of the DAC outputs is dependent on the RC time constant of the load. MONITOR 1CS5340 RLoaD RLoap GND GND Figure 1 - Double Termination Buffered Signal (Figure 2) Ifthe GENDAC drives large capacitive loads (for instance long cable runs), it may be necessary to buffer the DAC outputs. The buffer will have a relatively high input impedance. The connection between the DAC outputs and the buffer inputs should also be considered as a transmission line. The buffer output will havea relatively low impedance. It should be matched to the transmission line between it and the monitor with a series terminating resistor. The transmission line should be terminated at the monitor. Rs MONITOR 1C$5340 GND | Ry RLoap GND Figure 2 - Buffered Signal SENSE Output The GENDAC contains three comparators, one each for the DAC output (R, G and B) lines. The reference voltage to the comparators is proportional to the Vpgr (internal or external) and is typically 0.33 for Vppp =1.23 Volts. When the voltage on any of these pins go higher than the reference voltage to the comparators, the SENSE* pin is driven low. This signal is used to detect the type of (or lack of) monitor connected to the system. PLL Clock The ICS5340 has dual PLL frequency generators for gen- erating the video clock (CLKQ) and memory clock (CLK1) needed for graphics subsystems. Both these clocks are generated from a single 14.318 MHz crystal or can be driven by an external clock source. The chip includes the capacitors for the crystal and all the components needed for the PLL loop filters, minimizing board component count. There are eight possible video clock, CLKO, frequencies (f0-7) which can be selected by the external pins CS0- CS2. Pins are software selectable by setting a bitin the PLL control register. Two of these frequencies (f0-f1) are fixed and the other six (f2-f7) can be programmed for any frequency by writing appropriate parameter values tothe PLL parameter registers. The default frequencies on power up are commonly used video frequencies (table 1). At power up, the frequencies can be selected by pins CS0- CS2. There are two programmable memory clock fre- quencies (fA, fB ). On power up this frequency defaults to the frequency given in table 2. The memory clock transi- tion between frequencies is smooth and glitch free if the transition is kept between the limits 45-65 MHz. VLCK fA| (MHz) | Comments f0} 25.175] VGAO (VGA Graphics) (fixed) ft] 28.322] VGA1 (VGA Text) (fixed) f2| 31.500} VESA 640 x 480 @72 Hz (programmable) f3| 36.00 | VESA 800 x 600 @56 Hz (programmable) f4| 40.00 | VESA 800 x 600 @60 Hz (programmable) f5| 44.889] 1024 x 768 @43 Hz Interlaced (programmable) f6| 65.00 | 1024 x 768 @ 60 Hz, 640 x 480 Hi-Color @ 72 Hz (programmable) {7| 75.00 | VESA 1024 x 768 @ 70 Hz, True Color 640 x 480 (programmabie) Table 1 - Video clock (CLKO) default frequency register (with a 14.318 MHz input) H-73ICS5340 GENDAC fn MHz Comments fA |45.00 MHz} Memory and GUI subsystem clock fB {55.00 MHz] Memory and GUI subsystem clock Table 2 - Memory Clock (CLK1) default frequency register Microprocessor Interface Below are listed the six microprocessor interface registers within the ICS5340, and the register addresses through which they can be accessed. RS2 a Dn - RSO | Register Name Pixel Address (write mode) Pixel Address (read mode) Color Value Pixel Mask PLL Address (write mode) PLL Parameter Command PLL Address (read mode) Command Register accessed by (hidden) flag after special sequence of events Tere sso OO PAROORFROFSO COForaoHHo Oo Table 3 - Microprocessor Interface Registers Asynchronous Access to Microprocessor Interface Accesses to all registers may occur without reference to the high speed timing of the pixel bit stream being processed by the GENDAC. Data transfers between the color palette RAM and the Color Value register, as well as modifications to the Pixel Mask register, are synchronized to the Pixel Clock by internal logic. This is done in the period between microprocessor interface accesses. Thus, various minimum periods are specified between microprocessor interface accesses to allow the appropriate transfers or modifications to take place. Access to PLL address, PLL parameter and to the command register are asynchronous to the pixel clock. The contents of the palette RAM can be accessed via the Color Value register and the Pixel Address registers. Writing to the color palette RAM To seta new color definition, a value specifying a location in the color palette RAM is first written to the Write mode Pixel Address register. The values for the red, green and blue intensities are then written in succession to the Color Value register. After the blue data is written to the Color Value register, the new color definition is transferred to the RAM, and the Pixel Address register is automatically incremented. Writing new color definitions to a set of consecutive locations in the RAM is made easy by this auto- incrementing feature. First, the start address of the set of locations is written to the write mode Pixel Address register, followed by the color definition of that location. Since the address is incremented after each color definition is written, the color definition for the next location can be written immediately. Thus, the color definitions for consecutive locations can be written sequentially to the Color Value register without re-writing to the Pixel Address register each time. Reading from the RAM To read a color definition, a value specifying the location in the palette RAM to be read is written to the read mode Pixel Address register. After this value has been written, the contents of the location specified are copied to the Color Value register, and the Pixel Address register automatically increments. The red, green and blue intensity values can be read by a sequence of three reads from the Color Value register. After the blue value has been read, the location in the RAM currently specified by the Pixel Address register is copied to the Color Value register and the Pixel Address again automatically increments. A set of color values in consecutive locations can be read simply by writing the start address of the set to the read mode Pixel Address register and then sequentially reading the color values for each location in the set. Whenever the Pixel Address register is updated, any unfinished color definition read or write is aborted and a new one may begin. The Pixel Mask Register The pixel address used to access the RAM through the pixel interface is the result of the bitwise ANDing of the H-74ICS5340 GENDAC incoming pixel address and of the contents of the Pixel Mask register. This pixel masking process can be used to alter the displayed colors without altering the video memory or the RAM contents. By partitioning the color definitions by one or more bits in the pixel address, such effects as rapid animation, overlays, and flashing objects can be produced. The Pixel Mask register is independent of the Pixel Address and Color Value registers. The Command Register The Command register is used to select the various GEN- DAC color modes and to set the power down mode. On power up this register defaults to an 6-bit Pseudo Color mode. This register can be accessed by control pins RS2- RSO, or by a special sequence of events for graphics subsystems that do not have the control signal RS2. For graphic systems that do not have RS2, this pin is tied low and an internal flag (HF; Hidden Flag) is set when the pixel mask register is read four times consecutively. Once the flag is set, the following Read or Write to the pixel mask register is directed to the command register. The flag is reset for Read or Write to any register other than the pixel mask register. The sequence has to be repeated for any subsequent access to the command register. The PLL Parameter Register The CLKO and CLK1 of the ICS5340 can be programmed for different frequencies by writing different values to the PLL parameter register bank. There are eight registers in the parameter register; seven are two bytes long and one (OE) is one byte long. Writing to the PLL parameter register To write the PLL parameter data, the corresponding address location is first written to the PLL address regis- ter. For software compatibility with other chips, two address registers are defined; the Write mode PLL ad- dress register and the Read mode PLL address register. They are actually a single Read/Write register in the 1CS5340. The next PLL parameter write will be directed to the first byte of the address location specified by the PLL address register. The next Write to the parameter register will automatically be to the second byte of this register. At the end of the second Write the address is automatically incremented. For the one byte "QE" register the address location is incremented after the first byte Write. If this frequency is selected while programming, the output frequency will change at the end of the second Write. Reading the PLL parameter register To read one of the registers of the PLL parameter register the address value corresponding to the location is first written to the PLL address register. The next PLL param- eter read will be directed to the first byte of the address location pointed by this index register. A next Read of the parameter register will automatically be the second byte of this register. At the end of the second Read, the address location is automatically incremented. The address regis- ter (QE) is incremented after the first byte Read. Power Down Mode When bit 0 in the Command register is high (set to 1) , the GENDAC enters the DAC power down mode. The DACs are turned off, and the data is retained in the RAM. It is possible to access the RAM, in which case the current will temporarily increase. While the RAM is being accessed, the current consumption will be proportional to the speed of the clock. There is no effect on either clock generator while in this mode. Power Supply As a high speed CMOS device, the ICS5340 may draw large transient currents from the power supply, it is necessary to adopt high frequency board layout and power distribution techniques to ensure proper opera- tion of the GENDAC. Please refer to the suggested layout on page 27. To supply the transient currents required by the ICS5340, the impedance in the decoupling path should be kept to a minimum between the power supply pins Vpp and GND. Itis recommended that the decoupling capacitance between Vpp and GND should bea 0.1 F high frequency capacitor, in parallel with a large tantalum capacitor with H-75ICS5340 GENDAC a value between 22uF and 471F. A ferrite bead may be added in series with the positive supply to form a low pass filter and further improve the power supply local to the GENDAC. It will also reduce EMI. The combination of series impedance in the ground supply to the GENDAC, and transients in the current drawn by the device will appear as differences in the GND voltages to the GENDAC and to the digital devices driving it. To minimize this differential ground noise, the impedance in the ground supply between the GENDAC and the digital devices driving it should be minimized. Digital Output Information The PCB trace lines between the outputs of the TTL devices driving the GENDAC and the input to the GEN- DAC behave like low impedance transmission lines driven from a low impedance transmission source and termi- nated with a high impedance. In accordance with trans- mission line principles, signal transitions will be reflected from the high impedance input to the device. Similarly, signal transitions will be inverted and reflected from the low impedance TTL output. Line termination is recom- mended to reduce or eliminate the ringing, particularly the undershoot caused by reflections. The termination may either be series or parallel. Series termination is the recommended technique to use. It has the advantages of drawing no DC current and of using fewer components. Series termination is accom- plished by placing a resistor in series with the signal at the output of the TTL driver. This matches the TTL output impedance to that of the transmission line and ensures that any signal incident on the TTL outputis not reflected. To minimize reflections, some experimentation will have to be done to find the proper value to use for the series termination. Generally, a value around 100Q will be required. Since each design will result ina different signal impedance, a resistor of a predetermined value may not properly match the signal path impedance. Therefore, the proper value of resistance should be found empirically. H-76<= PN ICS5340 GENDAC Functional Description Bit 7-4 This section describes the register address and bit definition for RAMDAC and the Frequency Synthesizer sections. Color Palette Command Register (RSO-RS2 = 011) (RSO-RS1 = 01 with hidden flag) Bit3-1 Bit 0 By setting bits in the command register the ICS5340 can be programmed for different color modes and can be powered down for low power operation. 7 6 5 | 4 3 2 1 0 Color Mode Reserved = 0 Snooze 2 1 0 3 Table 3 - Command Registers Color Mode Select These three bits select the Color Mode of RAMDAC operation as shown in the following table 4 (default is 0 at power up): (Reserved) Power Down Mode of RAMDAC Wher this bit is set to 0 (default is 0), the device operates normally. If this bit is set to 1, the power and clock to the Color Palette RAM and DACs are turned off. The data in the Color Palette RAM are still preserved. The CPU can access without loss of data by internal auto- matic clock start/stop control. The DAC out- puts become the same as BLANK* (sync) level output during power down mode. This bit does not effect the PLL clock synthesizer func- tion. 8-BIT INTERFACE Mode | CM3 | CM2 | CM1 | CMO Clock Cycles/ Number | (CR4) | (CR7) | (CR6) |(CR5) | Color Mode Pixel Bits 0 0 0 0 0 8-Bit Pseudo Color with Palette (Default) 1 1 0 0 0 1 15-Bit Direct Color with Bypass (Hi-Color) 2 3 0 0 1 0 24-Bit True Color with Bypass (True Color) 3 2 0 0 1 1 16-Bit Direct Color with Bypass (XGA) 2 1 0 1 0 0 15-Bit Direct Color with Bypass (Hi-Color) 2 1 0 1 0 1 15-Bit Direct Color with Bypass (Hi-Color) 2 2 0 1 1 0 16-Bit Direct Color with Bypass (XGA) 2 3 0 1 1 1 24-Bit True Color with Bypass (True Color) 3 16-BIT INTERFACE Mode | CM3 | CM2 | CM1 | CMO Clock Cycles/ Number | (CR4) | (CR7) |(CR6) | (CR5)| Color Mode Pixel Bits 4 1 0 0 0 Muxed 16-Bit Pseudo Color with Palette 1/2 5 1 0 0 1 15-Bit Direct Color with Bypass (Hi-Color) 1 6 1 0 1 0 16-Bit Direct Color with Bypass (XGA) 1 7 1 0 1 1 24-Bit Direct Color with Bypass (True-Color) 8 1 1 0 0 24-Bit Packed Direct Color with Bypass (True-Color) 3/2 1 1 0 1 Reserved 1 1 1 0 Reserved I 1 1 1 Reserved Table 4 - Color Mode Select H-77ICS5340 GENDAC Color Modes The nineselectable color modes are described here. Modes 0-3 are 8-bit interfaces with P0-P7 bits, P8-P15 are Don't Care bits. Mode 0: 8-bit Pseudo Color (one clock per pixel). This mode is the 8-bit per pixel Pseudo Color mode. In this mode, inputs P0-P7 are the pixel address for the color palette RAM and are latched on the rising edge of every PCLK. This is the default mode on power up and it is selected by setting bits CR7-CR4 to 0000. There are three clock cycles pipe line delays from input to DAC output. 8-bit Pseudo Color Mode PIXE onl Ww fw ope YTE P 1 P PPP 5 210 5 210 DRESS >e [AD Gg PP 7 6 7 6 PIXEL Mode 1: (15-bit per color bypassHi-Color mode). This mode is the 15-bit per pixel bypass mode. In this mode, inputs PO-P7 are the color DATA and are input directly to the DAC, bypassing the color palette. The two bytes of data is latched in two successive PCLK rising edges. IC55340 supports only the two clock mode and does not support the mode where the data are latched on the rising and the falling edges. For compatibility, the 15/ 16 one clock modes are selected as two clock modes in this chip. Thelow-byte, high bytesynchronization is internally done by the rising edge of BLANK*. Each color is 5-bit wide and is packed into two bytes as shown below. This mode can be selected by setting bits CR7-CR4 to 0010, 1000 or 1010. 15-Bit Color Mode 1 Pixel Description 3LSB = set to zero SECOND BYTE PPPPPPPIP 4321 7 5 4 3 erg PY NS [a WY P 7 x w jor 3 0 4 6 i 65 7 6 R DB m ic n> 5 ED GREER Mode 2: (16-bit per pixel bypass XGA mode). This mode is the 16-bit per pixel bypass mode and the P0- P7 inputs to go to the DAC directly, bypassing the color palette. The 2 bytes data is latched on two successive rising edges and the low-byte, high-byte synchronization is internally done by the rising edge of BLANK*. In this mode, blue and red colors are 5 bits wide and green is 6 bits wide. The 2 bytes of data is packed as shown below. This mode canbe selected by setting bits CR7-CR4 to0110 or 1100. 16-Bit Color Mode 2 Pixel Description 2LSB = set to zero (green) 3LSB = set to zero (blue, red) SECOND BYTE FIRST BYTE PPPPPPPPIPPPPPPPP 76543210 P 76543210 5 765 4 3/7 RED 76543 BLUE Mode 3: (24-bit per pixel True Color Mode). This mode is the 24-bit per pixel bypass mode. The three bytes of data are latched on three successive PCLK edges and the first byte is synchronized by the rising edge of BLANK. In this mode, each of the colors are 8-bit wide and the DAC is an 8-bit wide DAC. The first byte is blue followed by green and red. This mode can be selected by setting bits CR7-CR4 to 0100 or 1110. The DAC outputs changes every three cycles and the pipeline delay from the first byte to output is five cycles. 24-bit Color Mode 3 Pixel Description THIRD BYTE _|SECOND BYTE FIRST BYTE PPPPPPPP 7654321 0/7 PPPPPPPP 6543210 PPPPPPPP 76543210 76543210 76543210 76543210 RED GREEN BLUE Modes 4 - 8 use the 16-bit pixel interface. Mode4: (86-bit Pseudo Color two pixels per clock) In thismode, inputs PO-P15are latched on the rising edge of every PCLK. PO- 7 and P8-P15 are used for successive addresses for the palette RAM using an internal clock that mins at twice the PCLK frequency. The DAC outputs change twice forevery PCLKand the pipeline delay from the first word to outputis one and a one half cycles. This mode can be selected by setting bits CR7-CR4 to 0001. H-78ICS5340 GENDAC Multiplexed 8-bit Pseudo Color Word Mode 4 Pixel Description PIXEL WORD PPPPPPPPPPPPP 15 1413121110 9 876543 7654321 01765 4 3 2nd PIXEL 1st PIXEL ADDRESS ADDRESS Mode 5: (16-bit pixel interface, 15-bit per color bypass Hi- Color Mode) In this mode inputs PO-P15 are the color Data and are input directly to the DAC, bypassing the color palette. The Data is latched by the rising edge of PCLK and is pipelined to the DAC. The pipeline delay from input to DAC output is 3 PCLK cycles. Each color is 5-bit wide as shown below. This mode is selected by setting bits CR7- CR&4 to 0011. 15-Bit Color Word Mode 5 Pixel Description 3LSB = set to zero PPPPPPPPPPPPPPPP 1514131211109 876543210 X17 65 4 317 65 4 3/7 65 4 3 RED GREEN BLUE Mode 6: (16-bit pixel interface, 16-bit per color bypass XGA mode) In this mode input P0-P15 are the color Data and are input directly to the DAC bypassing the color Palette. The Data is latched by the rising edge of PCLK and is pipelined to the DAC. The pipeline delay, from input to DAC output, is 3 PCLK cycles. In this mode Blue and Red colors are 5 bits wide, and Green is 6 bits wide. This mode is selected by selecting bits CR7-CR4 to 0101. 16-Bit Color Word Mode 6 Pixel Description 2LSB = set to zero (GREEN) 3LSB = set to zero (BLUE, RED) PPPPPPPPPPPPPPPP 1514131211109 876543210 765 43/765 43 2176543 RED GREEN BLUE Mode 7: (16-bit pixel interface, 24-bit per color bypass TRUE color mode) In this mode inputs PO-P15 are the color Data and are input directly to the DAC bypassing the color Palette. Two words are latched on two successive rising edge of PCLK to form the 24-bit DAC input. The first word and the lower byte of the second word form the 24-bit pixel input to the DAC. The higher byte of the second word is ignored. The low and high word synchro- nization is internally done by the rising edge of the BLANK. The pipeline delay from latching of first word to DAC output is 4 cycles and each pixel is 2 pixel clocks wide. In this mode, each of the colors are 8-bits wide and the DAC is 8-bit wide DAC. The first byte is Blue followed by Green and Red. This mode is selected by setting bits CR7-CR4 to 0111. 24-Bit Direct Color Word Mode 7 Pixel Description FIRST WORD PPPPPPPPPP 1514131211109 8 7 6 76543210 GREEN SECOND WORD PPPPPPPPPPPP 514131211109 8765 4 76543210 Mode 8: (16-bit pixel interface packed 24-bit per color bypass TRUE color mode) In this mode inputs P0-P15 are the color Data and are input directly to the DAC bypassing the color Palette. Three words are latched on three succes- sive rising edge of PCLK to form two successive 24-bit DAC inputs. The 16-bit first word and the lower byte of the second word from the first 24-bit pixel input and the second byte of the second word with the 16 bits of the third word from the second 24-bit pixel input. This cycle repeats every 3 cycles. The three word synchronization is inter- nally done by the rising edge of BLANK*. The pipeline delay from latching of first word to DAC output is 3 14 cycles and each of the colors are 8-bits wide and DAC is 8- bit wide DAC. The first byte is Blue followed by Green and Red. Repeats. This mode is selected by setting bits CR7- CR4 to 1001. H-79iICS5340 GENDAC Packed 24-bit Word Mode 8 Pixel Description 1st DAC Cycle SECOND WORD FIRST WOR) PPPPPPPPIPPPPPPPPPP 76543 2 1 0/1514131211109 8 7 6 6 wy]O 7654321017654321 0/7 RED GREEN 2nd DAC Cycle THIRD WORD PPPPPPPPPP 1514131211109 8 7 6 7 6 SECOND WORD PIPPPPPPPP 0/1514131211109 8 0 76543210 BLUE 76543210 RED Frequency Generators The ICS5340 clock synthesizer can be reprogrammed through the microprocessor interface for any set of frequencies. This is done by writing appropriate values to the PLL Parameter Register Bank (table 5). PLL Address Registers The address of the parameter register is written to the PLL address registers before accessing the parameter register. This register is accessed by register select pins RS2-RSO = 100 or 111. Z7 6 5 4 3 2 1 =0 PLL REGISTER ADDRESS 7 6 5 4 3 2 1 0 PLL Parameters Registers There are sixteen registers in the PLL parameter register (table 5). Registers 00 to 07 are for the CLKO selectable frequency list, Register 0A for CLK1 programmable fre- quency and register OE is the PLL CLKO control register. Index|} R/W | Register 00 | R/- CLKO f0 PLL Parameters (2 bytes) O01 | R/- CLKO f1 PLL Parameters (2 bytes) 02 | R/W] CLKOf2PLL Parameters (2 bytes) 03 | R/W] CLKOf3PLL Parameters (2 bytes) 04 R/W | CLKO f4 PLL Parameters (2 bytes) 05 | R/W| CLKOf5 PLL Parameters (2 bytes) 06 | R/W| CLKO f6 PLL Parameters (2 bytes) 07 | R/W | CLKOf7 PLL Parameters (2 bytes) 08 | R/- (Reserved) = 0 (2 bytes) 09 | R/- (Reserved) = 0 (2 bytes) OA | R/W] CLK1fA PLL (2 bytes) OB | R/W| CLK1B PLL (2 bytes) oc | R/- (Reserved) = 0 (2 bytes) OD | R/- (Reserved) = 0 (2 bytes) OE | R/W] PLL Control Register (1-byte) OF | R/- (Reserved) = 0 (2-byte) Table 5 - PLL Parameter Registers PLL CONTROL REGISTER Bits in this register determine internal or external CLKO select. 7 6 5 4 3 2 1 0 (RV)] (RV) |ENBL | CLK1)(RV) INTERNAL SELECT =0 =0_JINCS | SEL j = X X xX Bit 7,6,3 Reserved. Enable Internal Clock Select (INCS) for CLKO. When this bit is set to 1, the CLKO output frequency is selected by bit 2 - 0 in this register. External pins CSO - CS2 are ignored. Bit5 Clk1 Select When this bit is set to 0, fA is selected. When it issetto1,fBis selected. Default is 0, fA selected, at power up. Bit 4 Internal Clock Select for CLKO (INCS). These three bits selects the CLKO output fre- quency if bit 5 of this register is on. They are interpreted as an octal number, n, that selects fn. Default selects 0. Bit 2-0 H-80ICS5340 GENDAC PLL Data Registers The CLKO and CLK1 input frequency is determined by the parameter values in this register. These are two bytes registers; the first byte is the M-byte and the second is the N-byte. M-Byte PLL Parameter Input The M-byte has a 7-bit value (1-127) which is the feedback divider of the PLL. 7 6 5 4 3 2 1 0 Reserved M-Divider Value =0 X W xX XK X XX X N-Byte PLL Parameter Input The N-byte has two values. N1 sets a 5-bit value (1-31) for the input pre scalar and N2 is a 2-bit code for selecting 1, 2, 4, or 8 post divide clock output. 7 6 5]4 3 2 1 +90 Reserved} N2-Code N1-Divider Value =0 XX _X xX xX xX N2 Post Divide Code If mode 4 is set in the command register, CR7~CR4 equal 0001, N2 code must be 10. N2 code Divider 00 1 01 2 10 4 11 8 The block diagram of the PLL clock synthesizer is shown in figure 3. Based on the M and N values, the output frequency of the clocks is given by the following equation: (M+2) x Fre Fout = _ (N1+2) x22 M and N values should be programmed such that the frequency of the VCO is within the optimum range for duty cycle, jitter and glitch free transition. Optimum duty cycle is achieved by programming N2 for values greater than one. See the next section for programming example. Programming Example Suppose an output frequency of 25.175 MHz is desired. The reference crystal is 14.318 MHz. The VCO should be targeted to run in the 100 to 180 MHz range, so choosing a post divide of 4 gives a VCO frequency of : 4 X 25.175=101.021 MHz From the table in the previous section, we find N2 = 2 Substituting Fp-p = 14.318 and 2N? = 4 into the equationon page 17: (25.175 (M + 2) 14.318 NI +2) by trial and error: 25.175\ 4. 127 14.318 18 so M+2=127 M=125 N1+2=18 N1 = 16 so the registers are: M=125d=1111101b N=0&N2code&N1=-0&10&10000 N=01010000b Additional Information on Programming the Frequency Generator section of the GENDAC When programming the GENDAC PLL parameter regis- ters, there are many possible combinations of parameters which will give the correct output frequency. Some combinations are better than others, however. Here is a method to determine how the registers need to be set: The key guidelines come from the operation of the phase locked loop, which has the following restrictions: 1. 2MHz < fer < 32 MHz This refers to the input reference frequency. Most users simply connect a 14.318 MHz crystal to the crystal inputs, so this is not a problem. 2. 600kHz < fppp <8 MHz (N1+2) This is the frequency input to the phase detector. H-81ICS5340 GENDAC 3. 60 MHz < (M+2) f.,, < 270 MHz (N142) This is the VCO frequency. In general, the VCO should run as fast as possible, because it has lower jitter at higher frequencies. Also, running the VCO at multiples of the desired frequency allows the use of output divides, which tends to improve the duty cycle. 4. forxoand for_, < 135 MHz This is the output frequency. These rules lead to the following procedure for deter- mining the PLL parameters, assuming rules 1 and 4 are satisfied. A. Determine the value of N2 (either 1, 2, 4 or 8) by selecting the highest value of N2, which satisfies the condition N2* fo, < 270 MHz B. Calculate (M+2) _ 2N? fout (N1+2)~ __ fref C. Now (M+2) and (N1+2) must be found by trial and error. With a 14.318 MHz reference frequency, there will generally be a small output frequency error due to the resolution limit of (M+2) and (N1+2). For a given frequency tolerance, several different (M+2) and (N1+2) combinations can usually be found. Usually, a few minutes trying out numbers with a calculator will produce a workable combination. Multiplying possible values of (N1+2) by the desired ratio will indicate approximately the value of M. This method is shown in the example below. A program could be written to try all possible combinations of (M+2) and (N1+2) (3937 possible combinations), dis- card those outside error band, and select from those remaining by giving preference to ratios which use lower values of (M+2). Lower values of (M+2) and (N1+2) provide better noise rejection in the phase locked loop. Example: Suppose we are using a 14.318 MHz reference crystal and wish to output a frequency of 66 MHz withan error of no greater than 0.5%. What are the values of the PLL data registers? A. 66*8 = 528 > 250 VCO speed too high 66*4 = 264 > 250 VCO speed too high 66*2 = 132 < 250 VCO speed OK, N2 = 2, N2 code = 01 from table on page 17 of the data sheet. B. 132/14.31818 = 9.219 This is the desired frequency multiplication ratio. C. Setting (N1+2) = 3,4,...12, 13 and performing some simple calculations yields the following table: (Note that N1 cannot be 0). (N1+2) (N142)*9.219 rounded (=M+2) Actual Ratio Percent Error 3 27.657 28 9.33 -1.23 4 36.876 37 9.25 -0.34 5 46.095 46 9.20 0.21 6 55.314 55 9.17 0.57 7 64.533 65 9.29 -0.72 8 73.752 74 9.25 -0.34 9 82.971 83 9.22 -0.03 10 92.19 92 9.20 0.21 11 101.409 101 9.18 0.40 12 110.628 111 9.25 -0.34 13 119.847 120 9.23 -0.13 H-82ICS5340 GENDAC The ratio 83/9 is closest. Thus (N2+2) = 9; N2=7. (M+2) = 83;M=81. The M-byte PLL parameter word is simply 81 in binary, plus bit 7 (which must be set to 0), or 01010001. The N-byte PLL parameter word is N2 code (01) concatenated with 5 bits of N2 in binary (00111), or 00100111. Once again, bit 7 must be zero. We havechosen the combination with the least frequency error, but several other combinations are within the 0.5% tolerance. Because the lowest value of (M+2) offers the best damping, the 37/4 combination will have the best power supply rejection. This results in lower jitter due to external noise. Pref J 4 > PHASE CHG LOOP N2_ | Fout (N12) DETECT || PUMP J" FILTER[ | YOO [7] cntr [> | _l1_ |, } (M142) [~ Figure 3 - PLL Clock Synthesizer Block Diagram External Select (Internal Select PLL Control Register) C52 CS1 CSO BIT 2 BIT 1 BIT O CLK 0 Frequency 0 0 0 0 0 0 0 0 0 1 0 0 1 fl 0 1 0 0 1 0 f2 0 1 1 0 1 1 {3 1 0 0 1 0 0 4 1 0 1 1 0 1 5 1 1 0 1 1 0 6 1 1 1 1 1 1 {7 Video Clock Selection TableICS5340 GENDAC PLCK PO-P7 BLANK* RED BN ng EON GREEN mJ BLUE TN BOT ng agg System Timing - Pseudo Color, Mode 0 PLCK PO-P7 tevcn t cuax BLANK* tcHav Cc RED A ~BL oN BLANK tonav BLANK B GREEN __a__/ BLANK Sf c ~\___ BLANK tora A c BLUE \ a _ a BLANK Detailed Timing Specifications - Pseudo Color, Mode 0 BLANK ~iICS5340 GENDAC o WU UN BLANK / | PO-P7 } LOW BYTE X HIGH BYTE LOW BYTE X HIGH BYTE A A B B | | | DAC-RD | a__ 4 DAC-GR DAC-BL | 7 a__7 System Timing Bypass - 15 (5/5/5) and 16 (5/6/5) Modes 1, 2 Ons 25ns 50ns 75ns 100ns 125ns 150ns PLCK BLANK* PO-P7 DAC-BL DAC-GR ~~ DAC-RD DoT)? System Timing Bypass True Color 24 (8,8,8) Mode 3 H-85ICS5340 GENDAC GREEN BLUE L Ap ~~ D~_ 3 aNK-_ rx System Timing - Multiplexed 8-bit Pseudo Color, Mode 4 mk / V/XL/XN/SASNS XS N PO-P15 BLANK* RED ATT B \___ BLANK GREEN BLUE Am B BLANK System Timing - 16-bit Color, Mode 5 (5,5,5) and 6 (5,6,5) H-86ICS5340 GENDAC PCLK PO-P15 BLANK* GREEN BLUE & \ BLANK A \ BLANK A BLANK System Timing - 16-bit Direct True Color, Mode 7 BLANK* RED GREEN System Timing - 24-bit Packed Color, Mode 8 H-87ICS5340 GENDAC twiwH WR* RSO-RS1 DOo-D7 Basic Write Cycle Timing trLRH RD* RSO-RS1 tarav DO-D7 taLox Basic Read Cycle Timing twewu {were WR* RD* _ RSO RS1 Write to Pixel Mask Register Followed by Write Write to Pixel Mask Register Followed by Read WR* trop t Rewer RD* Read from Pixel or Pixel Address Register Read from Pixel or Pixel Address Register (Read or Write) followed by Read (Read or Write) followed by Write H-88ICS5340 GENDAC WR* RD" RSO RS1 RS2 DO-D7 twors ADDRESS ADDRESS +1 Write and Read Back Pixel Address Register (Read Mode) WR RD* RSO RS1 RS2 Do-D7 t wars ADDRESS ADDRESS + Write and Read Back Pixel Address Register (Write Mode) WR* RD* RSO RS1 RS2 Do-D7 t wHALS RHRLI _teaRu tan ~sF. Seek i Seay See ADDRES { RED ) GREEN BLUE ADDRESS +2 Read Color Value then Pixel Address Register (Read Mode) eee H-89ICS5340 GENDAC th wawu | twHw tw twrrce RSO RS1 RS2 Color Value Write followed by any Read t wHwii WR* t wHwe1 twawu RD* RSO RS1 RS2 { RED } { GREEN } Color Value Write followed by any Write H-90ICS5340 GENDAC WR* twHrL3 RAL _t RHA ,_t RHALZ RD* RSO RS1 RS2 Color Value Read followed by any Read WR* twrris tt awRU | Tt RHRLD | RHWL2 RD* RSO RS1 RS2 Color Value Read followed by any Write H-91ICS5340 GENDAC t warts WR* D0-D7 ADDRESS ADDRESS Write and Read back PLL Address Register (Write Mode) t wHais WR* RD* RSO RS1 RS2 DO-D7 ADDRESS Write and Read back PLL Address Register (Read Mode) H-92ICS5340 GENDAC 4 WHRL3 WR* { RHRLI { RHRL2 { RHAL RSO Ro" SS ss LJ WS VS WS J \_\ f \ FN RS1 ~ OT VT VT DO-D7 Read Two bytes PLL Register then PLL Address Register t wHrLa WR* taHAL , taurie t RHRL RSo | / \ . oo _/ \ / \__/ rst tf \\ s/s N rz [f/f \/ \__/ DO-D7 PLL 4 ADD +1 } Read One Byte PLL Register then PLL Address Register H-93ICS5340 GENDAC Monitor SENSE Signal RED, GREEN, BLUE 335V _Y <_ | 'soo SENSE} The high performance of which the ICS5340 GENDAC is capable is dependent on careful PC board layout. The use ofa four layer board (internal power and ground planes, signals on the two surface Recommended Layout layers) is recommended. The layout below shows a suggested configuration. The ground plane is continuous, but the power plane is separated into analog and digital sections as shown. Power is supplied to the analog power plane through the ferrite bead, and bypassed at the power entry point by C3, a 10 uF tantalum capacitor. These high current connections should have multiple vias to the ground and power planes, if possible. Power connections should be connected to the analog or digital power plane, as shown in the diagram. Power pins 5 and 29 should be connected to digital power, power pins 20 and 24 to analog power. Decoupling capacitors (indicated by C1 and C2) should be placed as close to the GENDAC as possible. The analog and digital I/O lines are not shown. Analog signals (DAC outputs, Vref, Rset) should only be routed above the analog power plane. Digital signals should only be routed above the digital power plane. Cl C2 + SSSURALAGLSSERS O 61 1 62 O 6 DO 4 O 6 OO 65 O66 nd #7 1CS5340 DO 6 o1 oO 2 O03 O4 Os O 6 O?7 Os SInGERS OoOonoo0on Ci Cc o- VIA to ground plane O+ VIA to power plane C1 @luf chip capacitor c2 :luf chip capacitor c3 10uf tantulum capacitor FB1 Ferrite Bead Rl 140 ohm 1% resistor R2 100 ohm 5% resistor Y1 parallel resonant crysal cut forC , = 12 pf oOoooo00o0o0o otooood DIGITAL . Power Plane an E OoOomopo0o0 , oo000 } qo c Analog Power o Plane Island o_OICS5340 GENDAC Ordering Information ICS5340V Example: ICS XXXX M Package Type V=PLCC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device H-95