1
Standard Products
UT54ACS374/UT54ACTS374
Octal D-Type Flip-Flops with Three-State Outputs
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
1.2μ CMOS
- Latchup immune
High speed
Low power consumpti on
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 20-pin DIP
- 20-lead flatpack
UT54ACS374 - SMD 5962-96590
UT54ACTS374 - SMD 5962-96591
DESCRIPTION
The UT54ACS374 and the UT54ACTS37 4 are non -inverting
octal D type flip-flops with three-state outputs designed for driv-
ing highly capacitive or relatively low-impedance loads. The
device is suitable for buffer registers, I/O ports, and bidirectional
bus drivers.
The eight flip-flops are edge triggered D-type flip-flops. On the
positive transition of the clock the Q outputs will follow the data
(D) inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic level) or a high-impedance
state. The high-impedance third state and increased drive pro-
vide the capability to drive the bus line in a bus-organized system
without the need for interface or pull-up components.
The output control OC does not affect the internal operations of
the flip-flops. Old data can be retained or new data can be en-
tered while the outputs are off.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
PINOUTS 20-Pin DIP
Top View
20-Lead Flatpa ck
Top View
LOGIC SYMBOL
INPUTS OUTPUT
OC CLK nD nQ
L ↑H H
L ↑L L
L L X nQ0
H X X Z
1
2
3
4
5
7
6
20
19
18
17
16
14
15
OC
1Q
1D
2D
2Q
3Q
3D
VDD
8Q
8D
7D
7Q
6D
8134D 5D
6Q
9124Q 5Q
10 11VSS CLK
1
2
3
4
5
7
6
20
19
18
17
16
14
15
OC
1Q
1D
2D
2Q
3Q
3D
VDD
8Q
8D
7D
7Q
6D
8134D 5D
6Q
9124Q 5Q
10 11VSS CLK
(1)
OC EN
(3)
1D (4)
2D (7)
(2) 1Q
(6)
(5) 2Q
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC
Publication 617-12.
3D (8)
4D (13)
5D (14)
6D
3Q
(15) 6Q
(12) 5Q
(9) 4Q
(17)
7D (18)
8D (19) 8Q
(16) 7Q
(11)
CLK C1
1D
2
LOGIC DIAGRAM
OC
CLK
1D2D3D4D5D6D7D8D
(1)
(11)
(4)(7)(8)
(13)(14)(17)(18)
(2)(5)(6)(9)(12)(15)(16)(19)
1Q2Q3Q4Q5Q6Q7Q8Q
CD
CDCD
CD
C
D
CD
(3)
D CCD
QQQQ
Q
QQ
Q
3
OPERATIONAL ENVIRONMENT1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyo nd limits indicated in the opera tional sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E6 rads(Si)
SEU Thresh old 280 MeV-cm2/mg
SEL Threshold 120 MeV-cm2/mg
Neutron Fluence 1.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 7.0 V
VI/O Voltage any pin -.3 to VDD +.3 V
TSTG Storage Temperature range -65 to +150 °C
TJMaximum junction temperature +175 °C
TLS Lead temperature (soldering 5 seconds) +300 °C
ΘJC Thermal resistance junction to case 20 °C/W
IIDC input current ±10 mA
PDMaximum power dissipation 1 W
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TCTemperature range -55 to + 125 ×C
4
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low-level input voltage 1
ACTS
ACS 0.8
.3VDD
V
VIH High-level input voltage 1
ACTS
ACS .5VDD
.7VDD
V
IIN Input leakage current
ACTS/ACS VIN = VDD or VSS -1 1μA
VOL Low-level output voltage 3
ACTS
ACS IOL = 8.0mA
IOL = 100μA0.40
0.25 V
VOH High-level output voltage 3
ACTS
ACS IOH = -8.0mA
IOH = -100μA.7VDD
VDD - 0.25 V
IOZ Three-state output leakage current VO = VDD and VSS -20 20 μA
IOS Short-circuit output current 2 ,4
ACTS/ACS VO = VDD and VSS -200 200 mA
IOL Output current10
(Sink)
VIN = VDD or VSS
VOL = 0.4V
8mA
IOH Output current10
(Source)
VIN = VDD or VSS
VOH = VDD - 0.4V
-8 mA
Ptotal Power dissipatio n 2, 8, 9 CL = 50pF 1.9 mW/
MHz
IDDQ Quiescent Supply Current VDD = 5.5V 10 μA
ΔIDDQ Quiescent Supply Current Delta
ACTS For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6 mA
CIN Input capacitance 5ƒ = 1MHz @ 0V 15 pF
COUT Output capacitance 5 ƒ = 1MHz @ 0V 15 pF
5
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal ampl itude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
6
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPLH CLK to Qn 1 15 ns
tPHL CLK to Qn 1 18 ns
tPZL OC low to Qn active 1 13 ns
tPZH OC low to Qn active 1 13 ns
tPLZ OC high to Qn three-state 111 ns
tPHZ OC high to Qn three-state 1 12 ns
fMAX Maximum clock frequency 71 MHz
tSU Data setup time befo re CLK ↑5ns
tHData hold time after CLK ↑2ns
tWMinimum pulse width
CLK high, CLK low 7ns
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PACKAGING Side-Brazed Packages
8
FLATPACK PACKAGES
9
UT54ACS374/U T54ACTS374: SMD
5962 ***** ** * * **
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 20-lead ceramic bottom-brazed dual-in-line Flatpack
C = 20-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96590 = UT54ACS374
96591 = UT54AC TS374
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specif i ed.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when o rdering. QML Q and QML V not available withou t radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offer ed with a TID toler ance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-8 83 Test Method 1019 Condition A.
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