1
MARCH 2013
IDT72205LB, IDT72215LB,
IDT72225LB, IDT72235LB,
IDT72245LB
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2766/3
CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
FEATURES:
••
••
•256 x 18-bit organization array (IDT72205LB)
••
••
•512 x 18-bit organization array (IDT72215LB)
••
••
•1,024 x 18-bit organization array (IDT72225LB)
••
••
•2,048 x 18-bit organization array (IDT72235LB)
••
••
•4,096 x 18-bit organization array (IDT72245LB)
••
••
•10 ns read/write cycle time
••
••
•Empy and Full flags signal FIFO status
••
••
•Easy expandable in depth and width
••
••
•Asynchronous or coincident read and write clocks
••
••
•Programmable Almost-Empty and Almost-Full flags with
default settings
••
••
•Half-Full flag capability
••
••
•Dual-Port zero fall-through time architecture
••
••
•Output enable puts output data bus in high-impedence state
••
••
•High-performance submicron CMOS technology
••
••
•Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
••
••
•Industrial temperature range (–40°°
°°
°C to +85°°
°°
°C) is available
••
••
•Green parts available, see ordering information
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high
speed, low-power First-In, First-Out (FIFO) memories with clocked read and
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
•
•
•
•
OFFSET REGISTER
FLAG
LOGIC
/( )
READ POINTER
READ CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
WCLK D0-D17
()/
RCLK
Q0-Q17
2766 drw 01
write controls. These FIFOs are applicable for a wide variety of data buffering
needs, such as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The read clock can be tied to the write clock for single clock operation or the
two clocks can run asynchronous of one another for dual-clock operation. An
Output Enable pin (OE) is provided on the read port for three-state control of
the output.
The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),
and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The
offset loading of the programmable flags is controlled by a simple state machine,
and is initiated by asserting the Load pin (LD). A Half-Full flag (HF) is available
when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain technique. The
XI and XO pins are used to expand the FIFOs. In depth expansion configu-
ration, First Load (FL) is grounded on the first device and set to HIGH for all
other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated
using high-speed submicron CMOS technology.
2
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
PIN CONFIGURATIONS
PLCC (J68-1, order code: J)
TOP VIEW
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
18
26
19
20
22
23
24
25
21
10
11
12
13
14
15
16
17
56
44
45
46
47
48
49
50
51
52
53
54
55
57
58
59
60 V
CC
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
9 8 7 6 5 4 3 2 68 67 66 65 64 63 62 61
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2766 drw 02
D
15
D
16
V
CC
D
17
GND
RCLK
REN
LD
OE
RS
GND
EF
V
CC
Q
17
Q
16
GND
Q
15
PAE
FL
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
Q
0
Q
1
GND
Q
2
Q
3
V
CC
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D
16
D
17
GND
RCLK
V
CC
GND
Q
17
Q
16
GND
Q
15
V
CC
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
WCLK
V
CC
/
Q
0
Q
1
GND
Q
2
Q
3
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
2766 drw 03
3
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
PIN DESCRIPTION
Symbol Name I/O Description
D0–D17 Data Inputs I Data inputs for a 18-bit bus.
RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and PAF
go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
WCLK Write Clock I When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WEN Write Enable I When WEN is LOW and LD is HIGH, data is written into the FIFO on every LOW-to-HIGH transition of
WCLK. When WEN is HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF
is LOW.
RCLK Read Clock I When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
REN Read Enable I When REN is LOW, and LD is HIGH, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
When REN is HIGH, the output register holds the previous data. Data will not be read from the FIFO if the EF
is LOW.
OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
LD Load I When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
FL First Load I In the single device or width expansion configuration, FL is grounded. In the depth expansion configuration, FL
is grounded on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXI Write Expansion I In the single device or width expansion configuration, WXI is grounded. In the depth expansion configuration,
WXI is connected to WXO (Write Expansion Out) of the previous device.
RXI Read Expansion I In the single device or width expansion configuration, RXI is grounded. In the depth expansion configuration,
RXI is connected to RXO (Read Expansion Out) of the previous device.
FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO
is not full. FF is synchronized to WCLK.
EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the
FIFO is not empty. EF is synchronized to RCLK.
PAE Programmable O When PAE is LOW, the FIFO is almost empty based on the offset programmed into the FIFO. The default
Almost-Empty Flag offset at reset is 31 from empty for IDT72205LB, 63 from empty for IDT72215LB, and 127 from empty for
IDT72225LB/72235LB/72245LB.
PAF Programmable O When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset at
Almost-Full Flag reset is 31 from full for IDT72205, 63 from full for IDT72215LB, and 127 from full for IDT72225LB/72235LB/
72245LB.
WXO/HF Write Expansion O In the single device or width expansion configuration, the device is more than half full when HF is LOW. In the
Out/Half-Full Flag depth expansion configuration, a pulse is sent from WXO to WXI of the next device when the last location in the
FIFO is written.
RXO Read Expansion O In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last
Out location in the FIFO is read.
Q0–Q17 Data Outputs O Data outputs for an 18-bit bus.
VCC Power +5V power supply pins.
GND Ground Eight ground pins for the PLCC and seven gound pins for the TQFP/STQFP.
4
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
Commercial/Industrial
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.0 — — V
Commercial/Industrial
VIL(1) Input Low Voltage — — 0.8 V
Commercial/Industrial
TAOperating Temperature 0 — 70 °C
Commercial
TAOperating Temperature -40 ⎯85 °C
Industrial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol Rating Commercial Unit
VTERM Terminal Voltage –0.5 to +7.0 V
with respect to GND
TSTG Storage –55 to +125 °C
Temperature
IOUT DC Output Current –50 to +50 mA
Symbol Parameter(1) Conditions Max. Unit
CIN(2) Input VIN = 0V 10 pF
Capacitance
COUT(1,2) Output VOUT = 0V 10 pF
Capacitance
CAPACITANCE (TA = +25°C, f = 1.0MHz)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
IDT72205LB
IDT72215LB
IDT72225LB
IDT72235LB
IDT72245LB
Commercial and Industrial(1)
tCLK = 10, 15, 25 ns
Symbol Parameter Min. Typ. Max. Unit
ILI(2) Input Leakage Current (any input) –1 — 1 μA
ILO(3) Output Leakage Current –10 — 10 μA
VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — V
VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 V
ICC1(4,5,6) Active Power Supply Current — — 60 mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%V, TA = -40°C to +85°C)
NOTES:
1. Industrial Temperature Range Product for the 15ns and the 25ns speed grades are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
6. For the IDT72205/72215/72225 the typical ICC1 = 1.81 + 1.12*fS + 0.02*CL*fS (in mA);
for the IDT72235/72245 the typical ICC1 = 2.85 + 1.30*fS + 0.02*CL*fS (in mA)
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
ICC2(4,7) Standby Current — — 5 mA
5
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = -40°C to +85°C)
Commercial Commercial & Industrial(1)
IDT72205LB10 IDT72205LB15 IDT72205LB25
IDT72215LB10 IDT72215LB15 IDT72215LB25
IDT72225LB10 IDT72225LB15 IDT72225LB25
IDT72235LB10 IDT72235LB15 IDT72235LB25
IDT72245LB10 IDT72245LB15 IDT72245LB25
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fSClock Cycle Frequency — 100 — 66.7 — 40 MHz
tAData Access Time 2 6.5 2 10 2 15 ns
tCLK Clock Cycle Time 10 — 15 — 25 — ns
tCLKH Clock HIGH Time 4.5 — 6 — 10 — ns
tCLKL Clock LOW Time 4.5 — 6 — 10 — ns
tDS Data Set-up Time 3 — 4 — 6 — ns
tDH Data Hold Time 0 — 1 — 1 — ns
tENS Enable Set-up Time 3 — 4 — 6 — ns
tENH Enable Hold Time 0 — 1 — 1 — ns
tRS Reset Pulse Width(2) 10 — 15 — 25 — ns
tRSS Reset Set-up Time 8 — 10 — 15 — ns
tRSR Reset Recovery Time 8 — 10 — 15 — ns
tRSF Reset to Flag and Output Time — 15 — 20 — 25 ns
tOLZ Output Enable to Output in Low-Z(3) 0—0—0—ns
tOE Output Enable to Output Valid 3 6 3 8 3 12 ns
tOHZ Output Enable to Output in High-Z(3) 3638312ns
tWFF Write Clock to Full Flag — 6.5 — 10 — 15 ns
tREF Read Clock to Empty Flag — 6.5 — 10 — 15 ns
tPAF Clock to Asynchronous Programmable Almost-Full Flag — 17 — 24 — 26 ns
tPAE Clock to Programmable Almost-Empty Flag — 17 — 24 — 26 ns
tHF Clock to Half-Full Flag — 17 — 24 — 26 ns
tXO Clock to Expansion Out — 6.5 — 10 — 15 ns
tXI Expansion In Pulse Width 3 — 6.5 — 10 — ns
tXIS Expansion In Set-Up Time 3.5 — 5 — 10 — ns
tSKEW1 Skew time between Read Clock & Write Clock forFull Flag 5 — 6 — 10 — ns
tSKEW2(2) Skew time between Read Clock & Write Clock for Empty Flag 5—6—10—ns
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
1.1K
5V
680Ω
D.U.T.
2766 drw 04
NOTES:
1. Industrial temperature range product for the 15ns and the 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
6
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D0 - D17)
Data inputs for 18-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (FF), Half-Full Flag (HF) and Programmable Almost-Full Flag (PAF)
will be reset to HIGH after tRSF. The Empty Flag (EF) and Programmable
Almost-Empty Flag (PAE) will be reset to LOW after tRSF. During reset, the output
register is initialized to all zeros and the offset registers are initialized to their default
values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WEN)
When the WEN input is LOW and LD input is HIGH, data may be loaded into
the FIFO RAM array on the rising edge of every WCLK cycle if the device is
not full. Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow, FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle, FF will go HIGH allowing a write to
occur. The FF flag is updated on the rising edge of WCLK. WEN is ignored
when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK), when Output Enable (OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (REN)
When Read Enable is LOW and LD input is HIGH, data is loaded from the
RAM array into the output register on the rising edge of every RCLK cycle if
the device is not empty.
When the REN input is HIGH, the output register holds the previous data and
no new data is loaded into the output register. The data outputs Q0-Qn maintain
the previous data value.
Every word accessed at Qn, including the first word written to an empty
FIFO, must be requested using REN. When the last word has been read from
the FIFO, the Empty Flag (EF) will go LOW, inhibiting further read operations.
REN is ignored when the FIFO is empty. Once a write is performed, EF will
go HIGH allowing a read to occur. The EF flag is updated on the rising edge
of RCLK.
OUTPUT ENABLE (OE)
When Output Enable (OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
LOAD (LD)
The IDT72205LB/72215LB/72225LB/72235LB/72245LB devices con-
tain two 12-bit offset registers with data on the inputs, or read on the outputs.
When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs
D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH
transition of the Write Clock (WCLK). When the LD pin and (WEN) are held
LOW then data is written into the Full Offset register on the second LOW-to-HIGH
transition of (WCLK). The third transition of the write clock (WCLK) again writes
to the Empty Offset register.
However, writing all offset registers does not have to occur at one time. One
or two offset registers can be written and then by bringing the LD pin HIGH, the
FIFO is returned to normal read/write operation. When the LD pin is set LOW,
and WEN is LOW, the next offset register in sequence is written.
EMPTY OFFSET REGISTER
17 11 0
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
FULL OFFSET REGISTER
17 11 0
DEFAULT VALUE
DEFAULT VALUE
001FH (72205) 003FH (72215):
007FH (72225/72235/72245)
2766 drw 05
Figure 2. Write Offset Register
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 3. Offset Register Location and Default Values
NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
LD WEN WCLK Selection
0 0 Writing to offset registers:
Empty Offset
Full Offset
0 1 No Operation
1 0 Write Into FIFO
1 1 No Operation
7
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
When the LD pin is LOW and WEN is HIGH, the WCLK input is disabled;
then a signal at this input can neither increment the write offset register pointer,
nor execute a write.
The contents of the offset registers can be read on the output lines when the
LD pin is set LOW and REN is set LOW; then, data can be read on the LOW-
to-HIGH transition of the read clock (RCLK). The act of reading the control
registers employs a dedicated read offset register pointer. (The read and write
pointers operate independently).
A read and a write should not be performed simultaneously to the offset
registers.
FIRST LOAD (FL)
FL is grounded to indicate operation in the Single Device or Width Expansion
mode. In the Depth Expansion configuration, FL is grounded to indicate it is the
first device loaded and is set to HIGH for all other devices in the Daisy Chain.
(See Operating Configurations for further details.)
WRITE EXPANSION INPUT (WXI)
This is a dual purpose pin. WXI is grounded to indicate operation in the Single
Device or Width Expansion mode. WXI is connected to Write Expansion Out
(WXO) of the previous device in the Daisy Chain Depth Expansion mode.
READ EXPANSION INPUT (RXI)
This is a dual purpose pin. RXI is grounded to indicate operation in the Single
Device or Width Expansion mode. RXI is connected to Read Expansion Out
(RXO) of the previous device in the Daisy Chain Depth Expansion mode.
OUTPUTS:
FULL FLAG(FF)
When the FIFO is full, FF will go LOW, inhibiting further write operations.
When FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72205LB,
512 for the IDT72215LB, 1,024 for the IDT72225LB, 2,048 for the IDT72235LB
and 4,096 for the IDT72245LB.
The FF is updated on the LOW-to-HIGH transition of the write clock (WCLK).
EMPTY FLAG/ (EF)
When the FIFO is empty, EF will go LOW, inhibiting further read operations.
When EF is HIGH, the FIFO is not empty.
The EF is updated on the LOW-to-HIGH transition of the read clock (RCLK).
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full Flag (PAF) will go LOW when FIFO
reaches the Almost-Full condition. If no reads are performed after Reset (RS),
the PAF will go LOW after (256-m) writes for the IDT72205LB, (512-m) writes
for the IDT72215LB, (1,024-m) writes for the IDT72225LB, (2,048–m) writes
for the IDT72235LB and (4,096–m) writes for the IDT72245LB. The offset “m”
is defined in the FULL offset register.
If there is no Full offset specified, the PAF will be LOW when the device is
31 away from completely full for IDT72205LB, 63 away from completely full for
IDT72215LB, and 127 away from completely full for IDT72225LB/72235LB/
72245LB.
The PAF is asserted LOW on the LOW-to-HIGH transition of the write clock
(WCLK). PAF is reset to HIGH on the LOW-to-HIGH transition of the read clock
(RCLK). Thus PAF is asynchronous.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The ProgrammableAlmost-Empty Flag(PAE) will go LOW when the read
pointer is "n+1" locations less than the write pointer. The offset "n" is defined in
the EMPTY offset register.
If there is no Empty offset specified, the Programmable Almost-Empty Flag
(PAE) will be LOW when the device is 31 away from completely empty for
IDT72205LB, 63 away from completely empty for IDT72215LB, and 127 away
from completely empty for IDT72225LB/72235LB/72245LB.
The PAE is asserted LOW on the LOW-to-HIGH transition of the read clock
(RCLK). PAE is reset to HIGH on the LOW-to-HIGH transition of the write clock
(WCLK). Thus PAE is asynchronous.
WRITE EXPANSION OUT/HALF-FULL FLAG (WXO/HF)
This is a dual-purpose output. In the Single Device and Width Expansion
mode, when Write Expansion In (WXI) and Read Expansion In (RXI) are
grounded, this output acts as an indication of a half-full memory.
Number of Words in FIFO
IDT72205LB IDT72215LB IDT72225LB IDT72235LB IDT72245LB FF PAF HF PAE EF
00 0 0 0HHHLL
1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) 1 to n(1) HH H LH
(n + 1) to 128 (n + 1) to 256 (n + 1) to 512 (n + 1) to 1,024 (n + 1) to 2,048 H H H H H
129 to (256-(m+1)) 257 to (512-(m+1)) 513 to (1,024-(m+1)) 1,025 to (2,048-(m+1)) 2,049 to (4,096-(m+1))
HH L HH
(256-m)
(2)
to 255 (512-m)
(2)
to 511 (1,024-m)
(2)
to 1,023 (2,048-m)
(2)
to 2,047 (4,096-m)
(2)
to 4,095 H L L H H
256 512 1,024 2,048 4,096 L L L H H
TABLE 1 — STATUS FLAGS
NOTES:
1. n = Empty Offset (Default Values : IDT72205LB n=31, IDT72215LB n = 63, IDT72225LB/72235LB/72245LB n = 127)
2. m = Full Offset (Default Values : IDT72205LB m=31, IDT72215LB m = 63, IDT72225LB/72235LB/72245LB m = 127)
8
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
After half of the memory is filled, and at the LOW-to-HIGH transition of the next
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The HF is
asynchronous.
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO of
the previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device writes to the last location
of memory.
READ EXPANSION OUT (RXO)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXI) is connected to Read Expansion Out (RXO) of the previous device. This
output acts as a signal to the next device in the Daisy Chain by providing a pulse
when the previous device reads from the last location of memory.
DATA OUTPUTS (Q0-Q17)
Q0-Q17 are data outputs for 18-bit wide data.
, ,
,
, ,
t
t
t
t
RSF
RSF
RS
RSR
Q
0
- Q
17
t
RSF
= 0
= 1
(1)
2766 drw 06
t
RSS
NOTES:
1. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 4. Reset Timing(2)
9
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
WCLK
D0 - D17
tCLK
tCLKH tCLKL
tDS
tENS
tDH
tENH
tWFF tWFF
DATA IN VALID
NO OPERATION
RCLK
SKEW1t(1)
2766 drw 07
NOTE:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than tSKEW2, then EF may not change state until the next RCLK edge.
NO OPERATION
RCLK
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
tREF
t
REF
VALID DATA
t
A
t
OLZ
t
OE
t
OHZ
Q
0
- Q
17
WCLK
SKEW2
t
(1)
2766 drw 08
10
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
NOTES:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
Figure 7. First Data Word Latency after Reset with Simultaneous Read and Write
Figure 8. Full Flag Timing
WCLK
D0 - D17
RCLK
Q0 - Q17
tDS
tSKEW2
tENS
tREF
tA
012 3
DDDD
01
DD
(first valid write)
tOE
tOLZ
tA
tFRL
(1)
D
4
tENS
2766 drw 09
NOTE:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
DATA READ
WCLK
D
0
- D
17
RCLK
Q
0
- Q
17
t
A
t
WFF
DATA WRITE
t
WFF
t
ENH
t
ENS
t
DS
t
WFF
t
DS
DATA
WRITE
NEXT DATA READ
t
A
NO WRITE NO WRITE
DATA IN OUTPUT REGISTER
LOW
t
SKEW1
(1)
t
SKEW1
(1)
t
ENH
t
ENS
2766 drw 10
11
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
NOTE:
1. When tSKEW2 minimum specification, tFRL (maximum) = tCLK + tSKEW2. When tSKEW2 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW2 or tCLK + tSKEW2.
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 9. Empty Flag Timing
Figure 10. Write Programmable Registers
WCLK
D0 - D17
RCLK
Q0 - Q17
tDS
tENS
tA
tSKEW2
DATA WRITE 1
DATA READ
tENH
tREF
tDS
tENS
DATA WRITE 2
tENH
tREF
DATA IN OUTPUT REGISTER
tFRL(1)
LOW
2766 drw 11
tREF
tSKEW2
tFRL(1)
WCLK
tCLKH tCLKL
tCLK
tENS tENH
LD
WEN
D0–D15
tDS tDH
PAE OFFSET PAF OFFSET D0–D11
PAE OFFSET
tENS
2766 drw 12
Figure 11. Read Programmable Registers
RCLK
t
CLKH
t
CLKL
t
CLK
t
ENS
t
ENH
Q
0
–Q
15
PAE OFFSET PAF OFFSET
PAE OFFSET
UNKNOWN
t
A
t
ENS
2766 drw 13
12
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 12. Programmable Almost-Empty Flag Timing
Figure 13. Programmable Almost-Full Flag Timing
WCLK
tCLKH tCLKL
tENS tENH
tENS
tPAE n + 1 words in FIFO n words in FIFO
RCLK
tPAE
2766 drw 14
WCLK
tCLKH tCLKL
tENS tENH
tENS
tPAF
D – m + 1 words
in FIFO memory
RCLK
tPAF
(1)
2766 drw 15
D – m words
in FIFO memory(2)
(1)
D – m + 1 words in FIFO memory (1)
Figure 14. Half-Full Flag Timing
WCLK
t
ENS
t
ENH
t
ENS
t
HF
RCLK
t
HF
D/2 words in
FIFO memory
(1)
2766 drw 16
D/2 + 1 words in
FIFO memory
(2)
D/2 words in FIFO memory
(1)
t
CLKL
t
CLKH
NOTES:
1. D = maximum FIFO Depth =
256 words for the IDT72205LB, 512 words for the IDT72215LB, 1,024 words for the IDT72225LB, 2,048 words for the IDT72235LB and 4,096 words
for the IDT72245LB.
NOTE:
1. n = PAE offset. Number of data words written into FIFO already = n.
NOTES:
1. m = PAF offset. D = maximum FIFO Depth. Number of data words written into FIFO memory
= 256 - m + 1 for the IDT72205LB, 512 - m + 1 for the IDT72215LB,
1,024 - m + 1 for the IDT72225LB, 2,048 - (m + 1) for the IDT72235LB and 4,096 - (m + 1) for the IDT72245LB.
2.
256 - m words for the IDT72205LB, 512 - m words for the IDT72215LB, 1,024 - m words for the IDT72225LB, 2,048 - m words for the IDT72235LB and 4,096 - m words for
the IDT72245LB.
13
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
WCLK
tENS
tCLKH
tXO
Note 1
tXO
2766 drw 17
NOTE:
1. Write to Last Physical Location.
Figure 18. Read Expansion In Timing
RCLK
tENS
tCLKH
tXO
Note 1 tXO
2766 drw 18
RCLK
t
t
XI
XIS
2766 drw 20
NOTE:
1. Read from Last Physical Location.
Figure 16. Read Expansion Out Timing
Figure 15. Write Expansion Out Timing
Figure 17. Write Expansion In Timing
WCLK
tXI
tXIS
2766 drw 19
14
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
A single IDT
72205LB/72215LB/72225LB/72235LB/72245LB may be used
when the application requirements are for 256/512/1,024/2,048/4,096 words
or less. These FIFOs are in a single Device Configuration when the First Load
(FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs
are grounded (Figure 19).
Figure 19. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
NOTE:
1. Do not connect any output control signals directly together.
Figure 20. Block Diagram of 256 x 36, 512 x 36, 1,024 x 36, 2,048 x 36, 4,096 x 36
Synchronous FIFO Memory Used in a Width Expansion Configuration
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the Empty Flag and Full Flag. Because of variations in skew
between RCLK and WCLK, it is possible for flag assertion and deassertion to
vary by one cycle between FIFOs. To avoid problems the user must create
composite flags by ANDing the Empty Flags of every FIFO, and separately
ANDing all Full Flags. Figure 20 demonstrates a 36-word width by using two
IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Any word width can
be attained by adding additional IDT72205LB/72215LB/72225LB/72235LB/
72245LBs. Please see the Application Note AN-83.
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
READ CLOCK (RCLK)
READ ENABLE (REN)
LOAD (LD)
OUTPUT ENABLE (OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG (FF)
PROGRAMMABLE (PAE)
HALF FULL FLAG (HF)
EMPTY FLAG (EF)
PROGRAMMABLE (PAF)
RESET (RS)
72205LB
72215LB
72225LB
72235LB
72245LB
72205LB
72215LB
72225LB
72235LB
72245LB
RESET (RS)
36
36
18 18
18
18
FF FF EFEF
2766 drw 22
FIRST LOAD (FL)
READ EXPANSION IN (RXI)
WRITE EXPANSION IN (WXI)
WRITE CLOCK (WCLK)
WRITE ENABLE ( )
READ CLOCK (RCLK)
READ ENABLE ( )
LOAD ( )OUTPUT ENABLE ( )
DATA IN (D
0
- D
17
)DATA OUT (Q
0
- Q
17
)
FULL FLAG ( )
PROGRAMMABLE ( )
HALF-FULL FLAG ( )
EMPTY FLAG ( )
PROGRAMMABLE ( )
RESET ( )
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
2766 drw 21
FIRST LOAD ( )READ EXPANSION IN ( )
WRITE EXPANSION IN ( )
15
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
MARCH 2013
Figure 21. Block Diagram of 768 x 18, 1,536 x 18, 3,072 x 18, 6,144 x 18, 12,288 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
LOAD
WRITE CLOCK
WRITE ENABLE
READ CLOCK
READ ENABLE
OUTPUT ENABLE
DATA IN DATA OUT
RESET
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
FIRST LOAD ( )
Vcc
Vcc
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
IDT
72205LB
72215LB
72225LB
72235LB
72245LB
2766 drw 23
RCLK
WCLK
RCLK
WCLK
RCLK
WCLK
Dn Qn
Dn Qn
Dn Qn
DEPTH EXPANSION CONFIGURATION —
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than 256/
512/1,024/2,048/4,096 words of buffering. Figure 21 shows Depth Expansion
using three IDT72205LB/72215LB/72225LB/72235LB/72245LBs. Maximum
depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First Load (FL)
control input.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to
the Write Expansion In (WXI) pin of the next device. See Figure 21.
4.The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 21.
5.All Load (LD) pins are tied together.
6.The Half-Full Flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE
and PAF flags are not precise.
16
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1533
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
DATASHEET DOCUMENT HISTORY
10/02/2006 pgs. 1 and 16.
10/22/2008 pg. 16.
03/21/2013 pg. 1, 12, 16
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
BLANK
Clock Cycle Time (tCLK)
Speed in Nanoseconds
Process /
Temperature
Range
2766 drw24
Commercial Only
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
I
(1)
J
PF
TF
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
10
15
25
Commercial & Industrial
Commercial & Industrial
LB Low Power
X
G
(2)
Green
72205 256 x 18 Synchronous FIFO
72215 512 x 18 Synchronous FIFO
72225 1,024 x 18 Synchronous FIFO
72235 2,048 x 18 Synchronous FIFO
72245 4,096 x 18 Synchronous FIFO
X
BLANK
8
Tube or Tray
Tape and Reel
NOTES:
1. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
ORDERING INFORMATION
