MC100ES6039
Rev 2, 06/2005
Freescale Semiconductor
Technical Data
© Freescale Semiconductor, Inc., 2005. All rights reserved.
3.3 V ECL/PECL/HSTL/LVDS ÷2/4,
÷4/6 Clock Generation Chip
The MC100ES6039 is a low skew ÷2/4, ÷4/6 clock generation chip designed
explicitly for low skew clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output edges are all precisely
aligned. The device can be driven by either a differential or single-ended ECL or,
if positive power supplies are used, LVPECL input signals. In addition, by using
the VBB output, a sinusoidal source can be AC coupled into the device.
The common enable (EN) is synchronous so that the internal dividers will only
be enabled/disabled when the internal clock is already in the LOW state. This
avoids any chance of generating a runt clock pulse on the internal clock when the
device is enabled/disabled as can happen with an asynchronous control. The
internal enable flip-flop is clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the negative edge of the clock
input.
Upon startup, the internal flip-flops will attain a random state; therefore, for
systems which utilize multiple ES6039s, the master reset (MR) input must be
asserted to ensure synchronization. For systems which only use one ES6039,
the MR pin need not be exercised as the internal divider design ensures
synchronization between the ÷2/4 and the ÷4/6 outputs of a single device. All VCC
and VEE pins must be externally connected to power supply to guarantee proper
operation.
The 100ES Series contains temperature compensation.
Features
• Maximum Frequency >1.0 GHz Typical
• 50 ps Output-to-Output Skew
• PECL Mode Operating Range: VCC = 3.135 V to 3.8 V with VEE = 0 V
• ECL Mode Operating Range: VCC = 0 V with VEE = –3.135 V to –3.8 V
• Open Input Default State
• Synchronous Enable/Disable
• Master Reset for Synchronization of Multiple Chips
•V
BB Output
• LVDS and HSTL Input Compatible
• 20-Lead Pb-Free Package Available
MC100ES6039
ORDERING INFORMATION
Device Package
MC100ES6039DW SO-20
MC100ES6039DWR2 SO-20
MC100ES6039EG SO-20 (Pb-Free)
MC100ES6039EGR2 SO-20 (Pb-Free)
DW SUFFIX
20-LEAD SOIC PACKAGE
CASE 751D-07
EG SUFFIX
20-LEAD TSSOP PACKAGE
Pb-FREE PACKAGE
CASE 751D-07
Advanced Clock Drivers Device Data
2Freescale Semiconductor
MC100ES6039
Figure 1. 20-Lead Pinout (Top View)
CLKCLK MR VCC
1718 16 15 14 13 12
43 56789
Q0
11
10
Q1 Q1 Q2 Q2 Q3 Q3 VEE
EN
1920
21
VCC Q0
VBB
VCC
DIVSELb
NC
DIVSELa
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Table 1. Pin Description
Pin Function
CLK(1), CLK(1)
1. Pins will default low when left open.
ECL Diff Clock Inputs
EN(1) ECL Sync Enable
MR(1) ECL Master Reset
VBB ECL Reference Output
Q0, Q1, Q0, Q1 ECL Diff ÷2/4 Outputs
Q2, Q3, Q2, Q3 ECL Diff ÷4/6 Outputs
DIVSELa(1) ECL Freq. Select Input ÷2/4
DIVSELb(1) ECL Freq. Select Input ÷4/6
VCC ECL Positive Supply
VEE ECL Negative Supply
NC No Connect
Table 2. Function Tables
CLK EN MR Function
Z
ZZ
X
L
H
X
L
L
H
Divide
Hold Q0:3
Reset Q0:3
X = Don’t Care
Z = Low-to-High Transition
ZZ = High-to-Low Transition
DIVSELa Q0:1 Outputs
L
H
Divide by 2
Divide by 4
DIVSELb Q2:3 Outputs
L
H
Divide by 4
Divide by 6
Figure 2. Logic Diagram
CLK
CLK
EN
MR
÷2/4
Q0
Q0
Q1
Q1
÷4/6
Q2
Q2
Q3
Q3
R
R
DIVSELa
DIVSELb
VEE
Advanced Clock Drivers Device Data
Freescale Semiconductor 3
MC100ES6039
Figure 3. Timing Diagram
Figure 4. Timing Diagram
Table 3. Attributes
Characteristics Value
Internal Input Pulldown Resistor 75 kΩ
Internal Input Pullup Resistor 75 kΩ
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 4 kV
> 200 V
> 2 kV
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
CLK
Q (÷2)
Q (÷4)
Q (÷6)
tRR
CLK
RESET
Q (÷n)
Advanced Clock Drivers Device Data
4Freescale Semiconductor
MC100ES6039
Table 4. Maximum Ratings(1)
1. Maximum Ratings are those values beyond which device damage may occur.
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC PECL Mode Power Supply VEE = 0 V 3.9 V
VEE ECL Mode Power Supply VCC = 0 V –3.9 V
VIPECL Mode Input Voltage
ECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI ≤ VCC
VI ≥ VEE
3.9
–3.9
V
V
Iout Output Current Continuous
Surge
50
100
mA
mA
IBB VBB Sink/Source ± 0.5 mA
TAOperating Temperature Range –40 to +85 °C
Tstg Storage Temperature Range –65 to +150 °C
θJA Thermal Resistance (Junction-to-Ambient) 0 LFPM
500 LFPM
20 SOIC
20 SOIC
TBD
TBD
°C/W
°C/W
Table 5. DC Characteristics (VCC = 0 V, VEE = –3.8 V to –3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
1. MC100ES6139 circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
Symbol Characteristic
–40°C0°C to 85°C
Unit
Min Typ Max Min Typ Max
IEE Power Supply Current 35 60 35 60 mA
VOH Output HIGH Voltage(2)
2. All loading with 50 Ω to VCC–2.0 volts.
VCC –1150 VCC –1020 VCC –800 VCC –1200 VCC –970 VCC –750 mV
VOL Output LOW Voltage(2) VCC –1950 VCC –1620 VCC –1250 VCC –2000 VCC –1680 VCC –1300 mV
VIH Input HIGH Voltage (Single-Ended) VCC –1165 VCC –880 VCC –1165 VCC –880 mV
VIL Input LOW Voltage (Single-Ended) VCC –1810 VCC –1475 VCC –1810 VCC –1475 mV
VBB Output Reference Voltage VCC –1400 VCC –1200 VCC –1400 VCC –1200 mV
VPP Differential Input Voltage(3)
3. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.12 1.4 0.12 1.4 V
VCMR Differential Cross Point Voltage(4)
4. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
VEE+0.2 VCC–0.7 VEE+0.2 VCC–0.7 V
IIH Input HIGH Current 150 150 µA
IIL Input LOW Current 0.5 0.5 µA
Advanced Clock Drivers Device Data
Freescale Semiconductor 5
MC100ES6039
Figure 5. Typical Termination for Output Driver and Device Evaluation
Table 6. AC Characteristics (VCC = 0 V, VEE = –3.8 V to –3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 Ω to VCC –2.0 V.
Symbol Characteristic
–40°C25°C85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
fmax Maximum Frequency > 1 > 1 > 1 GHz
tPLH,
tPHL
Propagation Delay CLK, Q (Diff)
MR, Q
575
500
875
850
575
500
875
850
575
500
875
850
ps
ps
tRR Reset Recovery 200 100 200 100 200 100 ps
tsSetup Time EN, CLK
DIVSEL, CLK
200
400
120
180
200
400
120
180
200
400
120
180
ps
ps
thHold Time CLK, EN
CLK, DIVSEL
100
200
50
140
100
200
50
140
100
200
50
140
ps
ps
tPW Minimum Pulse Width MR 550 450 550 450 550 450 ps
tSKEW Within Device Skew Q, Q
Q, Q @ Same Frequency
Device-to-Device Skew(2)
2. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are
measured from the cross point of the inputs to the cross point of the outputs.
80
50
300
80
50
300
80
50
300
ps
ps
ps
tJITTER Cycle-to-Cycle Jitter (RMS 1σ)111ps
VPP Input Voltage Swing (Differential) 150 1400 150 1400 150 1400 mV
VCMR Differential Cross Point Voltage VEE+0.2 VCC–1.1 VEE+0.2 VCC–1.1 VEE+0.2 VCC–1.1 V
tr
tf
Output Rise/Fall Times Q, Q
(20% – 80%)
50 300 50 300 50 300 ps
Driver
Device
Receiver
Device
QD
50 Ω
Q D
50 Ω
VTT
VTT = VCC –- 2.0 V
Advanced Clock Drivers Device Data
6Freescale Semiconductor
MC100ES6039
PACKAGE DIMENSIONS
PAGE 1 OF 2
CASE 751D-07
ISSUE J
20-LEAD SOIC PACKAGE
Advanced Clock Drivers Device Data
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MC100ES6039
PACKAGE DIMENSIONS
PAGE 2 OF 2
CASE 751D-07
ISSUE J
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MC100ES6039
Rev. 2
06/2005
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