LP0701 P-Channel Enhancement-Mode Lateral MOSFET Features General Description * * * * * * * The LP0701 Enhancement-mode (normally-off) transistor uses a lateral MOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Ultra-Low Threshold High Input Impedance Low Input Capacitance Fast Switching Speeds Low On-Resistance Freedom from Secondary Breakdown Low Input and Output Leakage Applications * * * * * * The low threshold voltage and low on-resistance characteristics are ideally suited for handheld and battery-operated applications. Logic-Level Interfaces Solid-State Relays Battery-Operated Systems Photovoltaic Drives Analog Switches General Purpose Line Drivers Package Types 3-lead TO-92 (Top view) 8-lead SOIC (Top view) D D D D DRAIN SOURCE GATE NC NC S G See Table 3-1 and Table 3-2 for pin information. 2018 Microchip Technology Inc. DS20005447A-page 1 LP0701 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Drain-to-Source Voltage ...................................................................................................................................... BVDSS Drain-to-Gate Voltage ......................................................................................................................................... BVDGS Gate-to-Source Voltage ......................................................................................................................................... 10V Operating Ambient Temperature, TA ................................................................................................... -55C to +150C Storage Temperature, TS ..................................................................................................................... -55C to +150C Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = 25C unless otherwise specified. All DC parameters are 100% tested at 25C unless otherwise stated. Pulse test: 300 s pulse, 2% duty cycle Parameter Sym. Min. Drain-to-Source Breakdown Voltage BVDSS -16.5 -- -- V VGS = 0V, ID = -1 mA Gate Threshold Voltage VGS(th) -0.5 -0.7 -1 V VGS = VDS, ID = -1 mA VGS(th) -- -- -4 mV/C VGS = VDS, ID = -1 mA (Note 1) IGSS -- -- -100 nA VGS = 10V, VDS = 0V -- -- -100 nA VDS = -15V, VGS = 0V -- -- -1 mA VDS = 0.8 Maximum rating, VGS = 0V, TA= 125C (Note 1) Change in VGS(th) with Temperature Gate Body Leakage Current Zero-Gate Voltage Drain Current On-State Drain Current Static Drain-to-Source On-State Resistance Change in RDS(ON) with Temperature Note 1: IDSS ID(ON) RDS(ON) RDS(ON) Typ. Max. Unit Conditions -- -0.4 -- A VGS = VDS = -2V -0.6 -1 -- A VGS = VDS = -3V -1.25 -2.3 -- A VGS = VDS = -5V -- 2 4 VGS = -2V, ID = -50 mA -- 1.7 2 VGS = -3V, ID = -150 mA -- 1.3 1.5 VGS = -5V, ID = -300 mA -- -- 0.75 %/C VGS = -5V, ID = -300 mA (Note 1) Specification is obtained by characterization and is not 100% tested. DS20005447A-page 2 2018 Microchip Technology Inc. LP0701 AC ELECTRICAL CHARACTERISTICS Electrical Specifications: TA = 25C unless otherwise specified. Specification is obtained by characterization and is not 100% tested. Parameter Sym. Min. Typ. Max. Forward Transconductance GFS 500 700 -- Input Capacitance CISS -- 120 250 Common Source Output Capacitance COSS -- 100 125 pF Reverse Transfer Capacitance CRSS -- 40 60 pF Turn-On Delay Time td(ON) -- -- 20 ns tr -- -- 20 ns td(OFF) -- -- 30 ns tf -- -- 30 ns VSD -- -1.2 -1.5 V Rise Time Turn-Off Delay Time Fall Time Unit Conditions mmho VGS = -15V, ID = -1A pF V = 0V, GS VDS = -15V, f = 1 MHz VDD = -15V, ID = -1.25A, RGEN = 25 DIODE PARAMETER Diode Forward Voltage Drop Note 1: VGS = 0V, ISD = -500 mA (Note 1) Unless otherwise stated, all DC parameters are 100% tested at 25C. Pulse test: 300 s pulse, 2% duty cycle. TEMPERATURE SPECIFICATIONS Parameter Sym. Min. Typ. Max. Unit Operating Ambient Temperature TA -55 -- +150 C Storage Temperature TS -55 -- +150 C 3-lead TO-92 JA -- 132 -- C/W 8-lead SOIC JA -- 101 -- C/W Conditions TEMPERATURE RANGE PACKAGE THERMAL RESISTANCE Note 1: Note 1 Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm THERMAL CHARACTERISTICS ID (Note 1) (Continuous) (mA) ID (Pulsed) (A) 3-lead TO-92 -500 -1.25 8-lead SOIC -700 -1.25 Package Note 1: 2: Power Dissipation IDR (Note 1) at TA = 25C (mA) (W) 1 1.5 (Note 2) IDRM (mA) -500 -1.25 -700 -1.25 ID (continuous) is limited by maximum rated TJ. Mounted on an FR4 board 25 mm x 25 mm x 1.57 mm 2018 Microchip Technology Inc. DS20005447A-page 3 LP0701 2.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g. outside specified power supply range) and therefore outside the warranted range. -2.5 -2.5 VGS = -5.0V VGS = -5.0V -2.0 -2.0 ID (amperes) ID (amperes) -4V -1.5 -3V -1.0 -2V -0.5 -4V -1.5 -3V -1.0 -2V -0.5 -1V 0 0 -4 -8 -1V -12 0 -16 0 -1 -2 VDS (volts) FIGURE 2-1: Output Characteristics. FIGURE 2-4: 1.0 -4 -5 Saturation Characteristics. 2 VDS = -15V TA = -55OC 0.8 SO-8 TA = 25OC 0.6 TA = 125OC 0.4 PD (watts) GFS (seimens) -3 VDS (volts) TO-92 1 0.2 0 0 0 -2.0 -1.0 0 25 50 ID (amperes) Transconductance vs. Drain FIGURE 2-2: Current. FIGURE 2-5: Temperature. 100 125 150 Power Dissipation vs. Case 1.0 Thermal Resistance (normalized) -10 TO-92/SO-8 (pulsed) ID (amperes) 75 TC (OC) -1.0 TO-92 (DC) SO-8 (DC) -0.1 TC = 25OC -0.01 -0.1 -1.0 -10 -100 0.8 0.6 0.2 0 0.001 VDS (volts) FIGURE 2-3: Operating Area. DS20005447A-page 4 Maximum Rated Safe TO-92 TC = 25V PD = 1.0W 0.4 0.01 0.1 1.0 10 tp (seconds) FIGURE 2-6: Characteristics. Thermal Response 2018 Microchip Technology Inc. LP0701 10 VGS = -2.0V 1.1 VGS = -3.0V RDSS(ON) (ohms) BVDSS (normalized) 8 1.0 VGS = -5.0V 6 4 2 0.9 0 50 100 0 150 -1 0 TJ (OC) FIGURE 2-7: Temperature. -2 FIGURE 2-10: Current. BVDSS Variation with On-Resistance vs. Drain 1.4 VDS = -15V 1.6 1.2 VGS(th) (normalized) ID (amperes) TA = -55OC TA = 25OC -1 TA = 125OC 0 -1 -2 -3 -4 -5 1.0 1.2 0.8 1.0 RDS(ON) @ -5V, -300mA 0.4 -50 0 TJ ( C) Transfer Characteristics. FIGURE 2-11: Temperature. V(th) and RDS Variation with -10 f = 1.0MHz VDS = -10V -8 CISS VGS (volts) C (picofarads) 0.6 150 100 O 200 100 COSS CRSS 0 0.8 50 VGS (volts) FIGURE 2-8: 1.4 V(th) @ -1.0mA 0.6 0 -3 -2 ID (amperes) RDS(ON) (normalized) -50 0 -5 -10 -20V -6 238pF -4 -2 -15 0 CISS = 115pF 0 VDS (volts) FIGURE 2-9: Capacitance vs. Drain-to-Source Voltage. 2018 Microchip Technology Inc. 1 2 3 4 5 QG (nanocoulombs) FIGURE 2-12: Characteristics. Gate Drive Dynamic DS20005447A-page 5 LP0701 3.0 PIN DESCRIPTION The details on the pins of LP0701 3-lead TO-92 and 8-lead SOIC are listed in Table 3-1 and Table 3-2, respectively. Refer to Package Types for the location of pins. TABLE 3-1: 3-LEAD TO-92 PIN FUNCTION TABLE Pin Number Pin Name 1 Source Description Source 2 Gate Gate 3 Drain Drain TABLE 3-2: 8-LEAD SOIC PIN FUNCTION TABLE Pin Number Pin Name Description 1 NC No connection 2 NC No connection 3 Source 4 Gate Gate 5 Drain Drain 6 Drain Drain 7 Drain Drain 8 Drain Drain DS20005447A-page 6 Source 2018 Microchip Technology Inc. LP0701 4.0 FUNCTIONAL DESCRIPTION Figure 4-1 illustrates the switching waveforms and test circuit for LP0701. 0V INPUT Pulse Generator 10% -10V td(ON) RGEN 90% t(OFF) t(ON) tr td(OFF) D.U.T. tf INPUT 0V 90% OUTPUT VDD FIGURE 4-1: 10% OUTPUT RL 90% 10% VDD Switching Waveforms and Test Circuit. 2018 Microchip Technology Inc. DS20005447A-page 7 LP0701 5.0 PACKAGING INFORMATION 5.1 Package Marking Information 3-lead TO-92 XXXXXX XX e3 YWWNNN Legend: XX...X Y YY WW NNN e3 * Note: DS20005447A-page 8 Example LP0701 N3 e3 812325 8-lead SOIC Example XXXXXXX e3 YYWW NNN LP0701LG e3 1836 874 Product Code or Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC(R) designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for product code or customer-specific information. Package may or not include the corporate logo. 2018 Microchip Technology Inc. LP0701 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. 2018 Microchip Technology Inc. DS20005447A-page 9 LP0701 Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging. DS20005447A-page 10 2018 Microchip Technology Inc. LP0701 APPENDIX A: REVISION HISTORY Revision A (October 2018) * Converted Supertex Doc# DSFP-LP0701 to Microchip DS20005447A * Changed the package marking format * Removed the 3-lead TO-92 N3 P002, P003, P005, P013 and P014 media types * Added some sections to comply with the standard Microchip format * Made minor text changes throughout the document 2018 Microchip Technology Inc. DS20005447A-page 11 LP0701 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. XX PART NO. Package Options Device Device: Packages: Environmental: Media Types: - LP0701 = X - Environmental X Media Type P-Channel Enhancement-Mode Lateral MOSFET N3 = 3-lead TO-92 LG = 8-lead SOIC G = Lead (Pb)-free/RoHS-compliant Package (blank) = 1000/Bag for an N3 Package (blank) = 3300/Reel for an LG Package DS20005447A-page 12 Examples: a) LP0701N3-G: P-Channel EnhancementMode Lateral MOSFET, 3-lead TO-92, 1000/Bag b) LP0701LG-G: P-Channel EnhancementMode Lateral MOSFET, 8-lead SOIC, 3300/Reel 2018 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, All Rights Reserved. ISBN: 978-1-5224-3753-6 == ISO/TS 16949 == 2018 Microchip Technology Inc. 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