LP0701LG-G - Microchip Technology

 2018 Microchip Technology Inc. DS20005447A-page 1

LP0701

Features

• Ultra-Low Threshold

• High Input Impedance

• Low Input Capacitance

• Fast Switching Speeds

• Low On-Resistance

• Freedom from Secondary Breakdown

• Low Input and Output Leakage

Applications

• Logic-Level Interfaces

• Solid-State Relays

• Battery-Operated Systems

• Photovoltaic Drives

• Analog Switches

• General Purpose Line Drivers

General Description

The LP0701 Enhancement-mode (normally-off)

transistor uses a lateral MOS structure and a

well-proven silicon-gate manufacturing process. This

combination produces a device with the power

handling capabilities of bipolar transistors and the high

input impedance and positive temperature coefficient

inherent in MOS devices. Characteristic of all MOS

structures, this device is free from thermal runaway and

thermally induced secondary breakdown.

The low threshold voltage and low on-resistance

characteristics are ideally suited for handheld and

battery-operated applications.

Package Type

See Table 3-1 and Table 3-2 for pin information.

3-lead TO-92

(Top view)

GATE

SOURCE

DRAIN

8-lead SOIC

(Top view)

P-Channel Enhancement-Mode Lateral MOSFET

LP0701

DS20005447A-page 2  2018 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings†

Drain-to-Source Voltage ...................................................................................................................................... BVDSS

Drain-to-Gate Voltage ......................................................................................................................................... BVDGS

Gate-to-Source Voltage ......................................................................................................................................... ±10V

Operating Ambient Temperature, TA ................................................................................................... –55°C to +150°C

Storage Temperature, TS ..................................................................................................................... –55°C to +150°C

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only, and functional operation of the device at those or any other conditions above those

indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless

otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle

Parameter Sym. Min. Typ. Max. Unit Conditions

Drain-to-Source Breakdown Voltage BVDSS –16.5 — — V VGS = 0V, ID = –1 mA

Gate Threshold Voltage VGS(th) –0.5 –0.7 –1 V VGS = VDS, ID = –1 mA

Change in VGS(th) with Temperature VGS(th) — — –4 mV/°C VGS = VDS, ID = –1 mA

(Note 1)

Gate Body Leakage Current IGSS — — –100 nA VGS = ±10V, VDS = 0V

Zero-Gate Voltage Drain Current IDSS

— — –100 nA VDS = –15V, VGS = 0V

— — –1 mA

VDS = 0.8 Maximum rating,

VGS = 0V, TA= 125°C

(Note 1)

On-State Drain Current ID(ON)

—–0.4 — A VGS = VDS = –2V

–0.6 –1 — A VGS = VDS = –3V

–1.25 –2.3 — A VGS = VDS = –5V

Static Drain-to-Source On-State Resistance RDS(ON)

— 2 4 VGS = –2V, ID = –50 mA

—1.7 2VGS = –3V, ID = –150 mA

—1.3 1.5 VGS = –5V, ID = –300 mA

Change in RDS(ON) with Temperature RDS(ON) — — 0.75 %/°C VGS = –5V, ID = –300 mA

(Note 1)

Note 1: Specification is obtained by characterization and is not 100% tested.

AC ELECTRICAL CHARACTERISTICS

Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and is

not 100% tested.

Parameter Sym. Min. Typ. Max. Unit Conditions

Forward Transconductance GFS 500 700 —mmho VGS = –15V, ID = –1A

Input Capacitance CISS —120 250 pF VGS = 0V,

VDS = –15V,

f = 1 MHz

Common Source Output Capacitance COSS —100 125 pF

Reverse Transfer Capacitance CRSS —40 60 pF

Turn-On Delay Time td(ON) — — 20 ns

VDD = –15V,

ID = –1.25A,

RGEN = 25

Rise Time tr— — 20 ns

Turn-Off Delay Time td(OFF) — — 30 ns

Fall Time tf— — 30 ns

DIODE PARAMETER

Diode Forward Voltage Drop VSD —–1.2 –1.5 VVGS = 0V, ISD = –500 mA

(Note 1)

Note 1: Unless otherwise stated, all DC parameters are 100% tested at 25°C. Pulse test: 300 µs pulse, 2% duty

cycle.

TEMPERATURE SPECIFICATIONS

Parameter Sym. Min. Typ. Max. Unit Conditions

TEMPERATURE RANGE

Operating Ambient Temperature TA–55 —+150 °C

Storage Temperature TS–55 —+150 °C

PACKAGE THERMAL RESISTANCE

3-lead TO-92 JA —132 —°C/W

8-lead SOIC JA —101 —°C/W Note 1

Note 1: Mounted on an FR4 board, 25 mm x 25 mm x 1.57 mm

THERMAL CHARACTERISTICS

Package

ID (Note 1)

(Continuous)

(mA)

(Pulsed)

(A)

Power Dissipation

at TA = 25°C

(W)

IDR (Note 1)

(mA)

IDRM

(mA)

3-lead TO-92 –500 –1.25 1–500 –1.25

8-lead SOIC –700 –1.25 1.5 (Note 2)–700 –1.25

Note 1: ID (continuous) is limited by maximum rated TJ.

2: Mounted on an FR4 board 25 mm x 25 mm x 1.57 mm

 2018 Microchip Technology Inc. DS20005447A-page 3

LP0701

DS20005447A-page 4  2018 Microchip Technology Inc.

2.0 TYPICAL PERFORMANCE CURVES

-2.5

-2.0

-1.5

-1.0

-0.5

00 -4 -8 -12 -16

VGS = -5.0V

-4V

-3V

-2V

-1V

ID (amperes)

VDS (volts)

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g. outside specified power supply range) and therefore outside the warranted range.

FIGURE 2-1: Output Characteristics.

1.0

0.8

0.6

0.4

0.2

00-2.0

-1.0

= -55

(seimens)

(amperes)

= -15V

= 25

= 125

FIGURE 2-2: Transconductance vs. Drain

Current.

-0.1 -100-10-1.0

-0.1

-1.0

-10

-0.01

TO-92 (DC)

SO-8 (DC)

TO-92/SO-8 (pulsed)

(volts)

(amperes)

= 25

FIGURE 2-3: Maximum Rated Safe

Operating Area.

FIGURE 2-4: Saturation Characteristics.

0-1-2-3 -5-4

-4V

-3V

-2V

-1V

-2.5

-2.0

-1.5

-1.0

-0.5

(volts)

(amperes)

= -5.0V

015010050

01257525

TO-92

(watts)

(

SO-8

FIGURE 2-5: Power Dissipation vs. Case

Temperature.

Thermal Resistance (normalized)

1.0

0.8

0.6

0.4

0.2

0.001 100.01 0.1 1.0

tp (seconds)

TO-92

TC = 25V

PD = 1.0W

FIGURE 2-6: Thermal Response

Characteristics.

 2018 Microchip Technology Inc. DS20005447A-page 5

LP0701

FIGURE 2-7: BVDSS Variation with

Temperature

BVDSS (normalized)

-50 0 50 100 150

1.1

0.9

1.0

TJ (OC)

0 -1-2-3-4-5

-2

-1

= -15V

= 125OC

(amperes)

GS (volts)

= 25OC

= -55OC

FIGURE 2-8: Transfer Characteristics.

200

C (picofarads)

0 -5 -10 -15

100

f = 1.0MHz

VDS (volts)

CISS

COSS

CRSS

FIGURE 2-9: Capacitance vs.

Drain-to-Source Voltage.

FIGURE 2-10:

00-3

-1 -2

VGS = -2.0V

ID (amperes)

RDSS(ON) (ohms)

VGS = -3.0V

VGS = -5.0V

On-Resistance vs. Drain

Current.

GS(th)

(normalized)

DS(ON)

(normalized)

1.4

1.2

1.0

0.8

0.6

0.4

1.6

1.4

1.2

1.0

0.8

0.6

-50 0 50 100 150

DS(ON)

@ -5V, -300mA

(

(th)

@ -1.0mA

FIGURE 2-11: V(th) and RDS Variation with

Temperature.

(nanocoulombs)

-10

-8

-6

-4

-2

0012345

238pF

-20V

ISS

= 115pF

= -10V

(volts)

FIGURE 2-12: Gate Drive Dynamic

Characteristics.

LP0701

DS20005447A-page 6  2018 Microchip Technology Inc.

3.0 PIN DESCRIPTION

The details on the pins of LP0701 3-lead TO-92 and

8-lead SOIC are listed in Ta b l e 3-1 and Tab le 3-2,

respectively. Refer to Package Types for the location

of pins.

TABLE 3-1: 3-LEAD TO-92 PIN FUNCTION TABLE

Pin Number Pin Name Description

1Source Source

2Gate Gate

3Drain Drain

TABLE 3-2: 8-LEAD SOIC PIN FUNCTION TABLE

Pin Number Pin Name Description

1NC No connection

2NC No connection

3Source Source

4Gate Gate

5Drain Drain

6Drain Drain

7Drain Drain

8Drain Drain

 2018 Microchip Technology Inc. DS20005447A-page 7

LP0701

4.0 FUNCTIONAL DESCRIPTION

Figure 4-1 illustrates the switching waveforms and test

circuit for LP0701.

90%

10%

90% 90%

10%

Pulse

Generator

VDD

OUTPUT

D.U.T.

t(ON)

td(ON)

t(OFF)

td(OFF) tf

INPUT

GEN

INPUT

OUTPUT

VDD

-10V

FIGURE 4-1: Switching Waveforms and Test Circuit.

LP0701

DS20005447A-page 8  2018 Microchip Technology Inc.

5.0 PACKAGING INFORMATION

5.1 Package Marking Information

Legend: XX...X Product Code or Customer-specific information

Y Year code (last digit of calendar year)

YY Year code (last 2 digits of calendar year)

WW Week code (week of January 1 is week ‘01’)

NNN Alphanumeric traceability code

Pb-free JEDEC® designator for Matte Tin (Sn)

*This package is Pb-free. The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package.

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for product code or customer-specific information. Package may or

not include the corporate logo.

3-lead TO-92

YWWNNN

XXXXXX

XXe3

Example

812325

LP0701

N3 e3

8-lead SOIC Example

NNN

XXXXXXX

YYWW

874

LP0701LG

1836

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

 2018 Microchip Technology Inc. DS20005447A-page 9

LP0701

Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.

LP0701

DS20005447A-page 10  2018 Microchip Technology Inc.

 2018 Microchip Technology Inc. DS20005447A-page 11

LP0701

APPENDIX A: REVISION HISTORY

Revision A (October 2018)

• Converted Supertex Doc# DSFP-LP0701 to

Microchip DS20005447A

• Changed the package marking format

• Removed the 3-lead TO-92 N3 P002, P003,

P005, P013 and P014 media types

• Added some sections to comply with the standard

Microchip format

• Made minor text changes throughout the

document

LP0701

DS20005447A-page 12  2018 Microchip Technology Inc.

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Examples:

a) LP0701N3-G: P-Channel Enhancement-

Mode Lateral MOSFET,

3-lead TO-92, 1000/Bag

b) LP0701LG-G: P-Channel Enhancement-

Mode Lateral MOSFET,

8-lead SOIC, 3300/Reel

PART NO.

Device

Device: LP0701 = P-Channel Enhancement-Mode Lateral

MOSFET

Packages: N3 = 3-lead TO-92

LG = 8-lead SOIC

Environmental: G = Lead (Pb)-free/RoHS-compliant Package

Media Types: (blank) = 1000/Bag for an N3 Package

(blank) = 3300/Reel for an LG Package

Package

X - X

Environmental

Media Type

Options

 2018 Microchip Technology Inc. DS20005447A-page 13

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,

CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,

JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,

maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip

Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,

SuperFlash, tinyAVR, UNI/O, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity,

JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,

PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,

QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,

SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-3753-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

QUALITYMANAGEMENTS

YSTEM

CERTIFIEDBYDNV

== ISO/TS16949==

DS20005447A-page 14  2018 Microchip Technology Inc.

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