CS4382A-CQZ - Cirrus Logic

http://www.cirrus.com

114 dB, 192 kHz 8-Channel D/A Converter

Features

Advanced Multi-bit Delta Sigma Architecture

24-bit Conversion

Up to 192 kHz Sample Rates

114 dB Dynamic Range

-100 dB THD+N

Direct Stream Digital® (DSD™) Mode

On-chip 50 kHz Filter

Matched PCM and DSD Analog Output Levels

Selectable Digital Filters

Volume Control with 1 dB Step Size and Soft

Ramp

Low Clock-jitter Sensitivity

+5 V Analog Supply, +2.5 V Digital Supply

Separate 1.8 to 5 V Logic Supplies for the

Control & Serial Ports

Description

The CS4382A is a complete 8-channel digital-to-analog

system. This D/A system includes digital de-emphasis,

1 dB step size volume control, ATAPI channel mixing,

selectable fast and slow digital interpolation filters fol-

lowed by an oversampled, multi-bit delta-sigma

modulator which includes mismatch shaping technolo-

gy that eliminates distortion due to capacitor mismatch.

Following this stage is a multi-element switched capac-

itor stage and low-pass filter with differential analog

outputs.

The CS4382A also has a proprietary DSD processor

which allows for 50 kHz on-chip filtering without an in-

termediate decimation stage. The CS4382A is available

in a 48-pin LQFP package in both Commercial (-40°C to

+85°C) and Automotive grades (-40°C to +105°C). The

CDB4382A Customer Demonstration board is also

available for device evaluation and implementation sug-

gestions. Please see “Ordering Information” on page 48

for complete details.

The CS4382A accepts PCM data at sample rates from

4 kHz to 216 kHz, DSD audio data, and delivers excel-

lent sound quality. These features are ideal for multi-

channel audio systems inclu ding SACD players, A/V re-

ceivers, digital TV’s, mixing consoles, effects

processors, sound cards, and automotive audio

systems.

Control & Serial Audio Port

Supplies = 1.8 V to 5 V

Configuration

Inte rna l V oltage

Reference

Reset

Seria l Inte rfa ce

Level Translator

Digital Supply = 2.5 V

Hardware Mode or

I2C/SPI Software Mode

Control Data

Analog Supply = 5 V

Differential

Outputs

PCM Serial

Audio Input

Volume

Controls

Digital

F ilters

Switch-Cap

DAC and

Analog Filters

Multi-bit ∆Σ

Modulators

DSD Audio

Input

DSD Processor

-50 kHz filter

E xterna l Mute

Control Mute Signals

CS4382A

JAN '09

DS618F2

2DS618F2

CS4382A

TABLE OF CONTENTS

1. PIN DESCRIPTION ................................................................................................................................. 6

2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8

RECOMMENDED OPERATING CONDITIONS .................................................................................... 8

ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8

DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ........................................................... 10

POWER AND THERMAL CHARACTERISTICS .................................................................................. 11

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 12

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ...................................... 13

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE ............................................ 13

DIGITAL CHARACTERISTI CS ......................... ... ... ... .... ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ... ...... 14

SWITCHING CHARACTERISTICS - PCM .......................................................................................... 15

SWITCHING CHARACTERISTICS - DSD ........................................................................................... 16

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT ............................................. 17

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT ...................... ... ... .... ... ... ... ... 18

3. TYPICAL CONNECTION DIAGRAM .................................................................................................. 19

4. APPLICATIONS ................................................................................................................................... 21

4.1 Master Clock .................................................................................................................................. 21

4.2 Mode Select ................................................................................................................................... 21

4.3 Digital Interface Formats ................................................................................................................ 23

4.4 Oversampling Modes ..................................................................................................................... 24

4.5 Interpolation Filter .......................................................................................................................... 24

4.6 De-emphasis .................................................................................................................................. 24

4.7 ATAPI Specification ....................................................................................................................... 25

4.8 Direct Stream Digital (DSD) Mode .......... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 26

4.9 Grounding and Power Supply Arrangements ................................................................................ 26

4.9.1 Capacitor Placement ............................................................................................................. 26

4.10 Analog Output and Filtering ............... ... .... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... .... ............ 26

4.11 Mute Control ............ .... ... ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... ......................... 27

4.12 Recommended Power-Up Sequence .......................................................................................... 28

4.12.1 Hardware Mode ................................................................................................................... 28

4.12.2 Software Mode .................................................................................................................... 28

4.13 Recommended Procedure for Switching Operational Modes ...................................................... 29

4.14 Control Port Interface ................ ...... ... .......................................................................................... 29

4.14.1 MAP Auto Increment ........................................................................................................... 29

4.14.2 I²C Mode .......... .... ... ... ................ ... .... ... ... ................ .... ... ... ... ... ................. ... ... ... ... ................ 29

4.14.2.1 I²C Write ......... ... .... ... ... ... ... ................. ... ... ... .... ... ... ................ ... .... ... ... ... ... ................ 29

4.14.2.2 I²C Read .. ... ................ ... ... .... ... ... ................ .... ... ... ... ................ .... ... ... ... ................... 30

4.14.3 SPI Mode ............................................................................................................................. 30

4.14.3.1 SPI Write ........ ... .... ... ... ... ................ .... ... ... ... .... ... ... ................ ... .... ... ... ... ... ................ 30

4.15 Memory Address Pointer (MAP) ................................................................................................. 31

4.16 INCR (Auto Map Increment Enable) ............................................................................................ 31

4.16.1 MAP4-0 (Memory Address Pointer) ....... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ................ ... ... 31

5. REGISTER QUICK REFERENCE ........................................................................................................ 32

6. REGISTER DESCRIPTION .................................................................................................................. 33

6.1 Mode Control 1 (Address 01h) ....................................................................................................... 33

6.1.1 Control Port Enable (CPEN) .. ... ... ... .... ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ... ......... 33

6.1.2 Freeze Controls (FREEZE) ................................................................................................... 33

6.1.3 Master Clock Divide Enable (MCLKDIV) ............................................................................... 33

6.1.4 DAC Pair Disable (DACx_DIS ) . ... ... .... ... ... ................ .... ... ... ... ... .... ... ................ ... ... .... ... ... ... ...33

6.1.5 Power Down (PDN) ............................................................................................................... 34

6.2 Mode Control 2 (Address 02h) ....................................................................................................... 34

DS618F2 3

CS4382A

6.2.1 Digital Interface Format (DIF) ................................................................................................ 34

6.3 Mode Control 3 (Address 03h) ............. ... .... ... ................ ... .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 35

6.3.1 Soft Ramp and Zero Cross Control (SZC) .. .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... ... 35

6.3.2 Single Volume Control (SNGLVOL) ...................................................................................... 36

6.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... 36

6.3.4 Mutec Polarity (MUTEC+/-) ................................................................................................... 36

6.3.5 Auto-Mute (AMUTE) .............................................................................................................. 36

6.3.6 Mutec Pin Control (MUTEC) .................................................................................................. 37

6.4 Filter Control (Address 04h) ........................................................................................................... 37

6.4.1 Interpolation Filter Select (FILT_SEL) ...................................................................................37

6.4.2 De-Emphasis Control (DEM) ................................................................................................. 37

6.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN) .... ................ .... ... ... ... ... ................ 37

6.5 Invert Control (Address 05h) .......... ... ... .......................................................................................... 38

6.5.1 Invert Signal Polarity (Inv_Xx) ............................................................................................... 38

6.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)

Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)

Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)

Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh) .................................................................... 38

6.6.1 Channel A Volume = Channel B Volume (A=B) .................................................................... 38

6.6.2 ATAPI Channel Mixing and Muting (ATAPI) .......................................................................... 39

6.6.3 Functional Mode (FM) ........................................................................................................... 40

6.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0E h) ..... ... ... .... ... ... ... .... ................ ... ... ... ... 40

6.7.1 Mute (MUTE) ......................................................................................................................... 40

6.7.2 Volume Control (XX_VOL) .................................................................................................... 41

6.8 Chip Revision (Address 12h) ......................................................................................................... 41

6.8.1 Part Number ID (PART) [Read Only] .................................................................................... 41

6.8.2 Revision ID (REV) [Read Only] ............................................................................................. 41

7. FILTER PLOTS ..................................................................................................................................... 42

8. PARAMETER DEFINITIONS ................................................................................................................ 46

9. PACKAGE DIMENSIONS .................................................................................................................... 47

10. ORDERING INFORMATIO N ....................... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ... ......... 48

11. REFERENCES ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ................................... 48

12. REVISION HISTORY ...... .... ... ... ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ................... 49

4DS618F2

CS4382A

LIST OF FIGURES

Figure 1.Serial Audio Interface Timing ............... .... ... ... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... ... ................ 15

Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16

Figure 3.Control Port Timing - I²C Format . ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ............ 17

Figure 4.Control Port Timing - SPI Format ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 18

Figure 5.Typical Connection Diagram, Software Mode .......... ............. ............. ............. ............ ............. ...19

Figure 6.Typical Connection Diagram, Hardware Mode ........................................................................... 20

Figure 7.Format 0 - Left-Justified up to 24-bit Data .................................................................................. 23

Figure 8.Format 1 - I²S up to 24-bit Data .................................................................................................. 23

Figure 9.Format 2 - Right-Justified 16-bit Data ......................................................................................... 23

Figure 10.Format 3 - Right-Justified 24-bit Data ....................................................................................... 23

Figure 11.Format 4 - Right-Justified 20-bit Data ....................................................................................... 24

Figure 12.Format 5 - Right-Justified 18-bit Data ....................................................................................... 24

Figure 13.De-Emphasis Curve ........................... .... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... ................ 25

Figure 14.ATAPI Block Diagram (x = channel pair 1, 2, 3, or 4) ...... ... ... ... ... .... ... ... ... .... ... ... ... ................ ... 25

Figure 15.Full-Scale Output ............ ... .... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ................ ... ...................... 27

Figure 16.Recommended Output Filter ..................................................................................................... 27

Figure 17.Recommended Mute Circuitry ........... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 28

Figure 18.Control Port Timing, I²C Mode .................................................................................................. 30

Figure 19.Control Port Timing, SPI Mode ................................................................................................. 31

Figure 20.Single-Speed (fast) Stopband Rejection ................................................................................... 42

Figure 21.Single-Speed (fast) Transition Band ......................................................................................... 42

Figure 22.Single-Speed (fast) Transition Band (detail) ............................................................................. 42

Figure 23.Single-Speed (fast) Passband Ripple ....................................................................................... 42

Figure 24.Single-Speed (slow) Stopband Rejection ................................................................................. 42

Figure 25.Single-Speed (slow) Transition Band ........................................................................................ 42

Figure 26.Single-Speed (slow) Transition Band (detail) ............................................................................ 43

Figure 27.Single-Speed (slow) Passband Ripple ...................................................................................... 43

Figure 28.Double-Speed (fast) Stopband Rejection ................................................................................. 43

Figure 29.Double-Speed (fast) Transition Band ........................................................................................ 43

Figure 30.Double-Speed (fast) Transition Band (detail) ............................................................................ 43

Figure 31.Double-Speed (fast) Passband Ripple ...................................................................................... 43

Figure 32.Double-Speed (slow) Stopband Rejection .......... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 44

Figure 33.Double-Speed (slow) Transition Band ......... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 44

Figure 34.Double-Speed (slow) Transition Band (detail) .......... ................................................................ 44

Figure 35.Double-Speed (slow) Passband Ripple ....... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 44

Figure 36.Quad-Speed (fast) Stopband Rejection .... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 44

Figure 37.Quad-Speed (fast) Transition Band .................... ... ... ... .... ... ... ... ... .... ... ... ................ ... .... ... ......... 44

Figure 38.Quad-Speed (fast) Transition Band (det ail) ................. .... ... ... ... ... .... ... ... ... .... ... ................ ... ...... 45

Figure 39.Quad-Speed (fast) Passband Ripple ........................................................................................ 45

Figure 40.Quad-Speed (slow) Stopband Rejection ................................................................................... 45

Figure 41.Quad-Speed (slow) Transition Band ......................................................................................... 45

Figure 42.Quad-Speed (slow) Transition Band (detail) ............................................................................. 45

Figure 43.Quad-Speed (slow) Passband Ripple ....................................................................................... 45

DS618F2 5

CS4382A

LIST OF TABLES

Table 1. Common Clock Frequencies ....................................................................................................... 21

Table 2. Digital Interface Format, Stand-Alone Mode Options ............ ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 22

Table 3. Mode Selection, Stand-Alone Mode Options ........ ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .. .22

Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ........... ................ .... ... ... ... ... .... ............ 22

Table 5. Digital Interface Formats - PCM Mode ........................................................................................ 34

Table 6. Digital Interface Formats - DSD Mode ........................................................................................ 35

Table 7. ATAPI Decode .. ................ ... .... ... ... ... ... .... ... ... ................ .... ... ... ... ... .... ... ... ... ................................ 39

Table 8. Example Digital Volume Settings ................................................................................................ 41

6DS618F2

CS4382A

1. PIN DESCRIPTION

Pin Name # Pin Description

VD 4 Digital Power (Input) - Positive power supply for the digital section.

GND 5

31 Ground (Input) - Ground reference. Should be connected to analo g ground.

MCLK 6 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.

LRCK 7 Lef t Righ t Cloc k (Input) - Determines which channel, Left or Right, is currently active on the serial

audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SDIN1

SDIN2

SDIN3

SDIN4

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

SCLK 9 Serial Clock (Input) - Serial clock for the serial audio interface.

VLC 18 Control Port Power (Input) - Determines the required signal level for the Control Port. Refer to the

Recommended Operating Condition s for appropriate voltages.

RST 19 Reset (Input) - The device enters a low power mode and all intern al registers are reset to their default

settings when low.

FILT+ 20 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.

Requires the capacitive decoupling to analog ground, as shown in the Typical Conn ection Diagram.

VQ 21

Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively

coupled to analog ground, as shown in the Typical Connection Diagram. The nominal voltage level is

specified in the Analog Char acteristics and Specifications section. VQ presents an appreciable source

impedance and any current drawn from this pin will alter device pe rformance. However, VQ can be

used to bias the analog circuitry assuming there is no AC signal component and the DC current is less

than the maximum specified in the Analog Characteristics and Specifications section.

MUTEC1

MUTEC234 41

Mute Control (Output) - These pins are intended to be used as a control for external mute circuits to

prevent the clicks and pops that can occur in any single supply system. The use of external mute cir-

cuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous

clicks and pops.

SDIN3

GND

AOUTB2-

AOUTA3+

AOUTB3-

AOUTB2+

AOUTA3-

AOUTB3+

AOUTA4-

AOUTA4+

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

MCLK

DSDB1

SDIN1

TST

DSDA2

DSDA1

GND

SCLK

SDIN2

TST

LRCK(DSD_EN)

M3(DSD_SCLK)

DSDB3

DSDA3

DSDA4

CS4382A

DSDB4

VLS

SDIN4

M2(SCL/CCLK)

M1(SDA/CDIN)

VLC

RST

FILT+

MUTEC2

AOUTB4-

AOUTB4+

M0(AD0/CS)

AOUTA2+

AOUTA2-

AOUTB1+

AOUTB1-

AOUTA1-

AOUTA1+

DSDB2

MUTEC1

DS618F2 7

CS4382A

AOUTA1 +,-

AOUTB1 +,-

AOUTA2 +,-

AOUTB2 +,-

AOUTA3 +,-

AOUTB3 +,-

AOUTA4 +,-

AOUTB4 +,-

39, 40

38, 37

35, 36

34, 33

29, 30

28, 27

25, 26

24, 23

Differential Analog Output (Output) - The full-scale diff erential analog output level is specified in the

Analog Characteristics specification table.

VA 32 Analog Power (Input) - Positive power supply for the analog section.

VLS 43 Serial Audio Interface Power (Input) - Dete rmines the required signal level for the serial au dio inter-

face. Refer to the Recommended Operating Conditions for appropriate voltages.

TST 10

12 Test - These pin s ne ed to be tied to analog ground.

Soft ware Mode Definitions

SCL/CCLK 15 Serial Control Port Clock (Input) - Serial clock for the serial Control Port. Requires an external pull-up

resistor to the logic interface voltage in I²C® Mode as shown in the Typical Connection Diagram.

SDA/CDIN 16 Serial Control Data (Input/Output) - SDA is a data I/O line in I²C Mode and requires an external pull-up

resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDIN is the input

data line for the Control Port interface in SPI™ Mode.

AD0/CS 17 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C Mode;

CS is the chip select signal for SPI format.

Stand-Alone Definitions

Mode Selection (Input) - Determines the operational mode of the devi ce .

DSD Definitions

DSD_SCLK 42 DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface.

DSD_EN 7 DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD Mode (Stand-Alo ne mode only).

DSDA1

DSDB1

DSDA2

DSDB2

DSDA3

DSDB3

DSDA4

DSDB4

Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data.

Pin Name # Pin Description

8DS618F2

CS4382A

2. CHARACTERISTICS AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

(GND = 0 V; all voltages with respect to ground.)

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to ground.)

WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Parameters Symbol Min Typ Max Units

DC Power Supply Analog Power

Digital Internal Power

Serial Data Port Interface Power

Control Port Interface Power

VLS

VLC

4.75

2.37

1.71

5.0

2.5

5.0

5.25

2.63

5.25

Ambient Operating Temperature (power applied)

Commercial Grade (-CQZ)

Automotive Grade (-DQZ) TA-40

-40 -

-+85

+105 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Analog Power

Digital Internal Power

Serial Data Port Interface Power

Control Port Interface Power

VLS

VLC

-0.3

6.0

3.2

6.0

Input Current Any Pin Except Supplies Iin -±10mA

Digital Input Voltage Serial Data Port Interface

Control Port Interface VIND-S

VIND-C

-0.3

-0.3 VLS+ 0.4

VLC+ 0.4 V

Ambient Operating Temperature (power applied) Top -55 125 °C

Storage Temperature Tstg -65 150 °C

DS618F2 9

CS4382A

DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ)

Test Conditions (unless otherwise specified): VA = VLS = VLC = 5 V; VD = 2.5 V; TA = 25°C; Full-Scale 997 Hz

input sine wave (Note 1); Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as shown in

“Typical Connection Diagram” on page 19; Measurement Bandwidth 10 Hz to 20 kHz.

Notes: 1. One-half LSB of triangular PDF dither is added to data.

2. Performance limited by 16-bit quantization noise.

3. VFS is tested under load RL and include s attenuation due to ZOUT

Parameters Symbol Min Typ Max Unit

FS = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range 24-bit A-weighted

Unweighted

16-bit A-weighted

(Note 2) Unweighted

108

105

114

111

Total Harmonic Distortion + Noise 24-bit

0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

THD+N

-100

-91

-51

-94

-74

-34

-94

-45

Idle Channel Noise / Signal-to-noise Ratio - 114 - dB

Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - 100 - ppm/°C

Analog Output

Full-scale Differential Output Voltage VFS 128%•VA132%•VA136%•VAVpp

Output Impedance (Note 3) ZOUT -130-Ω

Max DC Current Draw From an AOUT Pin IOUTmax -1.0-mA

Min AC-load Resistance RL-3-kΩ

Max Load Capacitance CL-100-pF

Quiescent Voltage VQ- 50%•V

A-VDC

Max Current draw from VQIQMAX -10-µA

10 DS618F2

CS4382A

DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ)

Test Conditions (unless otherwise specified): VA = 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1.71 to 5.25 V; VD

= 2.37 to 2.63 V; TA = -40°C to 85°C; Full-Scale 997 Hz input sine wave (Note 1); Tested under max ac-load resis-

tance; Valid with FILT+ and VQ capacitors as shown in “Typical Connection Diagram” on page 19; Measurement

Bandwidth 10 Hz to 20 kHz.

Parameters Symbol Min Typ Max Unit

FS = 48 kHz, 96 kHz, 192 kHz and DSD

Dynamic Range 24-bit A-weighted

Unweighted

16-bit A-weighted

(Note 2) Unweighted

105

102

114

111

Total Harmonic Distortion + Noise 24-bit

0 dB

-20 dB

-60 dB

(Note 2) 16-bit 0 dB

-20 dB

-60 dB

THD+N

-100

-91

-51

-94

-74

-34

-91

-42

Idle Channel Noise / Signal-to-no ise Ratio - 114 - dB

Interchannel Isolation (1 kHz) - 110 - dB

DC Accuracy

Interchannel Gain Mismatch - 0.1 - dB

Gain Drift - 100 - ppm/°C

Analog Output

Full-scale Differential Output Voltage VFS 128%•VA132%•VA136%•VAVpp

Output Impedance (Note 3) ZOUT - 130 - Ω

Max DC Current Draw From an AOUT Pin IOUTmax -1.0-mA

Min AC-load Resistance RL-3-kΩ

Max Load Capacitance CL- 100 - pF

Quiescent Voltage VQ- 50%•VA-VDC

Max Current draw from VQIQMAX -10-µA

DS618F2 11

CS4382A

POWER AND THERMAL CHARACTERISTICS

Notes: 4. Cur rent consumption increases with increasing FS within a given speed mode and is sign al-dependent.

Max values are based on highest FS and highest MCLK.

5. ILC measured with no external loading on the SDA pin.

6. Power-down Mode is defined as RST pin = Low with all clock and data lines held static.

7. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figures 5 and 6.

Parameters Symbol Min Typ Max Units

Power Supplies

Power Supply Current Normal Operation, VA= 5 V

(Note 4) VD= 2.5 V

(Note 5) Interface Current, VLC=5 V

VLS=5 V

(Note 6) Power-down State (all supplies)

ILC

ILS

Ipd

200

µA

Power Dissipation (Note 4) VA = 5V, VD = 2.5V

Normal Operation

(Note 6) Power-down -

-470

1520

-mW

Package Thermal Resistance Multi-layer

Two-layer θJA

θJA

θJC

°C/Watt

Power Supply Rejection Ratio (Note 7) (1 kHz)

(60 Hz) PSRR -

-60

40 -

-dB

12 DS618F2

CS4382A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

The filter charact er istics have been norm a lized to th e sample rate (Fs) and can be referenced to the desired sam-

ple rate by multiplying the given characteristic by Fs.

See Note 12.

Notes: 8. Slow roll-off interpolation filter is only available in Software Mode.

9. Response is clock-dependent and will scale with Fs.

10. For Single-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs.

For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs.

11. De-emphasis is available only in Single-Speed Mode; only 44.1 kHz De-emphasis is available in Hard-

ware Mode.

12. Amplitude vs. Frequency p lots of this data are available in Section 7. “Filter Plots” on page 42.

Parameter Fast Roll-Off UnitMin Typ Max

Combined Digital and On -chip Analog Filter Response - Single-Speed Mode - 48 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.454

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band 0.547 - - Fs

Stop-band Atten uation (Note 10) 102 - - dB

Group Delay - 10.4/Fs - s

De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

±0.23

±0.14

±0.09

Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.430

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band .583 - - Fs

Stop-band Atten uation (Note 10) 80 - - dB

Group Delay - 6.15/Fs - s

Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.105

.490 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band .635 - - Fs

Stop-band Atten uation (Note 10) 90 - - dB

Group Delay - 7.1/Fs - s

DS618F2 13

CS4382A

COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

(CONTINUED)

DSD COMBINED DIGITAL & ON-CHIP ANALOG FILTER RESPONSE

Parameter Slow Roll-Off (Note 8) UnitMin Typ Max

Single-Spe e d Mo d e - 48 k Hz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-0.417

0.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band .583 - - Fs

Stop-band Attenuation (Note 10) 64 - - dB

Group Delay - 7.8/Fs - s

De-emphasis Error (Note 11) Fs = 32 kHz

(Relative to 1 kHz) Fs = 44.1 kHz

Fs = 48 kHz

±0.36

±0.21

±0.14

Double-Speed Mode - 96 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.296

.499 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band .792 - - Fs

Stop-band Attenuation (Note 10) 70 - - dB

Group Delay - 5.4/Fs - s

Quad-Speed Mode - 192 kHz

Passband (Note 9) to -0.01 dB corner

to -3 dB corner 0

-.104

.481 Fs

Frequency Response 10 Hz to 20 kHz -0.01 - +0.01 dB

Stop Band .868 - - Fs

Stop-band Attenuation (Note 10) 75 - - dB

Group Delay - 6.6/Fs - s

Parameter Min Typ Max Unit

DSD Processor mode

Passband (Note 9) to -3 dB corner 0 - 50 kHz

Frequency Response 10 Hz to 20 kHz -0.05 - +0.05 dB

Roll-off 27 - - dB/Oct

14 DS618F2

CS4382A

DIGITAL CHARACTERISTICS

13. Any pin except supplies. Transient currents of up to ±100 mA on the input pins will not cause SCR latch-

up.

Parameters Symbol Min Typ Max Units

Input Leakage Current (Note 13) Iin --±10µA

Input Capacitance - 8 - pF

High-level Input Voltage Serial I/O

Control I/O VIH

VIH

70%

70% -

-VLS

VLC

Low-level Input Voltage Serial I/O

Control I/O VIL

VIL

-30%

30% VLS

VLC

Low-level Output Voltage (IOL = -1.2 mA) Control I/O = 3.3 V, 5 V

Control I/O = 1.8 V, 2.5 V VOL

VOL

-20%

25% VLC

VLC

Maximum MUTEC Drive Current Imax -3-mA

MUTEC High-level Output Voltage VOH -VA-V

MUTEC Low-level Output Voltage VOL -0-V

DS618F2 15

CS4382A

SWITCHING CHARACTERISTICS - PCM

(Inputs: Logic 0 = GND, Logic 1 = VLS, CL = 30 pF)

Notes: 14. After powering up, RST should be held low until after the power supplies and clocks are settled.

15. See Table 1 on pa ge 21 for suggested MCLK frequencies.

Parameters Symbol Min Max Units

RST pin Low Pulse Width (Note 14) 1-ms

MCLK Frequency 1.024 55.2 MHz

MCLK Duty Cycle (Note 15) 45 55 %

Input Sample Rate - LRCK Single-speed Mode

Double-speed Mode

Quad-speed Mode

100

108

216

kHz

LRCK Duty Cycle 45 55 %

SCLK Duty Cycle 45 55 %

SCLK High Time tsckh 8-ns

SCLK Low Ti me tsckl 8-ns

LRCK Edge to SCLK rising edge tlcks 5-ns

SDIN Setup Time before SCLK rising edge tds 3-ns

SDIN Hold Time af ter SCLK rising edge tdh 5-ns

SDINx

tds

SCLK

LRCK

MSB

tdh

tsckh tsckl

tlcks

MSB-1

Figure 1. Serial Audio Interface Timing

16 DS618F2

CS4382A

SWITCHING CHARACTERISTICS - DSD

(Logic 0 = AGND = DGND; Logic 1 = VLS; CL=20pF)

Parameter Symbol Min Typ Max Unit

MCLK Duty Cycle 40 - 60 %

DSD_SCLK Pulse Width Low tsclkl 160 - - ns

DSD_SCLK Pulse Width High tsclkh 160 - - ns

DSD_SCLK Frequency (64x Oversampled)

(128x Oversampled) 1.024

2.048 -

-3.2

6.4 MHz

MHz

DSD_A / _B valid to DSD_SCLK rising setup time tsdlrs 20 - - ns

DSD_SCLK rising to DSD_A or DSD_B hold time tsdh 20 - - ns

sclkh

sclkl

DSDxx

DSD_SCLK

sdlrs

tsdh

Figure 2. Direct Stream Digital - Serial Audio Input Timing

DS618F2 17

CS4382A

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Notes: 16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL .

Parameter Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RST Rising Edge to Star t tirs 500 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 16) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise T ime of SCL and SDA trc, trc -1µs

Fall Time SCL and SDA tfc, tfc -300ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Falling tack 300 1000 ns

buf thdst

hdst

low

hdd

thigh

sud

sust

susp

Stop S ta rt

Start

Stop

Repeated

SDA

SCL

irs

RST

Figure 3. Control Port Timing - I²C Format

18 DS618F2

CS4382A

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT

(Inputs: Logic 0 = GND, Logic 1 = VLC, CL=30pF)

Notes: 17. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.

18. Data must be held for sufficient time to bridge the transition time of CCLK.

19. For FSCK < 1 MHz.

Parameter Symbol Min Max Unit

CCLK Clock Frequency fsclk -6MHz

RST Rising Edge to CS Falling tsrs 500 - ns

CCLK Edge to CS Falling (Note 17) tspi 500 - ns

CS High Time Between Tran smissions tcsh 1.0 - µs

CS Falling to CCLK Edge tcss 20 - ns

CCLK Low Time tscl 66 - ns

CCLK High Time tsch 66 - ns

CDIN to CCLK Rising Setup Time tdsu 40 - ns

CCLK Rising to DATA Hold Time (Note 18) tdh 15 - ns

Rise Time of CCLK and CDIN (Note 19) tr2 - 100 ns

Fall Time of CCL K and CDIN (Note 19) tf2 - 100 ns

tr2 tf2

tdsu t

sch

tscl

CCLK

CDIN

tcss t

csh

tspi

tsrs

RST

Figure 4. Control Port Timing - SPI Format

DS618F2 19

CS4382A

3. TYPICAL CONNECTION DIAGRAM

VLS

MCLK

VD AOUTA1+

0.1 µF +1 µF

+2.5 V

SDIN1

1 µF 0.1 µF

FILT+

LRCK

SCLK

SDIN3

SDIN2

0.1 µF47 µF

0.1 µF

1 µF

0.1 µF

+1.8 V to +5 V

+5 V

SDIN4

Analog Conditioning

and Muting

AOUTA1-

AOUTB1+ 38

37 Analog Conditioning

and Muting

AOUTB1-

AOUTA2+ 35

36 Analog Conditioning

and Muting

AOUTA2-

AOUTB2+ 34

33 Analog Conditioning

and Muting

AOUTB2-

AOUTA3+ 29

30 Analog Conditioning

and Muting

AOUTA3-

AOUTB3+ 28

27 Analog Conditioning

and Muting

AOUTB3-

AOUTA4+ 25

26 Analog Conditioning

and Muting

AOUTA4-

AOUTB4+ 24

23 Analog Conditioning

and Muting

AOUTB4-

MUTEC1 41

22 Mute

Drive

MUTEC234

GND GND

Micro-

Controller

VLC

0.1 µF

+1.8 V to +5 V 18

48 DSDB2

42 DSD_SCLK

DSDA1

DSDB3

DSDA3

DSDA4

DSDB1

DSDA2

44 DSDB4

15 SCL/CCLK

SDA/CDIN

ADO/CS

RST

2 KΩ

Note: Necessary for I2C

control po rt op era tion

Note*

CS4382A

TST*

NOTETST: Pins 10 and 12

DSD

Audio

Source

220 Ω

470 Ω

Digital

Audio

Source

PCM

Figure 5. Typical Connection Diagram, Software Mode

20 DS618F2

CS4382A

VLS CS4382A

MCLK

VD AOUTA1+

0.1 µF +1 µF

+2.5 V

SDIN1

1 µF 0.1 µF

FILT+

LRCK

SCLK

SDIN3

SDIN2

0.1 µF47 µF

0.1 µF

1 µF

0.1 µF

+1.8 V to +5 V

+5 V

SDIN4

Analog Conditioning

and Muting

AOUTA1-

AOUTB1+ 38

37 Analog Conditioning

and Muting

AOUTB1-

AOUTA2+ 35

36 Analog Conditioning

and Muting

AOUTA2-

AOUTB2+ 34

33 Analog Conditioning

and Muting

AOUTB2-

AOUTA3+ 29

30 Analog Conditioning

and Muting

AOUTA3-

AOUTB3+ 28

27 Analog Conditioning

and Muting

AOUTB3-

AOUTA4+ 25

26 Analog Conditioning

and Muting

AOUTA4-

AOUTB4+ 24

23 Analog Conditioning

and Muting

AOUTB4-

MUTEC234 22

Mute

Drive

MUTEC1

GND GND

Stand-Alone

Mode

Configuration

VLC

0.1 µF

+1.8 V to +5 V 18

48 DSDB2

42 M3(DSD_SCLK)

DSDA1

DSDB3

DSDA3

DSDA4

DSDB1

DSDA2

44 DSDB4

15 M2

RST

47 KΩ

VLS NoteDSD

NoteDSD: For DSD operation:

1) LRCK must be tied to VLS and

remain static high.

2) M3 PCM stand-alone configuration

pin becomes DSD_S CLK

Mute

Drive

NoteDSD

TST

10, 12

DSD

Digital

Audio

Source

PCM

Audio

Source

220 Ω

470 Ω

47 KΩ

Optional

Figure 6. Ty pical Connection Diagram, Hardware Mode

DS618F2 21

CS4382A

4. APPLICATIONS

The CS4382A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48,

44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data is input

via the serial data input pins (SDINx). The Left/Right Clock (LRCK) determines which channel is currently being input

on SDINx, and the Serial Clock (SCL K) clocks audio data into the input data buffer.

The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, an d DSD_EN pins and in Software

Mode through I²C or SPI.

4.1 Master Clock

MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequen-

cy at which words for e ach channel are input to the device. The M CLK-to-LRCK frequency ratio is de tected

automatically during the initialization sequence by counting th e number of MCLK tra nsitions during a single

LRCK period. Internal dividers are then set to generate the proper internal clocks. Table 1 illustrates several

standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no re-

quired phase relationship, but MCLK, LRCK, and SCLK must be synchronous.

4.2 Mode Select

In Hardware Mode, operation is determined by the Mode Se lect pins. The states of these pins are continu-

ally scanned for any changes; however, the mode should only be changed while the device is in reset

(RST pin low) to ensure proper switching from one mode to anothe r. These pins require co nnection to sup-

ply or ground as outlined in Figure 6. VLC supplies M0, M1, and M2. VLS supplies M3 and DSD_EN.

Tables 2 - 4 show the deco de of these pins.

In Software Mode, the operational mode and data format are set in the FM and DIF registers. See “Digital

Interface Format (DIF)” on page 34 and “Functional Mode (FM)” on page 40.

Speed Mode

(sample-rate range)

Sample

Rate

(kHz) MCLK (MHz) Software

Mode Only

MCLK Ratio 256x 384x 512x 768x 1024x*

Single-Speed

(4 to 50 kHz) 32 8.1920 12.2880 16.3840 24.5760 32.7680

44.1 11.2896 16.9344 22.5792 33.8688 45.1584

48 12.2880 18.4320 24.5760 36.8640 49.1520

MCLK Ratio 128x 192x 256x 384x 512x*

Double-Speed

(50 to 100 kHz) 64 8.1920 12.2880 16.3840 24.5760 32.7680

88.2 11.2896 16.9344 22.5792 33.8688 45.1584

96 12.2880 18.4320 24.5760 36.8640 49.1520

MCLK Ratio 64x 96x 128x 192x 256x*

Quad-Speed

(100 to 200 kHz) 176.4 11.2896 16.9344 22.5792 33.8688 45.1584

192 12.2880 18.4320 24.5760 36.8640 49.1520

Note: These modes are only available in Software Mode by setting the MCLKDIV bit = 1.

Table 1. Common Clock Frequencies

22 DS618F2

CS4382A

(DIF1) M0

(DIF0) DESCRIPTION FORMAT FIGURE

Left-justified, up to 24-bit data 0Figure 7

I²S, up to 24-bit data 1Figure 8

Right-justified, 16-bit Data 2Figure 9

Right-justified, 24-bit Data 3Figure 10

Table 2. Digi tal Interface Format, Stand-Alone Mode Options

M3 M2

(DEM) DESCRIPTION

Single-speed without De-emphasis (4 to 50 kHz sample rate s)

Single-speed with 44.1 kHz De-Emphasis; see Figure 13

Double-speed (50 to 100 kHz sample rates)

Quad-speed (1 00 t o 200 kHz sample rates)

Table 3. Mode Selection, Stand-Alone Mode Options

DSD_EN

(LRCK) M2 M1 M0 DESCRIPTION

1 000

64x oversampled DSD data with a 4x MCLK to DSD data rate

1 001

64x oversampled DSD data with a 6x MCLK to DSD data rate

1 010

64x oversampled DSD data with a 8x MCLK to DSD data rate

1 011

64x oversampled DSD data with a 12x MCLK to DSD data rate

1 100

128x oversampled DSD dat a with a 2x MCLK to DSD data rate

1 101

128x oversampled DSD dat a with a 3x MCLK to DSD data rate

1 110

128x oversampled DSD dat a with a 4x MCLK to DSD data rate

1 111

128x oversampled DSD dat a with a 6x MCLK to DSD data rate

Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options

DS618F2 23

CS4382A

4.3 Digital Interface Formats

The serial port operates as a slave and supports the I²S, Left-justified, and Right- justified digital interface

formats with varying bit depths from 16 to 24 as shown in Figures 7-12. Data is clocked into the DAC on the

rising edge.

LRCK

SCLK

Left Channel Right Channel

SDINx +3 +2 +1+5 +4

-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB LSB MSB LSB

Figure 7. Format 0 - Left-Justified up to 24-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx +3 +2 +1+5 +4

-1 -2 -3 -4 -5 +3 +2 +1+5 +4

-1 -2 -3 -4

MSB MSB

LSB LSB

Figure 8. Format 1 - I²S up to 24-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10 6543210987

15 14 13 12 11 10

32 clocks

Figure 9. Format 2 - Right-Justified 16-bit Data

LRCK

SCLK

Left Channel

SDINx 65432107

23 22 21 20 19 18 65432107

23 22 21 20 19 18

32 clocks

Right Channel

Figure 10. Format 3 - Right-Justified 24-bit Data

24 DS618F2

CS4382A

4.4 Oversampling Modes

The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection

is determined by the DSD_EN, M3, and M2 pins in Hardware Mode or the FM bits in Software Mode. Single-

speed mode supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-speed

Mode supports inpu t sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-speed Mode

supports input sample rates up to 200 kHz and uses an oversa mpling ratio of 32x.

4.5 Interpolation Filter

To accommodate the increasingly complex requirements of digital audio systems, the CS4382A incorpo-

rates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available

in each of Sing le, Double, and Quad-Speed modes. These filters have been designed to accommodate a

variety of musical tastes and styles. The FI LT_SEL bit is used to select which filter is use d (see the “Filter

Plots” on page 42 for more details).

When in Hardware Mode, only the “fast” roll-off filter is available.

Filter specifications can be found in Section 2, and filter response plots can be found in Figures 20 to 43.

4.6 De-emphasis

The CS4382A inclu des on -chip digit al de -emph asis f ilters. The de-emphasis feature is included to accom-

modate older audio recordings that utilize pre-emphasis equalization as a means of noise reduction.

Figure 13 shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale pro-

portionally with changes in sample rate (Fs) if the input sample rate does not match the coefficient which

has been selected.

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10

10 6543210987

15 14 13 12 11 10

17 16 17 16

32 clocks

19 18 19 18

Figure 11. Format 4 - Right-Justified 20-bit Data

LRCK

SCLK

Left Channel Right Channel

SDINx 6543210987

15 14 13 12 11 10

10 6543210987

15 14 13 12 11 10

17 16 17 16

32 clocks

Figure 12. Format 5 - Right-Justified 18-bit Data

DS618F2 25

CS4382A

In Software Mode, the requ ired de-emp hasis filter coefficients for 32 kHz, 44.1 kHz, or 48 kHz are selected

via the de-emphasis contro l bits.

In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the input sam-

ple rate is not 44.1 kHz and de-emphasis has been selected, the corner frequencies of the de-emphasis

filter will be scaled by a factor of the actual Fs over 44,100.

4.7 ATAPI Specification

The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The

ATAPI functions are applied per A-B pair. Refe r to Table 8 on page 41 and Figure 14 for additional informa-

tion.

Gain

-10dB

0dB

Frequency

T2 = 15 µs

T1=50 µs

F1 F2

3.183 k Hz 10. 61 k Hz

Figure 13. De-Emphasis Curve

ΣΣ

A Channel

Volume

Control AoutAx

AoutBx

Left Channel

Audio Data

Right Channel

Audio Data

BChannel

Volume

Control

MUTE

SDINx

Figure 14. ATAPI Block Diagram (x = channel pair 1, 2, 3, o r 4)

26 DS618F2

CS4382A

4.8 Direct Stream Digital (DSD) Mode

In Stand-alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD

data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio.

In Control Port Mode, the FM bits set the device into DSD Mode (DSD_EN pin is not required to be held

high). The DIF register then controls the expected DSD rate and MCLK ratio.

During DSD operation, the PCM related pins should either be tied low or remain active with clocks (except

LRCK in Stand-alone Mode). When the DSD related pins are not being used, they should either be tied static

low or remain active with clocks (except M3 in Stand-alone Mode).

4.9 Grounding and Power Supply Arrangements

As with any high-resolu tion converter, the CS4382A re quires careful at tention to po wer supply and ground-

ing arrangements if its potential pe rforma nce is to be realized . T he Typica l Conn ection Diagra m sho ws the

recommended power arrangeme nts, with VA, VD, VLC, and VLS connected to clean supplies. If th e ground

planes are split betw een digital grou nd and analog grou nd, the GND pins of the CS4382A should be con-

nected to the analog ground plane.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwanted

coupling into the DAC.

4.9.1 Capacitor Placement

Decoupling capacitors shou ld be plac ed as clos e to the DAC as possible, with the low-value ceramic ca-

pacitor being the closest. To further minimize impedance, these capacitors should be located on the same

layer as the DAC. If desired, all supply pins with similar voltage ratings may be connected to the same

supply, but a decoupling capacitor should still be placed on each supply pin.

Notes: All decoupling capacitors should be referenced to analog ground.

The CDB4382A evaluation board demon s trates the optimum layout and power supply arrangeme nts.

4.10 Analog Output and Filtering

The application note “Design Notes for a 2-pole Filter with Differential Input” discusses the second-order

Butterworth filte r and diff er ential -to- single-e nded convert er whic h was implem ente d on the CS4 382A eva l-

uation board, CDB4382A, as seen in Figure 16. The CS4382A does not include phase or amplitude com-

pensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent

on the external analog circuitry. The off-chip filter has been designed to attenuate the typical full-scale out-

put level to below 2 Vrms.

Figure 15 shows how the full-scale differential analog output level specification is derived.

DS618F2 27

CS4382A

4.11 Mute Control

The Mute Control pins go active during power-up initialization, muting, or if the MCLK-to-LRCK ratio is in-

correct. These pins are intended to be used as control for external mute circuits to prevent the clicks and

pops that can occur in any single-ended, single-supply system. The MUTEC output pins are high impedance

at the time of reset. The external mute circuitry ne eds to be self biased int o an active state in order to be

muted during reset. Once reset has been rele ased, the MUTEC pins are active high in hardware m ode and

the active state is set by the MUTEC+/- register in software mode (see Section 6.3.4).

Figure 17 shows a single example of both an active high and an active low mute drive circuit. In these de-

signs, the pull-up and pull-down resistors have bee n especially chosen to meet the input high/lo w threshold

when used with the MMUN 2111 and MMUN2211 intern a l bias resistances of 10 kΩ.

AOUT+

AOUT-

Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp

3.85 V

2.5 V

1.15 V

3.85 V

2.5 V

1.15 V

Figure 15. Full-Scale Output

Figure 16. Recommended Output Filter

28 DS618F2

CS4382A

Use of the Mute Control function is not mandatory but recommend ed for designs requiring the absolute min-

imum in extraneous clicks and pops. Also, use of the Mute Control function can enable the system designer

to achieve idle channel noise/signal-to-noise ratios which are only limited by the external mute circuit.

4.12 Recommended Power-Up Sequence

4.12.1 Hardware Mode

1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right

clocks are locked to the appro priate frequencies, as discussed in Section 4.1. In this state, the

registers are reset to the default settings, FILT+ will remain low, and VQ will be connected to VA/2.

If RST ca n not be held low long enough the SDINx pins should remain static low until all other clocks

are stable, and if possible th e RST should be toggled low again once the system is stable.

2. Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the

Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024

LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode).

4.12.2 Software Mode

1. Hold RST low until the power supply is stable, and the master an d left/right clocks are locked to the

appropriate frequencies, as discussed in Section 4.1. In this state, the registers are reset to the default

settings; FILT+ will remain low, and VQ will be connected to VA/2.

2. Bring RST high. The device will remain in a low-power state with FILT+ low for 512 LRCK cycles in

Single-speed Mode (1024 LRCK cycles in Double-speed Mode, and 2048 LRCK cycles in Quad-

speed Mode).

3. In order to reduce the chances of clicks and pops, perform a write to the CP_EN bit prior to the

completion of approximately 512 LRCK cycles in Single-speed Mode (1024 LRCK cycles in Double-

speed Mode, and 2048 LRCK cycles in Quad-speed Mode). The desired register settings can be

loaded while keeping the PDN bit set to 1. Set the RMP_UP and RMP_DN bits to 1; then set the

format and mode control bits to the desired settings.

If more than the stated number of LRCK cycles passes before CPEN bit is written, the chip will enter

Hardware Mod e and begin to operate with the M0-M3 as the mode settings. CPEN bit may be written

at anytime, even after the Hardware sequ ence has begun. It is advised that if the CPEN bit cannot be

set in time, the SDINx pins should remain static low (this way, no audio data can be converted

incorrectly by the Hardware Mode settings).

4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs.

Figure 17. Recommended Mute Circuitry

DS618F2 29

CS4382A

4.13 Recommended Procedure for Switching Operational Modes

For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE

bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).

The mute bits may then be released after clocks have settled and the proper modes have been set.

It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met

during clock source changes.

4.14 Control Port Interface

The Control Port is used to load all the internal register settings in order to operate in Software Mode (see

the “Filter Pl ots” on p age 42). The operation of the Control Port may be completely asynchronous with the

audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain

static if no operation is required.

The Control Port operates in one of two modes: I²C or SPI.

4.14.1 MAP Auto Increment

The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also

the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and

SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or

writes of successive registers.

4.14.2 I²C Mode

In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial

Control Port clock, SCL (see Figure 18 for the clock to data relationship). There is no CS pin. Pin AD0

enables the user to alter the chip address (0 01100[AD0][R/W ]) and should be tied to VLC or GND, as re-

quired, before powering up the device . If the d evice eve r detect s a high-t o-low t ransitio n on the AD0/ CS

pin after power-up, SPI Mode will be selected.

4.14.2.1 I²C Writ e

To write to the device, follow the proced ure below while adhering to the Control Port Switching Specifica-

tions in Section 2.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

001100. The seventh b it must match the settin g o f th e AD0 pin, and the eighth must be 0. The eighth

bit of the address byte is the R/W bit.

2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This

byte points to the register to be written.

3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by

the MAP.

4. If the INCR bit (see Section 4.14.1) is set to 1, repeat the previous step until all the desired registers

are written, then initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate

a repeated START condition and follow the procedure detailed from step 1. If no further writes to other

registers are desired, initiate a STOP condition to the bus.

30 DS618F2

CS4382A

4.14.2.2 I²C Read

To read from the device, follow the procedure below while adhering to the Control Port Switching Speci-

fications.

1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be

001100. The seventh bit m ust match the setting of the AD0 pin, and the eighth must be 1. The eighth

bit of the address byte is the R/W bit.

2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register

pointed to by the MAP. The MAP register will contain the address of the last register written to the

MAP, or the default address (see Section 4.14.1) if an I²C read is the firs t operation perform ed on the

device.

3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.

4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-

tinue providing a clock and issue an ACK after each byte until all the desired registers are read; then

initiate a STOP condition to the bus.

5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate

a repeated START condition and follo w the procedure detaile d from steps 1 and 2 from the I²C Write

instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-

sired, initiate a STOP condition to the bus.

4.14.3 SPI Mode

In SPI Mode, data is clocked into the serial contro l data line, CDIN, by the serial Control Port clock, CCLK

(see Figure 19 for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and

is used to control SPI writes to the Control Port. When the device de tects a h igh-to -low tran sition on th e

AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the

rising edge of CCLK.

4.14.3.1 SPI Write

To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-

tions in Section 2.

1. Bring CS low.

2. The address byte on the CDIN pin must then be 00110000.

3. Write to the memory address pointer, MAP. This byte points to the register to be written.

4. Write the desired data to the register pointed to by the MAP.

5. If the INCR bit (see Sec tion 4.14 .1) is set to 1, repeat the previous step until all the desired registers

are written, then bring CS high.

SDA

SCL

001100 ADDR

AD0 R/W

Start

ACK DATA

1-8 ACK DATA

1-8 ACK

Stop

Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.

Note 1

Figure 18. Control Port Timing, I²C Mode

DS618F2 31

CS4382A

6. If the INCR bit is set to 0 and further SPI writes to other registers are desired, it is necessary to bring

CS high, and follow the procedure detailed from step 1. If no further writes to other register s are de-

sired, bring CS high.

4.15 Memory Address Pointer (MAP)

4.16 INCR (Auto Map Increment Enable)

Default = ‘0’

0 - Disabled

1 - Enabled

4.16.1 MAP4-0 (Memory Address Pointer)

Default = ‘00000’

76543210

INCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP0

00000000

MAP

MSB LSB

DATA

byte 1 byte n

R/W

MAP = Memory Address Pointer

ADDRESS

CHIP

CDIN

CCLK

0011000

Figure 19. Control Port Timing, SPI Mode

32 DS618F2

CS4382A

5. REGISTER QUICK REFERENCE

Addr Function 7 6 5 4 3 2 1 0

01h Mode Control 1 CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN

default 00000001

02h Mode Control 2 Reserved DIF2 DIF1 DIF0 Reserved Reserved Reserved Reserved

default 00000000

03h Mode Control 3 SZC1 SZC0 SNGLVOL RMP_UP MUTEC+/- AMUTE Reserved MUTEC

default 10000100

04h Filter Control Reserved Reserved Reserved FILT_SEL Reserve d DEM1 DEM0 RMP_DN

default 00000000

05h Invert Control INV_B4 INV_B3 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

default 00000000

06h Mixing Control

Pair 1 (AOUTx1) P1_A=B P1ATAPI4 P1ATAPI3 P1ATAPI2 P1ATAPI1 P1ATAPI0 FM1 FM0

default 00100100

07h Vol. Control A1 A1_MUTE A1_VOL6 A1_VOL5 A1_VOL4 A1_VOL3 A1_VOL2 A1_VOL1 A1_VOL0

default 00000000

08h Vol. Control B1 B1_MUTE B1_VOL6 B1_VOL5 B1_VOL4 B1_VOL3 B1_VOL2 B1_VOL1 B1_VOL0

default 00000000

09h Mixing Control

Pair 2 (AOUTx2) P2_A=B P2ATAPI4 P2ATAPI3 P2ATAPI2 P2ATAPI1 P2ATAPI0 Reserved Reserved

default 00100100

0Ah Vol. Control A2 A2_MUTE A2_VOL6 A2_VOL5 A2_VOL4 A2_VOL3 A2_VOL2 A2_VOL1 A2_VOL0

default 00000000

0Bh Vol. Control B2 B2_MUTE B2_VOL6 B2_VOL5 B2_VOL4 B2_VOL3 B2_VOL2 B2_VOL1 B2_VOL0

default 00000000

0Ch Mixing Control

Pair 3 (AOUTx3) P3_A=B P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 P3ATAPI0 Reserved Reserved

default 00100100

0Dh Vol. Control A3 A3_MUTE A3_VOL6 A3_VOL5 A3_VOL4 A3_VOL3 A3 _VOL2 A3_VOL1 A3_VOL0

default 00000000

0Eh Vol. Control B3 B3_MUTE B3_VOL6 B3_VOL5 B3_VOL4 B3_VOL3 B3_VOL2 B3_VOL1 B3_VOL0

default 00000000

0Fh Mixing Control

Pair 4 (AOUTx4) P4_A=B P4ATAPI4 P4ATAPI4 P4ATAPI2 P4ATAPI1 P4ATAPI0 Reserved Reserved

default 00100100

10h Vol. Control A4 A4_MUTE A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 A4_VOL2 A4_VOL1 A4_VOL0

default 00000000

11h Vol. Control B4 B4_MUTE B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 B4_VOL2 B4_VOL1 B4_VOL0

default 00000000

12h Chip Revision PART4 PART3 PART 2 PART1 PART0 REV2 REV1 REV0

default 01110xxx

DS618F2 33

CS4382A

6. REGISTER DESCRIPTION

Note: All registers are read/write in I²C Mode and write only in SPI, unle ss ot herwise noted.

6.1 Mode Control 1 (Address 01h)

6.1.1 Control Port Enable (CPEN)

Default = 0

0 - Disabled

1 - Enabled

Function:

This bit defaults to 0, allowing the device to power-up in Stand-Alone Mode. The Control Port Mode can

be accessed by setting this bit to 1. This will allow the operation of the device to be controlled by the reg-

isters and the pin definitions will conform to Control Port Mode. To accomplish a clean power-up, the user

should write this bit within 10 ms following the release of Re set.

6.1.2 Freeze Controls (FREEZE)

Default = 0

0 - Disabled

1 - Enabled

Function:

This function allows modifications to be made to the registers without the changes taking effect until the

FREEZE is disabled. To make multiple changes in the Control Port registers take effect simultaneously,

enable the FREEZE Bit, make all register changes, then Disable the FREEZE bit.

6.1.3 Master Clock Divide Enable (MCLKDIV)

Default = 0

0 - Disabled

1 - Enabled

Function:

The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other

internal circuitry.

6.1.4 DAC Pair Disable (DACx_DIS)

Default = 0

0 - DAC Pair x Enabled

1 - DAC Pair x Disabled

Function:

When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state.

It is advised that changes to these bits be made while the power-down (PDN) bit is enable d to eliminate

the possibility of audible artifacts.

76543210

CPEN FREEZE MCLKDIV DAC4_DIS DAC3_DIS DAC2_DIS DAC1_DIS PDN

00000001

34 DS618F2

CS4382A

6.1.5 Power Down (PDN)

Default = 1

0 - Disabled

1 - Enabled

Function:

The entire device will enter a low-power state when this function is enabled, and the contents of the control

registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be

disabled before normal operation in Control Port Mode can occur.

6.2 Mode Control 2 (Address 02h)

6.2.1 Digital Interface Format (DIF)

Default = 000 - Format 0 (Left-Justified, up to 24-bit data)

Function:

These bits select the interface format for the serial audio input. The Functional Mode bits determine

whether PCM or DSD Mode is selected.

PCM Mode: The required relationship between the Left/Right clock, serial clock and serial da ta is defined

by the Digita l Interface Format and the options are detailed in Figures 7-12.

Note: While in PCM Mode, the DIF bits shou ld only be chang ed whe n the power-do wn (PDN) b it is set

to ensure proper switching from one mode to another.

76543210

Reserved DIF2 DIF1 DIF0 Reserved Reserved Reserved Reserved

00000000

DIF2 DIF1 DIF0 DESCRIPTION Format FIGURE

0 0 0 Left-Justified, up to 24-bit data 0 7

0 0 1 I²S, up to 24-bit data 1 8

0 1 0 Right-Justified, 16-b it data 2 9

0 1 1 Right-Justified, 24-b it data 3 10

1 0 0 Right-Justified, 20-b it data 4 11

1 0 1 Right-Justified, 18-b it data 5 12

1 1 0 Reserved -

1 1 1 Reserved -

Table 5. Digital Interface Formats - PCM Mode

DS618F2 35

CS4382A

DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required

master clock-to -D SD-data-rate is defined by the Digital Interface F or ma t pin s.

6.3 Mode Control 3 (Address 03h)

6.3.1 Soft Ramp and Zero Cross Control (SZC)

Default = 10

00 - Immediate Change

01 - Zero Cross

10 - Soft Ramp

11 - Soft Ramp on Zero Crossings

Function:

Immediate Chan ge

When Immediate Change is selected, all level changes will take effect immediately in one step.

Zero Cross

Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur

on a signal zero crossing to minimize audible artifacts. The requ ested level change will occur after a time-

out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 4 8 kHz sample rate) if the signal

does not encounter a zero crossing. The zero cross function is independently monitored and implemented

for each channel.

Soft Ramp

Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-

ing, in 1/8 dB steps, from the current level to th e new level at a rate of 1 dB per 8 left/right clock periods.

Soft Ramp on Ze ro Crossing

Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes or

muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level change

will occur after a time-out period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz

sample rate) if the signal does not encounter a zero crossing. Th e zero cross funct ion is independe ntly

monitored and implemented for each channe l.

DIF2 DIF1 DIFO DESCRIPTION

0 0 0 64x oversampled DSD data with a 4x MCLK to DSD data rate

0 0 1 64x oversampled DSD data with a 6x MCLK to DSD data rate

0 1 0 64x oversampled DSD data with a 8x MCLK to DSD data rate

0 1 1 64x oversampled DSD data with a 12x MCLK to DSD data rate

1 0 0 128x oversampled DSD data with a 2x MCLK to DSD data rate

1 0 1 128x oversampled DSD data with a 3x MCLK to DSD data rate

1 1 0 128x oversampled DSD data with a 4x MCLK to DSD data rate

1 1 1 128x oversampled DSD data with a 6x MCLK to DSD data rate

Table 6. Digital Interface Formats - DSD Mod e

76543210

SZC1 SZC0 SNGLVOL RMP_UP MUTEC+/- AMUTE Reserved MUTEC

10000100

36 DS618F2

CS4382A

6.3.2 Single Volume Control (SNGLVOL)

Default = 0

0 - Disabled

1 - Enabled

Function:

The individual channel volume levels are independently controlled by their respective Volume Control

Bytes when this function is disabled. The volume on all channels is determined by the A1 Channel Volume

Control Byte, and the other Volume Control Bytes are ignored when this function is enabled.

6.3.3 Soft Volume Ramp-Up After Error (RMP_UP)

Default = 0

0 - Disabled

1 - Enabled

Function:

An un-mute will be performed after a LRCK/MCLK ratio change or error, and after changing the Functional

Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft

and Zero Cross bits in the Mode Control 3 register. When disabled, an immediate un-mute is performed

in these instances.

Notes: For best results, it is recommended that this feature be used in conju nction with the RMP_DN bit.

6.3.4 Mutec Polarity (MUTEC+/-)

Default = 0

0 - Active High

1 - Active Low

Function:

The active polarity of the MUTEC pin(s) is determined by this register. When set to 0 (default), the MUTEC

pins are high when active. When set to 1 the MUTEC pin(s) are low when active.

Note: During reset the MUTEC output pins are high impedance and the external mute circuitry will need

to be self biase d into an activ e stat e, see Se ction 4.11. Once reset has been released, the MUTEC out-

puts’ active polarity will be set by this bit.

6.3.5 Auto-Mute (AMUTE)

Default = 1

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute following the reception of 8192 consecutive audio sam-

ples of static 0 or -1. A single sample of non-static data will release the mute. Detection and muting is

done independently for each channel. The quiescent voltage on the ou tput will be retained, and the Mute

Control pin will go a ctive during the mute period. The mu ting function is affected, similar to volume control

changes, by the Soft and Zero Cross bits in the Mode Control 3 register.

DS618F2 37

CS4382A

6.3.6 Mutec Pin Control (MUTEC)

Default = 0

0 - Two Mute control signals

1 - Single mute control signal on MUTEC1

Function:

Selects how the internal mute signals are routed to the MUTEC1 and MUTEC234 pins. When set to ‘0’,

a logical AND of DAC pair 1 mute control signals are output on MUTEC1 and a logical AND of the mute

control signals of DAC pairs 2, 3, and 4 are output on MUTEC234. When set to ‘1’, a logical AND of all

DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in-

formation on the use of the mute control function se e the MUTEC1 and MUTEC234 pins in Section 5.

6.4 Filter Control (Address 04h)

6.4.1 Interpolation Filter Select (FILT_SEL)

Default = 0

0 - Fast roll-off

1 - Slow roll-off

Function:

This function allows the user to select whether the interpol ation filter has a fast or slow roll off . For filter

characteristics, please see Section 2.

6.4.2 De-Emphasis Control (DEM)

Default = 00

00 - Disabled

01 - 44.1 kHz

10 - 48 kHz

11 - 32 kHz

Function:

Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re-

sponse at 32, 44.1 or 48 kHz sample rates. (see Figure 13)

De-emphasis is only available in Sing le-Speed Mode.

6.4.3 Soft Ramp-Down Before Filter Mode Change (RMP_DN)

Default = 0

0 - Disabled

1 - Enabled

Function:

If either the FILT_SEL or DEM bits are changed, the DAC will stop conversion for a period of time to

change filter values. This bit selects how the data is effected prior to an d after the change of the filter val-

ues. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp

76543210

Reserved Reserved Reserved FILT_SEL Reserved DEM1 DEM0 RMP_DN

00000000

38 DS618F2

CS4382A

from mute to the origina l volume value after a filter-mode change according to the settings of the Soft a nd

Zero Cross bits in the Mode Control 3 register. When disabled, an immediate mute and unmute is per-

formed.

Loss of clocks or a change in the FM bits will always cause an immediate mute; unmute in these condi-

tions is affected by the RMP_UP bit.

Note: For best results, it is recommended that this feature be used in conjunction with the RMP_UP bit.

6.5 Invert Control (Address 05h)

6.5.1 Invert Signal Polarity (Inv_Xx)

Default = 0

0 - Disabled

1 - Enabled

Function:

When enabled, these bits will invert the signal polarity of their respective channels.

6.6 Mixing Control Pair 1 (Channels A1 & B1)(Address 06h)

Mixing Control Pair 2 (Channels A2 & B2)(Address 09h)

Mixing Control Pair 3 (Channels A3 & B3)(Address 0Ch)

Mixing Control Pair 4 (Channels A4 & B4)(Address 0Fh)

6.6.1 Channel A Volume = Channel B Volume (A=B)

Default = 0

0 - Disabled

1 - Enabled

Function:

The AOUTAx and AOUTBx volume levels a r e in de p end en tly controlled by the A a n d t he B Ch an n el Vo l-

ume Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter-

mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes

are ignored when this function is enabled.

76543210

INV_B4 INV_A4 INV_B3 INV_A3 INV_B2 INV_A2 INV_B1 INV_A1

00000000

76543210

Px_A=B PxATAPI4 PxATAPI3 PxATAPI2 PxATAPI1 PxATAPI0 PxFM1 PxFM0

00100100

DS618F2 39

CS4382A

6.6.2 ATAPI Channel Mixing and Muting (ATAPI)

Default = 01001 - AOUTAx =aL, AOUTBx=bR (Stereo)

Function:

The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI

functions are applied per A-B pair. Refer to Table 7 and Figure 14 for additional information.

ATAPI4 ATAPI3 ATAPI2 ATAPI1 ATAPI0 AOUTAx AOUTBx

00000 MUTE MUTE

00001 MUTE bR

00010 MUTE bL

0 0 0 1 1 MUTE b[(L+R)/2]

00100 aR MUTE

00101 aR bR

00110 aR bL

0 0 1 1 1 aR b[(L+R)/2]

01000 aL MUTE

01001 aL bR

01010 aL bL

0 1 0 1 1 aL b[(L+R)/2]

01100 a[(L+R)/2] MUTE

01101 a[(L+R)/2] bR

01110 a[(L+R)/2] bL

0 1 1 1 1 a[(L+R)/2] b[(L+R)/2]

10000 MUTE MUTE

10001 MUTE bR

10010 MUTE bL

1 0 0 1 1 MUTE [(aL+bR)/2]

10100 aR MUTE

10101 aR bR

10110 aR bL

1 0 1 1 1 aR [(bL+aR)/2]

11000 aL MUTE

11001 aL bR

11010 aL bL

1 1 0 1 1 aL [(aL+bR)/2]

11100 [(aL+bR)/2] MUTE

11101 [(aL+bR)/2] bR

11110 [(bL+aR)/2] bL

1 1 1 1 1 [(aL+bR)/2] [(aL+bR)/2]

Table 7. ATAPI Decode

40 DS618F2

CS4382A

6.6.3 Functional Mode (FM)

Default = 00

00 - Single-Speed Mode (4 to 50 kHz sample rates)

01 - Double-Speed Mode (50 to 100 kHz sample rates)

10 - Quad-Speed Mode (100 to 200 kHz sample rates)

11 - Direct Stream Digital Mode

Function:

Selects the required range of input samp le rates or DSD Mode. All DAC pairs are required to be set to the

same functional mode setting be fore a speed-mode change is accepted. When DSD Mo de is selected for

any channel pair, all pairs switch to DSD Mode.

6.7 Volume Control (Addresses 07h, 08h, 0Ah, 0Bh, 0Dh, 0Eh)

Note: These eight registers provide individual volum e and mute control for each of the eight channels.

The values for “xx” in the bit fields above are as follows:

6.7.1 Mute (MUTE)

Default = 0

0 - Disabled

1 - Enabled

Function:

The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will

be retained. The m uting function is affecte d, similarly to attenuation ch anges, by th e Soft and Zero Cross

bits. The MUTE pins will go active during the mute period according to the MUTEC bit.

76543210

xx_MUTE xx_VOL6 xx_VOL5 xx_VOL4 xx_VOL3 xx_VOL2 xx_VOL1 xx_VOL0

00000000

DS618F2 41

CS4382A

6.7.2 Volume Control (XX_VOL)

Default = 0 (No attenuation)

Function:

The Digital Volume Control registers allow independent control of the signal levels in 1 dB increments

from 0 to -127 dB. Volume settings are decoded as shown in Table 8. The volume changes are imple-

mented as dictated by the Soft and Zero Cross bits. All volume settings less than -127 dB are equivalent

to enabling the MUTE bit.

6.8 Chip Revision (Address 12h)

6.8.1 Part Number ID (PART) [Read Only]

01110 - CS4382A

6.8.2 Revision ID (REV) [Read Only]

000 - Revision A

001 - Revision B

Function:

This read-only register can be used to identify the model and revision number of the device.

Binary Code Decimal Value Volume Setting

0 0 0 0 0 0 0 0 0 dB

0 0 1 0 1 0 0 20 -20 dB

0 1 0 1 0 0 0 40 -40 dB

0 1 1 1 1 0 0 60 -60 dB

1 0 1 1 0 1 0 90 -90 dB

Table 8. Example Digital Volume Setting s

76543210

PART4 PART3 PART2 PART1 PART0 REV2 REV1 REV0

01110- - -

42 DS618F2

CS4382A

7. FILTER PLOTS

0.4 0.5 0.6 0.7 0.8 0.9 1

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 20. Single-Speed (fast) Stopband Rejectio n Figure 21. Single-Speed (fast) Tra nsi tion Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 22. Single-Speed (fast) Transition Band (detail) Figure 23. Single-Speed (fast) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

−120

−100

−80

−60

−40

−20

Frequency(normalized to Fs)

Amplitude (dB)

Figure 24. Single-Speed (slow) Stopband Rejection Figu re 25. Single-Speed (slow) Transition Band

DS618F2 43

CS4382A

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

−0.02

−0.015

−0.01

−0.005

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

−10

−9

−8

−7

−6

−5

−4

−3

−2

−1

Frequency(normalized to Fs)

Amplitude (dB)

Figure 26. Single-Speed (slow) Transition Band (detail) Figure 27. Single-Speed (slow) Passband Ripple

0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.4 0.42 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 0.6

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 28. Double-Spee d (fas t) Stop ba n d Rejec tion Figure 29. Double-Speed (fast) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 30. Double-Speed (fast) Transition Band (detail) Figure 31. Dou ble-Sp eed (fast) Passband Ripple

44 DS618F2

CS4382A

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.8

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 32. Double-Speed (slow) Stopband Rejection Figure 33. Double-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

00.05 0.1 0.15 0.2 0.25 0.3 0.35

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 34. Doub le-Speed (slow) Transition Ba nd (detail) Figure 35. Double-Speed (slow) Passband Ripple

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.2 0.3 0.4 0.5 0.6 0.7 0.8

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 36. Quad-Speed (fast) Stopband Reje ction Figure 37. Quad-Speed (fast) Transition Band

DS618F2 45

CS4382A

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.05 0.1 0.15 0.2 0.25

0.2

0.15

0.1

0.05

0.1

0.15

0.2

Frequency(normalized to Fs)

Amplitude (dB)

Figure 38. Quad-Speed (fast) Transition Band (detail) Figure 39. Quad-Speed (fast) Pass band Ripple

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

120

100

Frequency(normalized to Fs)

Amplitude (dB)

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

120

100

Frequency(normalized to Fs)

Amplitude (dB)

Figure 40. Quad-Speed (slow) Stopband Rejection Figure 41. Quad-Speed (slow) Transition Band

0.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55

Frequency(normalized to Fs)

Amplitude (dB)

0 0.02 0.04 0.06 0.08 0.1 0.12

0.02

0.015

0.01

0.005

0.01

0.015

0.02

Frequency(normalized to Fs)

Amplitude (dB)

Figure 42. Quad-Speed (slow) Transition Ban d (detail) Figure 43. Quad-Speed (slow) Passband Ripple

46 DS618F2

CS4382A

8. PARAMETER DEFINITIONS

Total Harmonic Distortion + Noise (THD+N)

The ratio of the rms value of the signal to the rms su m of all other spectral components over the specified

bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.

Dynamic Range

The ratio of the full-scale rms value of the signa l to the rms sum of all other spectral components over the

specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth

made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measure-

ment to full scale. This technique ensures that the distortion components are below the noise level and

do not affect the measuremen t. This measurement technique has be en accepted by the Audi o Engineer-

ing Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.

Interchannel Isolation

A measure of crosstalk between the left and right channels. Measured for each channel at the converter's

output with all zeros to the input under test and a full-scale signal applied to the other channel. Un its in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channels. Units in decibels.

Gain Error

The deviation from the nominal full-scale analog output for a full-scale digital input.

Gain DriftThe change in gain value with temperature. Units in ppm/°C.

DS618F2 47

CS4382A

9. PACKAGE DIMENSIONS

INCHES MILLIMETERS

DIM MIN NOM MAX MIN NOM MAX

A --- 0.055 0.063 --- 1.40 1.60

A1 0.002 0.004 0.006 0.05 0.10 0.15

B 0.007 0.009 0.011 0.17 0.22 0.27

D 0.343 0.354 0.366 8.70 9.0 BSC 9.3 0

D1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

E 0.343 0.354 0.366 8.70 9.0 BSC 9.3 0

E1 0.272 0.28 0.280 6.90 7.0 BSC 7.10

e* 0.016 0.020 0.024 0.40 0.50 BSC 0.60

L 0.018 0.24 0.030 0.45 0.60 0.75

µ 0.000° 4° 7.000° 0.00° 4° 7.00°

* Nominal pin pitch is 0.50 mm

Controlling dimension is mm.

JEDEC Designation: MS022

48L LQFP PACKAGE DRAWING

∝

48 DS618F2

CS4382A

10.ORDERING INFORMATION

11.REFERENCES

1. How to Achieve O ptimum Per formance fr om Delta-Sigma A/D & D/A Converters, by St even Harr is. Paper

presented at the 93rd Convention of the Au d i o Eng i ne ering Societ y, Oct ob er 1992.

2. CDB4382A data sheet, available at http://www.cirrus.com.

3. Design Notes for a 2-Pole Filter with Differential Input, by Steven Green. Cirrus Logic Application Note

AN48.

4. The I²C Bus Specification: Version 2.0, Philips Semiconductors, December 1998

http://www.semiconductors.philips.com.

Product Description Package Pb-Free Grade Temp Range Container Order #

CS4382A 114 dB, 192 kHz 8-

channel D/A Converter 48-pin

LQFP YES Commercial -40°C to +85°C Tray CS4382A-CQZ

Tape & Reel CS4382A-CQZR

Automotive -40°C to +105°C Tray CS4382A-DQZ

Tape & Reel CS4382A-DQZR

CDB4382A CS4382A Evaluation Board - - - - CDB4382A

DS618F2 49

CS4382A

12.REVISION HISTORY

Release Changes

PP1 Updated output impedance spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.

Improved interchannel isola tion spec in “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.

PP2 Corrected package type.

Corrected reg i ste r de scri p ti o n in “DAC Pair Disable (DACx_DIS)” on page 33.

Added note to “Digital Interface Format (DIF)” on page 34.

Added PCM mode format changeable in reset only to “Mode Sele ct” on page 21.

Updated ambient operating temperature range for Commercial and Automotive grade.

Updated “DAC Analog Characteristics - Commercial (-CQZ)” on page 9.

Updated “DAC Analog Characteristics - Automotive (-DQZ)” on page 10.

Updated “Power and Thermal Characteristics” on page 11.

Updated “Digital Characteristics” on page 14.

Updated Legal Information under “IMPORTANT NOTICE” on page 50

F2 Updated MUTEC1 and MUTEC234 description in “Pin Description” on page 6.

Updated “Mute Control” on page 27.

Updated “Mutec Polarity (MUTEC+/-)” on page 36.

50 DS618F2

CS4382A

Contacting Cirrus Logic Support

For all product questions and inqu iries, contact a Cirrus Logic Sales Representative.

To find the one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries ("Cirrus") beli eve that t he information contained in this document is accu rate and rel iable. However, the information is subje ct

to change without no tice an d is provid ed "AS IS" withou t warra nty of any k ind (expre ss or impl ied). Customers are advise d to obtain the latest version of relevant

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Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

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