INTEGRATED CIRCUITS DATA SHEET SAA7206H DVB compliant descrambler Product specification Supersedes data of 1996 Oct 02 File under Integrated Circuits, IC02 1996 Oct 09 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 MPEG-2 systems parsing PES level descrambling Descrambler core Microcontroller interface Output interfacing Boundary scan test Programming the descrambler 8 LIMITING VALUES 9 HANDLING 10 THERMAL CHARACTERISTICS 11 DC CHARACTERISTICS 12 AC CHARACTERISTICS 13 PACKAGE OUTLINE 14 SOLDERING 14.1 14.2 14.3 14.3.1 14.3.2 14.3.3 14.4 Introduction Reflow soldering Wave soldering QFP SO Method (QFP and SO) Repairing soldered joints 15 DEFINITIONS 16 LIFE SUPPORT APPLICATIONS 1996 Oct 09 2 Philips Semiconductors Product specification DVB compliant descrambler 1 SAA7206H * Descrambler, based on the super descrambler mechanism algorithm with stream decipher and block decipher. The descrambler is initialized with a 64-bit Control Word (CW) at the beginning of a transport stream packet payload of a selected Packet Identification (PID). The descrambler operates on transport stream packet or Packetized Elementary Stream (PES) packet payloads FEATURES * Input data fully compliant with the Transport Stream (TS) definition of the MPEG-2 systems specification * Input data signals; [Forward Error Correction (FEC) Interface] - modem data input bus (8-bit wide) - valid input data indicator * Microcontroller support; only for control, no specific descrambling tasks are performed by the microcontroller. However, parsing and processing of conditional access information (such as EMM and ECM data) is left to the system microcontroller - erroneous packet indicator - first packet byte indicator - byte strobe signal (for asynchronous mode only). The interface can be programmed to one of two modes: * Boundary scan test port for boundary scan. - Asynchronous mode; byte strobe input signal (MBCLK) < 9 MHz, for connection to a modem (FEC) 2 - Synchronous mode; MBCLK is not used. Data is delivered to the descrambler synchronized with the chip clock (DCLK) [9 MHz (typ.) with a 33% duty cycle]. GENERAL DESCRIPTION The SAA7206H (DVB compliant) is designed for use in MPEG-2 based digital TV receivers, incorporating conditional access filters. Such receivers are to be implemented in, for instance, a digital video broadcasting top set box, or an integrated digital TV receiver. An example of a demultiplexer/descrambler system configuration, containing a channel decoder module, a demultiplexer, a system controller and a conditional access system is shown in Fig.3. The main function of the descrambler is to descramble the payloads of MPEG-2 TS packets or PES packets. In addition, the descrambler retrieves Conditional Access (CA) data [such as Entitlement Management Messages (EMM) and Entitlement Control Messages (ECM) etc.] from the stream and passes it to the system microcontroller for processing. * No external memory * Effective bit rate; fbit 72 MHz * Control interface; 8-bit multiplexed data/address, memory mapped I/O (90CE201 microcontroller parallel bus compatible), in combination with a microcontroller interrupt signal (IRQ) * Output ports are identical to the input data interface (demultiplexer interface) - except for the packet error indicator (MB/MB), as the descrambler translates an active MB signal to the `transport_error_indicator' bit in the transport stream - except for the byte strobe input signal (MBCLK), as data is delivered to the demultiplexer, synchronized with the descrambler chip clock which is generated by the demultiplexer 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7206H 1996 Oct 09 QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm 3 VERSION SOT319-2 Philips Semiconductors Product specification DVB compliant descrambler 4 SAA7206H QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VDDD digital supply voltage - - 5.5 V VDDD(core) digital supply voltage for core - - 3.6 V Ptot total power dissipation VDDD(core) = 3.3 V, VDDD = 5 V, CL = 15 pF - - 250 mW fclk clock frequency duty cycle = 30 to 55% - - 9 MHz Tamb operating ambient temperature 0 - 70 C 5 BLOCK DIAGRAM handbook, full pagewidth TC1 61 TDI TCK TMS TRST TDO DAT7 to DAT0 DCS R/W A1 A0 IRQ VDDD(core) VDDD1 to VDDD9 18 19 20 46 60 47 to 50, 53 to 56 7 to 9, 12 to 16 3 4 1 45 43 59 22 62 SAA7206 MICROCONTROLLER INTERFACE 63 5 44 TRANSPORT STREAMS AND AF PARSER TEST CONTROL BLOCK FOR BOUNDARY SCAN TEST AND SCAN TEST 37 MB/MB MBCLK MDV MSYNC MIN7 to MIN0 TC0 PACKET IDENTIFICATION BANK CONTROL WORD BANK STREAM DECIPHER BLOCK DECIPHER CONDITIONAL ACCESS FILTERS 40 24, 25, 28 to 31, 34, 35 36 OUTPUT INTERFACE 6, 11, 21, 26, 32, 41, 51, 57, 64 2, 17, 23, 27, 33, 52, 58 38 39 10, 42 MGG313 VSSD1 to VSSD7 VSSD1(core), VSSD2(core) Fig.1 Block diagram. 1996 Oct 09 4 DCLK POR OE DATO0 to DATO7 DVO SYNCO Philips Semiconductors Product specification DVB compliant descrambler 6 SAA7206H PINNING SYMBOL PIN I/O DESCRIPTION IRQ 1 O VSSD1 2 GND interrupt request output for microcontroller (active LOW, open-drain output) DCS 3 I descrambler chip select input (active LOW) A1 4 I A1 = address/data indicator input A0 5 I A0 = MSByte indicator input VDDD1 6 supply DAT7 7 I/O microcontroller bidirectional data bus bit 7 DAT6 8 I/O microcontroller bidirectional data bus bit 6 DAT5 9 I/O microcontroller bidirectional data bus bit 5 VSSD1(core) 10 GND VDDD2 11 supply DAT4 12 I/O microcontroller bidirectional data bus bit 4 DAT3 13 I/O microcontroller bidirectional data bus bit 3 DAT2 14 I/O microcontroller bidirectional data bus bit 2 DAT1 15 I/O microcontroller bidirectional data bus bit 1 DAT0 16 I/O microcontroller bidirectional data bus bit 0 digital ground 1 digital supply voltage 1 (+5 V) digital ground 1 for core digital supply voltage 2 (+5 V) VSSD2 17 GND TDI 18 I boundary scan test data input TCK 19 I boundary scan test clock input TMS 20 I VDDD3 21 supply DCLK 22 I VSSD3 23 GND DATO0 24 O data output to demultiplexer bit 0 DATO1 25 O data output to demultiplexer bit 1 VDDD4 26 supply VSSD4 27 GND DATO2 28 O data output to demultiplexer bit 2 DATO3 29 O data output to demultiplexer bit 3 DATO4 30 O data output to demultiplexer bit 4 DATO5 31 O data output to demultiplexer bit 5 VDDD5 32 supply VSSD5 33 GND DATO6 34 O data output to demultiplexer bit 6 DATO7 35 O data output to demultiplexer bit 7 VDDD(core) 36 supply TDO 37 O boundary scan test data output DVO 38 O valid output data indicator SYNCO 39 O indicates the first output byte (sync) of a transport packet 1996 Oct 09 digital ground 2 boundary scan test mode select input digital supply voltage 3 (+5 V) 9 MHz descrambler chip clock input (duty cycle range: 30 to 55%) digital ground 3 digital supply voltage 4 (+5 V) digital ground 4 digital supply voltage 5 (+5 V) digital ground 5 digital supply voltage for core (+3.3 V) 5 Philips Semiconductors Product specification DVB compliant descrambler SYMBOL PIN I/O OE 40 I SAA7206H DESCRIPTION output enable (active LOW), if HIGH, device outputs are high impedance, (connected to logic 0 in normal operation) VDDD6 41 supply VSSD2(core) 42 GND digital supply voltage 6 (+5 V) MSYNC 43 I indicates the first input byte (sync) of a transport packet MDV 44 I valid input data indicator MB/MB 45 I packet error indicator input (programmable polarity) TRST 46 I boundary scan reset input (LOW in normal operation) MIN7 47 I 8-bit wide modem data input bit 7 MIN6 48 I 8-bit wide modem data input bit 6 MIN5 49 I 8-bit wide modem data input bit 5 MIN4 50 I 8-bit wide modem data input bit 4 digital ground 2 for core VDDD7 51 supply VSSD6 52 GND MIN3 53 I 8-bit wide modem data input bit 3 MIN2 54 I 8-bit wide modem data input bit 2 MIN1 55 I 8-bit wide modem data input bit 1 MIN0 56 I 8-bit wide modem data input bit 0 VDDD8 57 supply VSSD7 58 GND MBCLK 59 I byte strobe input signal < 9 MHz TC0 60 I test control input 0 (not connected in normal operation) TC1 61 I test control input 1 (not connected in normal operation) POR 62 I power-on reset, must be active HIGH during at least 5 DCLK pulses R/W 63 I read/write input selection VDDD9 64 supply 1996 Oct 09 digital supply voltage 7 (+5 V) digital ground 6 digital supply voltage 8 (+5 V) digital ground 7 digital supply voltage 9 (+5 V) 6 Philips Semiconductors Product specification 52 VSSD6 53 MIN3 54 MIN2 55 MIN1 56 MIN0 57 VDDD8 58 VSSD7 59 MBCLK 60 TC0 SAA7206H 61 TC1 62 POR handbook, full pagewidth 63 R/W 64 VDDD9 DVB compliant descrambler IRQ 1 51 VDDD7 VSSD1 2 50 MIN4 DCS 3 49 MIN5 A1 4 48 MIN6 A0 5 47 MIN7 VDDD1 6 46 TRST DAT7 7 45 MB/MB DAT6 8 44 MDV DAT5 9 43 MSYNC SAA7206 VSSD1(core) 10 42 VSSD2(core) 41 VDDD6 VDDD2 11 DAT4 12 40 OE DAT3 13 39 SYNCO DAT2 14 38 DVO DAT1 15 37 TDO DAT0 16 36 VDDD(core) Fig.2 Pin configuration. 1996 Oct 09 7 VDDD5 32 DATO5 31 DATO4 30 DATO3 29 DATO2 28 VSSD4 27 VDDD4 26 DATO1 25 33 VSSD5 DATO0 24 TCK 19 VSSD3 23 34 DATO6 DCLK 22 TDI 18 VDDD3 21 35 DATO7 TMS 20 VSSD2 17 MGG312 Philips Semiconductors Product specification DVB compliant descrambler 7 SAA7206H * The CA filters select data on the basis of PIDs, and a combination of MPEG-2 section addressing fields. Selected CA data is stored in eighteen 256 byte (constrained random access) buffers which can be read by the microcontroller. The CA message section has a maximum length of 256 bytes. It consists of a 3 bytes long header with Table_id and section_length data. The remaining part of the CA message are the CA_data_bytes (see Fig.4). If a section is longer than 256 bytes, the data capture is stopped (with an interrupt to the microcontroller) after 256 bytes are in the buffer and the `section_to_long' bit is set. The filters are capable of monitoring 18 CA streams (containing EMM and ECM data) simultaneously. Two different lengths are used for address filtering: FUNCTIONAL DESCRIPTION A block diagram of the internal structure of the descrambler (DVB compliant) is illustrated in Fig.1. The block diagram illustrates the main functional modules in the descrambler. The modules are as follows: * The MPEG-2 syntax parser, which parses transport streams that comply with the MPEG-2 systems specification * The descrambler module consisting of: - A Packet Identification (PID) bank containing 6 PID values of the streams selected for descrambling. All bits of PID5 (address 0x0205) can be masked individually with PID5_mask (address 0x0209), to enable multiple PID selection. - 16 filters where the first 7 bytes of the CA_data_bytes field are used for address filtering - A Control Word (CW) bank containing 6 CW pairs and a default CW. A CW pair consists of 2 descrambler control words (odd and even), each word with a length of 64 bits. - 2 (DVB compliant) filters where the first 17 bytes of the CA_data_bytes field are used for address filtering - A chip identification byte (value 0x02) can be read by the software from address 0x0003 (see Table 10). - The descrambler core containing the actual descrambler with the stream cipher and the block cipher module. * A microcontroller interface providing protocol handling for the memory mapped I/O control bus (Philips 90CE201 compatible). This module contains an interrupt request handler and data filters for the retrieval of Conditional Access (CA) information: handbook, full pagewidth CONDITIONAL ACCESS SYSTEM DEMODULATOR AND FORWARD ERROR CORRECTOR MICROCONTROLLER DVB DESCRAMBLER DEMULTIPLEXER (SAA7206H) (SAA7205) MGG314 Fig.3 Demultiplexer system configuration. 1996 Oct 09 8 Philips Semiconductors Product specification DVB compliant descrambler 7 or 17 bytes of filtering handbook, full pagewidth table_id SAA7206H reserved section length CA_data_bytes [253 bytes (max.)] byte 0 byte 1 section header (3 bytes) section payload [253 bytes (max.)] MGG316 Fig.4 Syntax of the conditional access message. Table 1 Explanation of Fig.4 SYNTAX Table_id Reserved Section_length CA_data_byte 1996 Oct 09 DESCRIPTION 8-bit field for identification 4-bit field with section_syntax_indicator (1 bit), DVB_reserved (1 bit) and ISO_reserved (2 bits) 12-bit field that specifies the number of bytes that follow the section_length field up to the end of the section 8-bit field that carries private CA information. Up to the first 17 CA_data_bytes may be used for address filtering 9 Philips Semiconductors Product specification DVB compliant descrambler 7.1 SAA7206H The hierarchical multiplex level below the MPEG-2 transport stream is the packetized elementary stream. The PES header is only parsed partially by the DVB descrambler to locate its scrambling control bits. Parsing is performed for all incoming transport packets, and the parser is synchronized to a rising edge on its MSYNC input. A microcontroller can compose a set of 6 PIDs by programming the appropriate registers in the PID filter bank within the descrambler. MPEG-2 systems parsing The descrambler receives data from a Forward Error Correction (FEC) decoder (see Fig.5) in a digital TV receiver, in the following input data format: * 8 data bits via MIN7 to MIN0. * A valid input data indicator signal (MDV), which is HIGH for consecutive valid bytes and output by either a FEC decoder or a descrambler. Consequently the descrambler input data is allowed to have a `bursty' nature. These PIDs identify the packets of the streams that are to be descrambled. All 13 bits of PID5 (see Table 10, address 0x0205) can be individually enabled/disabled with a mask of 13 bits (see Table 10, address 0x0209) to enable multiple PID selection. The PIDs of PES scrambled packets must be indicated by programming a logic 1 to the corresponding bit of the `PIDi_is_pes' word (see Table 10, address 0x0206). * A transport packet error indicator (MB/MB) which is HIGH for the duration of each 188 byte transport packet in which the FEC decoder found more errors than it could correct. The polarity (active HIGH or LOW) of the error indicator is programmable [bit `Bad_polarity' (see Table 10, address 0x0100)]. * A packet sync signal (MSYNC) which goes HIGH at the start of the first byte of a transport packet. Only the rising edge of MSYNC is used for synchronization, the exact HIGH time of the signal is therefore irrelevant. MPEG-2 multiplex fields which are related to CA information, in so called sections, are parsed only partly. CA sections containing for instance Entitlement Management Messages (EMM) and Entitlement Control Messages (ECM) etc. are retrieved from the stream and stored in 256 byte buffers in the CA filter module. For the selection of CA data, 18 additional PIDs and section header information (table_id, address field, both with bit masks) can be programmed. All 13 bits of PID filters 16 and 17 can be individually enabled/disabled with a mask of 13 bits (see Table 10, addresses 0x03A6 and 0x03BA) to enable multiple PID selection for CA messages. A microcontroller may access data in the 256 byte CA buffers (each filter has its own buffer thus 18 in total) for software based parsing and processing. * A byte strobe signal (MBCLK; < 9 MHz) which indicates consecutive data bytes in the input stream, in the non 9 MHz mode only [bit `9 MHz_interface' = 0 (see Table 10, address 0x0100)]. MBCLK is used as an enable signal, and transport stream input bytes are sampled on its rising edges. If the input interface is programmed to the 9 MHz mode (`9 MHz_interface' = 1), the MBCLK signal is ignored and bytes are latched on rising edges of the DCLK. * A descrambler clock signal (DCLK; 9 MHz; duty cycle range 30 to 55%) which is the processing clock for the descrambler IC. If rising edges of this signal are used to input data to the descrambler, the 9 MHz mode must be programmed (bit `9 MHz_interface' = 1, see Table 10, address 0x0100). The parser module in the descrambler parses transport streams compliant to the MPEG-2 systems syntax. MPEG-2 systems specifies a hierarchical two-level multiplex (see Fig.6). The top hierarchical level is the transport stream, consisting of relatively short (188 byte) transport packets. Each transport packet consists of a 4 byte transport header, an optional adaptation field and a payload. The transport header contains a 13-bit PID field. The adaptation field may contain Program Clock Reference (PCR) data and transport private data, among others. Both transport header and optional adaptation fields are parsed by the TS parser module. 1996 Oct 09 10 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 8 handbook, full pagewidth MIN7 to MIN0 MBCLK MDV FEC DESCRAMBLER MB/MB MSYNC DCLK MBCLK MIN7 to MIN0 message invalid data message invalid data MSYNC MDV MB/MB error-free transport packet (programmable polarity) MB/MB erroneous transport packet MGG317 Fig.5 Signal constellation FEC decoder - descrambler Interfacing. handbook, full pagewidth transport stream packetized elementary stream elementary stream MGG318 = transport_header = pes_header = stuffing Fig.6 MPEG-2 two level hierarchical demultiplexing. 1996 Oct 09 11 Philips Semiconductors Product specification DVB compliant descrambler 7.2 SAA7206H PES level descrambling 7.3 PES level descrambling is possible in accordance with the recommendations of the DVB standard with the DVB descrambler IC. The actual restrictions however, required by the DVB descrambler IC, are less strict than to the recommendations in the DVB standard. The restrictions for PES level descrambling imposed by the IC are as follows: The descrambler core consists of three modules: * A PID filter which selects packets for descrambling * A control word bank containing 6 sets (odd and even) of control words and a Default Control Word (DCW) * The super descrambler core with the implementation of the stream decipherment and the block decipherment algorithms. * Scrambling shall only occur at one level (TS or PES) and is not allowed to occur at both levels simultaneously The PID filter contains 6 registers which hold data in the format indicated in Fig.7. Six individual PIDs are stored to identify 6 packet streams. All bits of PID5 (see Table 10, address 0x0205) can be masked with the `PID5_mask' (see Table 10, address 0x209), to enable descrambling on multiple PIDs. To disable a bit of PID5 with the `PID5_mask' a logic 0 must be programmed. After a power-on reset pulse all mask bits are preset to logic 1. * The complete PES header must be present in exactly one TS packet. Consequently, the size of a PES packet header shall not exceed 184 bytes * Only the PES packet data bytes (PES payload) are descrambled * TS packets resulting from scrambling at PES level are not chained and thus are independent. Consequently, the internal descrambler algorithms (stream decipher and block decipher) are initialized at the start of each (PES scrambled) TS packet payload. To each PID a 3-bit Control Word Pair Index pointer (CWPI) is attached. A CWPI prescribes which control word pair, consisting of odd and even control words, has to be used to initialize the DVB descrambler for payloads of packets with the associated PID. After a power-on reset all CWPIs are set to `111' to enable a correct initialization of the conditional access system. In order to be able to distinguish between sections and PES packets, a PID for a PES scrambled packet is indicated by programming the according `PIDi_is_pes' bit (see Table 10, address 0x0206) to logic 1. If the payload_unit_start_indicator bit is set in the TS packet header and the `PIDi_is_pes' bit is set for a particular PID, the PES scrambling control bits, which are present in the PES header, are stored in the accessible `pes_sc_PIDi' register (see Table 10, address 0x0208). If two or more programmed PIDs match the PID of the TS packet at the same time (while the CWPI value of the programmed PIDs is not equal to `110' or `111'), the programmed PID with the lower index number has a higher priority. However, the default control word, when enabled, has the highest priority. Descrambling at TS level always has priority over descrambling at PES level. Consequently, PES level descrambling is only possible when the transport_scrambling_control bits in the TS header are `00'. In that situation the payload of the PES packets is descrambled using the scrambling control bits of the `pes_sc_PIDi' register. Thus, the built-in priority (HIGH-to-LOW transition) for the programmed PIDs is; DCW, PID0, PID1, PID2, PID3, PID4 and PID5. A 2-bit scrambling_control field is present in the TS packet header and in the PES header (ts_sc1 and ts_sc0 and pes_sc1 and pes_sc0 respectively). The bits in this header field indicate whether the TS packet or PES payload is scrambled or not. In addition, these bits also indicate which control word (odd or even) of a control word pair was used to initialize the DVB descrambler, as indicated in Tables 2 and 3. Remark: PID masking (for PID5) should not be combined with PES level descrambling. Only one pair of PES scrambling control bits per PID is stored in an Internal register. Thus interleaving of PES messages, which can occur in the situation of multiple PID selection, can give the wrong descrambling result. As a consequence the microcontroller must program the `PID5_is_pes' bit (see Table 10, address 0x0206) to logic 0 when multiple PID selection is used. 1996 Oct 09 Descrambler core 12 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H If the payload of a packet is descrambled, the descrambler subsequently resets the scrambling_control bits in the TS or PES header (to `00'). For each of the 6 PIDs in the PID filter bank the values of the TS scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits: `ts_sc_PIDi1' and `ts_sc_PIDi0'; (see Table 10, address 0x0208), `i' is in the range 5 to 0]. For each of the 6 PIDs in the PID filter bank, of which the corresponding PIDi_is_pes bit (see Table 10, address 0x0206) is also set to logic 1, the values of the PES scrambling_control bits are stored in a microcontroller accessible register, prior to descrambling [bits:`pes_sc_PIDi1' and `pes_sc_PIDi0' (see Table 10, address 0x0208) `i' is in the range 5 to 0]. TS and PES scrambling_control retrieval is independent of the value of the CWPI. Table 2 The control word bank contains storage space for 6 control word pairs and a default control word. A control word pair consists of 2 CWs and an odd and even CW, as indicated in Table 4. A control word contains 64 bits. In conjunction with the control word selection mechanism given in Table 4, the CW bank allows any CW pair to be used with any PID. All PIDs may, therefore, use their own specific CW pair, but all of them may also share one CW pair. Definition of the bits in the PES scrambling_control field VALUE DESCRIPTION 00 data is not scrambled 01 data is not scrambled 10 data is scrambled with the EVEN control word 11 data is scrambled with the ODD control word Table 3 Remark: The payloads of packets with TS scrambling_control bits equal to `01' are descrambled using the default control word, regardless of their PID and/or CWPI values. Thus, even PIDs which are not programmed in the PID filter bank are descrambled with the DCW should transport_scrambling_control = `01'. For PIDs in the PID filter bank, if transport_scrambling_control = `01', the payload is descrambled with the default control word, regardless of the value of the associated CWPI. If the default CW is invalid however [`DCW_valid' = 0 (see Table 10, address 0x0206)], DCW based descrambling is disabled. Descrambling using the DCW is only possible on TS packet level. The super descrambler algorithm is implemented in the core of the descrambler. Descrambling is performed on the payload of a transport packet or a PES. The transport header, the (optional) adaptation field and the PES header are excepted. Definition of the bits in the TS scrambling_control field VALUE DESCRIPTION 00 data is not scrambled 01 data is scrambled with the default control word 10 data is scrambled with the EVEN control word 11 data is scrambled with the ODD control word 1996 Oct 09 13 Philips Semiconductors Product specification DVB compliant descrambler Table 4 SAA7206H Descrambler control word storage; see Table 10 CONTROL WORD (128 BITS) ADDRESS Control word 0 odd Control word 0 even 0x1000 to 0x1007 Control word 1 odd Control word 1 even 0x1008 to 0x100F Control word 2 odd Control word 2 even 0x1010 to 0x1017 Control word 3 odd Control word 3 even 0x1018 to 0x101F Control word 4 odd Control word 4 even 0x1020 to 0x1027 Control word 5 odd Control word 5 even 0x1028 to 0x102F Default control word - 0x1030 to 0x1033 15 handbook, full pagewidth 32 15 0 PID_0 CWPI_0 0x0200 - W PID_5 CWPI_5 0x0205 - W 7 6 2 1 PID5_is_pes to PID0_is_pes 0 DCW_valid 0x0206 - W 12 11 15 ts_sc_PID5[1..0] to ts_sc_PID0[1..0] 0x0207 - R pes_sc_PID5[1..0] to pes_sc_PID0[1..0] 0x0208 - R 12 11 15 13 12 15 PID5_mask 0x0209 - W MGG319 See Table 10 for details. Fig.7 Syntax and definition of PID and control word pair Index. Table 5 CWPI values; see Fig.7 1996 Oct 09 CWPI VALUE DESCRIPTION 000 select control word pair 0 001 select control word pair 1 010 select control word pair 2 011 select control word pair 3 100 select control word pair 4 101 select control word pair 5 110 DO NOT descramble 111 DO NOT descramble 14 Philips Semiconductors Product specification DVB compliant descrambler 7.4 SAA7206H Microcontroller interface The microcontroller interface provides a means of communication between a system controller (for instance "Philips 90CE201") in a digital TV receiver and the descrambler internal registers and buffers. The physical interface consists of: 0x0002/0x0004 handbook, halfpage (read only) momentary status of the individual interrupt bits 19-bit status 0x0001 (write only) * DAT7 to DAT0; an 8-bit wide bidirectional data bus. Data and address information are multiplexed on this bus. enables/disables individual interrupts 15-bit mask * DCS; an active LOW chip select signal. The descrambler only responds to microcontroller communication if this signal is driven LOW. 0x0000 (read/write) latched interrupts, indicating which interrupt(s) set IRQ 15-bit interrupt * R/W; an active HIGH read signal, indicating that the microcontroller is attempting to read data from registers or buffers inside the descrambler. If this signal is LOW, data is being written to registers or buffers inside the descrambler. IRQ * A1 and A0; a 2-bit address bus. If the least significant address bit (0) is logic 0, the most significant byte of a 16-bit register is addressed, otherwise the least significant byte is selected. If the most significant address bit (1) is logic 1 DAT7 to DAT0 carries the address information, otherwise it will carry control data. The interrupt register is reset when addressed. Fig.8 * IRQ; an active LOW (open-drain output) interrupt request signal. An interrupt is set if one of the15 bits in the descramblers internal interrupt register is set. The interrupt mechanism consists of three 15-bit registers and one 4-bit register, as illustrated in Fig.8. The interrupt status register enables the microcontroller to monitor the momentary status of the interrupts. This is particularly useful during read operations in the descramblers CA buffers, as the interrupt status bits in question [`flt0_stat', `flt1_stat', etc. (see Table 10, addresses 0x0002 and 0x0004)] are reset when the buffers have been emptied or released. Table 6 Descrambler version 3, microcontroller interrupt mechanism. Definition of interrupt mechanism; see Fig.8 BIT NUMBER The interrupt mask register (see Table 10, address 0x0001) prevents individual interrupts from resetting IRQ (to logic 0). The interrupt status bits are logically ANDed with the mask. If a rising edge occurs on one of the resulting signals, it is latched into the interrupt register, thus resetting IRQ. 1996 Oct 09 MGG320 15 MEANING OF INTERRUPT 0 filter 0 retrieved CA data 1 filter 1 retrieved CA data 2 filter 2 retrieved CA data 3 filter 3 retrieved CA data 4 filter 4 retrieved CA data 5 filter 5 retrieved CA data 6 filter 6 retrieved CA data 7 filter 7 retrieved CA data 8 filter 8 retrieved CA data 9 filter 9 retrieved CA data 10 filter 10 retrieved CA data 11 filter 11 retrieved CA data 12 filter 12 retrieved CA data 13 filter 13 retrieved CA data 14 filter 14, 15, 16 or 17 retrieved CA data 15 empty Philips Semiconductors Product specification DVB compliant descrambler SAA7206H The interrupt register itself is reset (to 0000000000000000) as soon as it is addressed (0x0000) by the microcontroller. In the buffer mode, the remaining address bits (11 to 0) are part of the word address (range depending on the buffer, see Table 10). In the register mode, bits 11 to 8 specify the register unit number (see Fig.10). The remaining 8 bits of the address (7 to 0) indicate specific register addresses within a selected unit. The address range in a specific register unit depends on the number of registers present and is different for each unit. For details refer to Table 10. A typical example of communication between microcontroller and descrambler is illustrated in Fig.9. The descrambler contains an auto increment address counter which can be loaded by performing a write address operation. The present operation, whether read or write, is now performed on the current address. The next operation, whether read or write, is performed on the current address plus 1. The CA filter module in the microcontroller interface unit is capable of accessing general CA messages (ECM and EMM, etc.) in the transport stream. The CA filter module consists of 18 filters and 18 buffers of 256 bytes each, thus each filter has its own data buffer. The 18 filters are divided into two types of filters, which are specified in Table 9. For each filter the `table_id' of the section (the first byte of the section see Fig.9), can be masked. Remark: Avoid resetting the auto increment address counter to 0x0000, when not handling interrupts, as addressing it causes the interrupt register to be reset. Consequently, interrupt information might be lost. The descrambler internal register and buffer addresses are organized as illustrated in Fig.10. The first 4 address bits (15 to 12) are used to select either the descrambler registers (equals 0) or one of the descrambler buffers (ranges 1 and 2). The architecture of the 9 CA filter pairs is shown in Fig.11. handbook, full pagewidth A1 A0 R/W >24 ns DCS DAT7 to DAT0 MSByte LSByte MSByte LSByte >666 ns write address N MSByte LSByte >666 ns read data @ N write data @ N+1 MGG321 The descrambler internal register address is incremented automatically. Fig.9 Microcontroller descrambler communication (example). 1996 Oct 09 16 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H Table 7 Buffer contents BUFFER NUMBER handbook, halfpage (1) if 0, registers are addressed, if >0, buffers are addressed (2) register unit number, range 0 to 3 individual register addresses, range depending on the unit number 0xHHHH Table 8 MGG322 (1) See Table 7. (2) See Table 8. Fig.10 Descrambler, register organization (see Table 10). Table 9 BUFFER CONTENTS 1 CW bank 2 CA data buffers for filters 0 to 15 3 CA data buffers for filters 16 and 17 Unit contents REGISTER UNIT NUMBER UNIT CONTENTS 0 interrupt request handling control 1 parser input control 2 PID filter bank control 3 CA filtering control Specification of the number of CA_data_bytes which can be used for address filtering in the three types of filters in the CA filter module (all bits in the filter can be masked individually) FILTER NUMBER NUMBER OF FILTERS FILTER LENGTH (BYTES) PID MASKABLE Filters 0 to 15 16 7 no Filters 16 and 17 (DVB compliant) 2 17 yes The filter consists of 18 section detectors. Each section detector selects and retrieves section data for CA_messages on the basis of: The maximum section length of a conditional access message is 256 bytes. If the section length of a message is higher, data acquisition into the buffer is stopped after 256 bytes and an interrupt signal (plus filter fired signal) is generated as normal. In this (erroneous) situation the `section_to_long' bit of the filter is also set, which can be read by the microcontroller (see Table 10). * PID; which is maskable only for filters 16 and 17 * Table_id; which is maskable for all filters * For filters 0 to 15; the first 7 bytes in the section payload, which are maskable for all filters (see Fig.4) The CA filters allow retrieval of multiple consecutive CA messages, even if these messages have identical selection criteria. For this purpose the 18 filters are grouped in 9 filter pairs (0 and 1, 2 and 3 to 16 and 17). Each of the CA filters in a pair can be programmed equivalently. To prevent two filters from firing at the same time the `equal conditions' bits of the appropriate filter pair can be programmed to logic 1. As a result, the filter with the even (equals lowest) index number (for instance filter_8 of filter pair 8 and 9) fires at the first occurrence of a matching section. If, at the time of the second occurrence of a matching section, the buffer of the filter with the even index number is still occupied, the other filter (with odd index number) of a filter pair fires, thus storing the section data in its buffer. * For filters 16 and 17; the first 17 bytes in the section payload, which are maskable * For all filters (see Fig.4). The CA data detected by a certain filter is stored in the 256 byte buffer, only if its buffer is empty. As soon as an entire section of CA data is stored, an interrupt is generated (see Table 10, address 0x0000). The 18 section detectors can be separately enabled, to avoid unnecessary interrupts. The `filter fired' registers enable the microcontroller to track which filter caused a buffer to be loaded (see Table 10, addresses 0x0300 and 0x0301). 1996 Oct 09 17 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H If the microcontroller decides to read data from one of the CA buffers (see Table 10, address range filter_0: 0x2000 to 0x207F to filter_17: 0x2880 to 0x28FF) it can determine when to stop reading in two ways. It can periodically poll the `flt0_stat' to `flt17_stat' bits in the interrupt status register (see Table 10, address 0x0002 and 0x0004). Each of these bits goes LOW as soon as the last valid section data is read from the associated CA buffer. 7.5 The output data stream consists of a sequence of bytes. A new byte is present at the data output pins DATO7 to DATO0 at each rising edge of the descrambler chip clock DCLK. The control signals SYNCO and DVO are a delayed (9 MHz) version of the input interface signals MSYNC and MDV respectively. By this form of delay correction the relationship between the data and control signals is maintained. Another possibility is to read the `high_flt_address' word (`haddr7 to 0', Table 10, addresses 0x0302 to 0x0313). The high address indicates the number of valid section words (1 word = 2 bytes) that were written into the buffer. This number equals the number of read cycles that has to be performed to retrieve all valid data from the buffer. The MB/MB and MBCLK signals are not output to the demultiplexer. The descrambler converts the MB/MB signal to the transport_error_indicator bit in the TS packets. At the descrambler output all information is consequently contained in the stream. MBCLK is only used to clock data into the descrambler, interfacing to the demultiplexer is performed using the 9 MHz DCLK, which is generated by the demultiplexer. If the buffer contents have to be removed without being read, the microcontroller can write a logic 1 to the `rst_bf17-0' bit (see Table 10, address 0x0314 and 0x0315) thus releasing the buffer. Another possibility is to perform a write address operation with a value of haddr7 to haddr0 plus buffer base address. The internal auto increment address counter is thus set to the last word in the buffer, causing the interrupt status bit to be reset and the filters to be reactivated, after having been idle during buffer emptying. 7.6 Boundary scan test The DVB compliant descrambler is equipped with a 5-pins test port interface for Boundary Scan Test (BST). The implementation is in accordance with the BST standard. If, during the acquisition of a CA message, one of the TS packets composing a message contains an error (`transport_error_indicator' = `1') the erroneous TS packet is removed and CA message acquisition is restarted. Thus the complete CA message is lost when at least one of the TS packets which composes this message contains an error. Duplicate TS packets containing CA messages are also removed. 1996 Oct 09 Output interfacing 18 1996 Oct 09 256B BUFFER_1 19 FILTER 17 equal conditions FILTER 16 256B BUFFER_17 256B BUFFER_16 identical filter (pairs) 2 to15 FILTER 1 256B BUFFER_0 table_id z address d address c = filter fired indicator PID s table_id y = filter enable equal conditions CA filter pair architecture interrupt to microcontroller interrupt to microcontroller MGG323 CA BUFFER (256 bytes) CA BUFFER (256 bytes) DVB compliant descrambler Fig.11 CA two filter architecture. INPUT STREAM PID r handbook, full pagewidth equal conditions FILTER 0 CA module structure Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0200- W 0x0201- W 0x0202- W 0x0203- W 0x0204- W 0x0205- W PID1, CWPI1 PID2, CWPI2 PID3, CWPI3 PID4, CWPI4 PID5, CWPI5 0x0005 to 0x00FF EMPTY PID0, CWPI0 0x0004- R IRPT_ STATUS_ FLT14-17 0x0101 to 0x01FF 0x0003- R CHIP_ IDENTIFICATION EMPTY 0x0002- R IRPT_ STATUS 0x0100- W 0x0001- R/W IRPT_ MASK PRS_INP CTRL 0x0000- R/W ADDRESS (HEX) IRPT REGISTER FUNCTION 20 - - - - - - - - - - pid3 pid4 pid3 pid11 pid4 pid12 pid11 pid3 pid12 pid11 pid4 pid2 pid10 pid2 pid10 pid2 pid10 pid2 pid10 pid2 pid10 pid2 pid10 - - - - - - - - 0 - flt5_stat flt13_stat msk5 msk13 flt5_irp flt13_irp 13/5 pid1 pid9 pid1 pid9 pid1 pid9 pid1 pid9 pid1 pid9 pid1 pid9 - - - - - - - - 0 - flt4_stat flt12_stat msk4 msk12 flt4_irp flt12_irp 12/4 BITS pid0 pid8 pid0 pid8 pid0 pid8 pid0 pid8 pid0 pid8 pid0 pid8 - - - - - - flt17_stat - 0 - flt3_stat flt11_stat msk3 msk11 flt3_irp flt11_irp 11/3 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 cwpi2 pid7 - - - - - - flt16_stat - 0 - flt2_stat flt10_stat msk2 msk10 flt2_irp flt10_irp 10/2 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 cwpi1 pid6 - - bad_ polarity - - - flt15_stat - 1 - flt1_stat flt9_stat msk1 msk9 flt1_irpt flt9_irp 9/1 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 cwpi0 pid5 - - 9 MHz_ interface - - - flt14_stat - 1 - flt0_stat flt8_stat msk0 msk8 flt0_irpt flt8_irp 8/0 DVB compliant descrambler pid12 pid3 pid4 pid3 pid11 pid4 pid12 pid11 pid12 pid3 - pid4 - - - pid11 - - pid12 - 0 flt7_stat - flt6_stat - 0 msk6 flt14-17_stat msk7 msk14 - flt14-17_irp 14/6 flt6_irp 15/7 flt7_irp Programming the descrambler Table 10 Descrambler programming. 7.7 Philips Semiconductors Product specification SAA7206H 0x0206- W 0x0207- R 0x0208- R 0x0209- W 0x0210 to 0x02FF 0x0300- R 0x0301- R 0x0302- R 0x0303- R 0x0304- R 0x0305- R TS_SCR_ CTRL PES_SCR_CTRL PID5_MASK EMPTY FLT17-16 FIRED STATUS FLT15-0 FIRED STATUS FLT0 STATUS FLT1 STATUS FLT2 STATUS FLT3 STATUS ADDRESS (HEX) DCW_ VALID REGISTER FUNCTION 1996 Oct 09 21 - hadr2_5 - - hadr2_6 - hadr3_6 hadr2_7 section to_long hadr3_7 hadr3_4 - hadr2_4 - hadr1_4 - hadr0_4 - flt4_frd flt12_frd - - - - pid5_ msk4 pid5_ msk12 pes_sc_ pid2_0 - ts_sc_ pid2_0 - PID3_ is_pes - 12/4 hadr3_3 - hadr2_3 - hadr1_3 - hadr0_3 - flt3_frd flt11_frd - - - - pid5_ msk3 pid5_ msk11 pes_sc_ pid1_1 pes_sc_ pid5_1 ts_sc_ pid1_1 ts_sc_ pid5_1 PID2_ is_pes - 11/3 hadr3_2 - hadr2_2 - hadr1_2 - hadr0_2 - flt2_frd flt10_frd - - - - pid5_ msk2 pid5_ msk10 pes_sc_ pid1_0 pes_sc_ pid5_0 ts_sc_ pid1_0 ts_sc_ pid5_0 PID1_ is_pes - 10/2 hadr3_1 - hadr2_1 - hadr1_1 - hadr0_1 - flt1_frd flt9_frd flt17_frd - - - pid5_ msk1 pid5_ msk9 pes_sc_ pid0_1 pes_sc_ pid4_1 ts_sc_ pid0_1 ts_sc_ pid4_1 PID0_ is_pes - 9/1 hadr3_0 - hadr2_0 - hadr1_0 - hadr0_0 - flt0_frd flt8_frd flt16_frd - - - pid5_ msk0 pid5_ msk8 pes_sc_ pid0_0 pes_sc_ pid4_0 ts_sc_ pid0_0 ts_sc_ pid4_0 DCW_valid - 8/0 DVB compliant descrambler hadr3_5 hadr1_5 hadr1_6 hadr1_7 section to_long - - - flt13_frd section to_long - - hadr0_5 - - - - hadr0_6 - - hadr0_7 - - pid5_ msk5 - - pid5_ msk7 - - pid5_ msk6 - pes_sc_ pid2_1 section to_long - pes_sc_ pid3_1 - flt5_frd pes_sc_ pid3_0 - ts_sc_ pid2_1 flt6_frd - ts_sc_ pid3_1 - flt7_frd ts_sc_ pid3_0 - - PID4_ is_pes flt14_frd - - 13/5 flt15_frd - PID5_ is_pes - 14/6 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x030D- R 0x030E- R 0x030F- R FLT12 STATUS FLT13 STATUS 0x030A- R FLT8 STATUS FLT11 STATUS 0x0309- R FLT7 STATUS 0x030C- R 0x0308- R FLT6 STATUS FLT10 STATUS 0x0307- R FLT5 STATUS 0x030B- R 0x0306- R FLT4 STATUS FLT9 STATUS ADDRESS (HEX) REGISTER FUNCTION hadr5_5 - hadr6_5 - hadr7_5 - hadr5_6 - hadr6_6 - hadr7_6 - hadr8_6 hadr5_7 section to_long hadr6_7 section to_long hadr7_7 section to_long hadr8_7 22 hadr13_5 hadr13_6 hadr12_7 hadr13_7 - - section to_long - hadr11 _5 hadr11 _6 hadr11 _7 hadr12_5 - - section to_long - hadr10_5 hadr10_6 hadr10_7 hadr12_6 - - hadr13_4 - hadr12_4 - hadr11 _4 - hadr10_4 - hadr9_4 - hadr8_4 - hadr7_4 - hadr6_4 - hadr5_4 - hadr4_4 - 12/4 hadr13_3 - hadr12_3 - hadr11 _3 - hadr10_3 - hadr9_3 - hadr8_3 - hadr7_3 - hadr6_3 - hadr5_3 - hadr4_3 - 11/3 hadr13_2 - hadr12_2 - hadr11 _2 - hadr10_2 - hadr9_2 - hadr8_2 - hadr7_2 - hadr6_2 - hadr5_2 - hadr4_2 - 10/2 hadr13_1 - hadr12_1 - hadr11 _1 - hadr10_1 - hadr9_1 - hadr8_1 - hadr7_1 - hadr6_1 - hadr5_1 - hadr4_1 - 9/1 hadr13_0 - hadr12_0 - hadr11 _0 - hadr10_0 - hadr9_0 - hadr8_0 - hadr7_0 - hadr6_0 - hadr5_0 - hadr4_0 - 8/0 DVB compliant descrambler section to_long hadr9_5 hadr9_6 - section to_long hadr9_7 - - section to_long - hadr4_5 hadr4_6 hadr4_7 section to_long - - section to_long hadr8_5 13/5 14/6 15/7 BITS Philips Semiconductors Product specification SAA7206H ADDRESS (HEX) 0x0310- R 0x0311- R 0x0312- R 0x0313- R 0x0314- W 0x0315- W 0x0316- W 0x0317- W 0x0318- W 0x0319- W 0x031A- W 0x031B- W 0x031C- W REGISTER FUNCTION FLT14 STATUS FLT15 STATUS FLT16 STATUS FLT17 STATUS 1996 Oct 09 RESET BUFFER 16 and 17 RESET BUFFER 0 to 15 FLT0 CNTRL FLT0 TBL_ID FLT0 ADR BYTE0 FLT0 ADR BYTE1 FLT0 ADR BYTE2 FLT0 ADR BYTE3 FLT0 ADR BYTE4 - - - - 23 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable rst_bf5 rst_bf13 - - adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 rst_bf4 rst_bf12 - - hadr17_4 - hadr16_4 - hadr15_4 - hadr14_4 - 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 rst_bf3 rst_bf11 - - hadr17_3 - hadr16_3 - hadr15_3 - hadr14_3 - 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 rst_bf2 rst_bf10 - - hadr17_2 - hadr16_2 - hadr15_2 - hadr14_2 - 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 rst_bf1 rst_bf9 rst_bf17 - hadr17_1 - hadr16_1 - hadr15_1 - hadr14_1 - 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 rst_bf0 rst_bf8 rst_bf16 - hadr17_0 - hadr16_0 - hadr15_0 - hadr14_0 - 8/0 DVB compliant descrambler msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 tblid_6 tblid_7 msk7 msk6 msk7 pid6 hadr17_6 hadr17_7 equal_cond - - section to_long - hadr16_5 hadr16_6 hadr16_7 pid7 - - section to_long rst_bf6 hadr15_5 hadr15_6 hadr15_7 rst_bf7 - - section to_long rst_bf14 hadr14_5 hadr14_6 hadr14_7 rst_bf15 - - section to_long hadr17_5 13/5 14/6 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0327- W 0x0328- W 0x0329- W 0x032A- W 0x032B- W FLT2 CNTRL FLT2 TBL_ID FLT2 ADR BYTE0 FLT2 ADR BYTE1 0x0323- W FLT1 ADR BYTE2 FLT1 ADR BYTE6 0x0322- W FLT1 ADR BYTE1 0x0326- W 0x0321- W FLT1 ADR BYTE0 FLT1 ADR BYTE5 0x0320- W FLT1 TBL_ID 0x0325- W 0x031F- W FLT1 CNTRL FLT1 ADR BYTE4 0x031E- W FLT0 ADR BYTE6 0x0324- W 0x031D- W FLT0 ADR BYTE5 FLT1 ADR BYTE3 ADDRESS (HEX) REGISTER FUNCTION 24 msk6 adr6 adr7 adr6 adr7 msk7 msk6 tblid_6 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 13/5 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 12/4 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 11/3 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 10/2 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 9/1 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 tblid_7 pid6 msk6 equal_cond - pid7 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0336- W 0x0337- W 0x0338- W 0x0339- W 0x033A- W FLT3 ADR BYTE4 FLT3 ADR BYTE5 FLT3 DR BYTE6 FLT4 CNTRL 0x0332- W FLT3 TBL_ID FLT3 ADR BYTE3 0x0331- W FLT3 CNTRL 0x0335- W 0x0330- W FLT2 ADR BYTE6 FLT3 ADR BYTE2 0x032F- W FLT2 ADR BYTE5 0x0334- W 0x032E- W FLT2 ADR BYTE4 FLT3 ADR BYTE1 0x032D- W FLT2 ADR BYTE3 0x0333- W 0x032C- W FLT2 ADR BYTE2 FLT3 ADR BYTE0 ADDRESS (HEX) REGISTER FUNCTION 25 adr6 equal_cond pid6 adr7 - pid7 adr6 msk6 adr7 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 13/5 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 12/4 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 11/3 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 10/2 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 9/1 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0345- W 0x0346- W 0x0347- W 0x0348- W 0x0349- W FLT5 ADR BYTE0 FLT5 ADR BYTE1 FLT5 ADR BYTE2 FLT5 ADR BYTE3 FLT5 ADR BYTE4 0x0341- W FLT4 ADR BYTE5 0x0344- W 0x0340- W FLT4 ADR BYTE4 FLT5 TBL_ID 0x033F- W FLT4 ADR BYTE3 0x0343- W 0x033E- W FLT4 ADR BYTE2 FLT5 CNTRL 0x033D- W FLT4 ADR BYTE1 0x0342- W 0x033C- W FLT4 ADR BYTE0 FLT4 ADR BYTE6 0x033B- W ADDRESS (HEX) FLT4 TBL_ID REGISTER FUNCTION 26 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 13/5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 tblid_6 pid6 tblid_7 equal_cond - pid7 msk6 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 msk7 14/6 tblid_7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0354- W 0x0355- W 0x0356- W 0x0357- W 0x0358- W FLT7 CNTRL FLT7 TBL_ID FLT7 ADR BYTE0 FLT7 ADR BYTE1 0x0350- W FLT6 ADR BYTE2 FLT6 ADR BYTE6 0x034F- W FLT6 ADR BYTE1 0x0353- W 0x034E- W FLT6 ADR BYTE0 FLT6 ADR BYTE5 0x034D- W FLT6 TBL_ID 0x0352- W 0x034C- W FLT6 CNTRL FLT6 ADR BYTE4 0x034B- W FLT5 ADR BYTE6 0x0351- W 0x034A- W FLT5 ADR BYTE5 FLT6 ADR BYTE3 ADDRESS (HEX) REGISTER FUNCTION 27 msk6 adr6 adr7 adr6 adr7 msk7 msk6 tblid_6 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 13/5 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 12/4 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 11/3 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 10/2 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 9/1 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 tblid_7 pid6 msk6 equal_cond - pid7 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0363- W 0x0364- W 0x0365- W 0x0366- W 0x0367- W FLT8 ADR BYTE4 FLT8 ADR BYTE5 FLT8 ADR BYTE6 FLT9 CNTRL 0x031F- W FLT8 TBL_ID FLT8 ADR BYTE3 0x035E- W FLT8 CNTRL 0x0362- W 0x035D- W FLT7 ADR BYTE6 FLT8 ADR BYTE2 0x035C- W FLT7 ADR BYTE5 0x0361- W 0x035B- W FLT7 ADR BYTE4 FLT8 ADR BYTE1 0x035A- W FLT7 ADR BYTE3 0x0360- W 0x0359- W FLT7 ADR BYTE2 FLT8 ADR BYTE0 ADDRESS (HEX) REGISTER FUNCTION 28 adr6 equal_cond pid6 adr7 - pid7 adr6 msk6 adr7 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 13/5 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 12/4 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 11/3 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 10/2 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 9/1 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0372- W 0x0373- W 0x0374- W 0x0375- W 0x0376- W FLT10 ADR BYTE0 FLT10 ADR BYTE1 FLT10 ADR BYTE2 FLT10 ADR BYTE3 FLT10 ADR BYTE4 0x036E- W FLT9 ADR BYTE5 0x0371- W 0x036D- W FLT9 ADR BYTE4 FLT10 TBL_ID 0x036C- W FLT9 ADR BYTE3 0x0370- W 0x036B- W FLT9 ADR BYTE2 FLT10 CNTRL 0x036A- W FLT9 ADR BYTE1 0x0363F- W 0x0369- W FLT9 ADR BYTE0 FLT9 ADR BYTE6 0x0368- W ADDRESS (HEX) FLT9 TBL_ID REGISTER FUNCTION 29 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 13/5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 tblid_6 pid6 tblid_7 equal_cond - pid7 msk6 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 msk7 14/6 tblid_7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0381- W 0x0382- W 0x0383- W 0x0384- W 0x0385- W FLT11 ADR BYTE6 FLT12 CNTRL FLT12 TBL_ID FLT12 ADR BYTE0 FLT12 ADR BYTE1 0x037D- W FLT11 ADR BYTE2 0x0380- W 0x037C- W FLT11 ADR BYTE1 FLT11 ADR BYTE5 0x037B- W FLT11 ADR BYTE0 0x037F- W 0x037A- W FLT11 TBL_ID FLT11 ADR BYTE4 0x0379- W FLT11 CNTRL 0x037E- W 0x0378- W FLT10 ADR BYTE6 FLT11 ADR BYTE3 0x0377- W ADDRESS (HEX) FLT10 ADR BYTE5 REGISTER FUNCTION 30 msk6 adr6 adr7 adr6 adr7 msk7 msk6 tblid_6 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 13/5 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 12/4 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 11/3 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 10/2 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 9/1 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 tblid_7 pid6 msk6 equal_cond - pid7 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x0390- W 0x0391- W 0x0392- W 0x0393- W 0x0394- W FLT13 ADR BYTE3 FLT13 ADR BYTE4 FLT13 ADR BYTE5 FLT13 ADR BYTE6 FLT14 CNTRL 0x038C- W FLT13 TBL_ID 0x038F- W 0x038B- W FLT13 CNTRL FLT13 ADR BYTE2 0x038A- W FLT12 ADR BYTE6 0x038E- W 0x0389- W FLT12 ADR BYTE5 FLT13 ADR BYTE1 0x0388- W FLT12 ADR BYTE4 0x038D- W 0x0387- W FLT12 ADR BYTE3 FLT13 ADR BYTE0 0x0386- W ADDRESS (HEX) FLT12 ADR BYTE2 REGISTER FUNCTION 31 adr6 equal_cond pid6 adr7 - pid7 adr6 msk6 adr7 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 13/5 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 12/4 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 11/3 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 10/2 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 9/1 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 msk6 tblid_6 pid7 msk7 pid6 - tblid_7 adr6 equal_cond adr7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x039F- W 0x03A0- W 0x03A1- W 0x03A2- W 0x03A3- W FLT15 ADR BYTE1 FLT15 ADR BYTE2 FLT15 ADR BYTE3 FLT15 ADR BYTE4 0x039B- W FLT14 ADR BYTE5 FLT15 ADR BYTE0 0x039A- W FLT14 ADR BYTE4 0x039E- W 0x0399- W FLT14 ADR BYTE3 FLT15 TBL_ID 0x0398- W FLT14 ADR BYTE2 0x039D- W 0x0397- W FLT14 ADR BYTE1 FLT15 CNTRL 0x0396- W FLT14 ADR BYTE0 0x039C- W 0x0395- W FLT14 TBL_ID FLT14 ADR BYTE6 ADDRESS (HEX) REGISTER FUNCTION 32 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 13/5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 tblid_6 pid6 tblid_7 equal_cond - pid7 msk6 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 msk7 msk6 tblid_6 msk7 14/6 tblid_7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x03AE- W 0x03AF- W 0x03B0- W 0x03B1- W 0x03B2- W FLT16 ADR BYTE5 FLT16 ADR BYTE6 FLT16 ADR BYTE7 FLT16 ADR BYTE8 FLT16 ADR BYTE9 0x03AA- W FLT16 ADR BYTE1 0x03AD- W 0x03A9- W FLT16 ADR BYTE0 FLT16 ADR BYTE4 0x03A8- W FLT16 TBL_ID 0x03AC- W 0x03A7- W FLT16 CNTRL FLT16 ADR BYTE3 0x03A6- W FLT16 PID MASK 0x03AB- W 0x03A5- W FLT15 ADR BYTE6 FLT16 ADR BYTE2 0x03A4- W ADDRESS (HEX) FLT15 ADR BYTE5 REGISTER FUNCTION equal_cond pid6 - pid7 33 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable msk5 - adr5 msk5 adr5 msk5 13/5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 msk4 msk12 adr4 msk4 adr4 msk4 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 msk3 msk11 adr3 msk3 adr3 msk3 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 msk2 msk10 adr2 msk2 adr2 msk2 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 msk1 msk9 adr1 msk1 adr1 msk1 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 msk0 msk8 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 tblid_6 msk6 msk7 tblid_7 - - msk6 adr6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x03BD- W 0x03BE- W 0x03BF- W 0x03C0- W 0x03C1- W FLT17 ADR BYTE0 FLT17 ADR BYTE1 FLT17 ADR BYTE2 FLT17 ADR BYTE3 FLT17 ADR BYTE4 0x03B9- W FLT16 ADR BYTE16 0x03BC- W 0x03B8- W FLT16 ADR BYTE15 FLT17 TBL_ID 0x03B7- W FLT16 ADR BYTE14 0x03BB- W 0x03B6- W FLT16 ADR BYTE13 FLT17 CNTRL 0x03B5- W FLT16 ADR BYTE12 0x03BA- W 0x03B4- W FLT16 ADR BYTE11 FLT17 PID MASK 0x03B3- W ADDRESS (HEX) FLT16 ADR BYTE10 REGISTER FUNCTION 34 msk6 adr6 msk7 adr7 adr6 adr7 adr6 msk6 adr7 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 tblid_5 msk5 pid5 enable msk5 - adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 13/5 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 tblid_4 msk4 pid4 pid12 msk4 msk12 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 12/4 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 tblid_3 msk3 pid3 pid11 msk3 msk11 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 11/3 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 tblid_2 msk2 pid2 pid10 msk2 msk10 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 10/2 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 tblid_1 msk1 pid1 pid9 msk1 msk9 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 9/1 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 tblid_0 msk0 pid0 pid8 msk0 msk8 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 msk7 tblid_6 pid6 tblid_7 equal_cond - pid7 msk6 msk6 msk7 msk7 - adr6 adr7 - msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x03CC- W 0x03CD- W 0x03CE to 0x0FFF 0x1000- W 0x1001- W FLT17 ADR BYTE15 FLT17 ADR BYTE16 EMPTY CTRL WRD0_ EVEN3 CTRL_ WRD0_ EVEN2 0x03C8- W FLT17 ADR BYTE11 0x03CB- W 0x03C7- W FLT17 ADR BYTE10 FLT17 ADR BYTE14 0x03C6- W FLT17 ADR BYTE9 0x03CA- W 0x03C5- W FLT17 ADR BYTE8 FLT17 ADR BYTE13 0x03C4- W FLT17 ADR BYTE7 0x03C9- W 0x03C3- W FLT17 ADR BYTE6 FLT17 ADR BYTE12 0x03C2- W ADDRESS (HEX) FLT17 ADR BYTE5 REGISTER FUNCTION 35 cw46 cw38 cw47 cw39 cw54 - - cw55 - - cw62 adr6 adr7 cw37 cw45 cw53 cw61 - - adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 adr5 msk5 13/5 cw36 cw44 cw52 cw60 - - adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 adr4 msk4 12/4 cw35 cw43 cw51 cw59 - - adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 adr3 msk3 11/3 cw34 cw42 cw50 cw58 - - adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 adr2 msk2 10/2 cw33 cw41 cw49 cw57 - - adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 adr1 msk1 9/1 cw32 cw40 cw48 cw56 - - adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 adr0 msk0 8/0 DVB compliant descrambler cw63 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 adr6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 adr7 msk7 msk6 msk7 adr6 adr7 adr6 msk6 adr7 msk7 msk6 adr6 msk7 msk6 adr7 14/6 msk7 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x100C- W 0x100D- W 0x100E- W 0x100F- W 0x1010- W CTRL_ WRD1_ ODD2 CTRL WRD1_ ODD1 CTRL_ WRD1_ ODD0 CTRL WRD2_ EVEN3 0x1008- W CTRL WRD1_ EVEN3 CTRL WRD1_ ODD3 0x1007- W CTRL_ WRD0_ ODD0 0x100B- W 0x1006- W CTRL WRD0_ ODD1 CTRL_ WRD1_ EVEN0 0x1005- W CTRL_ WRD0_ ODD2 0x100A- W 0x1004- W CTRL WRD0_ ODD3 CTRL WRD1_ EVEN1 0x1003- W CTRL_ WRD0_ EVEN0 0x1009- W 0x1002- W CTRL WRD0_ EVEN1 CTRL_ WRD1_ EVEN2 ADDRESS (HEX) REGISTER FUNCTION 36 cw62 cw54 cw55 cw6 cw7 cw63 cw14 cw22 cw23 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 13/5 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 12/4 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 11/3 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 10/2 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 9/1 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 8/0 DVB compliant descrambler cw15 cw30 cw38 cw39 cw31 cw46 cw47 cw54 cw55 cw6 cw62 cw7 cw63 cw14 cw22 cw15 cw30 cw23 cw38 cw39 cw31 cw46 cw54 cw47 cw62 cw55 cw6 cw7 cw63 cw14 cw22 cw23 cw15 cw30 cw38 cw39 cw31 cw46 cw47 cw54 cw55 cw6 cw62 cw7 cw63 cw14 cw22 cw15 cw30 cw23 14/6 cw31 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x101B- W 0x101C- W 0x101D- W 0x101E- W 0x101F- W CTRL WRD3_ ODD3 CTRL_ WRD3_ ODD2 CTRL WRD3_ ODD1 CTRL_ WRD3_ ODD0 0x1017- W CTRL_ WRD2_ ODD0 CTRL_ WRD3_ EVEN0 0x1016- W CTRL WRD2_ ODD1 0x101A- W 0x1015- W CTRL_ WRD2_ ODD2 CTRL WRD3_ EVEN1 0x1014- W CTRL WRD2_ ODD3 0x1019- W 0x1013- W CTRL_ WRD2_ EVEN0 CTRL_ WRD3_ EVEN2 0x1012- W CTRL WRD2_ EVEN1 0x1018- W 0x1011- W CTRL_ WRD2_ EVEN2 CTRL WRD3_ EVEN3 ADDRESS (HEX) REGISTER FUNCTION 37 cw14 cw6 cw7 cw22 cw23 cw15 cw30 cw38 cw39 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 13/5 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 12/4 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 11/3 cw2 cw10 scw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 10/2 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 9/1 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 8/0 DVB compliant descrambler cw31 cw46 cw54 cw47 cw62 cw55 cw6 cw7 cw63 cw14 cw22 cw23 cw15 cw30 cw38 cw31 cw46 cw39 cw54 cw55 cw47 cw62 cw6 cw63 cw14 cw7 cw22 cw23 cw15 cw30 cw38 cw39 cw31 cw46 cw54 cw47 cw62 cw55 cw6 cw7 cw63 cw14 cw22 cw23 cw15 cw30 cw38 cw31 cw46 cw39 14/6 cw47 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x102A- W 0x102B- W 0x102C- W 0x102D- W 0x102E- W CTRL_ WRD5_ EVEN0 CTRL WRD5_ ODD3 CTRL_ WRD5_ ODD2 CTRL WRD5_ ODD1 0x1026- W CTRL WRD4_ ODD1 CTRL WRD5_ EVEN1 0x1025- W CTRL_ WRD4_ ODD2 0x1029- W 0x1024- W CTRL WRD4_ ODD3 CTRL_ WRD5_ EVEN2 0x1023- W CTRL_ WRD4_ EVEN0 0x1028- W 0x1022- W CTRL WRD4_ EVEN1 CTRL WRD5_ EVEN3 0x1021- W CTRL_ WRD4_ EVEN2 0x1027- W 0x1020- W CTRL WRD4_ EVEN3 CTRL_ WRD4_ ODD0 ADDRESS (HEX) REGISTER FUNCTION 38 cw30 cw22 cw23 cw38 cw39 cw31 cw46 cw54 cw55 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 13/5 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 12/4 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 11/3 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 10/2 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 9/1 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 8/0 DVB compliant descrambler cw47 cw62 cw6 cw63 cw14 cw7 cw22 cw23 cw15 cw30 cw38 cw39 cw31 cw46 cw54 cw47 cw62 cw55 cw6 cw7 cw63 cw14 cw22 cw23 cw15 cw30 cw31 cw38 cw39 cw54 cw46 cw55 cw47 cw62 cw6 cw7 cw63 cw14 cw15 cw22 cw23 cw38 cw30 cw39 cw31 cw46 cw54 cw47 cw62 cw63 14/6 cw55 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x2200 to 0x227F- R 0x2280 to 0x22FF 0x2300 to 0x237F- R 0x2380 to 0x23FF 0x2400 to 0x247F- R EMPTY FLT3_ BUFFER EMPTY FLT4_ BUFFER 0x2000 to 0x207F- R FLT0_ BUFFER FLT2_ BUFFER 0x1034 to 0x1FFF EMPTY 0x2180 to 0x21FF 0x1033- W DFLT_ CTRL_ WRD0 EMPTY 0x1032- W DFLT_ CTRL_ WRD1 0x2100 to 0x217F- R 0x1031- W DFLT_ CTRL_ WRD2 FLT1_ BUFFER 0x1030- W DFLT_ CTRL_ WRD3 0x2080 to 0x20FF 0x102F- W CTRL_ WRD5_ ODD0 EMPTY ADDRESS (HEX) REGISTER FUNCTION 39 data14 data6 - - data7 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - cw5 cw13 cw21 cw29 cw37 cw45 cw53 cw61 cw5 cw13 13/5 data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - cw4 cw12 cw20 cw28 cw36 cw44 cw52 cw60 cw4 cw12 12/4 data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - cw3 cw11 cw19 cw27 cw35 cw43 cw51 cw59 cw3 cw11 11/3 data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - cw2 cw10 cw18 cw26 cw34 cw42 cw50 cw58 cw2 cw10 10/2 data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - cw1 cw9 cw17 cw25 cw33 cw41 cw49 cw57 cw1 cw9 9/1 data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - cw0 cw8 cw16 cw24 cw32 cw40 cw48 cw56 cw0 cw8 8/0 DVB compliant descrambler data15 data6 data7 - - data14 - - data15 data6 - - data7 - - data14 data6 data15 data14 data7 - - data15 - - data6 - - data14 - - data7 cw6 cw7 data15 cw14 cw22 cw15 cw30 cw23 cw38 cw39 cw31 cw46 cw54 cw55 cw47 cw62 cw6 cw63 cw14 cw7 14/6 cw15 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x2980 to 0x29FF 0x2A00 0x2A7F- R 0x2A80 to 0x2AFF 0x2B00 to 0x2B7F- R 0x2B80 to 0x2BFF EMPTY FLT10_ BUFFER EMPTY FLT11_ BUFFER EMPTY 0x2780 to 0x27FF EMPTY 0x2900 to 0x297F- R 0x2700 to 0x277F- R FLT7_ BUFFER FLT9_ BUFFER 0x2680 to 0x26FF EMPTY 0x2880 to 0x28FF 0x2600 to 0x267F- R FLT6_ BUFFER EMPTY 0x2580 to 0x25FF EMPTY 0x2800 to 0x287F- R 0x2500 to 0x257F- R FLT5_ BUFFER FLT8_ BUFFER 0x2480 to 0x24FF ADDRESS (HEX) EMPTY REGISTER FUNCTION 40 data6 - - - - - - data7 - - data14 data6 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - 13/5 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - 12/4 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - 11/3 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - 10/2 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - 9/1 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - 8/0 DVB compliant descrambler data15 data14 - - data7 - - data15 data6 data7 - - data14 - - data15 data6 data7 - - data14 - - data15 data6 - - data7 - - data14 data6 data15 data14 - - data7 - - data15 data6 data7 - - data14 - - data15 14/6 15/7 BITS Philips Semiconductors Product specification SAA7206H 1996 Oct 09 0x3100 to 0x317F- R 0x3180 to 0xFFFF EMPTY 0x2F00 to 0x2F7F- R FLT15_ BUFFER FLT17_ BUFFER 0x2E80 to 0x2EFF EMPTY 0x3080 to 0x30FF 0x2E00 to 0x2E7F- R FLT14_ BUFFER EMPTY 0x2D80 to 0x2DFF EMPTY 0x3000 to 0x307F- R 0x2D00 to 0x2D7F- R FLT13_ BUFFER FLT16_ BUFFER 0x2C80 to 0x2CFF EMPTY 0x2F80 to 0x2FFF 0x2C00 to 0x2C7F- R FLT12_ BUFFER EMPTY ADDRESS (HEX) REGISTER FUNCTION 41 data6 - - - - - - data7 - - data14 data6 data15 data14 data7 - - data15 - data6 - data14 - - data7 - - data15 data6 data7 - - data14 - - data15 data6 - - data7 - - data14 data6 data15 data14 data7 14/6 data15 15/7 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 - - data5 data13 13/5 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 - - data4 data12 12/4 BITS - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 - - data3 data11 11/3 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 - - data2 data10 10/2 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 - - data1 data9 9/1 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 - - data0 data8 8/0 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER MIN. MAX. UNIT VDDD(pads) digital supply voltage for pads (+5 V) -0.5 +6.5 V VDDD(core) digital supply voltage for core (+3.3 V) -0.5 +5.0 V VI DC input voltage -0.5 VDDD + 0.5 V VO DC output voltage; -0.5 VDDD + 0.5 V IDDD, ISSD DC current; VDD or VSS - 52 mA Ii(max) maximum input current -10 +10 mA Io(max) maximum output current -20 +20 mA Ptot total power dissipation - 250 mW Tstg storage temperature -65 +150 C Tamb operating ambient temperature 0 70 C 9 HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. Every pin withstands the ESD test in accordance with "UZW-BO/FQ-B3020"; 0 , 200 pF Machine Model (300 V). 10 THERMAL CHARACTERISTICS SYMBOL Rth j-a PARAMETER CONDITIONS thermal resistance from junction to ambient VALUE UNIT 56 K/W MAX. UNIT in free air 11 DC CHARACTERISTICS VDDD(core) = 3.3 V 0.3 V; VDDD = 5 V 0.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. IDDD(q) quiescent supply current VDDD = 5.5 V; note 1 - 100 A IDDD(core) digital operating current for core VDDD = 5.5 V; VDDD(core) = 3.6 V; note 2 - 42 mA IDDD(pads) digital operating current for pads VDDD = 5.5 V; VDDD(core) = 3.6 V; note 2 - 10 mA VIL LOW level input voltage 0 0.8 V VIH HIGH level input voltage 2.0 VDDD V ILI input leakage current Vi = 0 V; Tamb = 25 C - 10 A Vi = 5.5 V; Tamb = 25 C - 10 A VOL LOW level output voltage Io = 4 mA 0 0.1VDDD V VOH HIGH level output voltage Io = 4 mA 0.9VDDD VDDD V Notes 1. All inputs at VSSD or VDDD. 2. Operating inputs, unloaded outputs. 1996 Oct 09 42 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 12 AC CHARACTERISTICS VDDD(core) = 3.3 V 0.3 V; VDDD = 5 V 0.5 V; Tamb = 0 to 70 C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Input interface; (see Fig.12) - 5 pF 111 - ns - 10 ns input clock fall time - 10 ns input clock HIGH time 20 - ns tCLKL input clock LOW time 20 - ns ti(r) input rise time - 10 ns ti(f) input fall time - 10 ns tsu(i) input set-up time 15 - ns th(i) input hold time 5 - ns - 5 pF Ci input capacitance Tcy byte strobe input cycle time (asynchronous mode) ti(r)(CLK) input clock rise time ti(f)(CLK) tCLKH note 1 Microcontroller interface Ci input capacitance Tcy(CS) chip select cycle time 111 - ns tr(CS) chip select rise time - 10 ns tf(CS) chip select fall time - 10 ns tCSH chip select HIGH time 20 - ns tCSL chip select LOW time 20 - ns see also Fig.9 WRITE CYCLE; (see Figs 14 and 15) ti(r) input rise time - 10 ns ti(f) input fall time - 10 ns tsu(i) input set-up time 15 - ns th(i) input hold time 5 - ns READ CYCLE; (see Fig.16) tCSLr chip select LOW time in read mode 240 - ns to(r) output rise time - 10 ns to(f) output fall time - 10 ns to(d) output delay time - 30 ns to(h) output hold time 5 - ns toL(Z) output low Z time note 2 3 30 ns toH(Z) output high Z time note 2 3 30 ns 1996 Oct 09 43 Philips Semiconductors Product specification DVB compliant descrambler SYMBOL PARAMETER SAA7206H CONDITIONS MIN. MAX. UNIT Output interface; (see Fig.13) Co output capacitance - 10 pF CL output load capacitance - 50 pF Tcy(DCLK) output clock cycle time (DCLK) 111 - ns to(r)(DCLK) output clock rise time - 10 ns to(f)(DCLK) output clock fall time - 10 ns tDCLKH output clock HIGH time 20 - ns tDCLKL output clock LOW time 20 - ns to(r) output rise time - 10 ns to(f) output fall time - 10 ns to(h) output hold time CL = 5 pF 3 - ns to(d) output delay time CL = 30 pF - 40 ns Notes 1. In the synchronous mode all input signals are referenced to the descrambler clock which is specified in the output interface part. In the asynchronous mode all input signals are referenced to the MBCLK. 2. Data output is low impedance when both (DCS = 0) AND (R/W = 1). toL(Z) is defined after the last change of both signals which makes the data output low impedance. toH(Z) is defined after the first change of both signals which makes the data output high impedance. 1996 Oct 09 44 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H ti(r)(CLK) handbook, full pagewidth ti(f)(CLK) tCLKH MBCLK (asynchronous mode) or tCLKL DCS (synchronous mode) Tcy(CLK) tsu(i) th(i) MIN 7 to MIN0 MDV MB/MB MSYNC MGG324 ti(r) ti(f) Fig.12 Timing definition of the input interface signals. handbook, full pagewidth to(f)(DCLK) to(r)(DCLK) tDCLKH tDCLKL DCS Tcy(DCLK) to(d) to(h) DATO7 to DATO0 DVO SYNCO to(r) to(f) Fig.13 Timing definition of the output interface signals. 1996 Oct 09 45 MGG325 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H tr(CS) handbook, full pagewidth tCSH tf(CS) tCSL DCS Tcy(CS) ti(r) ti(f) A1 tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) A0 R/W DAT0 to DAT7 MSByte LSByte MGG326 ti(r) ti(f) Fig.14 Timing definition of the microcontroller interface signals (address write cycle). 1996 Oct 09 46 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H tCSH tr(CS) handbook, full pagewidth tf(CS) tCSL DCS Tcy(CS) ti(f) ti(r) A1 tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) tsu(i) th(i) A0 R/W DAT0 to DAT7 MSByte LSByte MGG327 ti(r) ti(f) Fig.15 Timing definition of the microcontroller interface signals (data write cycle). 1996 Oct 09 47 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H handbook, full pagewidth tCSLr tf(CS) tr(CS) DCS A1 A0 tsu(i) th(i) R/W to(d) to(d) to(h) to(h) DATA MSByte toL(Z) to(r) LSByte to(f) toH(Z) Fig.16 Timing definition of the microcontroller interface signals (read cycle). 1996 Oct 09 48 MGG328 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 13 PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-2 1996 Oct 09 EUROPEAN PROJECTION 49 o 7 0o Philips Semiconductors Product specification DVB compliant descrambler SAA7206H If wave soldering cannot be avoided, the following conditions must be observed: 14 SOLDERING 14.1 Introduction * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 14.2 14.3.2 Reflow soldering Wave soldering techniques can be used for all SO packages if the following conditions are observed: Reflow soldering techniques are suitable for all QFP and SO packages. * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Manual" (order code 9397 750 00192). * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. 14.3.3 Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. 14.3.1 A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Wave soldering Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. QFP Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Oct 09 METHOD (QFP AND SO) During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. 14.3 SO 50 Philips Semiconductors Product specification DVB compliant descrambler SAA7206H 15 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Oct 09 51 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 247 9145, Fax. +7 095 247 9144 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (c) Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/02/pp52 Date of release: 1996 Oct 09 Document order number: 9397 750 01331