© Semiconductor Components Industries, LLC, 2015
May, 2015 − Rev. 12
1Publication Order Number:
NCP1230/D
NCP1230
Low-Standby Power High
Performance PWM
Controller
The NCP1230 represents a major leap towards achieving low
standby power in medium−to−high power Switched−Mode Power
Supplies such as notebook adapters, off−line battery chargers and
consumer electronics equipment. Housed in a compact 8−pin package
(SOIC−8, SOIC−7, or PDIP−7), the NCP1230 contains all needed
control functionality to build a rugged and efficient power supply. The
NCP1230 is a current mode controller with internal ramp
compensation. Among the unique features offered by the NCP1230 is
an event management scheme that can disable the front−end PFC
circuit during standby, thus reducing the no load power consumption.
The NCP1230 itself goes into cycle skipping at light loads while
limiting peak current (to 25% of nominal peak) so that no acoustic
noise is generated. The NCP1230 has a high−voltage startup circuit
that eliminates external components and reduces power consumption.
The NCP1230 also features an internal latching function that can be
used for OVP protection. This latch is triggered by pulling the CS pin
above 3.0 V and can only be reset by pulling VCC to ground. True
overload protection, internal 2.5 ms soft−start, internal leading edge
blanking, internal frequency dithering for low EMI are some of the
other important features offered by the NCP1230.
Features
•Current−Mode Operation with Internal Ramp Compensation
•Internal High−Voltage Startup Current Source for Loss−Less Startup
•Extremely Low No−Load Standby Power
•Skip−Cycle Capability at Low Peak Currents
•Direct Connection to PFC Controller for Improved No−Load Standby
Power
•Internal 2.5 ms Soft−Start
•Internal Leading Edge Blanking
•Latched Primary Overcurrent and Overvoltage Protection
•Short−Circuit Protection Independent of Auxiliary Level
•Internal Frequency Jittering for Improved EMI Signature
•+500 mA/−800 mA Peak Current Drive Capability
•Available in Three Frequency Options: 65 kHz, 100 kHz, and 133 kHz
•Direct Optocoupler Connection
•SPICE Models Available for TRANsient and AC Analysis
•This is a Pb−Free Device
Typical Applications
•High Power AC−DC Adapters for Notebooks, etc.
•Offline Battery Chargers
•Set−Top Boxes Power Supplies, TV, Monitors, etc.
MARKING
DIAGRAM
xxx = Device Code: 65, 100, 133
y = Device Code: 6, 1, 1
y= Device Code: 5, 0, 3
A = Assembly Location
L = Wafer Lot
Y, YY = Year
W, WW = Work Week
G = Pb−Free Package
G= Pb−Free Package
(Note: Microdot may be in either location)
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PDIP−7 VHVIC
P SUFFIX
CASE 626B
1
8
1
8
SOIC−8 VHVIC
D SUFFIX
CASE 751
PIN CONNECTIONS
DRVGND
18
VCC
CS
FB
HVPFC Vcc
See detailed ordering and shipping information in the ordering
information section on page 4 of this data sheet.
ORDERING INFORMATION
1230Pxxx
AWL
YYWWG
1
1
8SOIC−7
D1 SUFFIX
CASE 751U
30D16
ALYWG
G
1
8
230Dy
ALYWy
G
1
8
NCP1230
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2
Figure 1. Typical Application Example
1 8
2
3
4
7
6
5
CBulk
HV
+
MC33262/33260
PFC_VCC
OVP
1 8
2
3
4
7
6
5
NCP1230
OVP
+
GN-
D
Vout
Rsense
GND
Ramp Comp
10 k
VCC Cap
PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Pin Description
1PFC VCC This pin provides
the bias voltage to
the PFC controller.
This pin is a direct connection to the VCC pin (Pin 6) via a low impedance switch. In
standby and during the startup sequence, the switch is open and the PFC VCC is
shut down. As soon as the aux. winding is stabilized, Pin 1 connects to the VCC pin
and provides bias to the PFC controller. It goes down in standby and fault conditions.
2 FB Feedback Signal An optocoupler collector pulls this pin low to regulate. When the current setpoint
reaches 25% of the maximum peak, the controller skips cycles.
3 CS/OVP Current Sense This pin incorporates three different functions: the current sense function, an internal
ramp compensation signal and a 3.0 V latch−off level which latches the output off
until VCC is recycled.
4 GND IC Ground −
5 DRV Driver Output With a drive capability of +500 mA / −800 mA, the NCP1230 can drive large Qg
MOSFETs.
6 VCC VCC Input The controller accepts voltages up to 18 V and features a UVLO turn−off threshold of
7.7 V typical.
7 NC − −
8 HV High−Voltage This pin connects to the bulk voltage and offers a lossless startup sequence. The
charging current is high enough to support the bias needs of a PWM controller
through Pin 1.
NCP1230
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3
Figure 2. Internal Circuit Architecture
+
+
+
+
+
+
1
2
3
GND
CS
FB
PFC_Vcc
PFC_Vcc
125 msec
Timer
Vdd_fb
PFC_Vcc
Skip
Vdd
Error
LEB
Soft−Start Ramp (1V max)
10 V
10 V
20k
55k
25k
18k
1.25 Vdc
0.75 Vdc
3.0 Vdc
2.5 msec
SS Timer
PWM
Latch−Off
Thermal
Shutdown
Vccreset
OSC
2.3 Vpp
Ramp
Frequency
Modulation
/ 2
4.0 Vdc
4Vcomp
3.2 mAdc
20V
DRV
VCC
HV 8
6
5
Internal
Bias
Vcc Mgmt
Vccoff=12.6V
Vccmin=7.7V
Vcclatch=5.6V
QR
S
QR
S
4
SW1
−
−
−
−
−
−
Fault
NCP1230
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4
MAXIMUM RATINGS (Notes 1 and 2)
Rating Symbol Value Unit
Maximum Voltage on Pin 8
Maximum Current
VDS
IC2
−0.3 to 500
100
V
mA
Power Supply Voltage, Pin 6
Current
VCC
ICC2
−0.3 to 18
100
V
mA
Drive Output Voltage, Pin 5
Drive Current
VDV
Io
18
1.0
V
A
Voltage Current Sense Pin, Pin 3
Current
Vcs
Ics
10
100
V
mA
Voltage Feedback, Pin 2
Current
Vfb
Ifb
10
100
V
mA
Voltage, Pin 1
Maximum Continuous Current Flowing from Pin 1
VPFC
IPFC
18
35
V
mA
Thermal Resistance, Junction−to−Air, PDIP Version RJA 100 °C/W
Thermal Resistance, Junction−to−Air, SOIC Version RJA 178 °C/W
Maximum Power Dissipation @ TA = 25°C PDIP
SOIC
Pmax 1.25
0.702
W
Maximum Junction Temperature TJ150 °C
Storage Temperature Range Tstg −60 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and exceeds the following tests:
Pin 1−6: Human Body Model 2000 V per JEDEC Standard JES22, Method A114E.
Machine Model Method 200 V per JEDEC Standard JESD22, Method A115A.
Pin 8 is the HV startup of the device and is rated to the maximum rating of the part, or 500 V.
2. This device contains latchup protection and exceeds 100 mA per JEDEC Standard JESD78.
ORDERING INFORMATION
Device Package Shipping†
NCP1230D165R2G SOIC−7
(Pb−Free)
2500 / Tape & Reel
NCP1230D65R2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230D100R2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230D133R2G SOIC−8
(Pb−Free)
2500 / Tape & Reel
NCP1230P65G PDIP−7
(Pb−Free)
50 Units/ Rail
NCP1230P100G PDIP−7
(Pb−Free)
50 Units/ Rail
NCP1230P133G PDIP−7
(Pb−Free)
50 Units/ Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP1230
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5
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 13 V, VPIN8 = 30 V unless otherwise noted.)
Characteristic Symbol Pin Min Typ Max Unit
Supply Section (All frequency versions, otherwise noted)
Turn−On Threshold Level, VCC Going Up (Vfb = 2.0 V) VCCOFF 6 11.6 12.6 13.6 V
Minimum Operating Voltage after Turn−On VCC(min) 6 7.0 7.7 8.4 V
VCC Decreasing Level at which the Latch−Off Phase Ends (Vfb = 3.5 V) VCClatch 6 5.0 5.6 6.2 V
VCC Level at which the Internal Logic gets Reset VCCreset 6−4.0 −V
Internal IC Consumption, No Output Load on Pin 6 (Vfb = 2.5 V) ICC1 6 0.6 1.1 1.8 mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 65 kHz
(Vfb = 2.5 V)
ICC2 6 1.3 1.8 2.5 mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 100 kHz ICC2 6 1.3 2.2 3.0 mA
Internal IC Consumption, 1.0 nF Output Load on Pin 6, FSW = 133 kHz ICC2 6 1.3 2.8 3.3 mA
Internal IC Consumption, Latch−Off Phase ICC3 6 400 680 1000 A
Internal Startup Current Source
High−Voltage Current Source, 1.0 nF Load
(VCCOFF −0.2 V, Vfb = 2.5 V, VPIN8 = 30 V)
IC1 8 1.8 3.2 4.2 mA
High−Voltage Current Source (VCC = 0 V) IC2 8 1.8 4.4 5.6 mA
Minimum Startup Voltage (Ic = 0.5 mA, VCCOFF −0.2 V, Vfb = 2.5 V) VHVmin 8−20 23 V
Startup Leakage (VPIN8 = 500 V) IHVLeak 8 10 30 80 A
Drive Output
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of Output Signal Tr5−40 −ns
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of Output Signal Tf5−15 −ns
Source Resistance, RLoad 300 (Vfb = 2.5 V) ROH 5 6.0 12.3 25
Sink Resistance, at 1.0 V on Pin 5 (Vfb = 3.5 V) ROL 5 3.0 7.5 18
Pin 1 Output Impedance (or Rdson between Pin 1 and Pin 6 when SW1
is closed) Rload on Pin 1 = 680
RPFC 1 6.0 11.7 23
Current Comparator and Thermal Shutdown
Input Bias Current @ 1.0 V Input Level on Pin 3 IIB 3−0.02 −A
Maximum Internal Current Setpoint Tj = 25°C
Tj = −40°C to +125°C
ILimit 3 1.010
0.979
1.063
−
1.116
1.127
V
Default Internal Setpoint for Skip Cycle Operation and Standby
Detection
Vskip 3 600 750 900 mV
Default Internal Setpoint to Leave Standby Vstby−out −1.0 1.25 1.5 V
Propagation Delay from CS Detected to Gate Turned Off (VGate = 10 V)
(Pin 5 Loaded by 1.0 nF)
TDEL CS 3−90 180 ns
Leading Edge Blanking Duration TLEB 3 100 200 350 ns
Soft−Start Period (Note 3) SS − − 2.5 −ms
Temperature Shutdown, Maximum Value (Note 3) TSD −150 165 −°C
Hysteresis while in Temperature Shutdown (Note 3) TSD hyste − − 25 −°C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Verified by Design.
NCP1230
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6
ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C,
VCC = 13 V, VPIN8 = 30 V unless otherwise noted.)
Characteristic Symbol Pin Min Typ Max Unit
Internal Oscillator
Oscillation Frequency, 65 kHz Version (Vfb = 2.5 V) Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC −60
58
55
65
−
−
70
72
72
kHz
Oscillation Frequency, 100 kHz Version Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC −93
90
85
100
−
−
107
110
110
kHz
Oscillation Frequency, 133 kHz Version Tj = 25°C
Tj = 0°C to +125°C
Tj = −40°C to +125°C
fOSC −123
120
113
133
−
−
143
146
146
kHz
Internal Modulation Swing, in Percentage of Fsw (Vfb = 2.5 V) (Note 4) − − − "6.4 −%
Internal Swing Period (Note 4) − − − 5.0 −ms
Maximum Duty−Cycle (CS = 0, Vfb = 2.5 V) Dmax −75 80 85 %
Internal Ramp Compensation
Internal Resistor (Note 4) Rup 3 9.0 18 36 k
Ramp Compensation Sawtooth Amplitude −3−2.3 −Vpp
Feedback Section
Opto Current Source (Vfb = 0.75 V) −2 200 235 270 A
Pin 3 to Current Setpoint Division Ratio (Note 4) Iratio − − 2.8 − −
Protection
Timeout before Validating Short−Circuit or PFC VCC (Note 4) TDEL − − 125 −ms
Latch−Off Level Vlatch 3 2.7 3.0 3.3 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Verified by Design.
Figure 3. VCC
(
OFF
)
Threshold vs. Temperature
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. VCC
(
min
)
Threshold vs. Temperature
7.0
7.2
7.4
7.6
7.8
8.0
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 150
VPIN8 = 30 V
VCC(min) THRESHOLD (V)
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
12.0
12.2
12.4
12.6
12.8
13.0
VCC(off), THRESHOLD (V)
150
VCC = 0 V VPIN8 = 30 V
NCP1230
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7
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5. VCC Latch Threshold vs. Temperature Figure 6. ICC1 Internal Current Consumption, No Load
vs. Temperature
Figure 7. ICC2 Internal Current Consumption,
1.0 nF Load vs. Temperature
Figure 8. ICC3 Internal Consumption,
Latch−Off Phase vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
5.0
5.2
5.4
5.6
5.8
6.0
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
0.6
0.85
1.1
1.35
1.6
TJ, JUNCTION TEMPERATURE (°C)
1.5
1.9
2.3
2.7
3.1
1251007550250−25−50
400
500
700
600
800
VCC LATCH THRESHOLD (V)
150
VPIN8 = 30 V
150
ICC1 (mA)
VCC = 13 V
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 150
VCC = 13 V
ICC2 (mA)
150
ICC3 (A)
133 kHz
100 kHz
65 kHz
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
2.0
2.5
3.0
3.5
4.0
1251007550250−25−50
3.0
3.5
4.0
4.5
5.0
IC1 (mA)
150
VCC = VCC − 0.2 V VPIN8 = 30 V
IC2 (mA)
15
0
VPIN8 = 30 V VCC = 0 V
Figure 9. IC1 Startup Current vs. Temperature Figure 10. IC2 Startup Current vs. Temperature
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8
TJ, JUNCTION TEMPERATURE (°C)
19.0
20.0
20.5
21.0
21.5
22.0
1251007550250−25−50
8.0
10
12
16
18
5.0
8.0
10
11
15
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 150
VCC = VCC(off) − 0.2 V
VHV MINIMUM (V)
150
DRIVE SOURCE RESISTANCE ()
VCC = 13 V
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 150
VCC = 13 V
DRIVE SINK RESISTANCE ()
14
6.0
7.0
9.0
13
14
12
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. Minimum Startup Voltage vs. Temperature Figure 12. Leakage Current vs. Temperature
Figure 13. Drive Source Resistance vs. Temperature Figure 14. Drive Sink Resistance vs. Temperature
19.5
0
50
75
100
VDRAIN, VOLTAGE (V)
85080060040020050101 950
VCC = 13 V
LEAKAGE CURRENT (A)
25
TJ = −40 °C
TJ = +25 °C
TJ = +125 °C
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
1.00
1.10
1.20
ILimit (V)
15
0
VCC = 13 V
0.90
0.95
1.05
1.15
Figure 15. RPFC vs. Temperature Figure 16. ILimit vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
8.0
9.0
12
14
16
18
150
VCC = 13 V
RPFC, RESISTANCE ()
10
11
13
15
17
min
typ
max
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9
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
700
725
750
775
800
TJ, JUNCTION TEMPERATURE (°C)
1.10
1.15
1.20
1.30
1.35
1.40
1251007550250−25−50
1.5
2.0
2.5
3.5
4.0
Vskip (mV)
150
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 15
0
Vstby−out (V)
150
SOFT−START (ms)
VCC = 13 V
3.0
VCC = 13 V
1.25
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 17. Vskip vs. Temperature Figure 18. Vstby−out vs. Temperature
Figure 19. Soft−Start vs. Temperature Figure 20. Frequency (65 kHz) vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
50
60
70
80
150
FREQUENCY (kHz)
VCC = 13 V
55
65
75
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
90
94
98
106
110
150
FREQUENCY (kHz)
VCC = 13 V
102
Figure 21. Frequency (100 kHz) vs. Temperature Figure 22. Frequency (133 kHz) vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
125
129
133
141
145
15
0
FREQUENCY (kHz)
VCC = 13 V
137
NCP1230
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10
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
79.0
80.0
81.0
150
VCC = 13 V
DUTY CYCLE MAX (%)
79.5
TYPICAL PERFORMANCE CHARACTERISTICS
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
10
18
20
15
0
12
16
14
Rup (k)
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
230
260
280
Iopto (A)
150
200
210
240
270
220
250
Vfb = 0.75 V
80.5
4.0
6.0
10.0
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50 150
VCC = 13 V
INTERNAL MODULATION SWING (%)
5.0
7.0
fosc = 65 kHz
8.0
9.0
Figure 23. Internal Modulation Swing
vs. Temperature
Figure 24. Maximum Duty Cycle
vs. Temperature
Figure 25. Iopto vs. Temperature Figure 26. Internal Ramp Compensation Resistor
vs. Temperature
VCC = 13 V
22
24
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
2.50
3.00
3.50
Vlatch (V)
150
2.75
3.25
Figure 27. Fault Time Delay vs. Temperature Figure 28. Vlatch vs. Temperature
TJ, JUNCTION TEMPERATURE (°C)
1251007550250−25−50
100
140
150
150
110
130
120
TDEL FAULT TIME DELAY (ms)
NCP1230
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11
OPERATING DESCRIPTION
Introduction
The NCP1230 is a current mode controller which provides
a high level of integration by providing all the required
control logic, protection, and a PWM Drive Output into a
single chip which is ideal for low cost, medium to high
power off−line application, such as notebook adapters,
battery chargers, set−boxes, TV, and computer monitors.
The NCP1230 can be connected directly to a high voltage
source providing lossless startup, and eliminating external
startup circuitry. In addition, the NCP1230 has a PFC_VCC
output pin which provides the bias supply power for a Power
Factor Correction controller, or other logic. The NCP1230
has an event management scheme which disables the
PFC_VCC output during standby, and overload conditions.
PFC_VCC
As shown on the internal NCP1230 diagram, an internal
low impedance switch SW1 routes Pin 6 (VCC) to Pin 1
when the power supply is operating under nominal load
conditions. The PFC_VCC signal is capable of delivering up
to 35 mA of continuous current for a PFC Controller, or
other logic.
Connecting the NCP1230 PFC_VCC output to a PFC
Controller chip is very straight forward, refer to the “Typical
Application Example” all that is generally required is a
small decoupling capacitor (0.1 F).
Figure 29. Typical Application Example
1 8
2
3
4
7
6
5
High Voltage
MC33262/33260
1 8
2
3
4
7
6
5
NCP1230
+
GND
Vout
Rsense
GND
VCC Cap
PFC_VCC
NCP1230
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12
Feedback
The feedback pin has been designed to be connected
directly to the open−collector output of an optocoupler. The
pin is pulled−up through a 20 k resistor to the internal
Vdd_fb supply (5 volts nominal). The feedback input signal
is divided down, by a factor of three, and connected to the
negative (−) input of the PWM comparator. The positive (+)
input to the PWM comparator is the current sense signal
(Figure 30).
The NCP1230 is a peak current mode controller, where
the feedback signal is proportional to the output power. At
the beginning of the cycle, the power switch is turns−on and
the current begins to increase in the primary of the
transformer, when the peak current crosses the feedback
voltage level, the PWM comparators switches from a logic
level low, to a logic level high, resetting the PWM latching
Flip−Flop, turning off the power switch until the next
oscillator clock cycle begins.
Figure 30.
Vdd_fb
+
−
FB PWM
2.3 Vpp
Ramp
LEB
20k
18k
25k
55k
10 V
2
3
The feedback pin input is clamped to a nominal 10 volt for
ESD protection.
Skip Mode
The feedback input is connected in parallel with the skip
cycle logic (Figure 31). When the feedback voltage drops
below 25% of the maximum peak current (1.0 V/Rsense) the
IC prevents the current from decreasing any further and
starts to blank the output pulses. This is called the skip cycle
mode. While the controller is in the burst mode the power
transfer now depends upon the duty cycle of the pulse burst
width which reduces the average input power demand.
Vc+Ipk @Rs@3
where:
Vc = control voltage (Feedback pin input),
Ipk = Peak primary current,
Rs = Current sense resistor,
3 = Feedback divider ratio.
SkipLevel +3V @25% +0.75V
Ipk +0.75
Rs@3
where:
Ipk @Rs+1V
Ipk +2@Pin
Lp@f
Ǹ
where:
Pin = is the power level where the NCP1230 will go into
the skip mode
Lp = Primary inductance
f = NCP1230 controller frequency
Pin +Lp@f@Ipk2
2
Pin +Pout
Eff
where:
Eff = the power supply efficiency
Rout +Eout2
Pout
Figure 31.
+125 ms
−
+
−
+
FB
+
Vskip
S
R
PFC_VCC
CS Cmp
Latch
Reset
Vskip
/ Vstby−out
S is rising edge triggered
R is falling edge triggered
Vdd_fb
1.25 V
0.75 V
During the skip mode the PFC_Vcc signal (pin 1) is
asserted into a high impedance state when a light load
condition is detected and confirmed, Figure 32 shows
typical waveforms. The first section of the waveform shows
a normal startup condition, where the output voltage is low,
as a result the feedback signal will be high asking the
controller to provide the maximum power to the output. The
second phase is under normal loading, and the output is in
regulation. The third phase is when the output power drops
below the 25% threshold (the feedback voltage drops to 0.75
volts). When this occurs, the 125 msec timer starts, and if the
conditions is still present after the time output period, the
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13
NCP1230 confirms that the low output power condition is
present, and the internal SW1 opens, and the PFC_Vcc
signal output is shuts down. While the NCP1230 is in the
skip mode the FB pin will move around the 750 mV
threshold level, with approximately 100 mVp−p of
hysteresis on the skip comparator, at a period which depends
upon the (light) loading of the power supply and its various
time constants. Since this ripple amplitude superimposed
over the FB pin is lower than the second threshold (1.25
volt), the PFC_Vcc comparator output stays high (PFC_Vcc
output Pin 1 is low).
In Phase four, the output power demands have increases
and the feedback voltage rises above the 1.25 volts
threshold, the NCP1230 exits the skip mode, and returns to
normal operation.
Figure 32.
Regulation
1.25 V
0.75 V
Skip + 60%
PFC is Off
PFC is On
PFC is On
No Delay
125 ms
Delay
Max IP
PFC is Off
VFB
Leaving Standby (Skip Mode)
When the feedback voltage rises above the 1.25 volts
reference (leaving standby) the skip cycle activity stops and
SW1 immediately closes and restarts the PFC, there is no
delay in turning on SW1 under these conditions, refer to
Figure 32.
Current Sense
The NCP1230 is a peak current mode controller, where
the current sense input is internally clamped to 1.0 V, so the
sense resister is determined by Rsense = 1.0 V /Ipk
maximum.
There is a 18k resistor connected to the CS pin, the other
end of the 18k resistor is connect to the output of the internal
oscillator for ramp compensation (refer to Figure 33).
Ramp Compensation
In Switch Mode Power Supplies operating in Continuous
Conduction Mode (CCM) with a duty−cycle greater than
50%, oscillation will take place at half the switching
frequency. To eliminate this condition, Ramp Compensation
can be added to the current sense signal to cure sub harmonic
oscillations. To lower the current loop gain one typically
injects between 50 and 100% of the inductor down slope.
The NCP1230 provides an internal 2.3 Vpp ramp which
is summed internally through a 18 k resistor to the current
sense pin. To implement ramp compensation a resistor needs
to be connected from the current sense resistor, to the current
sense pin 3.
Example:
If we assume we are using the 65 kHz version of the
NCP1230, at 65 kHz the dv/dt of the ramp is 130 mV/s.
Assuming we are designing a FLYBACK converter which
has a primary inductance, Lp, of 350 H, and the SMPS has
a +12 V output with a Np:Ns ratio of 1:0.1. The OFF time
primary current slope is given by:
(Vout )Vf) @Ns
Np
Lp
= 371 mA/s or 37 mV/s
when imposed on a current sense resistor (Rsense) of 0.1 .
If we select 75% of the inductor current downslope as our
required amount of ramp compensation, then we shall inject
27 mV/s.
With our internal compensation being of 130 mV, the
divider ratio (divratio) between Rcomp and the 18 k is
0.207. Therefore:
Rcomp +18k @divratio
(1 *divratio) = 4.69 k
Figure 33.
+
−
CS
LEB
18 k
Rcomp
Rsense
Fb/3
2.3 V
0V
NCP1230
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14
Leading Edge Blanking
In Switch Mode Power Supplies (SMPS) there can be a
large current spike at the beginning of the current ramp due
to the Power Switch gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. To prevent prematurely turning off the PWM drive
output, a Leading Edges Blanking (LEB) (Figure 34) circuit
is place is series with the current sense input, and PWM
comparator. The LEB circuit masks the first 250 ns of the
current sense signal.
Figure 34.
-
+
+
-
CS
Vccreset
Latch−Off
R
S
Q
FB/3
2.3 Vpp
Ramp
Thermal Shutdown
Skip
125 msec Timer
PWM Comparator
18 k
10 V
LEB
3 V
3250 ns
Short−Circuit Condition
The NCP1230 is different from other controllers which
use an auxiliary windings to detect events on the isolated
secondary output. There maybe some conditions (for
example when the leakage inductance is high) where it can
be extremely difficult to implement short−circuit and
overload protection. This occurs because when the power
switch opens, the leakage inductance superimposes a large
spike on the switch drain voltage. This spike is seen on the
isolated secondary output and on the auxiliary winding.
Because the auxiliary winding and diode form a peak
rectifier, the auxiliary Vcc capacitor voltage can be charged
up to the peak value rather than the true plateau which is
proportional to the output level.
To resolve these issues the NCP1230 monitors the 1.0 V
error flag. As soon as the internal 1.0 V error flag is asserted
high, a 125 ms timer starts. If at the end of the 125 ms timeout
period, the error flag is still asserted then the controller
determines that there is a true fault condition and stops the
PWM drive output, refer to Figure 35. When this occurs,
Vcc starts to decrease because the power supply is locked
out. When Vcc drops below UVLOlow (7.7 V typical), it
enters a latch−off phase where the internal consumption is
reduced down to 680 A (typical). The voltage on the Vcc
capacitor continues to drop, but at a lower rate. When Vcc
reaches the latch−off level (5.6 V), the current source is
turned on and pulls Vcc above UVLOhigh. To limit the fault
output power, a divide−by−two circuit is connected to the
Vcc pin that requires two startup sequences before
attempting to restart the power supply. If the fault has gone
and the error flag is low, the controller resumes normal
operations.
Under transient load conditions, if the error flag is
asserted, the error flag will normally drop prior to the 125 ms
timeout period and the controller continues to operate
normally.
If the 125 msec timer expires while the NCP1230 is in the
Skip Mode, SW1 opens and the PFC_Vcc output will shut
down and will not be activated until the fault goes away and
the power supply resumes normal operations.
While in the Skip Mode, to avoid any thermal runaway it
is desirable for the Burst duty cycle to be kept below
20%(the burst duty−cycle is defined as Tpulse / Tfault).
NCP1230
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15
Figure 35.
125ms
12.6V
7.7V
125ms 125ms 125ms
The latch−off phase can also be initiated, more classically,
when Vcc drops below UVLO (7.7 V typical). During this
fault detection method, the controller will not wait for the
125 ms time−out, or the error flag before it goes into the
latch−off phase, operating in the skip mode under these
conditions, refer to Figure 36.
Figure 36.
Regulation
125 ms
Fault
Regulation
PFC
VCC
1 V
Flag
Timer
5.6 V
7.7 V
12.6 V
VCC PWM
125 ms
2.5 ms
SS
NCP1230
www.onsemi.com
16
Current Sense Input Pin Latch−Off
The NCP1230 features a fast comparator (Figure 34) that
monitors the current sense pin during the controller off time.
If for any reason the voltage on pin 3 increases above 3.0 V,
the NCP1230 immediately stops the PWM drive pulses and
permanently stays latched off until the bias supply to the
NCP1230 is cycled down (Vcc must drop below 4.0 V, e.g.
when the user unplugs the converter from the mains). This
offers the designer the flexibility to implement an externally
shutdown circuit (for example for overvoltage or
overtemperature conditions). When the controller is latched
off through pin 3 (current sense), SW1 opens and shuts off
PFC_Vcc output.
Figure 37 shows how to implement the external latch via
a Zener diode and a simple PNP transistor. The PNP actually
samples the Zener voltage during the OFF time only, hence
leaving the CS information un−altered during the ON time.
Various component arrangements can be made, e.g. adding
a NTC device for the Over Temperature Protection (OTP).
Figure 37.
Connecting the PNP to the drive only activates the offset
generation during Toff. Here is a solution monitoring the
auziliary Vcc rail.
1
2
3
45
8
6
7
Ramp
1k
CVcc
HV
Vz
Drive Output
The NCP1230 provides a Drive Output which can be
connected through a current limiting resistor to the gate of
a MOSFET. The Driver output is capable of delivering drive
pulses with a rise time of 40 ns, and a fall time of 15 ns
through its internal source and sink resistance of 12.3 ohms
(typical), measured with a 1.0 nF capacitive load.
Startup Sequence
The NCP1230 has an internal High Voltage Startup
Circuit (Pin 8) which is connected to the high voltage DC
bus (Refer to Figure 36). When power is applied to the bus,
the NCP1230 internal current source (typically 3.2 mA) is
biased and charges up the external Vcc capacitor on pin 6,
refer to Figure 38. When the voltage on pin 6 (Vcc) reaches
Vccoff (12.6 V typically), the current source is turned off
reducing the amount of power being dissipated in the chip.
The NCP1230 then turns on the drive output to the external
MOSFET in an attempt to increase the output voltage and
charge up the Vcc capacitor through the Vaux winding in the
transformer.
During the startup sequence, the controller pushes for the
maximum peak current, which is reached after the 2.5 ms
soft−start period. As soon as the maximum peak set point is
reached, the internal 1.0 V Zener diode actively limits the
current amplitude to 1.0 V/Rsense and asserts an error flag
indicating that a maximum current condition is being
observed. In this mode, the controller must determine if it is
a normal startup period (or transient load) or is the controller
is facing a fault condition. To determine the difference
between a normal startup sequence, and a fault condition, the
error flag is asserted, and the 125 ms timer starts to count
down. If the error flag drops prior to the 125 ms time−out
period, the controller resets the timer and determines that it
was a normal startup sequence and enables the low
impedance switch (SW1), enabling the PFC_Vcc output.
If at the end of the 125 ms period the error flag is still
asserted, then the controller assumes that it is a fault
condition and the PWM controller enters the skip mode and
does not enable the PFC_Vcc output.
Figure 38.
−
+
8
6
4
3.2 mA or 0
CVcc Aux
HV
12.6 V/
5.6 V
ON Semiconductor recommends that the Vcc capacitor be at
least 47 F to be sure that the Vcc supply voltage does not drop
below Vccmin (7.7 V typical) during standby power mode and
unusual fault conditions.
Soft−Start
The NCP1230 features an internal 2.5 ms soft−start
circuit. As soon as Vcc reaches a nominal 12.6 V, the
soft−start circuit is activated. The soft−start circuit output
controls a reference on the minus (−) input to an amplifier
(refer to Figure 39), the positive (+) input to the amplifier is
the feedback input (divided by 3). The output of the
amplifier drives a FET which clamps the feedback signal. As
the soft−start circuit output ramps up, it allow the feedback
pin input to the PWM comparator to gradually increased
from near zero up to the maximum clamping level of 1.0
V/Rsense. This occurs over the entire 2.5 ms soft−start
period until the supply enters regulation. The soft−start is
also activated every time a restart is attempted. Figure 40
shows a typical soft−start up sequence.
NCP1230
www.onsemi.com
18
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading out the average switching energy
around the controller operating switching frequency. The
NCP1230 offers a nominal ±6.4% deviation of the nominal
switching frequency. The sweep sawtooth is internally
generated and modulates the clock up and down with a 5 ms
period. Figure 41 illustrates the NCP1230 behavior:
Figure 41. An Internal Ramp is used to Introduce Frequency Jittering on the Oscillator Saw Tooth
Internal Ramp
62.4 kHz
67.6 kHz
65 kHz
5 ms
Internal Sawtooth
Thermal Protection
An internal Thermal Shutdown is provided to protect the
integrated circuit in the event that the maximum junction
temperature is exceeded. When activated (165°C typically)
the controller turns off the PWM Drive Output. When this
occurs, Vcc will drop (the rate is dependent on the NCP1230
loading and the size of the Vcc capacitor) because the
controller is no longer delivering drive pulses to the
auxiliary winding charging up the Vcc capacitor. When Vcc
drops below 4.0 volts and the Vccreset circuit is activated,
the controller will restart. If the user is using a fixed bias
supply (the bias supply is provided from a source other than
from an auxiliary winding, refer to the typical application )
and Vcc is not allow to drop below 4.0 volts under a thermal
shutdown condition, the NCP1230 will not restart. This
feature is provided to prevent catastrophic failure from
accidentally overheating the device.
NCP1230
www.onsemi.com
19
PACKAGE DIMENSIONS
SOIC−7
CASE 751U
ISSUE E
SEATING
PLANE
1
4
58
R
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B ARE DATUMS AND T
IS A DATUM SURFACE.
4. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
5. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
S
D
H
C
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−A−
−B−
G
M
B
M
0.25 (0.010)
−T−
B
M
0.25 (0.010) TSAS
M
7 PL
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP1230
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20
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45 _
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
NCP1230
www.onsemi.com
21
PACKAGE DIMENSIONS
PDIP−7 (PDIP−8 LESS PIN 7)
CASE 626B
ISSUE D
14
58
b2
NOTE 8
D
b
L
A1
A
eB
E
A
TOP VIEW
C
SEATING
PLANE
0.010 CA
SIDE VIEW
END VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACK-
AGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
E1
M
8X
c
D1
B
H
NOTE 5
e
e/2 A2
NOTE 3
MBMNOTE 6
M
DIM MIN MAX
INCHES
A−−−− 0.210
A1 0.015 −−−−
b0.014 0.022
C0.008 0.014
D0.355 0.400
D1 0.005 −−−−
e0.100 BSC
E0.300 0.325
M−−−− 10
−−− 5.33
0.38 −−−
0.35 0.56
0.20 0.36
9.02 10.16
0.13 −−−
2.54 BSC
7.62 8.26
−−− 10
MIN MAX
MILLIMETERS
E1 0.240 0.280 6.10 7.11
b2
eB −−−− 0.430 −−− 10.92
0.060 TYP 1.52 TYP
A2 0.115 0.195 2.92 4.95
L0.115 0.150 2.92 3.81
°°
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