ICS840011 FEMTOCLOCKSTM CRYSTAL-TOLVCMOS/LVTTL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS840011 is a Fibre Channel Clock Generator ICS and a member of the HiPerClocksTM family of high HiPerClockSTM performance devices from IDT. The ICS840011 uses a 26.5625MHz or 25MHz crystal to synthesize 106.25MHz or 100MHz respectively. The ICS840011 has excellent phase jitter performance, from 637kHz - 10MHz integration range. The ICS840011 is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. * One LVCMOS/LVTTL output, 7 output impedence * Crystal oscillator interface designed for 26.5625MHz or 25MHz, 18pF parallel resonant crystal * Output frequency: 106.25MHz (typical) * VCO range: 560MHz to 680MHz * RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal (637KHz - 10MHz): 0.780ps (typical) * RMS phase noise at 125MHz: Offset Noise Power 100Hz ............... -95.7 dBc/Hz 1kHz ................ -121 dBc/Hz 10kHz ................ -129 dBc/Hz 100kHz ............. -129.6 dBc/Hz * 3.3V operating supply * -30C to 85C ambient operating temperature * Available in both standard (RoHS 5) and lead-free (RoHS 6) packages FREQUENCY TABLE Inputs Crystal Frequency (MHz) 26.5625 Output Frequency (MHz) 106.25 25 100 BLOCK DIAGRAM PIN ASSIGNMENT OE (Pullup) XTAL_IN OSC XTAL_OUT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. Q0 /6 1 2 3 4 8 7 6 5 VDD Q0 GND nc ICS840011 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View M = /24 (fixed) IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR VDDA OE XTAL_OUT XTAL_IN 1 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name 1 VDDA Power Type 2 OE Input 3, 4 5 XTAL_OUT, XTAL_IN nc Unused 6 GND Power 7 Q0 Output 8 VDD Power Description Pullup Input Analog supply pin. Output enable pin. When HIGH, Q0 output is enabled. When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. Power supply ground. Single-ended clock output. LVCMOS/LVTTL interface levels. 7 output impedance. Core supply pin. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance CPD Power Dissipation Capacitance RPULLUP Input Pullup Resistor ROUT Output Impedance Minimum VDD, VDDA = 3.465V 5 Typical Maximum Units 4 pF 24 pF 51 k 7 12 TABLE 3. CONTROL FUNCTION TABLE Control Inputs Output OE Q0 0 Hi-Z 1 Active IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 2 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, JA 101.7C/W (0 mps) Storage Temperature, TSTG -65C to 150C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -30C TO 85C Symbol Parameter Minimum Typical Maximum Units VDD Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDA Analog Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 80 mA IDDA Analog Supply Current 10 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -30C TO 85C Symbol Parameter VIH Input High Voltage Test Conditions VIL Input Low Voltage IIH Input High Current OE VDD = VIN = 3.465V IIL Input Low Current OE VDD = 3.465V, VIN = 0V VOH Output High Voltage; NOTE 1 Minimum Maximum Units 2 Typical VDD + 0.3 V -0.3 0.8 V 5 A -150 A 2.6 V Output Low Voltage; NOTE 1 VOL NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Information Section, "3.3V Output Load Test Circuit". 0.5 V Maximum Units TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental 26.5625 MHz Equivalent Series Resistance (ESR) Frequency 50 Shunt Capacitance 7 pF TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V5%, TA = -30C TO 85C Symbol Parameter fOUT Output Frequency RMS Phase Jitter (Random); NOTE 1 Output Rise/Fall Time tjit(O) t R / tF odc Output Duty Cycle All parameters are characterized @ 106.25MHz. NOTE 1: Please refer to the Phase Noise Plot. IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR Test Conditions Minimum Typical Maximum Units 93.33 106.25 113.33 MH z fOUT = 106.25MHz, (637kHz to 10MHz) 20% to 80% 25 0 600 ps fOUT = 106.25MHz 48 52 % 3 0.780 ps ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TYPICAL PHASE NOISE AT 106.25MHZ 0 -10 Fibre Channel Filter -20 -30 106.25MHz -40 RMS Phase Jitter (Random) 637K to 10MHz = 0.780ps -50 NOISE POWER dBc Hz -60 -70 -80 -90 -100 Raw Phase Noise Data -110 -120 -130 -140 -150 -160 -170 -180 Phase Noise Result by adding Fibre Channel Filter to raw data -190 100 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 4 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 1.65V 5% Noise Power Phase Noise Plot SCOPE VDD Qx Phase Noise Mask LVCMOS GND f1 Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot -1.65V 5% 3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER 80% 80% tR tF Q0 t PW t odc = Clock Outputs PERIOD t PW 20% 20% x 100% t PERIOD LVCMOS OUTPUT RISE/FALL TIME LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 5 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS840011 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD and VDDA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VDDA pin. 3.3V VDD .01F 10 VDDA .01F 10F FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS840011 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 6 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This can also be accomplished by removing R1 and making R2 50. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 Zo = Ro + Rs XTAL_IN R2 XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 7 TO XTAL INPUT INTERFACE ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION SCHEMATIC 106.25MHz output frequency. The C1 = 27pF and C2pF = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 4A shows a schematic example of the ICS840011. An example of LVCMOS termination is shown in this schematic. Additional LVCMOS termination approaches are shown in the LVCMOS Termination Application Note. In this example, an 18pF parallel resonant 26.5625MHz crystal is used for generating VDD VDDA R2 10 C3 10uF C4 0.1u U1 1 2 3 4 OE C2 33pF VDDA OE XTAL_OUT XTAL_IN VDD Q0 GND NC 8 7 6 5 R3 43 VDD Q Zo = 50 Ohm X1 C5 0.1u ICS840011 C1 27pF LVCMOS VDD=3.3V FIGURE 4A. ICS840011 SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 4B shows an example of ICS840011 P.C. board layout. The crystal X1 footprint in this example allows either surface mount (HC49S) or through hole (HC49) package. C3 is 0805. C1 and C2 are 0402. Other resistors and capacitors are 0603. This layout assumes that the board has clean analog power and ground planes. FIGURE 4B. ICS840011 PC BOARD LAYOUT EXAMPLE IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 8 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP JA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7C/W 90.5C/W 89.8C/W TRANSISTOR COUNT The transistor count for ICS840011 is: 1521 IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 9 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 0 8 aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 10 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS840011AG 011A 8 lead TSSOP tube -30C to 85C ICS840011AGT 011A 8 lead TSSOP 2500 tape & reel -30C to 85C ICS840011AGLN 011AN 8 lead "Lead Free Annealed" TSSOP tube -30C to 85C ICS840011AGLNT 011AN 8 lead "Lead Free Annealed" TSSOP 2500 tape & reel -30C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 11 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR REVISION HISTORY SHEET Rev Table Page A T9 A T9 10 7 11 Description of Change Date Ordering Information Table - corrected count from 154 per tube to 100. Added LVCMOS to XTAL Interface. Ordering Information Table - deleted quantity from tube count. Updated datasheet format. IDT TM / ICSTM LVCMOS/LVTTL CLOCK GENERATOR 12 10/15/04 1/22/07 ICS840011AG REV. A JANUARY 22, 2007 ICS840011 FEMTOCLOCKSTM CRYSTAL-TO-LVCMOS/LVTTL CLOCK GENERATOR Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 (c) 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. 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