1
FEATURES DESCRIPTION
APPLICATIONS
RESET
GND
MR
6
5
4
VDD
SENSE
CT
1
2
3
DRVPACKAGE
2mmx2mmQFN
(TOPVIEW)
Power
PAD
DBVPACKAGE
SOT23
(TOPVIEW)
VDD
SENSE
CT
RESET
GND
MR
1
2
3
6
5
4
1.2V 3.3V
TPS3808G12 TPS3808G33 DSP
SENSE VDD
VDD SENSE VI/O VCORE
GPIO
GNDGNDGND
RESET MR
CT
CT
RESET
TypicalApplicationCircuit
TPS3808
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.......................................................................................................................................................... SBVS050J MAY 2004 REVISED AUGUST 2008
Low Quiescent Current, Programmable-Delay
Supervisory Circuit
23
Power-On Reset Generator with Adjustable
The TPS3808xxx family of microprocessorDelay Time: 1.25ms to 10s
supervisory circuits monitor system voltages from0.4V to 5.0V, asserting an open-drain RESET signalVery Low Quiescent Current: 2.4 µA typ
when the SENSE voltage drops below a presetHigh Threshold Accuracy: 0.5% typ
threshold or when the manual reset ( MR) pin drops toFixed Threshold Voltages for Standard Voltage
a logic low. The RESET output remains low for theRails from 0.9V to 5V and Adjustable Voltage
user-adjustable delay time after the SENSE voltageDown to 0.4V Are Available
and manual reset ( MR) return above the respectivethresholds.Manual Reset ( MR) Input
The TPS3808 uses a precision reference to achieveOpen-Drain RESET Output
0.5% threshold accuracy for V
IT
3.3V. The resetTemperature Range: 40 ° C to +125 ° C
delay time can be set to 20ms by disconnecting theSmall SOT23 and 2mm × 2mm QFN Packages
C
T
pin, 300ms by connecting the C
T
pin to V
DD
usinga resistor, or can be user-adjusted between 1.25msand 10s by connecting the C
T
pin to an externalcapacitor. The TPS3808 has a very low typicalDSP or Microcontroller Applications
quiescent current of 2.4 µA so it is well-suited toNotebook/Desktop Computers
battery-powered applications. It is available in a smallPDAs/Hand-Held Products
SOT23 and an ultra-small 2mm × 2mm QFNPortable/Battery-Powered Products
PowerPAD™ package, and is fully specified over aFPGA/ASIC Applications
temperature range of 40 ° C to +125 ° C (T
J
).
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
TPS3808
SBVS050J MAY 2004 REVISED AUGUST 2008 ..........................................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT NOMINAL SUPPLY VOLTAGE
(2)
THRESHOLD VOLTAGE (V
IT
)
TPS3808G01 Adjustable 0.405VTPS3808G09 0.9V 0.84VTPS3808G12 1.2V 1.12VTPS3808G125 1.25V 1.16VTPS3808G15 1.5V 1.40VTPS3808G18 1.8V 1.67VTPS3808G19 1.9V 1.77VTPS3808G25 2.5V 2.33VTPS3808G30 3.0V 2.79VTPS3808G33 3.3V 3.07VTPS3808G50 5.0V 4.65V
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .(2) Custom threshold voltages from 0.82V to 3.3V, 4.4V to 5.0V are available through the use of factory EEPROM programming. Minimumorder quantities apply. Contact factory for details and availability.
Over operating junction temperature range, unless otherwise noted.
TPS3808 UNIT
Input voltage range, V
DD
0.3 to 7.0 VC
T
voltage range, V
CT
0.3 to V
DD
+ 0.3 VOther voltage ranges: V
RESET
, V
MR
, V
SENSE
0.3 to 7 VRESET pin current 5 mAOperating junction temperature range, T
J
(2)
40 to +150 ° CStorage temperature range, T
STG
65 to +150 ° CESD rating, HBM 2 kVESD rating, CDM 500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under the Electrical Characteristicsis not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.(2) As a result of the low dissipated power in this device, it is assumed that T
J
= T
A
.
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Product Folder Link(s): TPS3808
ELECTRICAL CHARACTERISTICS
TPS3808
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.......................................................................................................................................................... SBVS050J MAY 2004 REVISED AUGUST 2008
1.7V V
DD
6.5V, R
LRESET
= 100k , C
LRESET
= 50pF, over operating temperature range (T
J
= 40 ° C to +125 ° C), unlessotherwise noted. Typical values are at T
J
= +25 ° C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
40 ° C < T
J
< +125 ° C 1.7 6.5V
DD
Input supply range V0 ° C < T
J
< +85 ° C 1.65 6.5V
DD
= 3.3V, RESET not asserted
2.4 5.0 µAMR, RESET, C
T
openI
DD
Supply current (current into V
DD
pin)
V
DD
= 6.5V, RESET not asserted
2.7 6.0 µAMR, RESET, C
T
open1.3V V
DD
< 1.8V, I
OL
= 0.4mA 0.3 VV
OL
Low-level output voltage
1.8V V
DD
6.5V, I
OL
= 1.0mA 0.4 VPower-up reset voltage
(1)
V
OL
(max) = 0.2V, I
RESET
= 15 µA 0.8 VTPS3808G01 2.0 ± 1.0 +2.0V
IT
3.3V 1.5 ± 0.5 +1.5Negative-going
V
IT
input threshold 3.3V < V
IT
5.0V 2.0 ± 1.0 +2.0 %accuracy
V
IT
3.3V 40 ° C < T
J
< +85 ° C 1.25 ± 0.5 +1.253.3V < V
IT
5.0V 40 ° C < T
J
< +85 ° C 1.5 ± 0.5 +1.5TPS3808G01 1.5 3.0V
HYS
Hysteresis on V
IT
pin 40 ° C < T
J
< +85 ° C 1.0 2.0 %V
ITFixed versions
1.0 2.5R
MR
MR Internal pull-up resistance 70 90 k
TPS3808G01 V
SENSE
= V
IT
25 25 nAInput current atI
SENSE
SENSE pin
Fixed versions V
SENSE
= 6.5V 1.7 µAI
OH
RESET leakage current V
RESET
= 6.5V, RESET not asserted 300 nAC
T
pin V
IN
= 0V to V
DD
5Input capacitance,C
IN
pFany pin
Other pins V
IN
= 0V to 6.5V 5V
IL
MR logic low input 0 0.3 V
DD
VV
IH
MR logic high input 0.7 V
DD
V
DD
SENSE V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20Input pulse widtht
w
µsto RESET
MR V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
0.001C
T
= Open 12 20 28 msC
T
= V
DD
180 300 420 mst
d
RESET delay time See Timing DiagramC
T
= 100pF 0.75 1.25 1.75 msC
T
= 180nF 0.7 1.2 1.7 sPropagation delay MR to RESET V
IH
= 0.7V
DD
, V
IL
= 0.3V
DD
150 nst
pHL
High to low level
SENSE to RESET V
IH
= 1.05V
IT
, V
IL
= 0.95V
IT
20 µsRESET delayθ
JA
Thermal resistance, junction-to-ambient 290 ° C/W
(1) The lowest supply voltage (V
DD
) at which RESET becomes active. T
rise(VDD)
15 µs/V.
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS3808
Adjustable Voltage Version Fixed Voltage Version
Reset
Logic
Timer
+
90k
VDD
VDD
GND
0.4V
VREF
SENSE
MR
CT
RESET
TPS3808G01
Adjustable Voltage
Reset
Logic
Timer
+
90k
VDD
VDD
GND
0.4V
VREF
SENSE
MR
CT
RESET
R1
R2
R1+ R2= 4M
PIN ASSIGNMENTS
RESET
GND
MR
6
5
4
VDD
SENSE
CT
1
2
3
Power
PAD
VDD
SENSE
CT
RESET
GND
MR
1
2
3
6
5
4
TPS3808
SBVS050J MAY 2004 REVISED AUGUST 2008 ..........................................................................................................................................................
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FUNCTIONAL BLOCK DIAGRAMS
Figure 1. Adjustable and Fixed Voltage Versions
DBV PACKAGE
DRV PACKAGESOT23
2mm × 2mm QFN(TOP VIEW)
(TOP VIEW)
Table 1. TERMINAL FUNCTIONS
TERMINAL
SOT23 (DBV)NAME PIN NO. DESCRIPTION
RESET 1 RESET is an open-drain output that is driven to a low impedance state when RESET is asserted (either theSENSE input is lower than the threshold voltage (V
IT
) or the MR pin is set to a logic low). RESET will remainlow (asserted) for the reset period after both SENSE is above V
IT
and MR is set to a logic high. A pull-upresistor from 10k to 1M should be used on this pin, and allows the reset pin to attain voltages higher thanV
DD
.GND 2 GroundMR 3 Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to V
DD
by a 90k pull-upresistor.C
T
4 Reset period programming pin. Connecting this pin to V
DD
through a 40k to 200k resistor or leaving itopen results in fixed delay times (see Electrical Characteristics ). Connecting this pin to a ground referencedcapacitor 100pF gives a user-programmable delay time. See the Selecting the Reset Delay Time sectionfor more information.SENSE 5 This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the thresholdvoltage V
IT
, then RESET is asserted.V
DD
6 Supply voltage. It is good analog design practice to place a 0.1 µF ceramic capacitor close to this pin.PowerPAD PowerPAD. Connect to ground plane to enhance thermal performance of package.
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Time
0.8V
0.0V
VIT + VHYS
VIT
0.7VDD
0.3VDD
MR
SENSE
RESET
VDD
tDtDtD
tD= Reset Delay
= Undefined State
TRUTH TABLE
TPS3808
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.......................................................................................................................................................... SBVS050J MAY 2004 REVISED AUGUST 2008
TIMING DIAGRAM
Figure 2. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing
MR SENSE > V
IT
RESET
L0LL1LH 0 LH 1 H
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS3808
TYPICAL CHARACTERISTICS
0 1 2 3 4 5 6 7
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
40_C
+25_C
+85_C
+125_C
IDD (µA)
VDD (V)
100
10
1
0.1
0.01
0.001
0.0001 0.001 0.01 0.1
CT(µF)
101
−40°C, +25°C, +125°C
RESET Timeout (sec)
10
8
6
4
2
0
10 30 50 70 90 110 130
Temperature (°C)
−50 −30 −10
−10
−8
−6
−4
−2
Normalized RESET Timeout Period (%)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOL Low−Level RESET Voltage (V)
VDD = 1.8V
RESET Current (mA)
1.0
0.8
0.6
0.4
0.2
0
10 30 50 70 90 110 130
Temperature (°C)
−50 −30 −10
−1.0
−0.8
−0.6
−0.4
−0.2
Normalized VIT (%)
TPS3808
SBVS050J MAY 2004 REVISED AUGUST 2008 ..........................................................................................................................................................
www.ti.com
At T
J
= +25 ° C, V
DD
= 3.3V, R
LRESET
= 100k , and C
LRESET
= 50pF, unless otherwise noted.
SUPPLY CURRENT RESET TIMEOUT PERIODvs vsSUPPLY VOLTAGE C
T
Figure 3. Figure 4.
NORMALIZED RESET TIMEOUT PERIODvs MAXIMUM TRANSIENT DURATION AT SENSETEMPERATURE vs(C
T
= OPEN, C
T
= V
DD
, C
T
= Any) SENSE THRESHOLD OVERDRIVE VOLTAGE
Figure 5. Figure 6.
NORMALIZED SENSE THRESHOLD VOLTAGE (V
IT
) LOW-LEVEL RESET VOLTAGEvs vsTEMPERATURE RESET CURRENT
Figure 7. Figure 8.
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0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VOL Low−Level RESET Voltage (V)
RESET Current (mA)
VDD = 3.3V
VDD = 6.5V
TPS3808
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.......................................................................................................................................................... SBVS050J MAY 2004 REVISED AUGUST 2008
TYPICAL CHARACTERISTICS (continued)At T
J
= +25 ° C, V
DD
= 3.3V, R
LRESET
= 100k , and C
LRESET
= 50pF, unless otherwise noted.
LOW-LEVEL RESET VOLTAGE
vsRESET CURRENT
Figure 9.
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS3808
DEVICE OPERATION
SENSE INPUT
RESET OUTPUT
VIN
TPS3808G01
VDD
SENSE
GND
RESET
R1
R2
1nF
V =(1+)0.405IT¢R1
R2
VOUT
MANUAL RESET ( MR) INPUT
2.5V
TPS3808G25 OMAP1510
VDD
SENSE VDDSHV 1, 3, 6, 7, 9
GNDGND
CT
MR RESET
1M
RESPWRON
TPS3808
SBVS050J MAY 2004 REVISED AUGUST 2008 ..........................................................................................................................................................
www.ti.com
supply line can be used to allow the reset signal forThe TPS3808 microprocessor supervisory product
the microprocessor to have a voltage higher than V
DDfamily is designed to assert a RESET signal when
(up to 6.5V). The pull-up resistor should be noeither the SENSE pin voltage drops below V
IT
or the
smaller than 10k as a result of the finite impedancemanual reset ( MR) is driven low. The RESET output
of the RESET line.remains asserted for a user-adjustable time after boththe manual reset ( MR) and SENSE voltages returnabove the respective thresholds. A broad range ofvoltage threshold and reset delay time adjustments
The SENSE input provides a terminal at which anyare available, allowing these devices to be used in a
system voltage can be monitored. If the voltage onwide array of applications. Reset threshold voltages
this pin drops below V
IT
, then RESET is asserted.can be factory-set from 0.82V to 3.3V or from 4.4V to
The comparator has a built-in hysteresis to ensure5.0V, while the TPS3808G01 can be set to any
smooth RESET assertions and de-assertions. It isvoltage above 0.405V using an external resistor
good analog design practice to put a 1nF to 10nFdivider. Two preset delay times are also
bypass capacitor on the SENSE input to reduceuser-selectable: connecting the C
T
pin to V
DD
results
sensitivity to transients and layout parasitics.in a 300ms reset delay, while leaving the C
T
pin open
The TPS3808G01 can be used to monitor anyyields a 20ms reset delay. In addition, connecting a
voltage rail down to 0.405V using the circuit shown incapacitor between C
T
and GND allows the designer
Figure 11 .to select any reset delay period from 1.25ms to 10s.
A typical application of the TPS3808G25 used withthe OMAP1510 processor is shown in Figure 10 . Theopen-drain RESET output is typically connected tothe RESET input of a microprocessor. A pull-upresistor must be used to hold this line high whenRESET is not asserted. The RESET output isundefined for voltage below 0.8V, but this is normallynot a problem since most microprocessors do notfunction below this voltage. RESET remains high(unasserted) as long as SENSE is above its threshold
Figure 11. Using the TPS3808G01 to Monitor a(V
IT
) and the manual reset ( MR) is logic high. If either User-Defined Threshold VoltageSENSE falls below V
IT
or MR is driven low, RESET isasserted, driving the RESET pin to a low impedance.
The manual reset ( MR) input allows a processor orother logic circuits to initiate a reset. A logic low(0.3V
DD
) on MR causes RESET to assert. After MRreturns to a logic high and SENSE is above its resetthreshold, RESET is de-asserted after the userdefined reset delay expires. Note that MR is internallytied to V
DD
using a 90k resistor so this pin can beleft unconnected if MR will not be used.
See Figure 12 for how MR can be used to monitormultiple system voltages. Note that if the logic signaldriving MR does not go fully to V
DD
, there will beFigure 10. Typical Application of the TPS3808with an OMAP Processor some additional current draw into V
DD
as a result ofthe internal pull-up resistor on MR. To minimizecurrent draw, a logic-level FET can be used asOnce MR is again logic high and SENSE is above V
IT
illustrated in Figure 13 .+ V
HYS
(the threshold hysteresis), a delay circuit isenabled which holds RESET low for a specified resetdelay period. Once the reset delay has expired, theRESET pin goes to a high impedance state. Thepull-up resistor from the open-drain RESET to the
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CT(nF) +ƪtD(s)*0.5 10*3(s)ƫ 175
(1)
1.2V 3.3V
TPS3808G12 TPS3808G33 DSP
SENSE VDD
VDD SENSE VI/O VCORE
GPIO
GNDGNDGND
RESET MR
CT
CT
RESET
IMMUNITY TO SENSE PIN VOLTAGE
3.3V
TPS3808xxx
VDD SENSE
MR
90kW
GND
SELECTING THE RESET DELAY TIME
Delay (s) = CT (nF) + 0.5 x 10−3 (s)
20ms Delay
300ms Delay
(c)
(b)
(a) 175
3.3V
TPS3808G33
VDD
SENSE
CTRESET
3.3V
TPS3808G33
VDD
SENSE
CT
CT
RESET
3.3V
TPS3808G33
VDD
SENSE
CT
50k
RESET
TPS3808
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.......................................................................................................................................................... SBVS050J MAY 2004 REVISED AUGUST 2008
by the choice of resistor. Figure 14 b shows a fixed20ms delay time by leaving the C
T
pin open.Figure 14 c shows a ground referenced capacitorconnected to C
T
for a user-defined program timebetween 1.25ms and 10s.
The capacitor C
T
should be 100pF nominal value inorder for the TPS3808xxx to recognize that thecapacitor is present. The capacitor value for a givendelay time can be calculated using the followingequation:
The reset delay time is determined by the time itFigure 12. Using MR to Monitor Multiple System
takes an on-chip precision 220nA current source toVoltages
charge the external capacitor to 1.23V. When aRESET is asserted the capacitor is discharged. Whenthe RESET conditions are cleared, the internalcurrent source is enabled and begins to charge theexternal capacitor. When the voltage on this capacitorreaches 1.23V, RESET is de-asserted. Note that alow leakage type capacitor such as a ceramic shouldbe used, and that stray capacitance around this pinmay cause errors in the reset delay time.
TRANSIENTS
The TPS3808 is relatively immune to short negativeFigure 13. Using an External MOSFET to Minimize
transients on the SENSE pin. Sensitivity to transientsI
DD
When MR Signal Does Not Go to V
DD
is dependent on threshold overdrive, as shown in theMaximum Transient Duration at Sense vs SenseThreshold Overdrive Voltage graph (Figure 6 ) in theTypical Characteristics section.The TPS3808 has three options for setting theRESET delay time as shown in Figure 14 .Figure 14 ashows the configuration for a fixed 300ms typicaldelay time by tying C
T
to V
DD
; a resistor from 40k to200k must be used. Supply current is not affected
Figure 14. Configuration Used to Set the RESET Delay Time
Copyright © 2004 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS3808
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS3808G01DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G01DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G09DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G09DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G09DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G09DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G125DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G125DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G125DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G125DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS3808G12DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G12DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G15DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G18DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G18DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G18DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS3808G18DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G18DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G18DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G19DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G19DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G19DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G19DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G25DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2012
Addendum-Page 4
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS3808G30DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G30DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G33DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G50DBVR ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G50DBVRG4 ACTIVE SOT-23 DBV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G50DBVT ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS3808G50DBVTG4 ACTIVE SOT-23 DBV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 20-Jul-2012
Addendum-Page 5
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS3808G01, TPS3808G12, TPS3808G125, TPS3808G18, TPS3808G30, TPS3808G33, TPS3808G50 :
Automotive: TPS3808G01-Q1, TPS3808G12-Q1, TPS3808G125-Q1, TPS3808G18-Q1, TPS3808G30-Q1, TPS3808G33-Q1, TPS3808G50-Q1
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS3808G01DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G01DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G01DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G01DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G09DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G09DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G125DBVR SOT-23 DBV 6 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS3808G125DBVT SOT-23 DBV 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS3808G12DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G12DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G12DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G12DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G15DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G15DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G15DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G15DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G18DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G18DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS3808G18DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G18DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G19DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G19DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G25DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G25DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G25DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G25DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G30DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G30DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G30DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G30DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G33DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G33DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G33DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G33DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS3808G50DBVR SOT-23 DBV 6 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TPS3808G50DBVT SOT-23 DBV 6 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
*All dimensions are nominal
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Jul-2012
Pack Materials-Page 2