DS023 (v1.5) January 8, 2002 www.xilinx.com 1
Preliminary Product Specification 1-800-255-7778
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All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
Features
• Lo west power 32 macrocell CPLD
• 5.0 ns pin-to-pin logic del ays
• System frequencies up to 200 MHz
• 32 macrocells with 750 usable ga tes
• Available in small footpri nt packages
- 48-ball CS BGA (36 user I/O pins)
- 44-pin VQF P (36 user I/O)
- 44-pin PLCC (36 user I/O)
• Opti mized for 3.3V systems
- Ultra-low power operatio n
- 5V tolerant I/O pins with 3.3V core supply
- A dva nc ed 0.35 micron five layer metal EEPROM
process
- Fast Zero Power™ (FZP) CMOS desig n
technology
• Advanced system fe at ur e s
- In-system programming
- Inp ut registers
- P redicta ble timi ng mode l
- Up to 23 available clocks per function block
- Excellent pin retention during design changes
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
- Four global clo cks
- E ight product term control ter m s per function bl ock
• Fast ISP programm ing tim es
• Por t Enable pin for dual function o f JTAG IS P pins
• 2.7V to 3.6V supply voltage at industrial temperature
range
• Programmable slew rate control per macrocell
• Security bit prevents unauthorized access
• Ref er to XPLA3 family data sheet (DS012) for
architecture descri ption
Description
The X CR3032XL is a 3.3V, 32-macrocell CPLD targeted at
power sensitive designs that require leading edge program-
mable logic s olution s. A total of two function blocks provide
750 us abl e gates. Pin-to-pin propagation delays are 5 .0 ns
with a maximum system frequency of 200 MHz.
TotalCMOS Design Technique for Fast
Zero Power
Xilinx offers a TotalCMOS CPLD, both in process technol-
ogy and design technique. Xilinx employs a cascade of
CMOS gates to implement its sum of products instead of
the traditional sense amp approach. This CMOS gate imple-
mentation allows Xilinx to offer CPLDs that are both high
perform ance and low power, breaking the paradigm that to
have low power, you must have low performance. Refer to
Figure 1 and Table 1 showing the ICC vs. Freq uency of our
XCR3032XL TotalCMOS CPLD (data taken with two
resetable up/down, 16-bit counters at 3.3V, 25°C).
0
XCR3032XL 32 Macrocell CPLD
DS023 (v1.5) January 8, 2002 014
Prelim inary Prod uct Specification
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Figure 1: ICC vs. Frequency at VCC = 3.3V, 25°C