NAPC/ SIGNETICS Philips Components-Signetics DocumentNo. | 853-0086 ECN No. 83082 Date of Issue April 4, 1986 Status Product Specification Data Communication Products DESCRIPTION The Signetics SCN2661 EPClis a universal synchronous/asynchronous data communications controller chip that is an enhanced version of the SCN2651. It interfaces easily to all 8-bit and 16-bit microprocessors and may be used ina polled or interrupt driven system environment, The SCN2661 accepts programmed instructions from the microprocessor while supporting many serial data communications disciplines synchronous and asynchronous in the full- or half-duplex mode. Special - support for BISYNG is provided. The EPCI serializes parallel data characters received from the microprocessor for {ransmission, Simultaneously, it can receive serial data and convert it into parallel data characters for input to the microcomputer. The SCN2661 contains a baud rate generator which can be programmed to either accept an external clock or to generate Internal transmit or receive clocks, Sixteen different baud rates can be selected under program control when operating in the internal clock made. Each version of the EPC! (A, B, C) has.a different set of baud rates, WIE D EM 6653924 0059326 O BASICS SCN2661/SCN68661 Enhanced programmable communications FEATURES Synchronous operation 5-to 8-bit characters plus parity Single or double SYN operation Internal or external character synchronization ~ Transparent or non-transparent mode Transparent mode DLE stuffing (Tx) and detection (Rx) Automatic SYN or DLE-SYN insertion SYN, DLE and DLESYN stripping Odd, even, or no parity ~ Local or remote maintenance. loopback mode Baud rate: DC to 1Mbps (1X clock) ' @ Asynchronous operation ~ 5-to 8-bit characters plus parity - 1, 1-1/2 or 2 stop bits transmitted. Odd, even, or no parity Parity, overrun. and framing error detection Line break detection and generation False start bit detection Automatic serial echo mode (echoplex) Local or remote maintenance loopback mode Baud rate: DC to 1Mbps (1X clack) DC to 62:.Skbps (16X clock) DC to 15.625kbps (64X clock) 45 interface (EPCI) OTHER FEATURES Internal or external baud rate clock @ 3 baud rate sets 16 internal rates for each set Double-buffered transmitter and receiver Dynamic character length switching Full- or half-duplex operation TTL compatible inputs and outputs RxC and TxC pins are short-circuit protected. Single +5V power supply No system clock required APPLICATIONS @ Intelligent terminals Network processors @ Front-end processors Remote data concentrators Computer-to-computer links Serial peripherals @ BISYNG adaptors T27S-37+0O7NAPC/ SIGNETICS HE D HM 6653924 0059327 2 BASICS Philips ComponentsSignetics Data Communication Products , Product Specification Enhanced programmable communications SCN2661/SCN68661 interface (EPCl) __ . ~1-15-37-67 PIN CONFIGURATIONS TOP VIEW NOTE: Pin Functions the same as 28-pin OP. ORDERING CODE Voo = t5V 45% PACKAGES Commerclal Automotive Military 0C to +70C -40C to 485C +55C-to +125C Ceramic. DIP SCN2661AC1F28 | SCN266iAA1F28: | SCN2661AMiF28 28-Pin SCN2661BC1F28 | SCN26s{BAiF28 | SCN2661BMiF28 0.6" Wide SCN2661CC1F28 | SCN2661CA1F28 | SCN2661CMIF28 Plastic DIP SON2661AC1N28 28-Pin SCN2661BC1N28 Contact Factory Not Available 0.6" Wide SCN2661CC1N28 SCN2661ACTA28 Plastic LCC SCN2661BC1A28 Contact Factory. Not Available SGN2661CC1A28 April 4, 1986 46NAPC/ SIGNETICS Philips ComponentsSignetics Data Communication Products WLE D 6653924 0059328 4 BBSIC3 Product Specification Enhanced programmable communication interface (EPCI) SCN2661/SCN68661 BLOCK DIAGRAM T-75- 32-07 DATA BUS SNE/OLE CONTROL DATA BUS Do-D7 ~ BUFFER VY _ SYN1 REGISTER 4 SYN 2 REGISTER _DLE REGISTER ESET _____-____y! openanioncontra. {4 Ag }_ |_ MODE REGISTER 1 NT A, |_ [_ MODE REGISTER 2 RAY -->|_ | COMMAND REGISTER - TRANSMITTER P > TROY" ve q [_ status ReGisTER . N] | qaansmir pata - y/| [HOLOING REGISTER TRANSMIT shirt Reaisten: | | Fx? BRCLK -_- [| ~ BAUD RATE | t Txt/SYNC <_____- GENERATOR CLOGK CONTROL RECEIVER D> AxRDY* RRCI <______ RCIBKOET RECEIVE DATA HOLOING REGISTER RECEIVE DSR -d SHIFT REGISTER | [* FxD wep --_>d jA ts _q MODEM NK RIS +d CONTROL pm <__4 TxERTR = C DSCRG NOTES: * Open-drain output pin, April 4, 1986 47NAPC/ SIGNETICS Philips Components~Signetics Data Communication Products 4LE D @M@ 6653924 005932e4 & MESIC3 Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 ABSOLUTE MAXIMUM RATINGS" T-75- 37-07 PARAMETER Storage tem All voltages Operating ambient temperature? perature with respect to ground? RATING UNIT Note 4 G . . os -65 to +150 C -0,5 to +6.0 Vv NOTES: 1 , Stresses above those listed under Absolute Maximum Ratings may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or at any other condition above. those indicated in the operation section-of this specification is not implied, 2. For operating at elevated temperatures, the device must.be derated based on +150C maximum function temperature. 8. This product includes circuitry specifically designed for the protection of its interrial devices front the damaging effect of excessive static charge. Nonetheless, itis suggested that conventional precautions be taken to avoid applying. any voltages larger than the rated maxima. > a Over recommended free-air operating temperature range and supply voltage range unless otherwise specified. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. DC ELECTRICAL CHARACTERISTICS. 2:3 LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max UNIT Input voltage Vir Low 0.8 Vv Vin High 2.0 Vv Output voltage _ . Vou Low Io, = 2.2mA 0.4 Vv Vout High lon =-400pA 24 Vv tie Input leakage current Vin=O0to55V 0 : 10. pA 3-State output leakage current ; __ lia Data bus high Vo = 4.0V 10 pA he Data bus low Vo = 0.45V 10 pA lec Power supply current 150 mA NOTES: or MAX, use the appropriate value specified under recommended operating conditions. 2. All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except tgny and tga.) and at 0.8V and 2,0V for outputs. Input levels swing between 0.4V and 2.4), with a transition time of < 20ns maximum. 3. Typical values are at +25C, typical supply voltages. and typical processing parameters. . Over recommended free-air operatirig temperature range and supply voltage range-unless otherwise specified, For conditions shown as MIN | | | 4, INTH, TxROY, RxADY and TXEMT/DSCHG outputs are open-drain. CAPACITANCE Ty = 28C, Veo = 0V ; LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max | UNIT Capacitance Cw Input 20 pF Cour Output fo = MHz 20 pF | Cio InpuyOutput Unmeasured pins tied to ground 20 pF | April 4, 1986 48NAPC/ SIGNETICS Philips ComponentsSignetics Data Communication Products WIE. D 6653924 0059350 2 BESICc3 -Praduct Specification Enhanced programmable co interface (EPCI) mmunications SCN2661/SCN68661 AC ELECTRICAL CHARACTERISTICS1:2 3 T= 7$- 37-67 LIMITS SYMBOL PARAMETER TEST CONDITIONS Min | Typ | Max. | UNIT Pulse width . tres Reset 1000 ns toe Chip.enable 250 ns Setup and hold time Sas Address setup 10 ns tan Address hold 10 ns tes RW control setup 10 ns ton FW control hold 10 ns tos Data setup for write 150 ns ton Data hold for write 10 ns taxs RX data setup 300 ns tax RX data hold 350 ns. top Data delay time for read GC. = 150pF 200 ns tor? Data bus floating time for read CG, = 150pF 100 ns ceo CE to CE delay 600 ns (nput clock frequency / faa Baud rate generator (2661A, B) _ 1.0 | 4.9152 } 4.9202 | MHz fang Baud rate generator (2661C) =~ 1.0. 5.0688 | 5.0738 MHz far TS of RxG de 1.0 MHz Clock width ; tary? Baud rate High (2661A, 8) 75 ns tary? Baud rate High (26610) 70 ns fer? Baud rate Low (2661A, By 75 ns tan Baud rate Low (2661C) 70 ns tary Txt or BxS High 480 ns tan TxT or Rx. Low 480 ns. ttxo TxD delay from falling edge of TxO Cy = 150pF 650 ns {tes Skew between TxD changing and falling edge CL.= 150pF 0 ns of TXT output! NOTES: 1, Over recommended free-air operating temperature range and supply volta or MAX, use the appropriate value specitied under recommended operating conditions. ? NO OSG nw April 4, 1986 49 ge range unless otherwise specified. For conditions shown as MIN All voltages measurements are referenced to ground. All time measurements are at the 50% level for inputs (except taqy and tgat)-and at 0,8V and 2.0V for outputs. Input levels swing between 0.4V and 2.4V, with a transition time of < 20ns maximum. . Typical values are at +25C, typical supply voltages and typical processing parameters. . Parameter applies when internal transmitter clock is used. . Under test conditions of 5.0688MHz fara (68661) and 4.9152MHz fgaq (68661A, B), tany and tga, measured at Vi; and Vi, respectively. . In asynchronous local loopback mode, using 1X clock, the following parameters. apply: farp = 0.83MHz max and tag. = 700ns min. . See AG load conditions. .NAPC/ SIGNETICS 4Y1E D BM 6653924 0059331 4 MMSIC3 Philips Components-Signetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) _ SCN2661/SCN68661 BLOCK DIAGRAM _ The EPClconsists of six major sections, These are the transmitter, receiver, timing, operation control, modern controf and SYN/OLE control. These sections communicate with each other via an internal data bus arid an internal control bus. The internal data bus interfaces to the mi- croprocessor data bus via a data bus buffer. Operation Control This functional block stores configuration and operation commands from the GPU and gener- ates appropriate signals to various internal sec~ tions to control the overall device operation. It contains read and write circuits to permit com- munications with the microprocessor via the data bus and contains mode registers 1 and 2, the command register, and the status register. Details of register addressing and protocol are presented in the EPC! programming section of this data sheet, Timing The EPCI contains a Baud Rate Generator (BRG) which is programmable to accept exter- nal transmit or receive clocks or to divide an ex- ternal clock to perform data communications. The unitcan generate 16 commonly used baud tates, any one of which can be selected for full-duplex operation. See Table 1. Receiver The receiver accepts serial data on the AxD pin, converts this serial input to paralfel format, checks for bits or characters that are unique to the communication technique and sends an *assembled character to the CPU. Transmitter The transmitter accepts parallel data from the CPU, converts it to a serial bit stream, inserts Table 1, Baud Rate Generator Characteristics 68661A (BRCLK = 4.9152MHz) To 75- 37-07 the appropriate characters or bits (basedon the communication technique) and outputs a com- posite serial stream of data on the TxD output pin. + Modem Control The modern control section provides interfac- ing for three input signals and three output sig- nals Used for handshaking and status indication between the GPU and a modem. SYN/DLE Control This section contains control circuitry and three 8-bit registers storing the SYNi, SYN2, and DLE characters provided by the CPU. These registers are used in the synchronous mode of operation to provide the characters required for synchronization, idle fill and data transparency. ACTUAL. FREQUENCY PERCENT MR23-20 BAUD RATE 16X. CLOCK ERROR pIVIsOR 0000 50 0,8kHz 6144 0001 75 1.2 4096 0010 110 1.7598 -0.01 2793 001t 134.5 2,152 _ 2284 0100 150 2.4 2048 Q101 200 3.2 1536 otto 300 4.8 1024 Ot 600 9.6 - 512 1000 1050 16.8329 0.196 292 1001 1200 19.2 256 1010 1800 28.7498 -0.19 171 {011 2000 31.9168 -0.26 154 1100 2400 38.4 126 1104 4800 76.8 64 1110 9600 153.6 _ a2 ditt 19200 307.2 _ 16 68661B (BRCLK = 4.9152MHz) , ACTUAL FREQUENCY PERCENT MR23-20 . BAUD RATE 16X CLOCK ERROR DIVISOR 0000 45.5 0.7279kHz 0.005 6752 0001 50 08 = 6144 0010 75 1.2. 4096. o0tt 110 1,7598 -0.01 2793 0100 134.5 2.152 _ 2284 o101 150 2.4 2048 otto 300 48 _ 1024 oii 600 9.6 ~ 512 1000 1200 19.2 ~ 256 1001 - 4800 28.7438 -0.19 171 {010 2000 31,9168 -0.26 184 1011 2400 48.4 _ 128 1100 4800 76.8 64 1104 9600 153.6 42 {110 19200 307.2 16 itt 38400 614.4 8 April 4, 1986 50NAPC/ SIGNETICS WILE D Ml 6653924 00593992 & MMSIC3 Philips ComponientsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCI) SCN2661/SCN68661 68661C (BRCLK = 5.0688MHz) [-75-37-67 PERCENT ACTUAL FREQUENCY MR23-20 BAUD RATE 16X CLOCK ERROR DIVISOR 0000, . 50 0.8kHz - 6336 0001 75 1.2 _ 4224 0010 110 1.76 - 2880 Oo1l 134.5 2.1523 0.016 2355 0100 150 2.4 - 2112 0104 300 48. - 1056 0110 600 9.6 _ 628 O1t 1200 19.2 _ 264 1000 1800 28.8 - 176 1001 2000 32.081 0,253 168 1010 2400 38.4 - 132 1011 3600 57.6 _ 88 1100 . 4800 76.8 _ 66 1101 7200 115.2 _ 44 1110 - 9600 163.6 = 33 1111 19200 316.8 3.125 16 NOTE; 16X clock Is used in asynchronous mode. In synchronous mode, clock multiplier is 1X and BAG can be used only for TxC. OPERATION The functional operation of the 68661 is pro- grammed by a set of control words supplied by the CPU. These control words specify items such as synchronous or asynchronous mode, baud rate, number of bits per character, ete, The programming procedure is describedin the EPCI prograrnming section of the data sheet. After programming, the EPCI Is ready to per- forrn the desired communications functions. The receiver performs serial to parallel conver- ston of data received froma modem or equiva- lent device. The transmitter converts parallel data recaived from the CPU to a serial bit stream. These actions are accomplished with- in the framework specified by the control words, Receiver The 68661 ts conditioned to receiver data when the DCD input is Low and the RxEN bit in the commands: register Is true. In the asynchro- nous modo, the receiver looks for High-to-Low (mark to space) transition of the start bit on the RxD input line. If a transition is detected, the state of the RxD line is sampled again after a delay of one-half of a bit-time. If RxD is now high, the search for a valid start bit is begun. again, If RxD Is still Low, a valid start bit is as- sumed and the receiver continues to sample the input line at one bit time-intervals until the proper number of data bits, the parity bit, and one stop bit have been assembled. The data are then transferred to the receive data holding register, the RXRDY bitin the status register is set, and the RxADY qutputis asserted. If the character length Is less than 8 bits, the High or- Aprit 4, 1986 der unused bits.in the holding register are set to zero. The parity error, framing error, and overrun error status bits are strobed into the status. register on. the positive going edge of Rx corresponding to the received character boundary. If the stop bitis present, the receiver will immediately begin its search for the next startbit. Ifthe stop bitis absent (framing error), the receiver will interpret a space as a start bit if it persists into the next bit timer interval. Ifa break condition is detected (RxD is Low for the entire character as-well as. the stop bit), only one character consisting of all zeros (with the FE status bit SR5 set) will be transferred to the holding register. The RxD input must return to a High condition before a search for the next start bit begins. Pin 25 can be programmed to be a break detect output by appropriate setting of MR27-MR24. If so, a datected break will cause that pin to go. High. When RxD returns to mark for one AxG time, pin 25 will go low. Refer to the Break De- tection Timing Diagram. When the EPCI is initialized into the synchro- nous: mode, the receiver first enters the hunt mode on a0 to 1 transition of RxEN (CR2), In this mode, as data are shifted into the receiver shift register a bit ata time, the contents of the register are compared to the contents of the. SYN register. If the two are not equal, the next bitis shifted in and the comparison is repeated. When the two registers match, the hunt mode is terminated and character assembly mode begins. If single SYN operation is pro- 51 grammed, the SYN DETECT status bit is set. If double SYN operation is programmed, the first character assembled after SYN1 must be SYN2 in order for the SYN DETECT bit to be set. Otherwise, the. EPCI. returns to the hunt mode. (Note that the sequence SYN1-SYN1-SYN2 will not achieve synchroni- zation.) Wher synchronization has been achieved, the EPCI continues to. assemble characters and transfer then to. the holding reg- ister, setting the RxRDY status bit and assert- ing the RXADY outputeachtime acharacter is transferred.. The PE and OE status bits are set as appropriate. Further receipt of the appropri- ate SYN sequence sets the SYN DETECT sta- tus bit. If the SYN stripping mode is commanded, SYN characters are not trans- ferred to the holding register. Note thatthe SYN characters used to establish initial synchroni- zation are nattransferred to the holding register in any case. External jam synchronization can be achieved via pin 9 by appropriate setting of MR27-MR24. When pin 9 is an XSYNC input, the internal SYN1, SYN1-SYN2, and DLE-SYN1 detec- tionis disabled. Each positive going signal on XSYNC will cause the receiver to establish syn- chronization on the rising edge of the next RxG pulse. Character assembly will start with the RxD input at this edge. XSYNCG may be low- ered ori the nextrising edge of RxD. This exter- nal. synchronization will cause the SYN DETECT status bit to be setuntil the status reg- isteris read. Refer to XSYNG timing diagram,NAPC/ SIGNETICS Philips ComponentsSignetics Data Communlcation Products Enhanced programmable communications interface (EPCI) 4HLE D MM 6653924 0059333 8 MBSIC3 SCN2661/SCN68661 1-25 37-07 Product Specification. Table 2. CPU-Related Signals INPUT/ PIN NAME PIN NO. OUTPUT FUNCTION RESET 24 | | AHigh onthis input performs a master reset on the 68661. This signal asynchronously termi- nates any device activity and clears the mode, command and status registers. The device as- sumes the idle state and remains there until initialized with the appropriate control words. AO, Ai 42,10 | Address lines used to select internal EPCI registers. : Rw 13 | Read command when Low, write command when High. CE W I Chip enable command. When Low, indicates that contro! and data lines to the EPCI are valid and that the operation specified by the RW, Ai andA0 inputs should be performed. When High, places the DO-D7 lines in the 3-State condition. 00-D7 27,28,1,2,5-8 vo 8-bit, 3-State data bus usedto transfer commands, data and status between EPC] andthe CPU. DO is the feast significant bit, D7 the most significant bit. TXRDY 15 9 This outputis the complementof status register bit SRO. When Low, itindicates thatthe transmit data holding register (THR) is ready to acceptadata character from the GPU. Itgoes High when the data character is loaded, This outputis valid only when the transmitter is enabled. {tis an : open-drain output which can be used as an interrupt to the CPU. RxADY i4 This outputis the complementof status register bit SR1, When Low, itindicates that the receive data holding register (RHR) has a character ready for input to the CPU. It goes High when the RHRisread by the CPU, andalsowhen the receiveris disabled. Itis an open-drain outputwhich can be used as an interrupt to the GPU, TXEMT/ 18 Q This outputis the complement of status register bit SR2. When Low, itindicates that the trans- DSCHG mitter has completed serialization of the last character loaded by the CPU, or that a change of state of the DSR or DCD inputs has occurred. This output goes High when the status register is ready by the OPU, Ifthe TxEMT condition does notexist. Otherwise, the THR must be loaded by the CPU for this line.to go high. Itis an open-drain output which can be used as aninterrupt fo the CPU. See Status Register (SR2) for details. Table 3. | Device-Related Signals INPUT, PIN NAME PIN NO. OUTPUT FUNCTION BRCLK 20 { Clock input to the Internal baud rate generator (see Table 1). Not required If external receiver and transmitter clocks are used. Rx/BKDET 25 vo Receiver clack, If external receiver clock is programmed, this input controls the rate at which the characteris to be received. Its frequency is 1X, 16X or 64X the baudrate, as programmed by mode register 1. Data are sampled on the rising edge of the clock. {finternal receiver clock ; is programmed, this pin can be a 1X/16X clock or a break detect output pin. TxO/XSYNG 9 vo Transmitter clock. If external transmitter clock is programmed, this input controls the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X the baud. rate, as pro- grammed by mode register 1. The transmitted data changes on the falling edge of the clock. Itinternal transmitter clock is programmed, this pin oan be a 1X/16X clock output or an external fam synchronization input. : . RxD 3 l Serial data input to the receiver. Mark" is High, space is Low. TxD 19 Oo Serial data output from the transmitter. "Mark" is High, Soace*is Low. Held in mark condition when the transmitter is disabled. / DSR 22 V General purpose input which can be used for data setready or ring indicator condition. Its com~ plement appears as status register bit SR7, Causes a Low output on TxEMT/DSCHG when its state changes if CR2 or CRO =.1. DOD 16 I Data carrier detect input. Must be Low in order for the receiver to operate. Its complementap- pears as status register bit SR6. Causes a Low output on TXEMT/DSCHG when its state changes it CR2 or GRO = 1. IE DCD goes High while receiving, the RxC is internally inhibited, OTs 17 wl Clear to send input. Must be Low in order for the transmitter to operate. Ifit goes High during transmission, the.character in the transmit shift register will be transmitted before termination, DTA 24 oO General purpose output whichis the complement of command reglster bit CAt. Normally used to Indicate data terminal ready. RAIS 23 General purpose outputwhich is the complement of command register bit GR5. Normally used a indicate request to send. See Command Register (CRS) for details. Apiil 4, 1986 52see NAPC/ SIGNETICS WLE D MM bbS34ay 0059334 T BESIC3 Philips Components-Signetics Data Communication Products Enhanced programmable communications | interface (EPCI) Product Specification SCN2661/SCN68661 Transmitter The EPCtis conditioned to transmit data when the CTS input is Low and the TxEN command register bitis set. The 6866T indicates to the CPU thatit can accept a character for transmis- sion by setting the TxADY status bit and assert- ing the TXRDY output. When the CPU writes acharacter into the transmit data holding regis- ter, these conditions are negated, Data are transferred from the holding register to the transmit shift register when itis idle or has com- plted transmission of the previous character. The TxRDY conditions are then asserted again. Thus, one full character time of bulfering is provided. In the asynchronous mode, the transmitter au- tomatically sends a start bit followed by the pro- grammed number of data bits, the least significant bit being sent first. It then appends an optional odd or even parity bit and the pro- grammed number of stop bits. [f, following transmission of the data bits, a new character is not available in the transmit holding register, the TxD output remains in the marking (High) condition and the TXEMT/DSCHG output and its corrasponding status bit are asserted. Transmission resumes when the CPU loads a new character into the holding register. The transmitter can be forced to output a continu- ous Low (BREAK) condition by setting the send break command bit (CR3) High. tn the synchronous mode, when the 68661 is initially conditioned to transmit, the TxD output remains High and the TxRDY condition is as- serted until the first character to be transmitted (usually a SYN character) is loaded by the CPU. Subsequentto this, acontinuous stream of characters is transmitted, No extra bits (oth- er than parity, if commanded) are generated by the EPCI unless the CPU fails to send a new character to the. EPCI by the time the transmit- ter has completed sending the previous char- acter. Since synchronous communication does not allow gaps between characters, the EPCI asserts TXEMT and automatically fills the gap by transmitting SYN1s, SYN1=SYN2 doublets, or DLE-SYN1 doubles, depending on the state of MR16 and MRi7. Normal transmission of the message resumes when anew characteris avaitable in the transmit data holding register. If the send OLE bit in the commands register is true, the DLE character is automatically trans- April 4, 1986. mitted prior to transmission of the message character in the THR. : EPC! PROGRAMMING Prior to initiating data communications, the 68661 operational mode must be programmed by performing write operations to the mode and commandregisters. tn addition, if synchronous operation is programmed, the appropriate SYN/DLE registers must be loaded. The EPCI canbe reconfigured at any time during program execution. A flowchart of the initialization pro- cess appears in Figure: 1. The internal registers of the EPCl are accessed by applying specific signals to the CE, RW, At and AO inputs. The conditions necessary to ad- dress each register ara shown in Table 4. The SYN1, SYN2, and OLE registers are ac- cessed by performing write operations with the conditions Ai =.0, AO = 1, and YW = 1. The first operation foads the SYN1 register. The next loads the DLE register, Reading or loading the mode registers is doneina similar manner. The first write (or read) operation. addresses mode register 1, and a subsequent operation. ad-_ dresses mode register 2. If more than the re- quired. number of accesses ar made, the internal sequencer recycles to point at the first register. The pointers are reset to SYN 1 regis- ter and mode register 1 bya RESET input or by performing a read command register opera- tion, but are unaffected by any other read or write operation, The 68661 register formats are summarized in Tables 5, 6, 7and 8. Mode registers 1 and 2de- fine the general operational. characteristics of the EPCI, while the command register controls the operation within this basic framework. The EPCI indicates its status in the status register. These registers are cleared when a RESET in- put is applied. Mode Register 1 (MR1) Table illustrates mode ragister 1. Bits MR11 and MR10 select the. communication format and baud rate multiplier. 00 specifies synchro- nous format. However, the multiplierin asynch- ronous format applies only if the external clock input option is selected by MR24 or MR25. MRi3 and MR12 selecta character length of5, 8,7 or8bits. Thecharacter length does notinc- 53 T= 75-37-67 clude the- parity bit, if programmed, and does not include the start and stop bits in asynchro- nous mode. MR14 controls parity generation. If enabled, a parity bit is added to the transmitted character and the receiver performs a parity check on in- coming data. MR15 selects odd or even parity when parity is enabled by MR14. In asynchro- nous mode, MR17 and MRI6 select character framing of 1, 1.5, or 2 stop bits. (If 2X baud rate is programmed, 1.5 stop bits defaults to 1 stop bits on transmit.) In synchronous mode, MR17 controls the number of SYN characters used to establish synchronization and for character fill when the tranismitteris idle. SYN1 aloneisused if MR17 = 1, and SYN1-SYN2 is used when MAI7 =0. Ifthe transparent mode is specified by MR16, DLE-SYN1 is used for character fill and SYN detect, but the normal synchroniza- tion sequence is used to establish character syne. When transmitting, a DLE character in the transmit holding register will cause a sec- ond DLE character to be transmitted, This DLE stuffing eliminates the software DLE compare and stuff on each transparent mode data char- acter. Ifthe send DLE command (CR3)is active when 4 DLE is loaded into THR, only one addi- tional DLE willbe transmitted. Also, DLE strip- ping and DLE detect (with MR14 = 0) are enabled, The bits in the mode register atfecting character assembly and disassembly (MR12-MA16) can be changed dynamically (during active receive/ transmitoperation). The character mode regis- ter affects both the transmitter and receiver: therefore in synchronous mode, changes should be made only in half-duplex mode (RXxEN = 1 or TXEN = 1, but not both simulta- neously = 1). Inasynchronous mode, character changes should be made when RxEN and TxEN =O orwhen TxEN = 1 and the transmitter is marking in half-duplex mode (RXEN = 0). To effect assembly/disassembly of the next re- ceived/transmitted character, MR1i2 15 must be changedwithinn bit times of the active going state of AxADY/TXADY. Transparent and non-transparent mode changes (MR16) must occur within n-1 bit times of the character to be alfected when the receiver or transmitter is ac- tive. (n- smaller of the new and old character lengths.)NAPC/ SIGNETICS YWLE D MM 6653924 0059335 1 MHSIC3 Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCl) SCN2661/SCN68661 Table 4. 68661. Register Addressing ~ 7-7$-37-01 LOAD _ MODE REGISTER 1 { LOAD MODE REGISTER 2 NOTE: Made Register 1 must be written clocks ara used. NOTE: poo it | OPERATE I 4 DISABLE RCVR AND XMTR Figure 1, 68661 Initialization Flowchart cE Ay Ao Rw FUNCTION 1 X Xx X 3-State data bus 0 0 0 0 Read receive holding register . 0 0 0 1 Write transmit holding register 0 o 1 0 Read status register 0 0 1 1 Write SYNI/SYN2/DLE registers 0 1 0 0 Read mode register 1/2 0 i 0 1 Write mode register 1/2 0 1 1 0 Read command register 0 1 1 1 Write command. register INITIAL RESET belora 2 can ba written. Mode Register 2 head not be programmed if external SYNi Register must be written before SYN2 can be written, and SYN2 belorg OLE can be wrilten, April 4, 1986 54YLE D Ml 6653924 0059336 3 MMSIC3 NAPC/ SIGNETICS Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications interface (EPCl) SCN2661/SCN68661 . _ T-95-37-67 Table 5. Mode Register 1 (MR1) MRI7 | _MRIG MR15 MR14 MRIS MRI2 | MR | MRTO Sync/Asyne Parity Type "| Parity Control Character Length Mode and Baud Rate Factor Asyno:. Stop bit length a . x 00 = invalid 0 = Odd 0 = Disabled 00 = 5 bits 00 = Synchronous 1X rate 01 = f stop bit 1 =Even 1 = Enabled 01 =6 bits 01 = Asynchronous 1X rate 10 = 1 1/2 stop bits , 10 = 7 bits 10= Asynchronous 16X rate 11 =2 stop bits 11 =8 bits 11 = Asynchronous 64X rate Syne: Syne: Number of Transparency SYN char control 0 = Double SYN | 0 = Normal 1=Single SYN | 1 = Transparent NOTE: Baud rate factor in asynchronous applies only if external clock is. selected. Factor is 16X if internal clockis selected. Mode must be selected (MR11, MR{0) in any case. Table 6. Mode Register 2 (MR2) MR27- MR24 : MR23 ~ MR20 Baud Rate Tx RxC Ping Pin 25 Txe Rxc Ping Pin 25 Mode Selection 0000 E E TxG RxG | = 1000 E E XSYNC* AXC/TxC syne : 0001 E i TxG 1X 1001 E I TxG BKDET asyne 0010 E 1X RxG 1010 ! E XSYNC* AxC. syne 0011 | I 1X 1X 1011 | I 1X BKDET asyne | See baud rates 0100 E E Txc RxC 1100 E E ~ XSYNC* RxC/TxC sync _ in Table. 1. 0101 E l TxG 16X 1101 E I TXG BKDET asyne 0110 Il E 16X Axc 1110 I E XSYNC* RxC syne Otft I | 16X 16X 141 I I 16X BKOET async NOTES: * When pin 9 is programmed as XSYNC input, SYN1, SYN1-SYN2, and DLE-SYN{1 detection Is disabled. E =xternal clock . * | =Internal clock (BRG) : 1X and 16X are clock outputs. Table 7, Command Register (CR) cR7 | _CR6 crs | CRa CR3 CR2 cRi | CRO : : Receive. Transmit Request . Data. Terminal Operating Mode Reset Error Syne/Async Control _ Control to Send (RxEN) Ready (TXEN) 00 = Normal operation 0=Forco RTS | 0 = Normal Asyne: 0 = Disable 0 = Force DTR | 0 = Disable 01 = Asyno: Output High | 1 = Reseterror | Force Break 1 = Enable output High | 1 = Enable Automatic one clock flags in 0 = Normal 1 = Force"DTR Echo mode time after status reg. 1 = Forcebreak oufput Low Syne: SYN and/or DLE TxSR (FE,OE,PE/ stripping mode serialization DLE detect.) 10 = Local loopback 1 = Force RTS Syne . Not applicable 1i = Remote loopback output Low Send DLE : in 0 = Normal 1 = Send DLE April 4, 1986 55NAPC/ SIGNETICS HE D MM 6653924 90599357 5 MESIC3 Philips ComponentsSignetics Data Communication Products Enhanced programmable communications interface (EPCI) Product Spcification SCN2661/SCN68661 Py Table 8. Status Register (SR) ; ; _SR7 SRE SRS SR4 SA3 _ SR2 Shi SRO Data Set Data Carrier -FE/SYN PE/DLE TXEMT . Ready Detect Detect Overrun Detect DSCHG . _ AxRDY TRRDY 0 = DSR input 0 = DCD input Asyne: 0 = Normal Asyne: 0 = Normal 0 = Receive 0 = Transmit is High is High 0 = Norma! 1 = Overrun 0 = Normal 1 = Change in holding holding 1 = DSR input 1. = DOD input 1 = Framing error. 1 = Parity error or register register is Low is Low error DCD, or empty busy transmit 1 = Receive 1 = Transmit Syne: Syne: shift holding halding 0 = Normal 0 = Normal register is register register 1= SYN 1 = Parity error empty has data empty detected or DLE received Mode Register 2 (MR2) contents prior to sending the character in the 3. TXADY output = 1. Table 6 illustrates mode register 2, MR23, tansmit data holding register. Since thisisa The TXEMT/DSCHG pin will retlect only MR22, MR21 and MR20 control the frequency of the internal baud rate generator (BAG), Six- teenrates are selectable for each EPCI version (-1,-2,-3). Versions 1 and 2 specify a 4.9152MHz TTL input at BROLK (pin 20); ver- sion 3 specifies a 5.0688MHz input which is identical to the Signetics 2651, MR23 - 20 are don't cares if external clocks are selected (MR25 MR24 = 0). The individual rates are given in. Table 1. MR24 ~ MR27 select the receive and transmit clock source (either the BRG or an external in- put) and the function at pins 9 and 25. Refer to Table 6, Command Register (CR) Table 7 illustrates the command register. Bits CRO (TXEN) and CR2 (RxEN) enable ordisable the transmitter and receiver respectively. A 0~ to-1 transition of CR2 forces start bit search (async mode) or hunt mode (syric mode} on the second RxC rising edge. Disabling the receiver causes RxADY to go High (inactive). If the transmitter is disabled, it will complete the transmission of the character in the transmit shift register (if any) prior to terminating opera- tion. The TxD output will then remain in the marking state (High) while TXADY and TxEMT will go High (inactive). If the receiver is. dis- abled, it will terminate operation immediately. Any character being assembled will be ne- glected. A 0-to-1 transition of CR2 will initiate start bit search (async) or hunt mode (sync). Bits CR1 (DTR) and CRS (RTS) control the. DTR and RTS outputs, Data at the outputs:.are the logical complement of the register data. In asynchronous mode, setting CR3.will force and hold the TxD output Low (spacing condi- tion) at the end of the current transmitted char- acter. Normal operation resumes when CR3is cleared, The TxD line will go High for atleast one bit time before beginning transmission of the next character in the transmit data holding register. In synchronous mode, setting CR3 causes the transmission of the OLE rgister April 4, 1986 ona time command, CR3 does not have to be reset by software, CR3 should be set when en- tering and exiting. transparent mode and for all DLE-non-DLE character sequences, Setting CR4 causes the error flags in the status register (SR3, SR4, and SAS) to be cleared; this.is a one time command. There is no jnter- nal lateh for this bit. When CRS (RTS) is set, the RTS pinis forced Low. A 1~to-0 transition of CR5 will cause RTS: to go High (inactive) one TxC time after the last serialbithas been transmitted. Ifa 1to-0 tran- sition of CRS occurs while data [s being trans- mitted, ATS will remain Low (active) until both the THR and the transmit shift register are empty and then go High (inactive) one TxC time later. The EPCI gan operate in one of four submodes within each major mode (synchronous or asynchronous). The operational sub-mode is determined by GR7 and CR6. CR7-CR6 = 00 is the normal mode, with the transmitter and re- ceive operating independently in accordance with the mode and status register instructions. Inasynchronous mode, CR7CR6 =01 places the EPCI in the automatic echo mode. Clocked, regenerated received data are auto- matically directed to the TxD line while normal recdiver operation continues. The: receiver must be enabled (CR2 = 1), but the transmitter need notbe enabled, CPU to receiver commu- nication continues normally, but the CPU to transmitter link is disabled,. Only the first char- acter of a break condition is echoed. The TxD output will go High until the next valid startis detected. The following conditions are true while in automatic echo mode: 1, Data assembled by the receiver are auto- matically placed in the transmit holding register and retransmitted by the transmit: ter on-the TxD output. 2. The transmitter is clocked by the receive clock. 56 the data set change condition. . The TxEN command (CRO) is ignored, In synchronous mode, GR7 CR6 = O1 places the EPCI in the automatic SYN/DLE stripping: mode. The exact action taken depends on the setting of bits MR17 and MRi6: 1. In the non-transparent, single SYN mode (MR17 MRI6 = 10), characters in the data stream matching SYN1 are not transferred to the Receive Data Holding register (RHR). 2. In the non-transparent, double SYN mede (MR17 MA16 = 00), character in the data stream matching SYN1, or SYN2 if immediately preceded by SYN1, are not transferred the RHR. 3. In transparent mode (MR16 = 1), chatac- ter in the data steam matching DLE, or SYN1 if immediately preceded by DLE, are not transferred to the RHA. However, only the first DLE of a DLE-DLE pair is stripped. Note that automatic stripping mode does notaf- feet the setting of the OLE detect and SYN de- tect status bits (SR3 and SRS). Two diagnostic sub-modes can also be confi- gured. In local loopback mode (CR7 CR6 = 10), the following loops ar connected internally: 1. The-transmitter output is connected to the receiver input. . 2. DTA is connected to DCD and RTS is connected to CTS. 3. The receiver is clocked by the transmit clock. 4. The DTR, RATS and TxD outputs are held High. 5. The CTS, DCD, DSH and RxD inputs are ignored.NAPC/ SIGNETICS Q1E D BM 6653924 0059338 7 BaSic3 Philips Components-Signetics Data Communication Products Enhanced programmable communications interface (EPCl) Product Specification SCN2661/SCN68661 Additional requirements to operate in the local loopback mode are that CRO (TxEN), CR1 (DTR) and CRS (RTS) must be set to 1, CR2 (RXEN) is ignored by the EPCI. The second diagnostic made is the remote. loopback mode (GR7 - CR6 = 11). In this mode: 1, Data assembled by the receiver are.auto- matically placed in the transmit holding register and retransmitted by the transmit- ter on the TxD output. 2. The transmitter is clocked by the receiver clock. 3. No data are sent to the local CPU, but he error status conditions (PE, FE) are set, 4. The RXADY, TxADY, and TXEMT/ DSCHG outputs are held High. 5. GRO (TxEN) is ignored.. 6. All other signals operate normally. Status Register The data contained In the status register (as shown in Table 8) indicates receiver and trans- mitter conditions and modem/data set status. SRQis the transmitter ready (TxRDY) status bit. It, and'its corresponding output, are valid only when the transmitter is enabled, If equal to 0-, itindicates that the transmit data holding regis- ter has bean loaded by the GPU and the data has not been transferred to the transmit regis- ter. If set equal to 1, itIndicates that the holding register is ready to accept data from the CPU, This bitis initially setwhen the transmitteris en- abled by CRO, unless a character has previous- April 4, 1986 ly been loadedinto the holding register. Itis not set when the automatic echo or remote loop- back modes are programmed. When this bit is set, the TXADY output pin is: Low, In the auto- matic echo and remote loopback mades, the output is held High. SRI, the receiver ready (RxRDY) status bit, in- dicates the condition of the receive data holding register. If set, itindicates thata character has been loaded into the holding register fronv the receive shift register and is ready to be read by the CPU. Ifequal to zero, there is.no new char- acter In the holding register. This bit is cleared when the GPU reads the receive data holding register or when the receiver is disabled by CR2. When set, the RxADY output is Low. The TxEMT/DSCHG bit, SR2, when set, indi- cates either a change of state of the DSH or DCD inputs. (when GR2 or CRO.= 1) or that the transmit shift register has completed transmis- sion of a character and no new character has been loaded into the transmit data holding reg- ister, Note thatin synchronous mode this bit will be seteven though the appropriate.fill" charac~ ter is transmitted. TXEMT will not go active until at least one character has been transmitted. It ts cleared by loading the transmit data holding register. The DSCHG conditions is enabled when TXEN = 1 or RxEN = 1. itis cleared when the status registeris readby the CPU. Itthesta- tus register is read twice and SR2~ 1 while SR6 and SR7 remain unchanged, then a TxEMT condition exists. When SR2is set, the TXEMT/ DSCHG output is Low. SR3, when set, indicates a received parity error when parity is enabled by MR14. In synchro- 57 T-75- 37-07 nous transparent mode (MR 16 = t), with parity disabled, itindicates that a character matching DLE register was received and the present character is neither SYN2 or DLE. This bit is cleared when the next character following the above sequence is loaded into RHR, when the receiver is disabled, or by a reset error com- mand, CR4. The overrun error status bit, SR4, indicates that the previous character loaded into the receive holding register was not ready the CPU at the time of new received character was transferred into it. This bit is cleared when the rceiver is: disabled or by the reset error command, GR4. In asynchronous mode, bit SRS signifies that the received character was not framed by a stop bit; i.e., only the first stop bit is checked. If RHR =0 when SRS = 1, a break condition is present. In synchronous non-transparent mode (MRI6 = 0), it indicates receipt of the SYN1 character in single SYN mode or the SYN1 SYN2 pair in double SYN mode. In synchronous transparent mode (MRI16 = 1), this bit is set upon detection of the initial syn- chronizing characters (SYN. or SYN1 -SYN2) and, after synchronization has been achieved, when a DLE-SYN1 pair is received. The bit is reset when the receiver is disabled, when the reset error commandis given in asynchronous mode, orwhen the status registeris read by the GPU in the.synchranous mode. SR6 and SR7 reflect the conditions of the DCD and DSR inputs, respectively, A Low input sets its corresponding status bit, and a High input clears it.NAPC/ SIGNETICS UE D Hl 6653924 0059335 9 BMSIC3 Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications an Prog - SCN2661/SCN68661 interface (EPCl) . T-75- 37-0) Table 9. 68661 EPCl vs 2651 PCI * ; FEATURE 7 EPCI / PCI 1. MR2 BIT 6, 7 . Control pins 9, 25 Not used / _* 2. DLE detect SAS SR3 = 0 for OLE-DLE, DLE -SYN1 SA3 = 1 for DLE-DLE, DLE SYN1 3. Reset of SR3, DLE detect Second character after DLE, or receiver dis- | Receiver disable, or CR4 = 1 * ___| able, or CR4 = 1 ; 4, Send DLE -CR3 ; One time command / Reset via GR3 on next TXADY 5. DLE stuffing in transparent mode Automatic OLE stuffing when DLE is loaded | Nona . exceptif CRS = 1 6. SYN1 stripping in double sync non-trans- | All SYN1 : First SYN1 of pair parent mode 7, Baud rate versions / Three One _ 8. Terminate ASYNC transmission (drop Reset. CRS in response to TXEMT changing Reset CRO when TxEMT goes from 1 to 0. RTS) fram 1 to 0 Then reset CR5 when TXEMT goes from 1to0 9. Break detect Pin 25 ; : FE and null character 10. Stop bit searched j -One J / - [Two | 11, External jam syne Ping No 12, Data.bus. timing | / Improved over 2651 ofa 13. Data bus drivers : : Sink 2.2mA Sink 1.6mA Source 400pA / Source 100A NOTES: * Internal BRG used for AxC. ** Internal BRG used for TxC. AC LOAD CONDITIONS 22v. +5V 7502 2kQ OUTPUT OUTPUT T CL = 150pF T CL = 50pF NOTES: , Open-drain outputs. CL = Load capacitance includes JIG and probe capacitance, April 4, 1986 58NAPC/ SIGNETICS WiE D HM 6653924 0059340 5 BASICS Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications . interface (EPCI) _ SCN2661/SCN68661 T-75 - 37-01 TIMING DIAGRAMS RESET . CLOCK | | K SRH >t IBRL >] | be tHe tT, . | RESET nem 4 KS L_ | taes 1apRG: - ~~ iad > | TRANSNIT RECEIVE ba TAIT TIME (1, 16, OR 64 CLOCK PERIODS) 7 we Ky a yo - ' = . RxD . no PX ~----------+-- Kk ee | taxs t<- 'RXH mi > (TxD >| txpp< . mee NL t {Tas Txo (OUTPUT) READ AND WRITE cE _ NY h i cE : < ced 1 pep pus | NOT , BUS eae niin ior xX DATA VAUD. | x FLOATING < Ipp >| oF April 4, 1986 59NAPC/ SIGNETICS YLE D Bl 6653924 0059341 7 BESICI Philips ComponentsSignetics Data Communication Products Product Specilication Enhanced programmable communications SCN2661/SCN68661 interface (EPCI) T- 78-37-01 SYNCHRONOUS MODE TIMING DIAGRAMS (Continued) I L lL w T T k T gy TEN __| | | | | a} 4 [ | Z { TXADY _ = = - | Ay TEFOR : ama LY LY ) ly DATA1 DATA2 DATA 3 DATA 4 NOTES: A Start ba B = Stop bit 1 O = Stop bit 2 D = TxD marking condition TXEMT goes low at tha begisining of the last data 53, of; if parity Is enabled, at the beginning of the pariy bil. TxROY, TxXEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous mode}) - 112034 St 273 4 1814 273 14 57d 253 4 S28 ys Sy f TxD | DATA 1 DATA 2 DATA3 | SYN1 | DATA 4 | | r r T t oF I | TsEN | | | | \ | | | | TiRDY | / \ | * Lt me WY YY de DATA1 DATA 2 DATAS DATA4 f mw DTP AL 234 8B SC A141 2/314 7;54;B C AL1121;91541:5,+B CD- A112 TxD - DATA1 | I | DATA 2 | paATAS [ DATA4 + April 4, 1986 606653924 OO5934e 4 BaASIC3 NAPC/ SIGNETICS ' YLE D Philips Components-Signetics Data Communication Products Produet Spectfication Enhanced programmable communications SCN2661/SCN68661 interface (EPCl) . TIMING DIAGRAMS (Continued) T-7-37-07 EXTERNAL SYNCHRONIZATION WITH-XSYNC 1X RxO | L XSYNG tog = XSYNC SETUP TIME = 300n8 tyy- XSYNC HOLD TIME = ONE Rx a tT me Ke Xe Xe Ke XA CHARACTER ASSEMBLY BREAK DETECTION TIMING Rx CHARACTER = 5 BITS, NO'PARITY X RxC + 16 OR 64 AxO LOOK FOR START BIT = LOW (IF AxD IS HIGH, LOOK FOR HIGH TO LOW: TRANSITION) [ FALSE START BIT CHECK MADE (RxD LOW) t MISSING STOP BIT DETECTED SET FE BIT* ed {stDATA BIT. SAMPLED MISSING STOP BIT DETECTED, SET FE BIT. 6 RHA, ACTIVATE RxROY. SET BKDET PIN RxD INPUT RxSR UNTIL A MARK TO SPACE TRANSITION OCCURS, NOTE: * I the stop bit Is present, the start bit search will commence immediately. April 4, 1986 6iCARNE ieHiocamPestria tee TERRY TOT cepa NAPC/ SIGNETICS YLE D BM 6653924 0059343 O BHSIC3 Philips ComponentsSignetics Data Communication Products Product Specification Enhanced programmable communications . SCN2661/SCN68661 interface (EPC) TIMING DIAGRAMS (Continued) T- 78-37 -07 | RxRDY (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous made]) f Tc JA L2F APS pV ZiT pH Set p23 js S itp 23 psi S irr 2s is pS ir 1213 is psi wf AxD SYN1 DATA 1 DATA2 | DATA3 | DATA4 | DATAS g . | l [_- ~~ 1GNORED 3 | [ 3p xen | 3 | | i | - & SYNOET | J I 9} Status air . L __t _L. : b I | [ FERDY wee || Ly yf YU READ READ READ RHR READ BHR READ RHR READ RHR STATUS STATUS {DATA 4). (DATA 2) (DATA 3) (DATA 3) pO p- (Dr A 11-7253 7445: BrC Api 32534 DATA 3 DATA 4 D ~~ A 141213 141.45 RxD OATA1 RxEN _| FxROY | Lo Le ic Ayi 4253 p48 DATA 2 a 8 | | J | | | ! | ASYNCHRONOUS MODE OVERRUN STATUS BIT cE FOR - A l - ee SY = READ RH READ RHR (DATA 1) (DATA 3) NOTES: A- Start 63 B we Stop hi t C= Stop bit2 D = TxO marking condition Only one stop bitis detected April 4, 1986 62NAPC/ SIGNETICS 4YLE D RM 6653924 GO593944 2 BASICS Philips ComponentsSignetics Data Communication Products Product Spetification ed program 1 ication Enhanced programmable communications SCN2661/SCN68661 interface (EPCI) T-79- 37-61 TYPICAL APPLICATIONS ASYNCHRONOUS INTERFACE TO CRT TERMINAL. " ADDRESS BUS } 4 " CONTROL BUS ) ( , DATA BUS _ ) i a 4 xO EIA TO TIL CONVERT TxD (OPT) | )) sCN2661/68661 Li LY er eaupemrsaae | al ASYNCHRONOUS INTERFACE TO TELEPHONE LINES ( : ~__ ADDRESS BUS ) 0 GONTROL BUS _ ) ( ~ DATA BUS ) RxD | Txb > DSK Pp<-_J PHONE ASYNG uNE DR bp MODEM INTERFACE SCN266160681 ory h~_ ATs b_ poo p<_~ BRCLK |}*}_ BAUD RATE CLOCK OSCILLATOR =|. TELEPHONE. LINE April 4, 1986 63NAPC/ SIGNETICS Philips ComponentsSignatics Data Communication Products GUE D MM 6653924 OO5934S 4 BASICS Product Specification Enhanced programmable communications - interface (EPCl) SCN2661/SCN68661 TYPICAL APPLICATIONS (Continued) T-7-37-0/ SCN2661/68661 FRC TE DEVICE BUS RxD TxD Re arog SCN2661/69661 DUD ors RTs DSR OTR SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE SYNCHRONOUS TERMINAL OR PERIPHERAL SYNCHRONOUS INTERFACE TO TELEPHONE LINES TELEPHONE CINE April 4, 1986 . 64