DS-CPC7584-R0.A www.clare.com 1
Preliminary
Features
•Small 16-pin surf ace-mount SOIC pac kage and v ery
small micro-leadframe package (MLP) a vailable
•Monolithic IC reliability
•Low matched RDSON
•Eliminates the need for zero cross switching
•Fle xible s witch timing to transition from ringing mode
to idle/talk mode .
•Clean, bounce free switching
•Tertiary protection consisting of integrate d current
limiting, thermal shutdown, and SLIC protection
•5 V operation with power consumption less than
10 mW
•Intelligent battery monitor
•Latched logic le vel inputs, no drive circuitry
Applications
•Central office (CO)
•Digital Loop Carrier (DLC)
•PBX Systems
•Digitally Added Main Line (DAML)
•Hybrid Fiber Coax (HFC)
•Fiber in the Loop (FITL)
•P air Gain System
•Channel Banks
Description
The CPC7584 is a monolithic solid state switch in a
16-pin surface-mount package. It provides the neces-
sary functions to replace tw o 2- Form-C electro-
mechanical rela ys on analog line cards f ound in Cen-
tral Office, Access, and PBX equipment. The device
contains solid state s witches f or tip and ring line break,
ring injection/ring return and test access. The
CPC7584 requires only a +5V supply and offers
“break-before-make” or “make-bef or e-break” switch
operation using simple logic-level input control.
The CPC7584xC diff e rs f rom the CPC75 84xA/B with
the addition of a logic state. See “Functional Descrip-
tion” on page 10 for more information. The
CPC7584xC also has a higher hold curre nt f or the pro-
tection SCR.
Ordering Information
Figure 1. CPC7584 Bloc k Diagram
Part Number Description
CPC7584BA SOIC 6-pole LCAS with protection SCR
CPC7584BB SOIC 6-pole LCAS without protection SCR
CPC7584BC SOIC 6-pole LCAS with protection SCR and
added logic state
CPC7584MA MLP 6-pole LCAS with protection SCR
CPC7584MB MLP 6-pole LCAS without protection SCR
CPC7584MC MLP 6-pole LCAS with protection SCR and
added logic state
CPC7584xx-TR Add -TR to the part number when ordering
tape and reel packaging
R1
R2
Ring
TIP
Secondary
Protection
SW1
Break
SW2
Break
SW3
Ringing
Return
SW5
Test-In
SW6
Test-In
SW4
Ringing
Access
SCR
and Trip
Circuit
SLIC
Ring Generator
VBAT
Reference (16)
CPC7584
Battery
+
-
TLINE
RLINE
T (2)BAT
R (15)BAT
(14)
(3)
R (12)
Test-In
R (13)RING
T (5)TEST-IN
T (4)RING
CPC7584
Line Card Access Switch
CPC7584
1 www.clare.com R0.A
Preliminary
1 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Absolute Maximum Ratings (at 25° C). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Electrical Characteristics, TA = -40° C to +85° C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.1 Power Supply Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.2 Break Switches, SW1 and SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2.3 Ring Return Switch, SW3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.4 Ringing Access Switch, SW4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.5 Test-In Switches, SW5 and SW6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Additional Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 Alternate Break-Before-Make Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.5 Protection Circuitry Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 CPC7584xA/B Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 CPC7584xC Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Package Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Switch Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Ring Access Switch Zero-Cross Current Turn Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.4 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.5 Battery Voltage Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6 Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.1 Diode Bridge/SCR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.6.2 Current Limiting function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 Temperature Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.8 External Protection Elements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.9 Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4 Manufacturing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1 Mechanical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2 Printed-Circuit Board Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.2.2 MLP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3 Tape and Reel Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.3.1 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.1 Moisture Reflow Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4.2 Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.5 Washing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CPC7584
Rev. 0.A www.clare.com 2
Preliminary
1. Specifications
1.1 Absolute Maximum Ratings (at 25° C)
1.2 Electrical Characteristics, T A = -40° C to +85° C
Unless otherwise specified, minimum and maxim um
v alu es ar e production testing r equir ements. Typical
v alu es ar e char acteristic of the device and are the
result of engineering e valuations. Typical v alues a re
provided for information purposes only and are not
part of the testing requirements.
Absolute maximum ratings are stress ratings. Stresses in
excess of these ratings can cause permanent damage to
the device. Functional operation of the device at these or
any other conditions beyond those indicated in the opera-
tional sections of this data sheet is not implied. Exposure of
the device to the absolute maximum ratings for an
extended period may degrade the device and affect its reli-
ability.
1.2.1 Power Supply Specifications
1.2.2 Break Switches, SW1 and SW2
Parameter Minimum Maximum Unit
Operating temperature -40 +110 °C
Storage temperature -40 +150 °C
Operating relative humidity 5 95 %
Pin soldering temperature
(10 seconds max) - +260 °C
+5 V power supply - 7 V
Battery Supply - -85 V
Logic input voltage - 7 V
Logic input to switch output
isolation -330V
Switch isolation (SW1,
SW2, SW3, SW5, SW6) -330V
Switch Isolation (SW4) - 480 V
Supply Minimum Typical Maximum Unit
VDD +4.5 +5.0 +5.5 V
VBAT
1-19 - -72 V
1VBAT is used only as a reference for internal protection circuitry. If VBAT rises above
-10 V, the device will enter the all-off state and will remain in the all-off state until the
battery drops below -15 V.
ESD Rating (Human Body Model)
1000 V
Parameter Conditions Symbol Minimum Typical Maximum Unit
Off-state leakage current
+25° C
VSW (differential) = -320 V to GND
VSW (differential) = -60 V to +260 V ISW -0.11µA
+85° C
VSW (differential) = -330 V to GND
VSW (differential) = -60 V to +270 V ISW -0.31µA
-40° C VSW (differential) = -310 V to GND
VSW (differential) = -60 V to +250 V ISW -0.11µA
RDSON
+25° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V-14.5- Ω
+85° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V-20.528Ω
-40° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V-10.5- Ω
RDSON match Per on-resistance test condition of
SW1, SW2RON SW1-RONSW2 Magnitude - 0.15 0.8 Ω
DC current limit
+25° C VSW (on) = ±10 V ISW - 300 - mA
+85° C VSW (on) = ±10 V ISW 80 160 - mA
-40° C VSW (on) = ±10 V ISW - 400 425 mA
CPC7584
3 www.clare.com Rev. 0.A
Preliminary
1.2.3 Ring Return Switch, SW3
Dynamic current limit
(t = <0.5 µs)
Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.
ISW -2.5- A
Logic input to switch output isolation
+25° C VSW (TLINE, RLINE) = ±320 V, logic
inputs = gnd
ISW -0.11µA
+85° C VSW (TLINE, RLINE) = ±330 V, logic
inputs = gnd ISW -0.31µA
-40° C VSW (TLINE, RLINE) = ±310 V, logic
inputs = gnd
ISW -0.11µA
dv/dt sensitivity Applied voltage = 100 V p-p square
wave at 100 Hz - - 200 - V/µs
Parameter Conditions Symbol Minimum Typical Maximum Unit
Off-state leakage current
+25° C
VSW (differential) = -320 V to GND
VSW (differential) = -60 V to +260 V ISW -0.11µA
+85° C
VSW (differential) = -330 V to GND
VSW (differential) = -60 V to +270 V ISW -0.31µA
-40° C
VSW (differential) = -310 V to GND
VSW (differential) = -60 V to +250 V ISW -0.11µA
RDSON
+25° C ISW (on) = ±0 mA, ±10 mA ∆ V- 60 - Ω
+85° C ISW (on) = ±0 mA, ±10 mA ∆ V - 85 100 Ω
-40° C ISW (on) = ±0 mA, ±10 mA ∆ V- 45 - Ω
DC current limit
+25° C VSW (on) = ±10 V ISW - 135 - mA
+85° C VSW (on) = ±10 V ISW -85-mA
-40° C VSW (on) = ±10 V ISW - 210 - mA
Dynamic current limit
(t = <0.5 µs)
Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.
ISW -2.5- A
Logic input to switch output isolation
+25° C VSW (TRING, TLINE) = ±320 V, logic
inputs = gnd
ISW -0.11µA
+85° C VSW (TRING, TLINE) = ±330 V, logic
inputs = gnd
ISW -0.31µA
-40° C VSW (TRING, TLINE) = ±310 V, logic
inputs = gnd ISW -0.11µA
Parameter Conditions Symbol Minimum Typical Maximum Unit
CPC7584
Rev. 0.A www.clare.com 4
Preliminary
1.2.4 Ringing Access Switch, SW4
1.2.5 Test-In Switches, SW5 and SW6
Parameter Conditions Symbol Minimum Typical Maximum Unit
Off-state leakage current
+25° C
VSW (differential) = -255 V to +210 V
VSW (differential) = +255 V to -210 V ISW -0.051 µA
+85° C
VSW (differential) = -270 V to +210 V
VSW (differential) = +270 V to -210 V ISW -0.11µA
-40° C
VSW (differential) = -245 V to +210 V
VSW (differential) = +245 V to -210 V ISW -0.051 µA
On Voltage ISW (on) = ± 1 mA --1.53V
Ring generator current
during ring VCC = 5 V, INaccess = 0 IR-0.10.25mA
Surge current - - - - 2 A
Release current - - - 300 - µA
RDSON ISW (on) = ±70 mA, ±80 mA ∆ V- 8.512Ω
Logic input to switch output isolation
+25° C VSW (RRING, RLINE) = ±320 V, logic
inputs = gnd ISW -0.051 µA
+85° C VSW (RRING, RLINE) = ±330 V, logic
inputs = gnd
ISW -0.11µA
-40° C VSW (RRING, RLINE) = ±310 V, logic
inputs = gnd ISW -0.051 µA
Parameter Conditions Symbol Minimum Typical Maximum Unit
Off-state leakage current
+25° C VSW (differential) = -320 V to GND
VSW (differential) = -60 V to +260 V ISW -0.11µA
+85° C VSW (differential) = -330 V to GND
VSW (differential) = -60 V to +270 V ISW -0.31µA
-40° C
VSW (differential) = -310 V to GND
VSW (differential) = -60 V to +250 V ISW -0.11µA
RDSON
+25° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V- 38 - Ω
+85° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V - 46 70 Ω
-40° C TLINE = ±10 mA, ±40 mA, TBAT = -2 V ∆ V- 28 - Ω
DC current limit
+25° C VSW (on) = ±10 V ISW - 175 - mA
+85° C VSW (on) = ±10 V ISW 80 110 - mA
-40° C VSW (on) = ±10 V ISW - 210 250 mA
Dynamic current limit
(t = <0.5 µs)
Break switches in on state, ringing
access switches off, apply ±1 kV at
10/1000 ms pulse, with appropriate
secondary protection in place.
ISW -2.5- A
CPC7584
5 www.clare.com Rev. 0.A
Preliminary
1.3 Additional Electrical Characteristics
Logic input to switch output isolation
+25° C VSW (TACCESS, TLINE) = ±320 V, logic
inputs = gnd
ISW -0.11µA
+85° C VSW (TACCESS, TLINE) = ±330 V, logic
inputs = gnd ISW -0.31µA
-40° C VSW (TACCESS, TLINE) = ±310 V, logic
inputs = gnd
ISW -0.11µA
Parameter Conditions Symbol Minimum Typical Maximum Unit
Parameter Conditions Symbol Minimum Typical Maximum Unit
Digital input characteristics
Input low voltage - ---1.5
V
Input high voltage - -3.5 - -
Input leakage current
(high) VDD = 5.5 V, VBAT = -75 V, Vlog = 5 V Ilog -0.11µA
Input leakage current
(low) VDD = 5.5 V, VBAT = -75 V, Vlog = 0 V Ilog -0.11
Power requirements
Power dissipation in
idle/talk and all-off
states
VDD = 5 V, VBAT = -48 V IDD, IBAT -5.510
mW
Power dissipation in
ringing and access
states
VSW (on) = ±10 V IDD 6.5 10
VDD current in idle/talk
and all off states VDD = 5 V
IDD -1.12.0
mA
VDD current in ringing
and access states
IDD -1.32.0
VBAT current in idle/talk
and all off states VBAT = -48 V
IBAT -0.110
µA
VBAT current in ringing
and access states
IBAT -0.110
Temperature Shutdown Requirements (temperature shutdown flag is active low)
Shutdown activation
temperature - - 110 125 150 °C
Shutdown circuit hyster-
esis --10-25°C
CPC7584
Rev. 0.A www.clare.com 6
Preliminary
1.3.1 Make-Before-Break Operation (Ringing to Idle/Talk Transition)
1.3.2 Break-Before-Make Operation (Ringing to Idle/Talk Transition)
1.4 Alternate Brea k-Before-Make Operation
Break-before-make oper ation can also b e achieved
using TSD as an input. In lines 2 an d 3 of “Break-
Bef ore-Mak e Oper ation (Ringing to Idle/Talk Transi-
tion)” on page 6, instead of using the logic input pins to
force the all-off state , force TSD to ground. This o ver-
rides the logic inputs and also forces the all off state.
Hold this state for 25 ms. During this 25 ms all-off
state, toggle t he inputs from the ringing state (Ring =
5 V, Test-In = 0 V) to the idle/talk sta te
(Ring = 0 V, Test-In=0 V). After 25 ms, release TSD to
return s witch control to the input pins which will set the
idle talk state.
When using the CPC7584 in this mode , forcing TSD
to ground overrides the input pins and force an all off
state. Setting TSD t o +5 V allows s witch control via the
logic input pins. Ho wever , setting TSD to +5 V also
disables the thermal shutdown mechanism. This is not
recommended. Theref ore , to allo w switch control via
the logic input pins , allow TSD to float.
When using TSD as an input, the two recommended
states are 0 (overrides logic input pins and forces all
off state) and float (allo ws s witch control via logic input
pins and the thermal shutdown mechanism is active).
This may require use of an open-collector buffer.
Test-In Input TSD State Timing
Break
Switches
1 and 2
Ring
Return
Switch 3
Ring
Access
Switch 4
Line
Access
Switches
5 and 6
0 V 5 V Floating Ringing - Open Closed Closed Open
0 V 0 V Floating
Make-
before-
break
SW4 waiting for next zero-current crossing
to turn off. Maximum time is one-half of ring-
ing. In this transition state, current that is
limited to the dc break switch current limit
value will be sourced from the ring node of
the SLIC.
Closed Open Closed Open
0 V 0 V Floating Idle/Talk Zero-cross current has occurred Closed Open Open Open
Test-In Input TSD State Timing
Break
Switches
1 and 2
Ring
Return
Switch 3
Ring
Access
Switch 4
Line
Access
Switches
5 and 6
0 V 5 V Floating Ringing - Open Closed Closed Open
5 V 5 V Floating All-off
Hold this state for at least 25 ms. SW4 wait-
ing for zero current to turn off. Open Open Closed Open
5 V 5 V Floating SW4 has opened. Open Open Open Open
0 V 0 V Floating Idle/Talk Release Break Switches Closed Open Open Open
CPC7584
7 www.clare.com Rev. 0.A
Preliminary
1.5 Protection Circuitry Electrical Spec ifications
1.6 CPC7584xA/B Truth Table
1.7 CPC7584xC Truth Table
Parameter Conditions Symbol Minimum Typical Maximum Unit
Parameters Related to the Diodes in the Diode Bridge
Voltage drop at continu-
ous current (50/60 Hz)
Apply ± dc current limit of break
switches
Forward
Voltage -2.13
V
Voltage drop at surge
current
Apply ± dynamic current limit of break
switches
Forward
Voltage -5-
Parameters Related to the Protection SCR
Surge current - - - - * A
Trigger current (+25° C) - ITRIG -60-mA
Hold current (+25° C) - IHOLD - 100 - mA
Trigger current (+85° C) - ITRIG -35-mA
Hold current (+85° C) - IHOLD 60 70 - mA
Gate trigger voltage Trigger current - VBAT -4 -VBAT -2 V
Reverse leakage cur-
rent VBAT -- -1.0µA
On-state voltage 0.5 A, t = 0.5 ms VON --3-V
2.0 A, t = 0.5 ms - - -5 - V
*Passes GR1089 and ITU-T K.20 with appropriate secondary protection in place.
State Ring Test-In TSD1
Tip
Break
Switch
Ring
Break
Switch
Ringing
Return
Switch
Ring
Switch
Tip Test-In
Switch
Ring Test-
In Switch
Idle/Talk 0 V 0 V
5 V/Floating
On On Off Off Off Off
Power Ring-
ing 5 V 0 V Off Off On On Off Off
Te s t - I n 0 V 5 V Off Off Off Off On On
All Off 5 V 5 V Off Off Off Off Off Off
All off Don’t care Don’t care 0 V Off Off Off Off Off Off
1If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.
State Ring Test-In TSD1
Tip
Break
Switch
Ring
Break
Switch
Ringing
Return
Switch
Ring
Switch
Tip Test-In
Switch
Ring Test-
In Switch
Idle/Talk 0 V 0 V
5 V/Floating
On On Off Off Off Off
Power Ring-
ing 5 V 0 V Off Off On On Off Off
Test Monitor 0 V 5 V On On Off Off On On
All Off 5 V 5 V Off Off Off Off Off Off
All off Don’t care Don’t care 0 V Off Off Off Off Off Off
1If TSD = 5V, thermal shutdown is disabled. If TSD is left floating, the thermal shutdown mechanism is enabled.
CPC7584
Rev. 0.A www.clare.com 8
Preliminary
2. Package Pinout 2.1 Pinout
1T
2 F
3T
4T
5T
6V
7T
8 D
TEST-IN
GND
BAT
LINE
RING
DD
SD
GND
R16
V15
R14
R13
R12
LATCH 11
IN 10
IN 9
TEST-IN
BAT
BAT
LINE
RING
RING
TEST-IN
Pin Name Description
1TTEST-IN Tip lead test input
2FGND Fault ground
3TBAT Connect to tip lead on SLIC side
4TLINE Connect to tip lead on the line side
5TRING Connect to ring generator return
6VDD +5 V supply
7TSD
Temperature shutdown pin. Can be used
as a logic-level input or output. See “Make-
Before-Break Operation (Ringing to Idle/
Talk Transition)” on page 6, “Break-
Before-Make Operation (Ringing to Idle/
Talk Transition)” on page 6, and
“CPC7584xA/B Truth Table” on page 7 for
details. As an output, TSD will read +5 V
when the device is in the operational mode
and 0 V in the thermal shutdown mode. To
disable thermal shutdown, tie this pin to +5
V (not recommended)
8DGND Digital ground
9INTEST-IN Logic-level switch control input
10 INRING Logic-level switch control input
11 LATCH Data latch control, active high, transparent
low
12 RACCESS Test access
13 RRING Connect to ring generator
14 RLINE Connect to ring lead on the line side
15 RBAT Connect to ring lead on the SLIC side
16 VTEST-IN Test-in access on ring
CPC7584
9 www.clare.com Rev. 0.A
Preliminary
3. Functional Description
3.1 Introduction
The CPC7584xA/B has four states:
•Idle/Talk. Line break switches SW1 and SW2
closed, ringing switches SW3 and SW4 open , and
test-in switches SW5 and SW6 open.
•Ringing. Line break s wit ches SW1 and SW2 open,
ringing swit ches SW3 and SW4 closed, and test-in
switches SW5 and SW6 open.
•Test-In. Line break s witches SW1 and SW2 open,
ringing s wit ches SW3 and SW4 open, and t est-in
switches SW5 and SW6 closed.
•All off . Line break switches SW1 and SW2 open,
ringing s wit ches SW3 and SW4 open, and loop test
switches SW5 and SW6 open.
In the CPC7584xC , the test-i n state is replaced with
the test monitor state , defined as: line break switches
SW1 and SW2 closed, Ringing switches SW3 and
SW4 open, and test-in switches SW5 and SW6
closed.
The CPC7584 offers break-before-make and make-
before-break s witching with simple logic- level input
control. Solid-state s witch construction means no
impulse noise is generated when s witching during ring
cadence or ring trip, eliminat ing the need for external
zero-cross switching circuitry. State-control is via
logic-le vel input so no additional driver circuitry is
required. The line break switches SW1 and SW2 are
linear switches that have exceptionally low RDSON
and e xcellent matching char acteristics . The ringing
access s witch SW4 has a breakdown voltage r ating of
greater than 480 V. This is sufficiently high, with
proper protection, to prevent breakdown in the pres-
ence of a transient fault condition (i.e., passing the
transient on to the ring gener ator).
Integr ated int o the CPC7584 is a diode bridge/SCR
clamping circuit, current limiting , and a th ermal shut-
down mechanism t o provide protection to the SLI C
de vice during a fault condition. P ositive and negative
surges are reduced by the current limiting circuitry and
steered to ground via diodes and t he integrated SCR.
Power-cross transients are also reduced b y the cur-
rent limiting and thermal shutdown circu its . Note t hat
only the CPC7584xA and CPC7584xC parts include
the integr ated protection SCR.
To protect the CPC7584 from an overvoltage fault
condition, use of a secondary protector is required.
The secondary protector must limit the v oltage seen at
the tip and ring terminals to a level below the maxi-
mum breakdown voltage of the s witches. To minimize
the stress on the solid-state cont acts, use of a fold-
back or crowbar type secondary protector is recom-
mended. With proper selection of the secondary
protector, a line card using the CPC7582BC will meet
all relevant ITU, LSSGR, FCC and UL protection
requirements.
The CPC7584 operates from a +5 V supply only. This
gives the device extremely lo w idle and active power
dissipation and allows use with virtually any range of
battery voltag e . A battery voltage is also used by the
CPC7584 as a ref erence for the integrated protection
circuit. In the event of a loss of bat tery vo ltage, the
CPC7584 enters the all-off st ate.
3.2 Switch Timing
The CPC7584 provides , when switching from the ring-
ing state to the idle/talk state, the ability to control the
release timing of the ringing access switches SW3
and SW4 relative to the state of the line break
s witches SW1 and SW2 using simple logic-lev el input.
This is referred to a mak e-before-break or break-
bef o re-make operation. When the line break switch
contacts (SW1 and SW2) are closed (or made) bef ore
the ringing access s witch contact s (SW3 and SW4)
are opened (or broken), this is referred to make-
bef o re-break operation. Break-before-make operation
occurs when the ringing access contacts (SW3 and
SW4) are opened (broken) before the line break
s wit ch contacts (SW1 and SW2) are closed (made) .
With the CPC7584, the make-before-break and break-
bef o re-make operations can easily be selected by
applying logic-le vel inputs to pins 9 and 10 (INRING
and INTEST-IN) of the device.
The logic sequences for either mode of operat ion are
given in “Make-Before-Break Operation (Ringing to
Idle/Talk Transition)” on page 6 and “Break-Before-
Make Operation (Ringing to Idle/Talk Transition)” on
page 6. Logic states and explanations are given in
“CPC7584xA/B Truth Table” on page 7.
Break-before-make oper at ion can also be achieved
using pin 7 (TSD) as an input. In “Break-Before- Mak e
Operation (Ringing to Idle/Talk Transition)” on page 6
lines 2 and 3, it is possible to induce the switches to
the all-off state by grounding pin 7 (TSD) instead o f
apply logic input to the pins. This has the effect of
ov erriding the logic inputs and f orcing the de vice to the
all-off state. Hold th is input state f or 25 ms. During this
hold period, toggle the inputs from the ringing state
CPC7584
Rev. 0.A www.clare.com 10
Preliminary
(10) to the idle/talk state (00). Aft er the 25 ms, release
pin 7 (TSD) to return the s wit ch contr ol to t he input
pins 9 and 10 and reset the device to the idle/talk
state.
Setting TSD to +5 V allows s witch control using the
logic pins 9 and 10. This setting, ho w ever, also dis-
ables t he thermal shutdown circuit and is theref ore not
recommended. When using logic controls via the input
pins 9 and 10, pin 7 (TSD) should be allowed to float.
As a result, the tw o recommend ed states when using
pin 7 (TSD) as a control ar e 0, which f orces the de vice
to the all-off state, or float, which allo ws logic inputs to
pins 9 and 10 to remain active. This may require the
use of an open-collector buff er.
3.3 Ring Access Switc h Zer o-Cross Current Turn Off
After the application of a logic input t o turn SW4 off,
the ring access switch is designed to dela y the change
in state until the next zero-crossing. Once on, the
switch requires a zero-current cross to turn off , and
therefore should not be used to switch a pure DC sig-
nal. The sw itch will remain in the on state no matter
what logic input until the next zero crossing. For
proper operation, pin 12 (RRING) should be connected
using proper impedance to a ring gener at or or other
A C source. These s witching characteristics will reduce
and possib ly eliminate o verall system impulse noise
normally associated with ringing access swit ches. The
attributes of ringing access switch SW4 may make it
possible t o eliminate the need for a zero-cross switch-
ing scheme. A minimum impedance of 300 Ω in series
with the ring generator is recommended.
3.4 Power Supplies
Both a +5 V supply and battery v oltage are connected
to the CPC7584. CPC7584 switch state control is
pow ered exclusively by the +5 V supply. As a result,
the CPC7584 e xhibits e xtremely low power dissipation
during both active and idle stat es.
The battery voltage is not used for switch control but
rather as a ref erence for the integrated secondary pro-
tection circuitry. The integrated SCR is designed to
trigger when pin 3 (TBAT) or pin 14 (RBAT) drops 2 to
4 V below the battery. This trigger prevents a fault
induced overvoltage event at the TBAT or RBAT nodes.
3.5 Battery Voltag e Mo n it or
The CPC7584 also uses the voltage reference to
monitor battery voltage. If battery voltage is lost, the
CPC7582BC immediately enters the all-off state. It
remains in this state until the bat tery volt age is
restored. The device also enters the all-off sta te if the
battery v oltag e rises abo ve –10 V and remains in the
all-off state until t he bat tery volt age drop s below
–15 V. This battery monitor feature dr aws a small cur-
rent from the battery (less than 1 mA typical) and will
add slightly to the device’s overall power dissipat ion.
3.6 Protection
3.6.1 Diode Bridge/SCR
The CPC7584 uses a combination of current limited
break s witches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient e v ents such as lightning. During a
positive transient condition, the fault current is con-
ducted through the diode bridge to ground. Voltage is
clamped to the diode drop above g ro und. During a
negative transient of 2 to 4 V more negat ive than the
battery, the SCR conducts and f aults are shunted to
ground via the SCR and diode bridge.
In order f or the SCR to crowbar or f oldback, the on
v oltage (see “Prot ection Circuitry Electrical Specifica-
tions” on page 7) of the SCR must be less negative
than the battery reference voltage. If the battery volt-
age is less negative the SCR on voltage, the SCR will
not crowbar, however it will conduct fault currents to
ground.
F or po w er induction or po w er-cross fault conditions,
the positive cycle of the transient is clamped to the
diode drop abov e ground and the f ault current directed
to ground. The negative cycle of the transient will
cause the SCR to conduct when the voltage exceeds
the battery reference voltage by two t o four volts,
steering the current to ground.
3.6.2 Current Limiting function
If a lightning strike transient occurs when the device in
the talk/idle state, the curre nt is passed along the line
to the integrated protection circuitry and limited by the
dynamic current limit response of break s witches SW1
and SW2. When a 1000V 10/1000 pulse (LSSGR
lightning) is applied to the line thoug h a pr operly
clamped e xternal protector, the current seen at pins 2
(TBAT) and pin 15 (RBAT) will be a pulse with a typical
magnitude of 2.5 A and a duration of less than 0.5 ms.
If a pow er-cross f ault occurs with the de vice in the talk/
idle state, the current is passed though break s witches
SW1 and SW2 on to the integ rated protection circuit
and is limited by the dynamic DC current limit
response of the tw o break switches. The DC current
limit, specified o ver temperature, is betw een 80 mA
CPC7584
11 www.clare.com Rev. 0.A
Preliminary
and 425 mA, and the circuitry has a negativ e tempera-
ture coefficient. As a res ult, if the device is subjected
to e xtended heating due to po wer cross f ault, the mea-
sured current at pin 2 (TBAT) and pin 15 (RBAT) will
decrease as the device temperature increases. If the
de vice te mper ature rises sufficiently, the temperature
shutdown mechanism will activate and the device will
default to the all-off state.
3.7 Temperature Shutdown
The thermal shutdown mechanism will activate when
the de vice temperature reaches a minimum of 110° C ,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 7
(TSD) will read 0 V. Normal output of TSD is +VDD.
If presented with a sh ort duration transient such as a
lightning e vent, the thermal shutdown feature will typi-
cally not activ ate . But in an e xt ended po wer-cross
transient, the de vice temper ature will rise and the ther-
mal shutdown will activate f or cing th e switches to the
all-off state . At this point the current measured at pin 3
(TBAT) and pin 14 (RBAT) will drop to z ero. Once the
de vice ent ers thermal shutdown it will remain in the
all-off state until the t emperature of the device drops
below the activation level of the thermal shutdown cir-
cuit. This will return the device to the state prior to
thermal shutdown. If the transient has not passed, cur-
rent will flow at th e value allowed b y the dyna mic DC
current limiting of the switches and heating will begin
again, reactiv ating the thermal shutdown mechanism.
This cycle of entering and exitin g the thermal shut-
down mode will con tinue as long as the fault condition
persists. If the magnitude of the fault condition is great
enough, the external secondary prot ector could a cti-
v ate and shu nt all cur rent to ground.
The thermal shutdown mechanism of the CPC7584
can be disable by applying +VDD to pin 7 (TSD).
3.8 External Protection Elements
The CPC7584 requires only one overvoltage second-
ary protector on the loop side of the device. The inte-
grated protection f eature described abov e negates the
need f or protection on the line side. The secondary
protector limits voltage transients to le vels that do not
e x ceed the br eakdown voltage or input-o utput isola-
tion barrier of the CPC7584. A foldback or crowbar
type protector is recommended to minimiz e st resses
on the de vice .
Consult Clare’s application note, AN-100, “Designing
Surge and Power Fault Protection Circuits for Solid
State Subscriber Line Interfaces” f or equations related
to the specifications of external secondary protectors,
fused resistors and PTCs.
3.9 Data Latch
The CPC7584 has an integr at ed data latch. The lat ch
operation is controlled by logic-le vel input pin 11
(LATCH). The data inp ut of the latch is pin 10 (IN RING)
and pin 9 (INTEST-IN) of the device while the output of
the data latch is an int ernal node used f o r st ate con-
trol. When LATCH control pin is at logic 0, the data
latch is transparent and data control signals f low
directly through to state contr ol. A chang e in input will
be reflected in a change is switch state. When LATCH
control pin is at logic 1, the dat a latch is active and a
change in input control will not affect s witch state . The
s wit ches will remain in t he posit ion they were in when
the LATCH changed from logic 0 to logic 1 and will not
respond to changes in input as long as the lat ch is at
logic 1. The TSD input is not t ied to the dat a latch.
Therefore, TSD is not affected by the LATCH input
and the TSD input will ov erride state control via pin 10
(INRING) and pin 9 (INTEST-IN) and the LATCH.
CPC7584
Rev. 0.A www.clare.com 12
Preliminary
4. Manufacturing Information
4.1 Mechanical D ime ns io n s
4.1.1 SOIC
4.1.2 MLP
7.40 MIN / 7.60 MAX
(.291 MIN / .299 MAX)
0.23 MIN / 0.32 MAX
(.0091 MIN / .0125 MAX)
1.27
(.050)
2.44 MIN / 2.64 MAX
(.096 MIN / .104 MAX)
0.51 MIN / 1.01 MAX
(.020 MIN / .040 MAX)
10.11 MIN / 10.51 MAX
(.398 MIN / .414 MAX)
0.36 MIN / 0.46 MAX
(.014 MIN / .018 MAX)
10.11 MIN / 10.31 MAX
(.398 MIN / .406 MAX)
16 Pin SOIC (JEDEC Package)
0.55
0.80
0.23
0.55
0.33
(+0.07, -0.05)
0.2
0.80
(±0.10)
0.02
(+0.05, -0)
Terminal Tip
INDEX AREA
SEATING
PLANE
EXPOSED PAD
TOP VIEW
SIDE VIEW
BOTTOM VIEW
16
12
7
6
4.0
(±0.05)
6.0
(±0.05)
0.55
(±0.1)
Dimensions in mm
CPC7584
13 www.clare.com Rev. 0.A
Preliminary
4.2 Printed-Circuit Board Layout
4.2.1 SOIC
4.2.2 MLP
4.3 Tape and Reel Packaging
4.3.1 SOIC
4.4 Soldering
4.4.1 Moisture Reflow Sensitivity
Clare has characterized the moist ure reflow sensitivity
of LCAS products using IPC/JEDEC standar d J-STD-
020A. Moisture uptake from atmospheric humidity
occurs by diff usion. During the solder reflo w process ,
in which the component is attached to the PCB, the
whole body of the compone nt is exposed to high pro-
cess temperatures. The combination of moisture
uptake and high r eflow soldering temperatures may
PC Board Pattern
(Top View)
1.193
(.047)
9.728 ± .051
(.383 ± .002)
.787
(.031)
1.270
(.050)
0.65
6.1
0.38
0.65
0.38
0.47
0.66
5.75
6.13
0.75 on center
5.35 on center
Detail A
Detail A
All dimensions in mm
Not drawn to scale
B0
16.00
7.50
R=.50
2.30
K0
K1
1.30
6.80
3.00
A0
2.00
4.00
2.00
1.50
12.00
6.50
2.70
A0 =
B0 =
K0 =
K1 =
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS AND CARRY TOLERANCES OF EIA
STANDARD 481-2. 2. THE TAPE COMPLIES WITH ALL "NOTES" FOR CONSTANT DIMENSIONS
LISTED ON PAGE 5 OF EIA-481-2.
6.5 mm
10.3 mm
2.3 mm
2.7 mm
Preliminary
lead to moisture induced delamination and cr acking of
the component. To prevent this, this compon ent must
be handled in accordance with IPC/JEDEC standard
J-STD-020A per the labeled moisture sensitivity level
(MSL), level 1 for the SOIC package , and level 2 for
the MLP pac kage.
4.4.2 Reflow Profile
The maximum ramp rates, dwell t imes, and tempera-
tures of the assemb ly reflo w profile should n ot e xceed
those specified in IPC/JEDEC standard J-STD-020A,
which were used to determine the moisture sensitivity
le vel of this component.
4.5 Washi ng
Clare does not recommend ultrasonic cleaning of
LCAS parts.
For additional information please visit www.clare.com
Clare, Inc. makes no representations or warr anties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make
changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses or indemnity are expressed or implied. Except as set
forth in Clare’s Standard Terms and Conditions of Sale, Clare, Inc. assumes no liability whatsoever, and disclaims any express or implied warranty relating to its
products, including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right.
The products described in this document are not designed, intended, authorized, or warranted for use as components in systems intended for surgical impl ant into
the body, or in other applications intended to support or sustain life, or where malfunction of Clare’s product may result in direct physical harm, injury, or death to a
person or severe property or environmental damage. Clare, Inc. reserves the right to discontinue or make changes to its products at any time without notice.
Specifications: DS-CPC7584-R0.A
© Copyright 2002 , Clare, Inc.
All rights reserved. Printed in USA.
5/6/2002
