VN920DSPTRE - STMICROELECTRONICS

1/19

September 2013

VN920DSP

HIGH SIDE DRIVER

Table 1. General Features

■ CMOS COMPATIBLE INPUT

■ ON STA TE OP EN LOAD D ETE CT ION

■ OFF STATE OPEN LOAD DETECTION

■ SHOR TED L OAD PRO TECTIO N

■ UNDERVOLTAGE AND OVERVOLTAGE

SHUTDOWN

■ PR OT ECTIO N AGAINST LOSS OF GROUND

■ VERY LOW STAND-BY CURRENT

■ REVERSE BATTERY PROTECTION (*)

DESCRIPTION

The VN920DSP is a monolithic device made by

using STMicroelectronics VIPower M0-3

Technology, intended for driving any kind of load

with one side connect ed to ground.

Act ive V CC pin voltage clamp protects the device

against low energy spikes (see ISO7637 transient

compatibility table).

Figure 1. Package

Active current limitation combined with thermal

shutdown and automatic restart protect the device

against ov erload.

The device detect s open load condition both is on

and off st ate. Output shorted to VCC is detected in

the off state. Device automatically turns of f in case

of ground pin disc onnection.

Table 2. Order Codes

Note: (* ) S ee application schematic at page 9

Type RDS(on) Iout VCC

VN920DSP 16 mΩ 25 A 36 V

PowerSO-10

Package Tube Tape and Reel

PowerSO-10™VN920DSP VN920DSP13TR

DocID10683 Rev 3

VN920DSP

2/19

Figu re 2. Blo ck D ia gra m

Table 3. Absolute Maximum Ratings

Symbol Parameter Value Unit

VCC DC Supply Voltage 41 V

- VCC Reverse DC Supply Voltage - 0.3 V

- IGND DC Reverse Ground Pin Current - 200 mA

IOUT DC Output Current Internally Limited A

- IOUT Reverse DC Output Current - 25 A

IIN DC Input Current +/- 10 mA

ISTAT DC Status Current +/- 10 mA

VESD

Electros tatic Disch arge (Huma n Body Model: R=1.5 KΩ; C=100pF)

- INPUT

- CURRENT SENSE

- OUTPUT

- VCC

4000

5000

EMAX Maximum Switching Energy

(L=0.25mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IL=45A) 362 mJ

Ptot Power Dissipation TC=25°C 96.1 W

TjJunction Operating Temperature Internally Limited °C

TcCase Operating Temperature - 40 to 150 °C

Tstg Storage Temperature - 55 to 150 °C

UNDERVOLTAGE

OVERTEMPERATURE

VCC

GND

INPUT OUTPUT

OVERVOLTAGE

CURRENT LIMITER

LOGIC

DRIVER

Power CLAMP

STATUS

VCC

CLAMP

ON STATE OPENLOAD

OFF STATE OPENLOAD

AND OUTPUT SHORTED TO VCC

DETECTION

3/19

VN920DSP

Figu re 3. Con f ig urat i on Diagram (Top View) & Su gg es te d Conne ct ions for U nu s ed an d N.C. Pins

Figure 4. Current and Vol tage Convention s

Table 4. Thermal Data

Note: (1) When m ounted on a stan dard sin gl e-sided F R-4 board wit h 0. 5cm 2 of Cu (at least 35µm thick).

Note: (2) W hen moun ted on a st andard si ngle- sided FR -4 board wi th 6 cm2 of Cu (at le ast 35µm thick).

Symbol Parameter Value Unit

Rthj-case Thermal Resistance Junction-case Max 1.3 °C/W

Rthj-amb Thermal Resistance Junction-ambient Max 51.3 (1) 37 (2) °C/W

OUTPUT

N.C.

OUTPUT

GROUND

INPUT

STATUS

N.C.

Connection / Pin St atus N.C. Output Input

Floating X X X X

T o Ground X Th rough 1 0KΩ resistor

IGND

VCC VCC

VSENSE

OUTPUT IOUT

CURRENT SENSE ISENSE

INPUT

IIN

VIN

VOUT

GND

VN920DSP

4/19

ELECTRICAL CHARACTERISTICS

(8V<VCC<36V; -40°C<Tj<150°C unless otherw ise specified)

Table 5. Po wer

Table 6. Swit ch ing (VCC=13V)

Table 7. Input Pin

Symbol Parameter Test Conditions Min Typ Max Unit

VCC Operating Supply Voltage 5.5 13 36 V

VUSD Undervoltage Shut-down 3 4 5.5 V

VUSDhyst Undervoltage Shut-down

hysteresis 0.5 V

VOV Overvoltage Shut-down 36 V

RON On State Resistance IOUT=10A; Tj=25°C

IOUT=10A

IOUT=3A; VCC=6V

mΩ

ISSupply Current

Off State; VCC=13V; VIN=VOUT=0V

Off State; VCC= 13V; VIN=VOUT=0V;

Tj=25°C

On State; VCC=13V; VIN=5V; IOUT=0A

µA

IL(off1) Off State Output Current VIN=VOUT=0V 0 50 µA

IL(off2) Off State Output Current VIN=0V; VOUT=3.5V -75 0 µA

IL(off3) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =125°C 5 µA

IL(off4) Off State Output Current VIN=VOUT=0V; VCC=13V; Tj =25°C 3 µA

Symbol Parameter Test Conditions Min Typ Max Unit

td(on) Turn-on Delay Time RL=1.3Ω 50 µs

td(off) Turn-off Delay Time RL=1.3Ω 50 µs

dVOUT/

dt(on) Turn-on Voltage Slope RL=1.3Ω See

relative

diagram V/µs

dVOUT/

dt(off) Turn-off Voltage Slope RL=1.3Ω See

relative

diagram V/µs

Symbo l P aram eter Test Conditions M in Typ Max Unit

VIL Input Low Level 1.25 V

IIL Low Level Input Current VIN=1.25V 1 µA

VIH Input High Level 3.25 V

IIH High Level Input Current VIN=3.25V 10 µA

VI(hyst) Input Hysteresis Voltage 0.5 V

VICL Input Clamp Voltage IIN=1mA

IIN=-1mA 6 6.8

-0.7 8V

5/19

VN920DSP

ELECTRICAL CHARACTERISTICS (conti nued)

Table 8. VCC - Output Diode

Table 9. Status Pin

Table 10. Pro tecti ons (see note 1)

Note: 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be

used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration

and n um ber of ac tivation cycles .

Table 11. Open load Detection

Symbol Paramete r Test Conditions Min Typ Ma x Unit

VFForward on Voltage -IOUT=5A; Tj=150°C 0.6 V

Symbol Parameter Test Conditions Min Typ Max Unit

VSTAT Status Low Output Voltage ISTAT=1.6mA 0.5 V

ILSTAT Status Leakage Current Normal Operation VSTAT=5V 10 µA

CSTAT Status Pin Input

Capacitance Normal Operation VSTAT=5V 100 pF

VSCL Status Clamp Voltage ISTAT=1mA

ISTAT=-1mA 66.8

-0.7 8V

Symbol Parameter Test Conditions Min Typ Max Unit

TTSD Shut-down Temperature 150 175 200 °C

TRReset Temperature 135 °C

Thyst Thermal Hysteresis 7 15 °C

tSDL Status delay in overload

condition Tj>TTSD 20 µs

Ilim Current limitation 5.5V<VCC<36V 30 45 75

75 A

Vdemag Turn-off Output Clamp

Voltage IOUT=2A; VIN=0V; L=6mH VCC-41 VCC-48 VCC-55 V

Symbol Parameter Test Conditions Min Typ Max Unit

IOL Openload ON State

Detection Threshold VIN=5V 300 500 700 mA

tDOL(on) Openload ON State

Detection Delay IOUT=0A 200 µs

VOL

Openload OFF State

Voltage Detection

Threshold VIN=0V 1.5 2.5 3.5 V

tDOL(off) Openload Detection Delay

at Turn Off 1000 µs

VN920DSP

6/19

Figure 5.

Figure 6. Switching time Wavefor ms

STAT

DOL(off)

OPEN LOAD STATUS TIMING

(with external pull-up) OVERTEMP STA TUS TIMING

OUT

< I

OUT

> V

DOL(on)

> T

TSD

STAT

SDL

VOUT

VIN

80%

10%

dVOUT/dt(on)

td(off)

90%

dVOUT/dt(off)

td(on)

7/19

VN920DSP

Table 12. Truth Table

Table 13. Electrical Transient Requiremen ts On V CC Pin

CONDITIONS INPUT OUTPUT STATUS

Normal Opera tion L

Current Limita tion L

(Tj < TTSD) H

(Tj > TTSD) L

Overtemperature L

Undervoltage L

Overvoltage L

Output Voltage > VOL L

Output Current < IOL L

ISO T/R 7637/1

Test Pulse TEST LEVELS

I II III IV Delays and

Impedance

1 -25 V -50 V -75 V -100 V 2 ms 10 Ω

2 +25 V +50 V +75 V +100 V 0.2 ms 10 Ω

3a -25 V -50 V -100 V -150 V 0.1 µs 50 Ω

3b +25 V +50 V +75 V +100 V 0.1 µs 50 Ω

4 -4 V -5 V -6 V -7 V 100 ms, 0.01 Ω

5 +26.5 V +46.5 V +66.5 V +86.5 V 400 ms, 2 Ω

ISO T/R 7637/1

Test Pulse TEST LEVELS RESULTS

I II III IV

1CCCC

2CCCC

3aCCCC

3bCCCC

4CCCC

5C E E E

CLASS CONTENTS

C All functions of the device are performed as designed after exposure to disturbance.

E One or more functions of the device is not performed as designed after exposure to disturbance

and cannot be returned to proper operation without replacing the device.

VN920DSP

8/19

Figure 7. Waveforms

OPEN LOAD without external pull-up

STATUS

INPUT NOR MAL OPER ATI ON

UNDERVOLTAGE

VCC VUSD

VUSDhyst

INPUT

OVERVOLTAGE

VCC

VCC>VOV

STATUS

INPUT

STATUS

INPUT

STATUS

INPUT

OPEN LOAD with external pull-up

undefined

LOAD VOLTAGE

VCC<VOV

LOAD VOLTA GE

LOAD VOLTAGE

OVERTEMPERATURE

INPUT

STATUS

TTSD

LOAD CURRENT

VOUT>VOL

VOL

9/19

VN920DSP

Figure 8. Application Schematic

GND PROTECTION NETWORK AGAINST

REVERSE BATTERY

Solution 1 : Resistor in the gr ound line (RGND only). T his

can be used with any type of load.

The following is an indication on how to dimension the

RGND resistor.

1) RGND ≤ 600mV / (IS(on)max).

2) RGND ≥ (−VCC) / (-IGND)

where -IGND is the DC reverse ground pin current and can

be found in the absolute maximum rating section of the

device’s datasheet.

Power Dissipation in RGND (w hen VCC< 0: durin g rever se

battery situations) is:

PD= (-VCC)2/RGND

This resistor can be shared amongst several different

HSD. Please note that the value of this resistor should be

calculated with fo rmula (1) where IS(on)max becom es the

sum of the maximum on-state currents of the different

devices.

Please note that if the microprocessor ground is not

common with the device ground then the RGND will

produce a shif t (IS(on)max * RGND) in the input thr esholds

and the status output values. This shift will vary

depending on many devices are ON in the case of several

high side drivers sharing the same RGND.

If the calculated power dissipation leads to a large

resistor or several devices have to share the same

resistor then the ST suggests to utilize Solution 2 (see

below).

Solution 2: A diode (DGND) in the ground line.

A resistor (RGND=1kΩ) should be inserted in parallel to

DGND if the device will be driving an inductive load.

This small signal diode can be safely shared amongst

several diffe rent HSD. Also i n this case, the pr esence of

the ground network will produce a shift (

600mV) in the

input threshold and the status output values if the

microprocessor ground is not common with the device

ground. This shift will not vary if more than one HSD

shares the same diode/resistor network.

Series resistor in INPUT line is also required to prevent

that, during battery voltage transient, the current exceeds

the Absolute Maximum Rating.

Safest c onfiguration for unused INPUT pin is to leave it

unconnected, while unused SENSE pin has to be

connected to Ground pin.

LOAD DUMP PROTECTION

Dld is necessary (Voltage Transient Suppressor) if the

load dump peak voltage exceeds VCC max DC rating.

The same applies if the device will be subject to

transients on the V CC line that are greater than the ones

shown in the ISO T/R 7637/1 table.

µC I/Os PROTECTION:

If a ground protection network is used and negative

transient are present on the VCC line, the control pins will

be pulled negative. ST suggests to insert a resistor (Rprot)

in line to prevent the µC I/Os pins to latch-up.

The value of these resistors is a compromise between the

leakage current of µC and the current required by the

HSD I/Os (Input levels compatibility) with the latch-up

limit of µC I/Os.

-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHµC-VIH-VGND) / IIHmax

Calculation example:

For VCCpeak= - 100V and Ilatchup ≥ 20mA; VOHµC ≥ 4.5V

5kΩ ≤ Rprot ≤ 65kΩ.

Recommen ded Rpr ot value is 10kΩ.

GND

OUTPUT

GND

+5V

prot

GND

STATUS

INPUT

+5V

prot

VN920DSP

10/19

Figure 9. Off State Output Current Figure 10. High Level Input Current

Figure 11. Input Low Level

Figure 12. Input Clamp Voltage

Figure 13. Input High Level

Figure 14. Input Hysteresis Voltage

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

IL(off1) (uA)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0.5

1.5

2.5

3.5

4.5

Iih (uA)

Vin=3.25V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

1.2

1.4

1.6

1.8

2.2

2.4

2.6

Vil (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

6.2

6.4

6.6

6.8

7.2

7.4

7.6

7.8

Vicl (V)

Iin=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

2.2

2.4

2.6

2.8

3.2

3.4

3.6

Vih (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

1.5

Vhyst (V)

11/19

VN920DSP

Figure 15. Overvoltage Shutdown

Figure 16. Turn-on Voltage Slope

Figure 17. On State Resistance Vs Tcase

Figure 18. I LIM Vs Tcase

Figure 19. Turn-off Voltage Slope

Figure 20. On State Resistance Vs VCC

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

Vov (V)

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

250

300

350

400

450

500

550

600

650

700

dVout/dt(on) (V/ms)

Vcc=13V

Rl=1.3Ohm

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

Ron (mOhm)

Iout=10A

Vcc= 8 V; 36 V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

100

Ilim (A)

Vcc=13V

-50 -25 0 25 50 75 100 125 150 175

Tc (°C)

100

150

200

250

300

350

400

450

500

550

dVout/dt(off) (V/ms)

Vcc=13V

Rl=1.3Ohm

5 10152025303540

Vcc (V)

Ron (mOhm)

Tc= - 40ºC

Tc= 25ºC

Tc= 150ºC

VN920DSP

12/19

Figure 21. Status Leakage Current

Figure 22. Status Cl amp Voltage

Figu re 23. S t at us Low Outp ut V ol ta ge

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

0.005

0.01

0.015

0.02

0.025

0.03

0.035

0.04

0.045

0.05

Ilstat(µA)

Vstat=5V

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

6.2

6.4

6.6

6.8

7.2

7.4

7.6

7.8

Vscl (V)

Istat=1mA

-50 -25 0 25 50 75 100 125 150 175

Tc (ºC)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Vstat (V)

Istat=1.6mA

13/19

VN920DSP

Figure 24. Maxi m um turn off curren t versus load i nductance

A = Single Pulse at TJstart=150ºC

B= Repet iti ve puls e at TJstart=100ºC

C= Repetitive Pulse at TJstart=125ºC

Conditions:

VCC=13.5V

Values are generated with RL=0Ω

In case of repetitive pulses , Tjstart (at beginning of

each demagnetization) of every pulse must not

exceed the temperature specified above for

curves B and C.

100

0.1 1 10 100

L(mH)

ILMA X (A )

VIN, IL

Demagnetization Demagnetization Demagnetization

VN920DSP

14/19

PowerS O-10™ Thermal Data

Figu re 25. P ow e rS O-1 0™ PC Boa rd

Figure 26. Rthj-amb Vs PCB copper area i n open box free air condition

Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm,

Cu thickness=35µm, Copper areas: from minimum pad lay-out to 8cm2).

0246810

PCB Cu heatsink area (cm^2)

RTHj_amb (°C/W)

Tj-Tamb=50°C

15/19

VN920DSP

Figure 27. P ow erS O-10 Th ermal Imp edance Jun ction Am bient Singl e Pulse

Figu re 28 . Th erm al fittin g m od e l of a double

channel HSD in PowerSO -10 Pulse calculation formula

Table 14. Thermal Parameter

0.01

0.1

100

0.0001 0.001 0.01 0.1 1 10 100 1000

Tim e ( s)

ZTH ( ° C/ W )

Footprint

6 cm 2

T_amb

R1 R2

Area/island (cm2) Footprint 6

R1 (°C/W) 0.02

R2 (°C/W) 0.1

R3( °C/W) 0.2

R4 (°C/W) 0.8

R5 (°C/W) 12

R6 (°C/W) 37 22

C1 (W.s/°C) 0.0015

C2 (W.s/°C) 7.00E-03

C3 (W.s/°C) 0.015

C4 (W.s/°C) 0.3

C5 (W.s/°C) 0.75

C6 (W.s/°C) 3 5

ZTHδRTH δZTHtp 1δ–()+⋅=

where δtpT⁄=

VN920DSP

16/19

PACKAGE MECHANICAL

Table 15. PowerSO-10™ Mechanical Data

No te : (* ) M uar only POA P0 13P

Figure 29. PowerSO-10™ Package Dimensions

Symbol millimeters

Min Typ Max

A 3.35 3.65

A (*) 3.4 3.6

A1 0.00 0.10

B 0.40 0.60

B (*) 0.3 7 0.53

C 0.35 0.55

C (*) 0.23 0.32

D 9.40 9.60

D1 7.40 7.60

E 9.30 9.50

E2 7.20 7.60

E2 (*) 7.30 7.50

E4 5.90 6.10

E4 (*) 5.90 6.30

e 1.27

F 1.25 1.35

F (*) 1.20 1.40

H 13.80 14.40

H (*) 13.85 14.35

h 0.50

L 1.20 1.80

L (*) 0.8 0 1.10

a0º 8º

α (*) 2º 8º

DETAIL "A"

PLANE

SEATING

= =

0.10 A

DET AIL "A"

SEATING

PL A NE

0.25

P095A

17/19

VN920DSP

Figure 30. PowerSO-10™ Suggested Pad Layout And Tube Shipment (no suffix)

Figure 31. Tape And Reel Shipment (suffix “13TR”)

6.30

10.8 - 11

14 .6 - 14 .9

9.5

51.27

0.67 - 0.73

0.54 - 0.6

MUARCASABLANCA

All d imensions are in mm.

Base Q. ty Bulk Q.t y Tube length (± 0.5) A B C (± 0.1)

Casablanca 50 1000 532 10.4 16.4 0.8

Muar 50 1000 532 4.9 17.2 0.8

REEL DIMENSIONS

All dimensions are in mm.

Base Q.ty 600

Bulk Q.ty 600

A (max) 330

B (min) 1.5

C (± 0.2) 13

F20.2

G (+ 2 / -0) 24.4

N (min) 60

T (max) 30.4

TAPE DIMENSIONS

According to Electronic Industries Association

(EIA) Standard 481 rev. A, Feb. 1986

All dimensions are in mm.

Tape width W 24

Tape Hole Spacing P0 (± 0.1) 4

Component Spacing P 24

Hole Diameter D (± 0.1/-0) 1.5

Hole Diameter D1 (min) 1.5

Hole Position F (± 0.05) 11.5

Compartment Depth K (max) 6.5

Hole Spacing P1 (± 0.1) 2

Top

cover

tape

End

Start

No componentsNo co m ponents Components

500m m min

500mm min

Em pt y com ponents pockets

saled with cover tape.

User direction of feed

VN920DSP

18/19

RE VISION HISTORY

Date Revision Description of Changes

Sep. 2004 1 - First Issue.

Oct. 20042- Minor text change.

24-Sep-2013 3- Updated Disclaimer

19/19

VN920DSP

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