Advanced Battery Management PMIC with Inductive Boost LED and Three LDO Regulators ADP5350 Data Sheet FEATURES TYPICAL APPLICATION CIRCUIT VBUSB C1 2.2F CFL1 ADP5350 SW1A 3MHz BUCK PGND1A ISOS C11 2.2F SCL INT PGOOD I2C AND GPIOs CHARGE CONTROL AND FUEL GAUGE ISOB BSNS Li-Ion THR BATOK VISOS C4 + 10F - RNTC VIN4 L2 C9 4.7F VISOS C3 10F PGND1B C2 4.7F CFL2 SDA L1 1.5H SW1B 4.7H SW4 PGND4 VOUT4 HIGH VOLTAGE BOOST FB4 150mA LDO D1 LED1 LED2 D2 LED3 LED4 D3 LED5 LED6 C10 4.7F VOUT2 C7 1F VOUT3 C8 1F (OR LOAD SWITCH) 150mA LDO (OR LOAD SWITCH) 150mA LDO D4 D5 (OR LOAD SWITCH) Rechargeable Li-Ion and Li-Ion polymer battery-powered devices Portable consumer devices Portable medical devices Portable instrumentation devices Wearable devices GENERAL DESCRIPTION The ADP5350, a power management IC (PMIC), combines one high performance buck regulator for single Li-Ion/Li-Ion polymer battery charging, a fuel gauge, a highly programmable boost regulator for LED backlight illumination, and three 150 mA LDO regulators. The ADP5350 operates in trickle charge mode and in constant current (CC) and constant voltage (CV) fast charge mode. It features an internal field effect transistor (FET) that permits battery isolation on the system power side. The ADP5350 fuel gauge is a space-saving and low current consuming solution. It is optimal for rechargeable Li-Ion batterypowered devices, and features a voltage-based, battery SOC measurement function. 14797-001 VOUT1 C6 1F PROGRAMMABLE LED DRIVER VIN123 C5 2.2F AGND APPLICATIONS Rev. B VBUSA USB 5V TO MCU Switching mode USB battery charger High accuracy and programmable charge terminal voltage and charge current 3 MHz buck for high efficiency and small footprint Tolerant input voltage from -0.5 V to +20 V (USB VVBUSx) Power path control allows system to operate with dead or missing battery Compliant with JEITA charge temperature specification Voltage-based state of charge (SOC) calculation algorithm Extra low quiescent current in sleep mode Battery impedance chemistry (Li-Ion) compensation Battery temperature compensation No need for external sense resistor Boost regulator with 5-channel LED driver Support up to 4 LED in series or in parallel 5 independent programmable LED current sinks 64 programmable LED current levels (up to 20 mA) Programmable on and off timer for LED blinking Adaptive headroom control to maximize the efficiency Three 150 mA linear LDO regulators Ultralow IQ with zero load at 1 A typical for LDO1 Optional load-switch full turn-on mode Full I2C programmability with dedicated interrupt pin Figure 1. The ADP5350 boost regulator operates at a 1.5 MHz switching frequency. It can be operated as a constant voltage regulator or as a supplemental constant current regulator for multiple LED backlight drivers. The ADP5350 LED drivers can support a wide range of LED backlight configurations, either multiple LEDs in parallel or in series. The ADP5350 low dropout (LDO) regulators are optimized to operate at low shutdown current and quiescent current to extend battery life. The device also operates as a load switch that can be fully turned off or on. The I2C-compatible interface enables the programmability of all parameters, including status bit readback for operation monitoring and safety control. The ADP5350 operates over the -40C to +125C junction temperature range and is available in a 32-lead, 5 mm x 5 mm LFCSP package and a 32-ball, 3 mm x 3 mm WLCSP package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2017-2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5350 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Battery Isolation FET ................................................................. 23 Applications ....................................................................................... 1 Battery Detection ....................................................................... 23 General Description ......................................................................... 1 Battery Temperature .................................................................. 24 Typical Application Circuit ............................................................. 1 Battery Charger Operational Flowchart .................................. 26 Revision History ............................................................................... 2 Battery Voltage-Based Fuel Gauge ........................................... 26 Detailed Functional Block Diagram .............................................. 3 Flowchart of SOC Calculation .................................................. 28 Specifications..................................................................................... 4 Boost and White LED Drivers .................................................. 29 Battery Charger Specifications ................................................... 4 Linear Low Dropout (LDO) Regulators .................................. 33 Battery Fuel Gauge Specifications .............................................. 6 Thermal Management ............................................................... 34 Boost and LED Driver Specifications ........................................ 7 I C Interface .................................................................................... 35 LDO Specifications ...................................................................... 8 I2C Addresses .............................................................................. 35 Recommended Input and Output Capacitance and Inductance Specifications .......................................................... 10 SDA and SCL Pins ...................................................................... 35 I2C-Compatible Interface Timing Specifications ................... 11 Interrupts ..................................................................................... 36 Absolute Maximum Ratings .......................................................... 12 Control Register Map ..................................................................... 37 Thermal Resistance .................................................................... 12 Register Bit Descriptions ........................................................... 39 ESD Caution ................................................................................ 12 Applications Information .............................................................. 58 Pin Configuration and Function Descriptions ........................... 13 External Components ................................................................ 58 Typical Performance Characteristics ........................................... 15 PCB Layout Guidelines.............................................................. 60 Typical Waveforms ..................................................................... 19 Typical Application Circuits ..................................................... 61 Theory of Operation ...................................................................... 21 Factory-Programmable Options .................................................. 62 Battery Charger Overview......................................................... 21 Outline Dimensions ....................................................................... 63 Charger Modes............................................................................ 22 Ordering Guide .......................................................................... 63 2 Default Reset ............................................................................... 35 REVISION HISTORY 5/2018--Rev. A to Rev. B Changes to Table 1 ............................................................................ 4 Changes to Table 3 ............................................................................ 7 Changes to Table 4 ............................................................................ 8 Change to Battery Pack Thermistor Input Section .................... 24 Change to Shutdown Current, Table 15 ...................................... 27 Changes to Figure 50 ...................................................................... 31 Change to Address 0x0C, Table 18 ............................................... 37 Change to Bits[1:0], Table 23 ........................................................ 41 Change to Bit 4 Mnemonic, Table 70 ........................................... 53 Updated Outline Dimensions ....................................................... 63 Changes to Table 1.............................................................................3 Changes to Table 4.............................................................................8 Changes to Figure 4 Caption and Table 9 Title .......................... 13 Added Figure 5; Renumbered Sequentially ................................ 14 Added Table 10; Renumbered Sequentially ................................ 14 Change to Figure 15 Caption ........................................................ 16 Change to Figure 23 Caption ........................................................ 17 Change to Figure 24 Caption ........................................................ 18 Changes to Figure 59...................................................................... 60 Updated Outline Dimensions ....................................................... 61 Changes to Ordering Guide .......................................................... 61 11/2017--Rev. 0 to Rev. A Added CB-32-1 .............................................................. Throughout Change to General Description ...................................................... 1 2/2017--Revision 0: Initial Version Rev. B | Page 2 of 63 Data Sheet ADP5350 DETAILED FUNCTIONAL BLOCK DIAGRAM CFL1 IND_PEAK_INT ADP5350 PEAK CURRENT DETECTION HIGH VOLTAGE BLOCKING FET SW1B SW1A VBUSA VBUSB PGND1A CMP ILIM BUCK CONTROL PGND1B ISOS ISOLATION FET CFL1 HIGH VOLTAGE FET 5.4V TRICKLE SOURCE ISOB 3.9V SCL SDA INT PGOOD CHARGE CONTROL BATTERY DETECTION SINK I2C INTERFACE, FUEL GAUGE ALGORITHM AND LOGIC CONTROL BSNS 12-BIT ADC ISOB ISOS BATOK VIN4 FB4 VOUT4 SW4 25kHz OSC NTC CURRENT CONTROL THR 0.5V D1 HV BOOST D2 PGND4 VIN123 LDO1 CONTROL D3 LED CONTROL D4 VOUT1 LDO2 CONTROL D5 VOUT2 REFERENCE BUFFER VOUT3 CFL2 AGND Figure 2. Detailed Functional Block Diagram Rev. B | Page 3 of 63 14797-022 LDO3 CONTROL ADP5350 Data Sheet SPECIFICATIONS BATTERY CHARGER SPECIFICATIONS -40C < TJ < 125C, VVBUSx = 5.0 V, RNTC = 47 k, VVIN4 = VVIN123 = VISOS= 3.6 V, C1 = 2.2 F, C2 = 4.7 F, C3 = 10 F, C4 = 10 F, C11 = 2.2 F, L1 = 1.5 H, all registers are at default values, unless otherwise noted. Table 1. Parameter GENERAL PARAMETERS Undervoltage Lockout Symbol VUVLO Input Current Limit ILIM Operation Current IQ Shutdown Current CHARGING PARAMETERS Fast Charge Current, Constant Current Mode Fast Charge Current Accuracy ISTDN ICHG Trickle Charge Current 2 Weak Charge Current Dead Battery, Trickle to Weak Charge Threshold2 Weak Battery Weak to Fast Charge Threshold2 Weak Battery Threshold Hysteresis1 Battery Termination Voltage2 ITRK_DEAD ICHG_WEAK VTRK_DEAD Battery Overvoltage Threshold VBAT_OV Charge Complete Current2 Recharge Voltage Differential2 Battery Node Short Threshold Voltage2 CHARGER DC-TO-DC REGULATOR Switching Frequency Maximum Duty Cycle 3 Peak Inductor Current Regulated System Voltage IEND VRCH VBAT_SHR Test Conditions/Comments TJ = 0C to 85C On BSNS, rising threshold, no VVBUSx On BSNS, falling threshold, no VVBUSx Set ILIM[3:0] = 100 mA Set ILIM[3:0] = 500 mA All enabled, no load, from VBUSx pin Only fuel gauge enabled (active), from ISOB, no VVBUSx Only fuel gauge enabled (sleep), from ISOB, no VVBUSx 1 Only boost regulator enabled, all LEDs enabled, no LED current, from ISOB, no VVBUS Only LDO1 enabled, from ISOB, no VVBUSx Only LDO2 enabled, from ISOB, no VVBUSx Only LDO3 enabled, from ISOB, no VVBUSx All disabled, from ISOB and BSNS, no VVBUSx Programmable via I2C, battery voltage > VTRK_DEAD ICHG = 200 mA TJ = 25C, ICHG = 200 mA Min 2.2 Typ Max Unit 2.45 2.3 92 475 4 160 2.6 V V mA mA mA A 100 500 6 230 4 2 2.6 mA 0.8 4 A 160 230 A 160 230 A 0.2 2.8 A 650 mA 220 +2.5 25 mA % mA mA V 25 180 -2.5 16 A 200 20 ICHG + ITRK_DEAD 2.5 When VTRK_DEAD < VBSNS < VWEAK On BSNS 2.4 VWEAK VWEAK On BSNS 2.9 3.0 90 3.15 V mV VTRM On BSNS, TJ = 0C to 85C On BSNS, TJ = 25C Relative to CFL1 voltage, BSNS rising, VCLF1 = 4.0 V VBSNS = VTRM, TJ = 0C to 85C Relative to VTRM, BSNS falling 4.158 -0.3 VCFL1 - 0.15 4.200 4.242 +0.3 V % V 20 35 260 2.4 50 mA mV V fSW_CHG DMAX IL1_PK VISOS_TRK 2.3 2.7 1500 VBSNS < VTRK_DEAD, trickle charge mode Rev. B | Page 4 of 63 3 96 1750 VTRM + 0.1 2.62 2.52 3.3 2200 MHz % mA V Data Sheet Parameter DC to DC Power PMOS On Resistance NMOS On Resistance SW1x Pin Leakage Current BATTERY ISOLATION FIELD EFFECT TRANSISTOR (FET) LFCSP Package WLCSP Package ADP5350 Symbol RDSON_P RDSON_N ISW1x VISOS_FC Battery Supplementary Threshold HIGH VOLTAGE BLOCKING FET VBUSx Input High Voltage Blocking FET On Resistance Current, Suspend Mode Input Voltage Power-Good Threshold Rising Falling Overvoltage Threshold Overvoltage Threshold Hysteresis THERMAL CONTROL Thermal Early Warning Temperature1 Thermal Shutdown Temperature1 THERMISTOR CONTROL Resistance Thresholds by Battery Temperature4 LFCSP Package Cool to Cold Cold to Cool Typical to Cool 4 Cool to Typical4 Warm to Typical4 Typical to Warm4 Hot to Warm Warm to Hot WLCSP Package Cool to Cold Cold to Cool Typical to Cool4 Cool to Typical4 Warm to Typical4 Typical to Warm4 Hot to Warm Warm to Hot Test Conditions/Comments Min Typ Max Unit 220 160 280 210 2 m m A 3.15 202 125 3.3 300 170 3.45 m m V 0 5 14 mV VSW1x = 5.0 V VTH_ISO VTRK_DEAD < VBSNS, fast charging constant current mode VISOS < VISOB RDSON_HV IVBUS = 100 mA, TJ = 0C to 85C 330 ISUSPEND EN_DCDC = low 1.45 1.8 mA 3.9 3.6 5.45 75 4.03 3.73 5.53 V V V mV VVBUSOK VVBUSOK_RISE VVBUSOK_FALL VVBUS_OV 3.77 3.47 5.38 TSD_W TSD TJ rising TJ falling m 130 C 140 110 C C RNTC = 47 k, BETA_NTC = 3800, TJ = 0C to +85C RCOOL_COLD RCOLD_COOL RTYP_COOL RCOOL_TPY RWARM_TYP RTYP_WARM RHOT_WARM RWARM_HOT 131 126 75 72.5 20 19.3 12 11 151.2 145.6 86.5 83.1 23.7 22 13.9 12.7 175 168 99 95 27 24.6 16 14.4 k k k k k k k k RCOOL_COLD RCOLD_COOL RTYP_COOL RCOOL_TPY RWARM_TYP RTYP_WARM RHOT_WARM RWARM_HOT 140 133 77 75 20 18.5 11.5 10.5 162 156 90 86 23 21 13 12 185 180 102 100 26 24 15 13.5 k k k k k k k k Rev. B | Page 5 of 63 ADP5350 Parameter BATTERY DETECTION Sink Current Source Current Battery Threshold Low High Battery Detection Timer TIMERS Start Charging Delay Timer Trickle Charge Timer2 Fast Charge Timer2 Charge Complete Timer Deglitch Timer Watchdog Timer2 Safety Timer Battery Node Short Timer2 I2C (SCL AND SDA) Input Voltage Low Level High Level Low Level Output Voltage PGOOD AND BATOK PGOOD Pin Leakage Current Output Low Voltage BATOK Pin Leakage Current Output Low Voltage Data Sheet Symbol Min Typ Max Unit ISINK ISOURCE 15 7 25 10 35 13 mA mA VBATL VBATH tBATOK 1.8 3.3 1.9 3.4 333 2.0 3.55 V V ms tSTART tTRK tCHG tEND tDG Test Conditions/Comments VBSNS = VTRM, ICHG < IEND Applies to VTRM, VRCH, IEND, VWEAK, VTRK_DEAD, VVBUSOK_FALL, and VVBUSOK_RISE tWD tSAFE tBAT_SHR VIL VIH VOL Applies to SCL, SDA Applies to SCL, SDA Applies to SDA, ISDA_SINK = 2 mA IPGOOD_LEAK VPGOOD_LOW VPGOOD = 5 V IPGOOD = 1 mA IBATOK_LEAK VBATOK_LOW VBATOK = 5 V IBATOK = 1 mA 1 60 600 7.5 31 sec min min min ms 32 40 30 sec min sec 0.5 0.4 V V V 50 0.5 100 A mV 50 0.5 100 A mV 1.2 Specification is not production tested, but is supported by characterization data at initial product release. These values are programmable via the I2C interface. Values are given with default register values. Guaranteed by design. 4 Typical temperature is the normal operation temperature. 1 2 3 BATTERY FUEL GAUGE SPECIFICATIONS VVIN4 = VVIN123 = VISOS= 4.2 V, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted Table 2. Parameter BATTERY VOLTAGE MONITORING Battery Monitor Voltage Range Resolution Voltage Reading Accuracy Test Conditions/Comments Min Typ 2.7 Based on 12-bit ADC TJ = 25C TJ = 0C to +85C Rev. B | Page 6 of 63 Max Unit 4.5 V mV mV mV 1.09 -12.5 -30 +12.5 +30 Data Sheet ADP5350 BOOST AND LED DRIVER SPECIFICATIONS VVIN4 = VVIN123 = VISOS= 3.6 V, C9 = 4.7 F, C10 = 4.7 F, L2 = 4.7 H, TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Input Voltage Range UNDERVOLTAGE LOCKOUT OUTPUT CHARACTERISTICS Output Voltage Range FB4 Voltage Reference Symbol VVIN4 VUVLO_VIN4_RISE VUVLO_VIN4_FALL Test Conditions/Comments Start-Up Time CURRENT LIMIT OSCILLATOR CIRCUIT Switching Frequency Minimum On Time LED CURRENT CONTROL LED Current Range, 6-Bit Accuracy Matching LED Pin Leakage Current LED Current Ramp-Up Time LED Current Ramp-Down Time LED Source Headroom LED ON/OFF TIMER LED Timer Accuracy 1 Typ Max Unit 5.5 2.85 V V V 16 0.68 +1.5 0.1 V V % %/V 90 5.5 2 2 % % ms ms 2.85 VIN4 rising VIN4 falling Standalone operation mode VVOUT4 VFB4 TJ = 25C Line Regulation1 POWER GOOD (PGOOD) PGOOD Rising Threshold PGOOD Hysteresis PGOOD Falling Delay PGOOD Rising Delay SW4 CHARACTERISTICS SW4 On Resistance Overvoltage Threshold Min 2.5 VISOS 0.62 -1.5 VVOUT4/VVIN4 2.7 2.6 0.65 Standalone operation mode VPGOOD4_RISE VPGOOD4_HYS tPGOOD4_FALL tPGOO4_RISE RDSON_NFET VOVP4 VOVP4_HYS tSS4 ILIM4 NFET at VVIN4 = 3.6 V Boost OVP threshold = 18.5 V Boost OVP threshold = 15 V Boost OVP threshold = 10 V Boost OVP threshold = 5.6 V OVP recovery hysteresis1 BST_IPK = 0 BST_IPK = 1 fSW4 tMIN_ON4 510 1.35 IDx IDx = 20 mA IDx = 20 mA IDx_LEAK tDx_RISE tDx_FALL VDx_HDRM 17.5 14.2 9.5 5.32 460 18.5 15 10 5.6 5 1.0 600 300 1.5 50 0 -10 800 19.5 15.8 10.5 5.9 2.7 690 1.65 MHz ns 20 +10 0.75 mA % % A s s V +10 % 2.0 0.5 IDx = 20 mA IDx = 20 mA ILEDx[5:0] =11111 Including on timer and off timer Specification is not production tested, but is supported by characterization data at initial product release. Rev. B | Page 7 of 63 20 20 0.65 -10 m V V V V % ms mA mA ADP5350 Data Sheet LDO SPECIFICATIONS VVBUSx = 5.0 V, VVIN4 = VVIN123 = VISOS= 3.6 V, C5 = C6 = C7 = C8 = 1 F; TJ = -40C to +125C for minimum/maximum specifications, and TA = 25C for typical specifications, unless otherwise noted. Table 4. Parameter LDO1 INPUT VOLTAGE RANGE KEEPALIVE LDO1 UNDERVOLTAGE LOCKOUT Output Voltage Range Output Accuracy Symbol VVIN123 Test Conditions/Comments VUVLO_LDO1_RISE VUVLO_LDO1_FALL VUVLO_LDO1_HYS VVOUT1 VIN123 rising VIN123 falling Line Regulation Load Regulation Dropout Voltage VVOUT1/VIN123 VVOUT1/IOUT1 VDROP_OUT1 Current-Limit Threshold Output Noise 1 Power Supply Rejection Ratio1 ILIM_LDO1 VNOISE_LDO1 PSRR LDO Start-Up Time PGOOD Rising Threshold PGOOD Hysteresis PGOOD Falling Delay PGOOD Rising Delay Load Switch Turn-On Rise Time Load Switch On Resistance COUT Discharge Switch On Resistance LDO2 INPUT VOLTAGE RANGE GENERAL-PURPOSE LDO2 Undervoltage Lockout Output Voltage Range Output Accuracy Line Regulation Load Regulation Dropout Voltage LFCSP Package WFCSP Package LFCSP Package WFCSP Package Current-Limit Threshold tSS_LDO1 VPGOOD1_RISE VPGOOD1_HYS tPGOOD1_Fall tPGOOD1_RISE tRISE_SWITCH1 RDSON_SWITCH1 RDIS_LDO1 Min 2.56 Unit V 2.56 V V mV V % % %/V %/mA mV mV mA V rms dB 200 Fuse trim or I2C, four bits IOUT1 = 10 mA, TJ = 25C IOUT1 = 10 mA VVIN123 = (VVOUT1 + 0.5 V) to 5.5 V IOUT1 = 100 A to 150 mA VVOUT1 = 3.3 V, IOUT1 = 10 mA VVOUT1 = 3.3 V, IOUT1 = 150 mA 1.0 -1 -2.0 -0.1 200 10 Hz to 100 kHz, VVIN123= 3.6 V, VVOUT1 = 3.3 V 100 Hz, VVIN123= 3.6 V, VVOUT1 = 3.3 V, IOUT1 = 10 mA 1 kHz, VVIN123= 3.6 V, VVOUT1 = 3.3 V, IOUT1 = 10 mA VVOUT1 = 3.3 V, LDO mode Only effective in LDO mode VOUT1 = 3.3 V, load switch mode VVIN123 = 3.6 V 2.85 VUVLO_LDO2_RISE VUVLO_LDO2_FALL VUVLO_LDO2_HYS VVOUT2 VIN4 rising VIN4 falling 2.5 Fuse trim or I2C, 4 bits IOUT2 = 10 mA, TJ = 25C IOUT2 = 10 mA VVIN123 = (VVOUT2 + 0.5 V) to 5.5 V IOUT2 = 100 A to 150 mA 2.7 2.6 100 1.0 -0.75 -1.5 -0.1 VVOUT2 = 3.3 V, IOUT2 = 10 mA VVOUT2 = 3.3 V, IOUT2 = 10 mA VVOUT2 = 3.3 V, IOUT2 = 150 mA VVOUT2 = 3.3 V, IOUT2 = 150 mA 220 Rev. B | Page 8 of 63 54 150 300 100 40 4.2 +1 +2.0 +0.1 0.015 130 240 440 35 600 90 4.5 120 2 120 700 500 VVIN4 = VVIN123 VDROP_OUT2 VDROP_OUT2 VDROP_OUT2 VDROP_OUT2 ILIM_LDO2 Max 5.5 1.78 VVIN4 (VVOUT2)/VVIN123 (VVOUT2)/IOUT2 Typ 76 65 100 80 320 dB s % % s ms s m 5.5 V 2.85 4.2 +0.75 +1.5 +0.1 0.01 V V mV V % % %/V %/mA 140 120 180 150 430 mV mV mV mV mA Data Sheet ADP5350 Parameter Output Noise1 Power Supply Rejection Ratio1 Symbol VNOISE_LDO2 PSRR LDO Start-Up Time Load Switch Turn-On Rise Time Load Switch On Resistance LFCSP Package WFCSP Package COUT Discharge Switch On Resistance LDO3 INPUT VOLTAGE RANGE GENERAL-PURPOSE LDO3 UNDERVOLTAGE LOCKOUT tSS_LDO2 tRISE_SWITCH2 Output Voltage Range Output Accuracy Line Regulation Load Regulation Dropout Voltage LFCSP Package WFCSP Package LFCSP Package WFCSP Package Current Limit Threshold Output Noise1 Power Supply Rejection Ratio1 LDO Start-Up Time Load Switch Turn-On Rise Time Load Switch On Resistance LFCSP Package WFCSP Package COUT Discharge Switch On Resistance 1 Test Conditions/Comments 10 Hz to 100 kHz, VVIN123 = 3.6 V, VVOUT2 = 3.3 V 100 Hz, VIN123 = 3.6 V, VVOUT2 = 3.3V, IOUT2 = 10 mA 1 kHz, VIN123 = 3.6 V, VVOUT2 = 3.3 V, IOUT2 = 10 mA VVOUT2 = 3.3 V, LDO mode VVOUT2 = 3.3 V, load switch mode Min RDSON_SWITCH2 RDSON_SWITCH2 RDIS_LDO2 VVIN123 = 3.6 V VVIN4 VVIN4 = VVIN123 2.85 VUVLO_LDO3_RISE VUVLO_LDO3_FALL VUVLO_LDO3_HYS VVOUT3 VVOUT3 VIN4 rising VIN4 falling 2.5 VOUT3/VVIN123 VOUT3/IOUT3 VDROP_OUT3 VDROP_OUT3 VDROP_OUT3 VDROP_OUT3 ILIM_LDO3 VNOISE_LDO3 PSRR tSS_LDO3 tRISE_SWITCH3 RDSON_SWITCH3 RDSON_SWITCH3 RDIS_LDO3 Fuse trim or I2C, four bits IOUT3 = 10 mA, TJ = +25C IOUT3 = 10 mA VVIN123 = (VVOUT3 + 0.5 V) to 5.5 V IOUT3 = 100 A to 150 mA Typ 120 60 50 80 80 Max Unit V rms dB dB s s 400 300 500 600 500 m m 5.5 V 2.85 V V mV V % % %/V %/mA 2.7 2.6 100 1.0 -0.75 -1.5 -0.1 VVOUT3 = 3.3 V, IOUT3 = 10 mA VVOUT3 = 3.3 V, IOUT3 = 10 mA VVOUT3 = 3.3 V, IOUT3 = 150 mA VVOUT3 = 3.3 V, IOUT3 = 150 mA 4.2 +0.75 +1.5 +0.1 0.01 140 120 180 150 430 10 Hz to 100 kHz, VVIN123 = 3.6 V, VVOUT3 = 3.3 V 100 Hz, VVIN123 = 3.6 V, VVOUT3 = 3.3 V, IOUT3 = 10 mA 1 kHz, VVIN123 = 3.6 V, VVOUT3 = 3.3 V, IOUT3 = 10 mA VVOUT3 = 3.3 V, LDO mode VVOUT3 = 3.3 V, load switch mode 76 65 100 80 320 120 60 50 80 80 mV mV mV mV mA V rms dB dB s s 600 500 VIN123 = 3.6 V 400 300 500 m m 220 Guaranteed by design. Rev. B | Page 9 of 63 ADP5350 Data Sheet RECOMMENDED INPUT AND OUTPUT CAPACITANCE AND INDUCTANCE SPECIFICATIONS Table 5. Parameter EFFECTIVE CAPACITANCE Charger Capacitance VBUSx Pin CFL1 Pin CFL2 Pin ISOS Pin ISOB Pin LDO Capacitance VIN123 Pin LDO1 LDO2 LDO3 Boost Capacitance VIN4 Pin VOUT4 Pin INDUCTANCE Buck Boost Min Typ 1.0 2.0 1.0 4.0 4.0 2.2 4.7 2.2 10 10 F F F F F 0.7 0.7 0.7 0.7 1 1 1 1 F F F F 1 0.47 4.7 4.7 F F 0.5 2 1.5 4.7 Rev. B | Page 10 of 63 Max 2.2 10 Unit H H Data Sheet ADP5350 I2C-COMPATIBLE INTERFACE TIMING SPECIFICATIONS Table 6. Parameter I2C-COMPATIBLE INTERFACE Capacitive Load, Each Bus Line SCL Clock Frequency High Time Low Time Data Setup Time Hold Time 1 Setup Time for Repeated Start Hold Time for Start/Repeated Start Bus Free Time Between a Stop and a Start Condition Setup Time for Stop Condition SCL/SDA Rise Time Fall Time Pulse Width of Suppressed Spike 1 Symbol Min Typ CS fSCL tHIGH tLOW 0.6 1.3 tSU,DAT tHD,DAT tSU,STA tHD,STA tBUF tSU,STO 100 0 0.6 0.6 1.3 0.6 tR tF tSP Max Unit 400 pF 400 kHz s s ns s s s s s 0.9 300 300 50 0 ns ns ns A master device must provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge of SCL. See Figure 3, the I2C timing diagram. Timing Diagram SDA tLOW tR tF tSU,DAT tF tHD,STA tSP tBUF tR SCL tHIGH tHD,DAT tSU,STA Sr tSU,STO P S 14797-002 S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Figure 3. I2C Timing Diagram Rev. B | Page 11 of 63 ADP5350 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 7. Parameter VBUSA, VBUSB to PGND1 SW4, VOUT4, D1, D2, D3, D4, D5 to PGND4 FB4 CFL2 to AGND PGND1, PGND4 to AGND All Other Pins to AGND Continuous Drain Current, Battery Supplementary Mode, from ISOB to ISOS, TJ = 125C Storage Temperature Range Operating Junction Temperature Range Soldering Conditions Rating -0.5 V to +20 V -0.5 V to +20 V -0.3 V to +6 V -0.3 V to +3.3 V -0.3 V to +0.3 V -0.3 V to +6 V 1.1 A -65C to +150C -40C to +125C JEDEC J-STD-020 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 8. Thermal Resistance Package Type CP-32-121 CB-32-1 1 JA 42 64 JC 2.1 0.7 Unit C/W C/W Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with nine thermal vias. See JEDEC JESD51. Maximum Power Dissipation The maximum safe power dissipation in the ADP5350 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the ADP5350. Exceeding a junction temperature of 175C for an extended period of time can result in changes in the silicon devices that potentially cause failure. ESD CAUTION Rev. B | Page 12 of 63 Data Sheet ADP5350 32 31 30 29 28 27 26 25 BATOK SDA SCL VOUT1 VOUT2 VIN123 CFL2 VOUT3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 ADP5350 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 D5 D4 D3 D2 D1 VIN4 FB4 VOUT4 NOTES 1. EXPOSED PAD (ANALOG GROUND). THE EXPOSED PAD MUST BE CONNECTED AND SOLDERED TO AN EXTERNAL GROUND PLANE. 14797-003 PGND1A PGND1B SW1A SW1B VBUSA VBUSB SW4 PGND4 9 10 11 12 13 14 15 16 INT PGOOD THR BSNS ISOB ISOS AGND CFL1 Figure 4. LFCSP Pin Configuration (Top View) Table 9. LFCSP Pin Function Descriptions Pin No. 1 Mnemonic INT 2 3 4 5 6 7 8 PGOOD THR BSNS ISOB ISOS AGND CFL1 9, 10 11, 12 13, 14 15 16 17 18 PGND1A, PGND1B SW1A, SW1B VBUSA, VBUSB SW4 PGND4 VOUT4 FB4 19 20 21 22 23 24 25 26 27 28 29 30 31 32 VIN4 D1 D2 D3 D4 D5 VOUT3 CFL2 VIN123 VOUT2 VOUT1 SCL SDA BATOK EPAD Description Processor Interrupt (Active Low). This pin requires an external pull-up resistor. If this pin is not used, it can be left floating. Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. Battery Pack Thermistor Connection. Battery Voltage Sense Pin. Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. Analog Ground. Power input to the charger regulator. Connect a ceramic filter capacitor between this pin and either PGND1A or PGND1B. Power Ground for the Battery Charger. Switching Node for the Battery Charger. Power Connection to USB Bus Voltage. Switching Node for the Boost Regulator. Power Ground for the Boost Regulator. Power Output for the Boost Regulator. Feedback Sensing Input for the Boost Regulator. In standalone mode, connect this pin to a resistor divider from VVOUT4. In LED operation mode, connect FB4 to ground. Input Voltage for the Boost Regulator and LDO Control Block. LED 1 Sink Channel. Connect this pin to the cathode of the LED. LED 2 Sink Channel. Connect this pin to the cathode of the LED. LED 3 Sink Channel. Connect this pin to the cathode of the LED. LED 4 Sink Channel. Connect this pin to the cathode of the LED. LED 5 Sink Channel. Connect this pin to the cathode of the LED. Power Output for LDO3. Internal Regulator Output for the Fuel Gauge. Connect a ceramic capacitor between this pin and AGND. Power Input for LDO1, LDO2, and LDO3. Power Output for LDO2. Power Output for LDO1. I2C Serial Clock. This pin requires an external pull-up resistor. I2C Serial Data. This pin requires an external pull-up resistor. Battery Status Open-Drain Output Flag (Active High). This pin enables the system when the battery reaches VWEAK. Exposed Pad (Analog Ground). The exposed pad must be connected and soldered to an external ground plane. Rev. B | Page 13 of 63 ADP5350 Data Sheet 1 2 3 A VOUT3 CFL2 VIN123 B D4 D5 SDA C D2 D3 4 VOUT2 SCL 5 6 VOUT1 PGOOD BATOK INT THR ISOB BSNS ISOS ADP5350 D1 VIN4 E VOUT4 FB4 VBUSA AGND SW1A PGND1A F PGND4 SW4 VBUSB CFL1 SW1B PGND1B 14797-105 TOP VIEW (Not to Scale) D Figure 5. WLCSP Pin Configuration (Top View) Table 10. WLCSP Pin Function Descriptions Pin No. B6 Mnemonic INT A6 C5 D5 C6 D6 E4 F4 PGOOD THR BSNS ISOB ISOS AGND CFL1 E6, F6 E5, F5 E3, F3 F2 F1 E1 E2 PGND1A, PGND1B SW1A, SW1B VBUSA, VBUSB SW4 PGND4 VOUT4 FB4 D2 D1 C1 C2 B1 B2 A1 A2 A3 A4 A5 B4 B3 B5 VIN4 D1 D2 D3 D4 D5 VOUT3 CFL2 VIN123 VOUT2 VOUT1 SCL SDA BATOK Description Processor Interrupt (Active Low). This pin requires an external pull-up resistor. If this pin is not used, it can be left floating. Power-Good Signal Output. This open-drain output is the power-good signal for the selected channels. Battery Pack Thermistor Connection. Battery Voltage Sense Pin. Battery Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. Charger Supply Side Input to Internal Isolation FET/Battery Current Regulation FET. Analog Ground. Power input to the charger regulator. Connect a ceramic filter capacitor between this pin and either PGND1A or PGND1B. Power Ground for the Battery Charger. Switching Node for the Battery Charger. Power Connection to USB Bus Voltage. Switching Node for the Boost Regulator. Power Ground for the Boost Regulator. Power Output for the Boost Regulator. Feedback Sensing Input for the Boost Regulator. In standalone mode, connect this pin to a resistor divider from VVOUT4. In LED operation mode, connect FB4 to ground. Input Voltage for the Boost Regulator and LDO Control Block. LED 1 Sink Channel. Connect this pin to the cathode of the LED. LED 2 Sink Channel. Connect this pin to the cathode of the LED. LED 3 Sink Channel. Connect this pin to the cathode of the LED. LED 4 Sink Channel. Connect this pin to the cathode of the LED. LED 5 Sink Channel. Connect this pin to the cathode of the LED. Power Output for LDO3. Internal Regulator Output for the Fuel Gauge. Connect a ceramic capacitor between this pin and AGND. Power Input for LDO1, LDO2, and LDO3. Power Output for LDO2. Power Output for LDO1. I2C Serial Clock. This pin requires an external pull-up resistor. I2C Serial Data. This pin requires an external pull-up resistor. Battery Status Open-Drain Output Flag (Active High). This pin enables the system when the battery reaches VWEAK. Rev. B | Page 14 of 63 Data Sheet ADP5350 TYPICAL PERFORMANCE CHARACTERISTICS VVBUSx = 5.0 V, VVIN4 = VVIN123 = VISOS = 3.6 V, CBUS = 2.2 F, C3 = 10 F, C4 = 10 F, CCFL1 = 4.7 F, LOUT1 = 1.5 H, all registers are at default values, unless otherwise noted. 600 450 430 HVFET ON RESISTANCE (m) INPUT CURRENT LIMIT (mA) 500 400 300 200 ILIM = 100mA ILIM = 500mA 100 410 390 370 350 330 310 290 20 80 50 TEMPERATURE (C) 250 14797-004 -10 0 4.34 4.33 3.8 3.7 3.6 4.32 4.31 4.30 4.29 4.28 3.5 4.27 3.4 4.26 -20 10 40 70 100 130 4.25 -40 -10 20 50 80 TEMPERATURE (C) Figure 7. VVBUSOK Threshold vs. Temperature 14797-008 SYSTEM VOLTAGE (V) 3.9 14797-005 Figure 10. System Voltage vs. Temperature 100 5 VISOB = 2.7V VISOB = 3.6V VISOB = 4.2V 90 VOUT = 3.6V VOUT = 4.3V VOUT = 4.5V 80 EFFICIENCY (%) 70 3 2 60 50 40 30 20 1 10 -20 0 20 40 60 TEMPERATURE (C) Figure 8. Shutdown Current vs. Temperature 80 0 0.001 14797-006 0 -40 0.01 0.1 IOUT (A) 1 14797-111 VVBUSOK THRESHOLD (V) 4.0 TEMPERATURE (C) SHUTDOWN CURRENT (A) 80 4.35 RISING FALLING 4.1 4 60 Figure 9. High Voltage FET (HVFET) On Resistance vs. Temperature 4.3 3.3 -50 40 TEMPERATURE (C) Figure 6. Input Current Limit vs. Temperature 4.2 20 14797-109 270 0 -40 Figure 11. Efficiency vs. Ouptut Current (IOUT), Buck Regulator Efficiency Rev. B | Page 15 of 63 ADP5350 Data Sheet 350 3080 300 3040 3020 3000 2980 2960 250 200 150 2940 VISOB = 2.6V VISOB = 3.0V VISOB = 3.6V VISOB = 4.2V 2920 -10 20 50 80 TEMPERATURE (C) 100 14797-010 2900 -40 Figure 12. Buck Switching Frequency vs. Temperature 20 0 40 60 80 TEMPERATURE (C) 14797-115 3060 ISOFET RESISTANCE (m) BUCK SWITCHING FREQUENCY (kHz) 3100 Figure 15. Isolation FET (ISOFET) Resistance vs. Temperature at Various Battery Voltage Levels, LFCSP Package 600 1.0 0.8 400 300 200 ICHG = 100mA ICHG = 500mA 100 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 VISOB = 2.7V VISOB = 3.6V VISOB = 4.2V -0.8 -10 20 80 50 TEMPERATURE (C) -1.0 14797-011 0 -40 60 80 Figure 16. ADC Voltage Accuracy vs. Temperature 1600 ICHG = 200mA, RBAT = 1 ICHG = 500mA, RBAT = 0.4 1580 BOOST SW FREQUENCY (kHz) 500 400 300 200 100 1560 1540 1520 1500 1480 1460 1440 0 4.3 4.5 4.7 4.9 5.1 VBUSx VOLTAGE (V) 5.3 Figure 14. Charge Current vs. VBUSx Voltage 1400 -40 -10 20 50 80 110 TEMPERATURE (C) Figure 17. Boost Switching Frequency vs. Temperature Rev. B | Page 16 of 63 14797-015 1420 14797-012 CHARGE CURRENT (mA) 40 TEMPERATURE (C) Figure 13. Charge Current vs. Temperature 600 20 0 14797-116 ADC VOLTAGE ACCURACY (%) CHARGE CURRENT (mA) 500 Data Sheet ADP5350 25 ILIM = 300mA ILIM = 600mA 20 LED CURRENT ACCURACY (%) 700 600 500 400 300 200 ILED = 1mA ILED = 10mA ILED = 20mA 15 10 5 0 -40 -10 20 50 80 110 0 -50 TEMPERATURE (C) 40 70 100 130 Figure 21. LED Current Accuracy vs. Temperature 100 11.0 90 10.8 80 10.6 70 10.4 60 10.2 ILED (mA) 50 40 10.0 9.8 9.6 D1 D2 D3 D4 D5 9.4 20 VOUT = 5V VOUT = 9V VOUT = 15V 0 0.001 9.2 0.1 0.01 IOUT (A) 9.0 3.6 14797-119 10 3.8 4.0 4.2 4.4 4.6 VVIN4 (V) 14797-020 30 Figure 22. LED Channel Current (ILED) vs. VVIN4 Figure 19. Boost Efficiency vs. Output Current (IOUT) 250 2.0 VOUT = 3.3V VOUT = 2.5V LDO1 DROPOUT VOLTAGE (mV) 1.5 1.0 0.5 0 -0.5 -1.0 200 150 100 50 -2.0 -40 -10 20 50 80 110 TEMPERATURE (C) 14797-120 -1.5 0 1 10 100 1000 LOAD CURRENT (mA) Figure 23. LDO1 Dropout Voltage vs. Load Current, LFCSP Package Figure 20. Boost Output Accuracy vs. Temperature, VVOUT4 = 5 V Rev. B | Page 17 of 63 14797-021 EFFICIENCY (%) 10 TEMPERATURE (C) Figure 18. Boost Input Current Limit vs. Temperature BOOST OUTPUT ACCURACY (V) -20 14797-019 100 14797-016 BOOST INPUT CURRENT LIMIT (mA) 800 ADP5350 0 VOUT2 = 3.3V -10 120 LDO2 PSRR (dB) 90 60 -30 -40 -50 -60 30 1 10 100 1000 LOAD CURRENT (mA) -80 10 100k 1M 10M Figure 26. LDO2 Power Supply Rejection Ratio (PSRR) vs. Frequency, VVOUT2 = 3.3 V, VIN123 = 3.6 V 0 100A 1mA 10mA 100mA -10 -20 100A 1mA 10mA 100mA -20 LDO3 PSRR (dB) -30 -40 -50 -60 -30 -40 -50 -60 -70 -70 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 14797-125 -80 -90 10 10k Figure 25. LDO1 PSRR vs. Frequency, VVOUT1 = 3.3 V, VVIN123 = 3.6 V -80 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 27. LDO3 PSRR vs. Frequency, VVOUT3 = 3.3 V, VIN123 = 3.6 V Rev. B | Page 18 of 63 14797-127 -10 1k FREQUENCY (Hz) Figure 24. LDO2/LDO3 Dropout Voltage vs. Load Current, LFCSP Package 0 100 14797-126 -70 0 LDO1 PSRR (dB) 100A 1mA 10mA 100mA -20 14797-124 LDO2/LDO3 DROPOUT VOLTAGE (mV) 150 Data Sheet Data Sheet ADP5350 TYPICAL WAVEFORMS T T VISOB VISOB VISOS VISOS VVBUSx 3 VVBUSx 1 2 2 1 3 IVBUS IVBUS CH2 2.00V CH4 500mA M4.0ms A CH1 T 15.9320ms 3.08V 14797-128 CH1 2.00V BW CH3 2.00V CH1 2.00V BW CH3 2.00V BW Figure 28. VBUSx Connected to USB Power CH2 2.00V CH4 200mA M200s A CH4 T 552.400s 92.0mA 14797-131 4 4 Figure 31. Charger Stop with EN_CHG Set Low, ILIM = 500 mA, ICHG = 200 mA, VVBUSx = 5 V T VISOB VISOS 1 VISOS SW1 VVBUSx 3 2 1 3 IL1 IVBUS CH2 2.00V CH4 500mA M100ms A CH1 3.08V 14797-129 CH1 2.00V BW CH3 2.00V CH1 10.0mV BW CH3 2.00V BW CH4 200mA Figure 29. VBUSx Disconnected from USB Power M400ns A CH3 T 400.000ns 1.68V 14797-132 4 4 Figure 32. Fast Charger Status, ICHG = 200 mA, VVBUSx = 5 V T T VISOB VISOS VISOS 1 VVBUSx 1 2 IISOS 3 IVBUS 4 CH2 2.00V CH4 200mA M200s A CH4 T 552.400s 92.0mA CH1 10.0mV B W CH4 500mA Figure 30. Charger Start with EN_CHG Set High, ILIM = 500 mA, ICHG = 150 mA, VVBUSx = 5 V M200s A CH4 -531.600s T 400mA 14797-133 CH1 2.00V BW CH3 2.00V BW 14797-130 4 Figure 33. VISOS Voltage Load Transient Response, VISOS = 4.3 V, VVBUSx = 5 V, Rev. B | Page 19 of 63 ADP5350 Data Sheet T T VISOS VVOUT4 VVOUT1 2 1 SW4 1 ILDO1 3 CH1 5.00V BW CH3 5.00V BW CH2 2.00V CH4 200mA M400s A CH1 T 560.000s 6.40V 4 14797-134 4 B CH1 100mV M2.00ms A CH4 T 5.56000ms W CH4 100mA 114mA 14797-137 IL4 Figure 37. LDO1 Output Load Transient Response Figure 34. Boost Voltage Soft Start, LED Mode; ILED1 = ILED2 = ILED3 = 10 mA T T VISOS VVIN123 VVOUT4 2 VVOUT2 SW4 2 1 3 IL4 CH1 5.00V BW CH3 5.00V BW CH2 2.00V CH4 200mA M1.00s A CH3 T 120.000ns 6.60V CH1 1.00V B W A CH1 M100s 190.000s T CH2 2.00V 1.54V 14797-138 4 14797-135 1 Figure 38. LDO2 Output Soft Start, RLDO1 = 330 Figure 35. Boost Operation, LED Mode; ILED1 = ILED2 = ILED3 = 10 mA T T VVIN123 VVOUT2 1 2 VVOUT1 ILDO2 CH2 2.00V M400s A CH1 T 814.000s 1.54V 4 14797-136 CH1 1.00V BW CH1 50.00mV B W CH4 100mA M200s A CH4 T 498.000s 114mA Figure 39. LDO2 Output Load Transient Response Figure 36. LDO1 Output Soft Start, RLDO1 = 330 Rev. B | Page 20 of 63 14797-139 1 Data Sheet ADP5350 THEORY OF OPERATION BATTERY CHARGER OVERVIEW The ADP5350 integrates a fully I C-programmable charger for single-cell Li-Ion or Li-Ion polymer batteries suitable for a wide range of portable applications. 2 Figure 40 shows the complete charge cycle of the ADP5350 when VBUSx is connected. The ISOS pin voltage remains at VISOS_TRK when the device is not charging or when it is in trickle charge mode. When the device begins a fast charge, the VISOS voltage follows the battery voltage until the charge is complete. The charge current keeps constant in CC mode and reduces to IEND in CV mode. When the battery voltage, VISOB, drops to VTRM - VRCH, the charger resumes to charge until the charge completes. The highly efficient switch dc-to-dc architecture enables higher charging currents as well as a lower temperature charging operation that results in faster charging times. The charger of the ADP5350 operates from an input voltage from 4 V to 5.4 V but is tolerant of voltages of up to 20 V. This tolerance alleviates concerns about USB bus spiking during disconnection or connection. The ADP5350 features an internal FET between the dc-to-dc charger output and the battery. This FET permits battery isolation and, therefore, system powering in a dead battery or no battery scenario, which allows immediate system function upon connection to a USB power supply. VISOS_TRK The charger of the ADP5350 is fully compliant with the USB 3.0 specification and enables charging via the mini USB VBUSx pin from a wall charger, car charger, or USB host port. Based on the type of USB source, which is detected by an external USB detection device, the ADP5350 can be set to apply the correct current limit for optimal charging and USB compliance. The USB charger permits correct operation under all USB compliant sources, such as wall chargers, host chargers, hub chargers, and standard hosts and hubs. A processor is able to control the USB charger using the I2C to program the charging current and numerous other parameters, including * * * * * * * * * * Trickle charge current level and voltage threshold Fast charge (CC) current level Fast charge (CV) voltage level Fast charge safety timer period Watchdog safety timer parameters Weak battery threshold detection End of charge current level for charge complete Recharge threshold VBUSx input current limit Charge enable and disable VISOS VTRM VRCH ICHG VISOS_FC VTRK_DEAD VISOB IEND IISOB TRICKLE CHARGE FAST CHARGE CC FAST CHARGE CV Figure 40. ADP5350 Battery Charging Profile Rev. B | Page 21 of 63 CHARGE COMPLETE RECHARGE CHARGE COMPLETE 14797-023 CHARGE DISABLE ITRK_DEAD ADP5350 Data Sheet CHARGER MODES Weak Charge Mode (Constant Current) Input Current Limit When the battery voltage exceeds VTRK_DEAD but is less than VWEAK, the charger switches to weak charge mode and the ISOS node is regulated to VISOS_FC by turning on the battery isolation FET. The ADP5350 features a programmable input current limit, from 100 mA to 1500 mA, via the ILIM[3:0] I2C bits, which ensures compatibility with the USB limits requirements listed in Table 11. The current limit defaults to 100 mA to allow compatibility with a USB host or hub that is not configured. This input current limit resets to the 100 mA default value during every power cycle on VBUSx to protect the USB port. When the input current limit feature is used, the available input current may be too low for the charger to meet the programmed charging current, ICHG, and the rate of charge is reduced. In this case, the VBUS_ILIM flag is set. When connecting an improper voltage level to VBUSx, the dcto-dc regulator shuts down, the ISOFET turns on, and the high voltage blocking part is in a state wherein it draws only 1.3 mA (typical) of current until VVBUSx reaches the VVBUS_OV_FALL level. The ADP5350 always monitors the VVBUSx voltage when there is a proper USB power connection. The VBUSOK bit, Bit 3 in Register 0x36, indicates whether the VVBUSx voltage is within VVBUS_OV and VVBUSOK, which can be programmed to be masked to the PGOOD pin via the VBUSOK_MASK bit in Register 0x37. The default setting of the VBUSOK_MASK is programmed via a factory fuse trim. Trickle Charge Mode A deeply discharged Li-Ion cell may exhibit a very low cell voltage, making it unsafe to charge the cell at high current rates. The ADP5350 charger uses a trickle charge mode to reset the battery pack protection circuit and lift the cell voltage to a safe level for fast charging. A cell with a voltage below VTRK_DEAD is charged with the trickle mode current, ITRK_DEAD. During trickle charge mode, the CHARGER_STATUS[3:0] bits are set. During trickle charging, the ISOS node is regulated to VISOS_TRK by the dc-to-dc regulator and the battery isolation FET is off, which means the battery is isolated from the system power supply. The enable of the trickle charging function is controlled via the I2C EN_TRK bit. Trickle Charge Mode Timer The duration of trickle charge mode is monitored to ensure the battery is revived from its deeply discharged state. If trickle charge mode runs for longer than 60 minutes without the cell voltage reaching VTRK_DEAD, a fault condition is assumed and the charging stops. The battery isolation FET turns on and the dcto-dc regulator stops working. The fault condition is asserted in the CHARGER_STATUS register, allowing the user to initiate the fault recovery procedure specified in the Fault Recovery section. In weak charge mode, the battery charges with the programmed ICHG current from the ISOS node through the isolation FET and trickle charge current, ITRK_DEAD. Due to the VBUSx input current limit, the real ICHG charge current from the ISOS node may be less than the programmed value. The system load can also share the current from the ISOS node. However, the trickle charge current, ITRK_DEAD, remains on to charge the battery in weak charge mode. Fast Charge Mode (Constant Current) When the battery voltage exceeds VTRK_DEAD and VWEAK, the charger switches to fast charge mode, charging the battery with the constant current, ICHG. During fast charge mode (CC), the CHARGER_STATUS[3:0] bits are set. During CC mode, other features may prevent the current, ICHG, from reaching its full programmed value. Isothermal charging mode or input current limiting for USB compatibility may affect the value of ICHG under certain operating conditions. The voltage on ISOS is regulated to stay at VISOS_FC by the battery isolation FET when VISOB < VISOS_FC. Fast Charge Mode (Constant Voltage) As the battery charges, its voltage rises and approaches the termination voltage, VTRM. The ADP5350 charger monitors the voltage on the BSNS pin to determine when charging ends. However, the internal ESR of the battery pack combined with PCB and other parasitic series resistances creates a voltage drop between the sense point at the BSNS pin and the cell terminal itself. To compensate for this and ensure a fully charged cell, the ADP5350 enters a constant voltage charge mode when the BSNS voltage reaches the termination voltage. The ADP5350 reduces charge current gradually as the cell continues to charge, maintaining a voltage of VTRM on the BSNS pin. During fast charge mode (constant voltage), the CHARGER_STATUS[3:0] bits are set. Fast Charge Mode Timer The duration of fast charge mode is monitored to ensure that the battery is charging correctly. If the fast charge mode runs for longer than tCHG without the voltage at the BSNS pin reaching VTRM, a fault condition is assumed and charging stops. The battery isolation FET remains on, and the dc-to-dc regulator shuts down. The fault condition is asserted on the CHARGER_STATUS register, allowing the user to initiate the fault recovery procedure specified in the Fault Recovery section. If the fast charge mode runs for longer than tCHG, and VTRM is reached on the BSNS pin but the charge current is not yet below IEND, charging stops by turning the battery isolation FET off, but the system voltage is maintained at VISOS_TRK by the dc-to-dc regulator. No fault condition is asserted in this circumstance, and the ADP5350 transitions to charge complete status. Rev. B | Page 22 of 63 Data Sheet ADP5350 Table 11. Input Current Compatibility with Standard USB Limits Mode USB 2.0 USB 3.0 Dedicated Charger Standard USB Limit 100 mA limit for standard USB host or hub 500 mA limit for standard USB host or hub 150 mA limit for super speed USB 3.0 host or hub 900 mA limit for super speed, high speed USB host or hub charger 1500 mA limit for dedicated charger or low/full speed USB host or hub charger Watchdog Timer The ADP5350 charger features a programmable watchdog timer function to ensure charging is under the control of the processor. The watchdog timer starts running when the ADP5350 charger determines that the processor is operational, that is, when the processor sets the RESET_WD bit for the first time or when the battery voltage is greater than the weak battery threshold, VWEAK. When the watchdog timer triggers, it must be reset regularly within the watchdog timer period, tWD. If the watchdog timer expires without being reset while in charger mode, the ADP5350 charger assumes there is a software problem and triggers the safety timer, tSAFE. For more information, see the Safety Timer section. Meanwhile, the ILIM current limit resets to the default value. Safety Timer If the watchdog timer (see the Watchdog Timer section for more information) expires while in charger mode, the ADP5350 charger initiates the safety timer, tSAFE. Charging continues for a period of tSAFE, and then stops. The battery isolation FET remains on while the dc-to-dc regulator shuts down. The CHARGER_ STATUS[3:0] bits are then set. Resetting the charger requires VBUSx to be powered down and powered up. Charge Complete The ADP5350 charger monitors the charging current while in CV fast charge mode. If the current falls below IEND and remains below IEND for tEND, the charger is stopped by turning the battery isolation FET off, but the system voltage is maintained at VISOS_TRK by the dc-to-dc regulator and the CHDONE flag is set. If the charging current falls below IEND for less than tEND and then rises above IEND again, the tEND timer resets. Recharge After the detection of a complete charge, and the isolated FET turns off, the ADP5350 charger continues to monitor the BSNS pin. If the BSNS pin voltage falls below VTRM - VRCH, the charger reactivates charging. Under most circumstances, triggering the recharge threshold results in the charger entering fast charge constant current mode. Battery Charging Enable/Disable The ADP5350 charging function can be disabled by setting the I2C EN_CHG bit to low. If the I2C EN_CHG bit is low, the dc-to-dc regulator is still on and regulates the ISOS voltage to ADP5350 Function 100 mA input current limit or I2C programmed value 500 mA input current limit or I2C programmed value 150 mA input current limit or I2C programmed value 900 mA input current limit or I2C programmed value 1500 mA input current limit or I2C programmed value VISOS_TRK, the battery isolation FET turns off, and the dc-to-dc regulator provides the power for the system. BATTERY ISOLATION FET The ADP5350 charger features an integrated battery isolation FET for power path control. The battery isolation FET isolates a deeply discharged Li-Ion cell from the system power supply in trickle charge mode and when charging is complete, thereby allowing the system to be powered from the VBUSx node. When the VVBUSx voltage is below VVBUSOK_FALL, the battery isolation FET is in full conduction mode. The battery isolation FET is off during trickle charge mode. When the battery voltage exceeds VTRK_DEAD, the battery isolation FET switches to the system voltage regulation mode and the battery isolation FET maintains the VISOS_FC voltage on the ISOS pin. When the battery voltage exceeds VISOS_FC, the battery isolation FET is in full conduction mode. The battery isolation FET supplements the battery to support high current functions on the system power supply. When the voltage on ISOS drops below ISOB, the battery isolation FET enters full conduction mode. When the voltage on ISOS rises above ISOB, the isolation FET enters regulating mode or full conduction mode, depending on the Li-Ion cell voltage and the dc-to-dc charger mode. BATTERY DETECTION Battery Level Detection The ADP5350 charger features a battery detection mechanism to detect an absent battery. The charger actively sinks and sources current into the ISOB/BSNS node when the enable charger and VVBUSx have reached the VVBUSOK_RISE level, and voltage vs. time is detected. The sink phase is used to detect a charged battery, whereas the source phase is used to detect a discharged battery. The sink phase (see Figure 41) sinks ISINK current from the ISOB and BSNS pin for a time, tBATOK. If the BSNS pin is below VBATL when the tBATOK timer expires, the charger assumes no battery is present or battery is shorted, and starts the source phase. If the BSNS exceeds the VBATL voltage when the tBATOK timer expires, the charger assumes the battery is present and begins a new charge cycle. The source phase sources ISOURCE current to ISOB or the BSNS pin for a time, tBATOK. If the BSNS pin exceeds VBATH before the Rev. B | Page 23 of 63 ADP5350 Data Sheet tBATOK timer expires, the charger assumes that no battery is present. If the BSNS does not exceed the VBATH voltage when the tBATOK timer expires, the charger assumes that a battery is present, and begins a new charge cycle. The battery pack temperature sensing can be controlled by I2C using the conditions shown in Table 12. Note that the I2C register default setting for EN_THR (Register 0x07) is 0 = temperature sensing off. When the ADP5350 battery monitor is enabled and detects that the battery voltage is higher than VWEAK, Bit 2 in Register 0x36, BATOK, asserts high. The PGOOD pin can be programmed to mask BATOK, which indicates whether the battery voltage is higher than VWEAK. Table 12. THR Input Function Conditions VBUSx Open or VBUS = 0 V to 4.0 V Open or VBUS = 0 V to 4.0 V VBUS = 4.0 V to 5.5 V Battery (ISOB) Short Detection A battery short occurs under a damaged battery condition or when the battery protection circuitry is enabled. THR Function Off Controlled by I2C Always on If the battery pack thermistor is not connected directly to the ADP5350 THR pin, connect a 47 k (tolerance 20%) dummy resistor between THR and AGND. Leaving the THR pin open results in a false detection of the battery temperature of <0C and charging being disabled. Alternatively, select the temperature source from the I2C interface by setting Register 0x20, Bit 6. After a source phase, if the voltage on ISOB or BSNS remains below VBATH, either the battery voltage is low or the battery node is shorted. When the battery voltage is low, trickle charge mode is initiated (see Figure 42). If the voltage on BSNS remains below VBAT_SHR after tBAT_SHR has elapsed, the ADP5350 assumes that the battery node is shorted. A fault is declared on Register 0x0A, Bit 3. The ADP5350 charger suspends charging if the battery temperature is outside the range of less than 0C or greater than 60C. For temperatures greater than 0C, and likewise for temperatures lower than 60C, the THR_STATUS[2:0] bits are set accordingly. The ISOFET remains on while the dc-to-dc regulator shuts down. The trickle charge branch is active during the battery short scenario, and trickle charge current to the battery is maintained until the 60 minutes of the trickle charge mode timer expires. BATTERY TEMPERATURE The ADP5350 charger is designed for use with a negative temperature coefficient (NTC) thermistor in the battery pack with a nominal resistance value of 47 k, 10 k, or 100 k at 25C, which is selected via the I2C interface in Register 0x0C, Bit 4, and Register 0x3D, Bit 0. The temperature coefficient curve (beta) of RNTC also can be fuse selected in the ADP5350. Battery Pack Thermistor Input The ADP5350 charger features battery pack temperature sensing that precludes charging when the battery pack temperature is outside the specified range. The THR pin provides an on and off switching current source, which must be connected directly to the battery pack thermistor, RNTC. The activation interval of the THR current source is 167 ms. SINK PHASE VISOB <2.5 V >2.5 V Don't care SOURCE PHASE LOGIC STATUS tBAT_OK VBATH ISOURCE VBATL LOGIC STATUS tBAT_OK OPEN OR SHORT OPEN ISOB 14797-024 OPEN OPEN ISINK ISOB Figure 41. Battery Detection Sequence ISOB SHORT OR LOW BATTERY Figure 42. Battery Short Detection Sequence Rev. B | Page 24 of 63 tBAT_SHR SHORT ISOB 14797-025 tBAT_OK LOGIC STATUS SHORT ISOB OPEN OR SHORT SHORT ISINK tBAT_OK LOGIC STATUS SHORT LOGIC STATUS TRICKLE CHARGE VBAT_SHR ITRK_DEAD SOURCE PHASE VBATH VBATL ISOURCE SINK PHASE Data Sheet ADP5350 Battery Temperature from I2C If a microcontroller has another accuracy temperature sense in system, it can select the temperature source via the I2C setting and write the temperature value to the BAT_TEMP[5:0] bits. The I2C source battery temperature range is between -2C and +61C. JEITA Li-Ion Battery Temperature Charging Specification The charge of the ADP5350 is compliant with the JEITA Li-Ion battery charging temperature specifications, as shown in Table 14. The JEITA function is enabled via the I2C interface. When the ADP5350 detects a JEITA cool condition, charging current is reduced according to Table 13. When the ADP5350 identifies a hot or cold battery condition, the battery isolation FET turns on and the dc-to-dc regulator shuts down. In this condition, the battery provides the VISOS supply. Table 13. JEITA Cool Temperature Limit--Reduced Charge Current Levels ICHG[3:0] 0000 = 25 mA 0001 = 50 mA 0010 = 75 mA 0011 = 100 mA 0100 = 125 mA 0101 = 150 mA 0110 = 200 mA 0111 = 250 mA 1000 = 300 mA 1001 = 350 mA 1010 = 400 mA 1011 = 450 mA 1100 = 500 mA 1101 = 550 mA 1110 = 600 mA 1111 = 650 mA ICHG JEITA (mA) ILIM_JEITA_COOL = 0 ILIM_JEITA_COOL = 1 25 25 25 25 25 25 50 25 50 25 75 25 100 25 125 25 150 50 175 50 200 50 225 50 250 50 275 50 300 50 325 50 Table 14. JEITA Default Li-Ion Battery Charging Specifications Parameter JEITA Cold Temperature Limits JEITA Cool Temperature Limits Symbol TJEITA_COLD TJEITA_COOL JEITA Typical Temperature Limits JEITA Warm Temperature Limits TJEITA_TYP TJEITA_WARM JEITA Hot Temperature Limits TJEITA_HOT Conditions No battery charging occurs. Battery charging occurs at approximately 50% or 10% of programmed level. See Table 13 for specific charging current reduction levels. Normal battery charging occurs at default/programmed levels. Battery termination voltage (VTRM) is reduced by 100 mV from the programmed value. No battery charging occurs. Rev. B | Page 25 of 63 Min 0 Max 0 10 Unit C C 10 45 45 60 C C 60 C ADP5350 Data Sheet BATTERY CHARGER OPERATIONAL FLOWCHART POWER-ON RESET NO RESET ALL REGISTERS YES VBUSOK YES RUN BATTERY DETECTION YES FAST CHARGE NO VBUS OK YES VBSNS < VTRK YES NO IVIN < ILIM YES tWD TEMP < TLIM EXPIRED IBUSLIM = HIGH IVIN = ILIM NO THERMLIM = HIGH TEMP = TLIM YES tSAFE /tTRK tWD EXPIRED YES EXPIRED WATCHDOG EXPIRED START tSAFE ILIM = 100mA NO NO RUN BATTERY DETECTION NO YES NO TIME FAULT/ BAD BATTERY NO YES YES WATCHDOG EXPIRED START tSAFE ILIM = 100mA NO POWER DOWN NO VBSNS < VTRK TRICKLE CHARGE VBUS OK tSTART EXPIRED tSAFE /tCHG YES YES EXPIRED TIME FAULT/ BAD BATTERY (SEE SAFETY TIMER SECTION) NO YES NO VBSNS VRCH VBSNS = VTRM VBSNS 3.5V NO CC MODE CHARGING NO CV MODE CHARGING NO YES CHARGE COMPLETE IOUT < IEND 14797-026 YES Figure 43. ADP5350 Charger Operational Flowchart BATTERY VOLTAGE-BASED FUEL GAUGE Operation Mode Overview The ADP5350 fuel gauge, in shut down mode by default, provides extremely low standby current consumption from the battery. After the fuel gauge function is enabled, two operation modes can be selected: active mode and sleep mode. The fuel gauge operation mode is controlled by the I2C. The ADP5350 Li-Ion battery fuel gauge is based on the voltage measurement with a 12-bit ADC. SOC is calculated with a battery model integrated in the ADP5350. Ten voltage values based on the battery characterization and the battery internal resistance at different temperatures must be written to the V_SOC_x register and RBAT_x register of the ADP5350 for SOC calculation. In active mode, the battery SOC is updated every 1 sec by the sensed battery voltage, which achieves better accuracy and indicates the remaining battery capacity but consumes 160 A Rev. B | Page 26 of 63 Data Sheet ADP5350 ADC Sample Rate None 37.5 sec 0.125 sec SOC Update Rate None 5 min 1 sec Battery Voltage Compensation The battery internal resistance impacts the accuracy of a traditional voltage-based SOC. A higher load current translates to a higher voltage drop (VDROP) over the internal resistance, RBAT (see Figure 44). ISOS TO SYSTEM 3.0 2.5 2.0 1.5 1.0 0.5 0 RDSON 0 10 20 30 40 BATTERY TEMPERATURE (C) Figure 45. RBAT Temperature Coefficient vs. Battery Temperature, Temperature Coefficient of the Li-Ion Battery, Relative to Battery RBAT at 25C + - 14797-027 BATTERY RESISTANCE VDROP = RBAT x IBAT Figure 44. Discharge Current Sensing Through Battery Isolation FET The ADP5350 uses the battery isolation FET for battery discharge current sensing. The device senses the ISOS and ISOB node voltages to obtain the delta voltage. Divide the delta voltage by RDSON to achieve the discharge current, which can be used for SOC calculation compensation. The voltage reading from the BSNS pin is compensated using the following equation and can be read in the VBAT_READ_H and VBAT_READ_L registers. VBAT = VBSNS + RBAT x IBAT where: VBSNS is the voltage on the BSNS pin. RBAT is the internal resistance of the battery. IBAT is the current through the battery. In addition, the internal resistance of the battery has a remaining capacity dependency, especially when the SOC is less than 20%. The ADP5350 allows the user to program different internal resistance coefficients when the SOC is in the 20% to 0% range during a discharge by programming the corresponding bits, K_RBAT_SOC (see Figure 46). 10 1 x 20% SOC 2 x 20% SOC 4 x 20% SOC 8 x 20% SOC RBAT SOC COEFFICIENT ISOB When the battery is charging, IBAT is the charging current. 5 0 During the battery discharges, IBAT is calculated by the voltage sense on the isolated FET. The internal resistance of the battery has strong temperature dependency. Figure 45 shows the internal resistance temperature coefficient using a 280 mAh, 3.7 V Li-Ion cell battery. Rev. B | Page 27 of 63 0 20 40 60 80 100 BATTERY SOC (%) Figure 46. RBAT SOC Coefficient vs. Battery SOC, SOC Coefficient of the Li-Ion Battery, Relative to Battery RBAT at 25C 14797-029 Current (Typical) 0.2 A 4 A 160 A It is strongly recommended to use the I2C bits, BAT_TEMP, to obtain an accurate battery temperature if the system has such temperature sense information. If using the ADP5350 internal sense circuitry as the temperature source, only four temperature levels for battery resistance compensation are available, which may cause errors in the SOC calculation relating to the battery resistance temperature coefficient. 14797-028 Table 15. Fuel Gauge Operation Mode Operation Mode Shutdown Sleep Active The ADP5350 contains I2C registers to calculate the RBAT value, where the user can program the battery internal resistance characterized from the battery at certain temperatures. The ADP5350 uses this data to calculate the battery internal resistance at different temperatures. RBAT TEMPERATURE COEFFICIENT (typical) of operation current. In sleep mode, the battery SOC is updated every 5 min and the battery instant current (IINS) is updated every 37.5 sec, which reduces the current to typically 4 A (see Table 15). The ADP5350 automatically switches from sleep mode to active mode when the current through the isolation FET is higher than typically 35 mA. The system current must be less than 35 mA when switching to sleep mode. Depending on the system load, the mode can be switched to active mode to achieve better SOC accuracy. ADP5350 Data Sheet For some batteries, the internal resistance is different when the battery is in charge vs. discharge mode. Use the K_RBAT_ CHARGE bits to program the battery internal resistance coefficient when charging. When the fuel gauge is enabled, the SOC value is reset based on the current battery voltage and internal resister compensation, without any initial filter effects. Repeatedly disabling and enabling the fuel gauge or setting Register 0x25, Bit 7 to reset the SOC value during a battery discharge increases errors in SOC calculation. It is recommended that the SOC be reset only when there is no discharge current and the battery voltage is in a completely relaxed state; that is, the battery voltage is stable. State of Charge Limit Filter To avoid impacting SOC accuracy caused by the effects of a battery discharge and the instantaneous interference on the battery current sense, the ADP5350 uses filter limitation for delta SOC calculation of each step. The filter limitation can be selected from a 0.125 C rate to a 3 C rate via I2C programming, which is equal to or greater than real system current consumption (the C rate is the battery charge or discharge current rate over the battery capacity). For example, when the full system load is 60 mA with 300 mAh, and the discharge current rate is 0.2 C, the filter limitation can be programmed to 0.25 C using the FILTER_DISCHARGE bits. During sleep mode, the filter limitation is reduced because the ADP5350 outputs a low discharge current. FLOWCHART OF SOC CALCULATION See Figure 47 for a flowchart of the SOC calculation. Down_Lim is the delta SOC in each step when the SOC reduces. Up_Lim is the delta SOC in each step when the SOC increases. ENABLE FUEL GAUGE first_start = True READ VBAT (12-BIT) YES NO SAMPLE TIMER OUT? CALCULATE THE RBAT MULTIPLY RBAT WITH CHARGING COEFFICIENT CHARGE IBAT > 25mA DISCHARGE IBAT < -25mA CALCULATE IBAT IDLE -25mA < I BAT < 25mA COMPENSATE VBAT TO VOCV COMPENSATE VBAT TO VOCV COMPENSATE VBAT TO VOCV FILTER LIMITS Up_Lim = FILT_CHARGE Down_Lim = 0 FILTER LIMITS Down_Lim = FILT_IDLE Up_Lim = 0 FILTER LIMITS Down_Lim = FILT_DISCHARGE Up_Lim = 0 CALCULATE SOC BASED ON VOCV YES first_start NO YES New_SOC = Old_SOC - Down_Lim New_SOC < Old_SOC - Down_lim New_SOC > Old_SOC NO NO YES New_SOC > Old_SoC + Up_lim New_SOC = Old_SOC YES New_SOC = Old_SOC + Up_Lim UPDATE New_SOC TO SOC REGISTER Figure 47. ADP5350 SOC Calculation Flowchart Rev. B | Page 28 of 63 14797-030 NO first_start = False Data Sheet ADP5350 BOOST AND WHITE LED DRIVERS The ADP5350 integrates a powerful 1.5 MHz frequency boost regulator with programmable LED control. Different LED configurations, like LEDs in parallel or LEDs in serial, are supported with careful design. Up to five LED strings are independently programmable up to 20 mA (typical) in 64 levels. All LED strings can be individually programmed or combined into a group to operate as the backlight LEDs or individual LED current sinks. A full suite of safety features, including current-limit, overvoltage, LED open-circuit, and overtemperature protection, allows a robust and safe design. The integrated soft start limits inrush currents during start-up and restart attempts. White LED Driver White LEDs are common in backlighting the displays of modern portable devices. White LEDs require a high forward voltage, VF (typically 3.3 V), before conducting current and emitting light. Display panels, depending on the size, can be backlit with multiple white LEDs in series or in parallel. The LEDs need a common current passing through all of them to achieve uniform brightness. The LED, however, must be biased with a voltage greater than the sum of each LED VF voltage before it can conduct. The ADP5350 integrates a 1.5 MHz boost regulator to power the LED bias voltage. If the LED forward voltage plus the current sink headroom voltage is higher than the battery voltage, the boost regulator turns on. If the battery voltage is higher than the sum of the LED forward voltage plus the required current sink headroom voltage, the boost regulator operates in passthrough mode. The ADP5350 uses an integrated negative channel field effect transistor (NFET) low-side current regulator for accurate brightness control, with up to five channels of current sink. The ADP5350 supports setting different LED currents for each LED string. Any mismatch in the forward voltage of the LEDs translates directly to lower efficiency, as well as lower accuracy of the current for the lower voltage LED string. The boost regulator in the ADP5350 has two operation modes, LED operation mode and boost standalone operation mode, which can be selected via the I2C-compatible interface. by any active LED current source. The EN_BST bit is not effective in this mode. Because the LED bias voltage may be coming from the battery system voltage instead of the boost output voltage (for example, LED indicators with relatively low forward voltage), those LEDs can be used in individual current sink channels by using the battery system voltage as the LED bias voltage. Use the BST_BL bit in the BST_CFG register to determine whether the bias voltage for individual current sink channels is coming from the boost regulator output or from the battery system voltage. Write 0 to BST_BL to set the boost regulator to provide the bias voltage for all active LED channels. In this configuration, the boost regulator provides the adaptive headroom regulation according to all active LED current sources, including both backlight and individual current sinks. Write 1 to BST_BL to set the boost regulator to provide the bias voltage only for the active LED backlight channels, excluding individual current sink. The bias voltage for an individual LED sink can be from the battery system voltage or from some other fixed rail; therefore, the headroom status in individual LED sinks does not affect the boost output regulation. BST_BL must be set to 1 when the indicator LED is connected to the battery system voltage instead of the boost output voltage; otherwise, the boost voltage may risk an overvoltage. The adaptive headroom control in the boost regulator may include individual LED channels whose bias voltage is not coming from the boost regulator. The boost feedback pin (FB4 pin) is tied to ground in LED operation mode. Boost Standalone Operation Mode When the boost regulator is used to provide the fixed output voltage for other system uses, including organic light emitting diode (OLED) backlight, audio system, or other auxiliary circuitries, the boost regulator must be configured in standalone operation mode by setting BST_MODE = 1 in the BST_CFG register. It is recommended that total output power be limited below 800 mW when the boost peak current is set to 600 mA. In standalone operation mode, the boost regulator provides the adjustable output voltage, VOUT4, configured by the external resistor divider. VOUT4 = VFB4 x (RFB1 + RFB2)/RFB2 LED Operation Mode When the boost regulator is required to provide a higher output voltage to the LED bias voltage, the boost regulator must be configured in LED operation mode by setting BST_MODE = 0 in the BST_CFG register. The activation status of the boost regulator is determined by the EN_BST bit in the BST_CFG register. In boost standalone operation mode, all LED functions are turned off and not allowed. In LED operation mode, the boost regulator provides the adaptive LED bias voltage with adaptive headroom regulation to optimize the system efficiency against LED forward voltage variation and aging. The boost regulator is attached to the LED current source control and, therefore, is automatically activated In standalone operation mode, the boost feedback pin (FB4 pin) must be tied to the boost output through an external resistor divider. Rev. B | Page 29 of 63 ADP5350 Data Sheet Figure 48 shows the typical boost regulator diagram in standalone operation. Table 16 summarizes the difference between LED operation mode and standalone operation mode. Table 16 provides four programmable OVP thresholds according to the boost output voltage. The various OVP thresholds provide different internal compensation depending on the boost output voltage. It strongly recommended to select the proper OVP level related to the set output voltage. C9 4.7F ADP5350 VOUT4 BOOST REGULATOR VISOS L2 SW4 4.7H VOUT4 (UP TO 16V) FB4 RFB1 C10 10F Soft Start The boost regulator in the ADP5350 includes soft start circuitry that ramps the output voltage in a controlled manner during startup, thereby limiting the inrush current of the battery. The soft start time is typically fixed at 1 ms for the boost regulator. Backlight Current Settings The backlight current setting is determined by a 6-bit code programmed by the user via the IBL_SET[5:0] bits. This 6-bit code allows the user to set the backlight to one of 64 levels between 0 mA and 20 mA. The ADP5350 uses a square law algorithm for the 64 levels, where the backlight current increases linearly for a corresponding increase of input code. The backlight current, in milliamperes (mA), is determined by the following equations: OLED (OR OTHER LOAD) RFB2 D1 Full-Scale Current Backlight Current (mA) = Code x 63 D2 LED DRIVER D3 D4 AGND 14797-031 D5 PGND4 2 where: Code is the input code programmed by the user. Full-Scale Current is the maximum sink current allowed (typically, 20 mA). 25 Operation Activation Control Output Regulation LED Operation Mode Activated by active LED EN_LEDx Adaptive to LED VF voltage variation FB4 Pin Tied to ground OVP 5.6 V, 10 V, 15 V, or 18.5 V threshold on the VOUT4 pin Standalone Operation Mode Activated by EN_BST Fixed and determined by external resistor divider Tied to boost output via resistor divider 5.6 V, 10 V, 15 V, or 18.5 V threshold on the VOUT4 pin PGOOD Indicator of Boost Output In boost standalone mode, the PGOOD pin can be programmed to indicate whether the boost PGOOD signal is output to the external PGOOD pin by setting the PG4_BST_MASK bit high in Register 0x37. The ADP5350 monitors the FB4 pin voltage, and asserts the PGOOD signal high when the FB4 pin voltage reaches up to 90% of the typical voltage with a typical 2 ms deglitch time. The PGOOD signal asserts low when the FB4 pin voltage drops to 86.5% of the typical voltage. The boost output PGOOD status can be read via the I2C interface, Register 0x36, Bit 1. 20 15 10 5 0 0 10 20 30 40 50 60 SINK CURRENT CODE 70 14797-032 Table 16. Two Operation Modes for the Boost Regulator BACKLIGHT CURRENT (mA) Figure 48. Boost Regulator in Standalone Operation Mode Figure 49. Backlight Current vs. Sink Current Code Backlight Linear Fade In and Fade Out When the ADP5350 operates in normal operation, the backlight can be turned on using the EN_BL bit. The backlight turns on when EN_BL = 1, and turns off when EN_BL = 0. To prevent abrupt turn on and turn off of the backlight, the ADP5350 contains timers to facilitate smooth fading between the turn on and turn off states. Fading is implemented using the square law backlight code algorithm. The BL_FI timer and BL_FO timer in the BL_FR register can be used for smooth fade in transitions from a low to high backlight setting. The BL_FI timer and BL_FO timer can be programmed to one of 15 settings ranging from 0.3 sec to 4.5 sec. The timer must be programmed before asserting EN_BL. Rev. B | Page 30 of 63 Data Sheet ADP5350 The time programmed in the BL_FI timer and BL_FO timer represents the time it takes the backlight current to go from 0 mA to 20 mA. Therefore, the fading time between intermediate settings is shorter. Smaller changes in current reduces the fade time. For square law fades, the fade time is given by BACKLIGHT CURRENT FADE IN OVERRIDDEN FADE OUT OVERRIDDEN MAX where the Fade Rate is as shown in Table 17. Table 17. Available Fade In and Fade Out Times Fade Rate (sec) Fade in or fade out disabled 0.3 0.6 0.9 1.2 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 EN_BL = 0 EN_BL = 1 (REASSERTED BY USER) EN_BL = 1 (REASSERTED BY USER) Figure 50. LED Backlight Fade Override Independent Sink Controls The LED current sink in Channel 2 to Channel 5 can be configured to operate as either part of a grouped backlight, or to operate as an independent LED channel. Setting BL_LEDx = 1 configures the selected LED channel (Channel 2 to Channel 5) as the part of a grouped backlight. In this setting, the backlight current setting and on/off control in Channel 1 apply to the configured channel. Setting BL_LEDx = 0 configures the selected LED channel (Channel 2 to Channel 5) as an independent current sink channel. Each channel current and on/off control are determined by independent register settings. Individual LED Blinking Timer Backlight Fade Override The independent current sinks in Channel 3, Channel 4, and Channel 5 have additional timers to facilitate the blinking functions. The on timer and the off timer in the LEDx_BLINK register allow individual LED current sinks to be configured in various blinking modes. Blink mode can be activated by setting the off timers to any setting other than disabled. The blink mode setting has no effect if the channel is configured as part of a grouped backlight. A fade override feature allows the BL_FI and BL_FO timers to be overridden when the EN_BL bit is reasserted during a fade in or fade out period and to set the backlight to its targeted current setting value immediately (see Figure 50). Setting the FOVR bit to 1 in the BST_CFG register enables the backlight fade override feature. The fade in and fade out function is effective in blink mode but the fade override feature is not effective in blink mode. See Figure 51 for a timing diagram of LED blinking with fading. Some applications (for example, red/green/blue (RGB) LEDs in blink mode) need the blinking timer to be in synchronization. If the blinking LEDs are enabled in the same I2C command, the rising time of the on timer for each blinking LED is synchronized. ILEDx_SET FADE IN ON TIME FADE OUT OFF TIME FADE IN ON TIME FADE OUT TIME EN_LEDx Figure 51. LED Blinking with Fading Rev. B | Page 31 of 63 14797-034 Code 0000 0001 0010 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 EN_BL = 0 EN_BL = 1 14797-033 Fade Time = Fade Rate x (Code/63) ADP5350 Data Sheet LEDs in Parallel C9 4.7F C9 4.7F ADP5350 SW4 VOUT4 BOOST L2 4.7H ADP5350 VOUT4 BOOST VISOS D1 D3 D4 D5 15mA D2 15mA D3 AGND PGND4 AGND BACKLIGHT 2mA D5 LED STRIP OR INDICATOR Figure 52 shows three LEDs in parallel (15 mA each), in grouped backlight configuration, connected to D1, D2, and D3, and one additional LED indicator (2 mA) connected to D5. 2. 3. 4. 5. C10 4.7F 15mA PGND4 30mA D1 30mA D2 15mA 15mA 15mA BACKLIGHT 2mA D5 LED STRIP OR INDICATOR Figure 53. Two LEDs in Parallel (30 mA each) for Grouped Backlight and One LED Strip or Indicator (2 mA) Figure 52. Thee LEDs in Parallel for Grouped Backlight and One LED Strip or Indicator 1. D4 D5 14797-035 D2 D1 D3 LED DRIVER D1 VISOS VOUT4 (UP TO 5.6V) D2 C10 4.7F 15mA L2 4.7H FB4 VOUT4 (UP TO 5.6V) FB4 LED DRIVER SW4 14797-036 Different configurations, for example, LEDs in series or LEDs in parallel, can be supported by ADP5350. Configure the boost regulator as follows: a. Set BST_MODE = 0 to configure the boost regulator in LED operation mode. b. Set BST_BL = 0 to configure the boost regulator to provide the bias voltage to all current sink channels. c. Set BST_OVP = 1 to configure the boost OVP threshold = 5.6 V. Configure the grouped backlight as follows: a. Set BL_LED2 = 1 and BL_LED3 = 1 to configure D1 to D3 as the grouped backlight. b. Set IBL[5:0] = 15 mA for the LED grouped backlight current. c. Set the BL_FI and BL_FO code for the fade in and fade out timer (if required). d. Set FOVR = 1 to enable the fading overwritten feature (if required). Configure the individual current sink as follows: a. Set ILED5 = 2 mA for the D5 sink current. b. Set the LED5_ON and LED5_OFF code for the blinking timer (if required). Set EN_BL = 1 to enable the LED backlight. Set EN_LED5 = 1 to enable the LED indicator. Figure 53 shows two LEDs in parallel (30 mA each), in grouped backlight configuration, connected from D1 to D4, and one additional LED indicator (2 mA) connected to D5. 1. 2. 3. 4. 5. Rev. B | Page 32 of 63 Configure the boost regulator as follows: a. Set BST_MODE = 0 to configure the boost regulator in LED operation mode. b. Set BST_BL = 0 to configure the boost regulator to provide the bias voltage to all current sink channels. c. Set BST_OVP = 1 to configure the boost OVP threshold = 5.6 V. Set EN_BL bit = 1 to enable the LED backlight. Configure the grouped backlight as follows: a. Set BL_LED2 = 1, BL_LED3 = 1, and BL_LED4 = 1 to configure D1 to D4 as the grouped backlight. b. Set IBL[5:0] = 15 mA for the LED grouped backlight current (two channels in parallel with 30 mA for each LED current). c. Set the BL_FI and BL_FO code for the fade in and fade out timer (if required). d. Set FOVR = 1 to enable the fading overwritten feature (if required). Configure the individual current sink as follows: a. Set ILED5 = 2 mA for the D5 sink current. b. Set the LED5_ON and LED5_OFF code for the blinking timer (if required). Set EN_BL = 1 to enable the LED backlight. Set EN_LED5 = 1 to enable the LED indicator. Data Sheet ADP5350 LED in Series As the battery discharges, the lower battery voltage results in higher peak current through the battery ESR, which may cause early shutdown of other devices on the battery. The programmable current threshold can be used to change the current limit according to different battery voltages. The ADP5350 supports connecting LEDs in series (see Figure 54 for an example). ADP5350 SW4 VOUT4 BOOST C9 4.7F L2 4.7H C10 4.7F 15mA D2 D1 D2 D3 D4 D3 LED DRIVER Overvoltage Fault VOUT4 (UP TO 17.5V) FB4 D1 VISOS D4 VISOS 2mA AGND PGND4 D6 LED STRIP OR INDICATOR 14797-037 D5 Figure 54. Four LEDs in Series (15 mA Each) for Grouped Backlight Connected to D1, and One LED Strip or Indicator (2 mA) in D5 with Connection to VISOS Rail The boost regulator contains OVP circuits to prevent damage if the VOUT4 voltage becomes excessive for any reason. To keep a safe output level, the integrated OVP circuit monitors the VOUT4 voltage. When the VOUT4 voltage exceeds the OVP rising threshold, the boost regulator stops switching, causing the output voltage to drop. When the VOUT4 voltage goes lower than the OVP falling threshold, the boot regulator begins switching, causing the output to rise. The overvoltage threshold is programmable (default of 18.5 V) in the BST_OVP register. Figure 54 shows four LEDs in series (15 mA each), in grouped backlight configuration, connected to D1, and one additional LED indicator (2 mA) connected to D5 and the VISOS rail. The overvoltage threshold level must be programmed according to the output voltage because the various OVP thresholds provide different internal compensation depending on the boost output voltage. 1. LED Open-Circuit Protection 2. 3. 4. 5. Configure the boost regulator as follows: a. Set BST_MODE = 0 to configure the boost in LED operation mode. b. Set BST_BL = 1 to configure the boost to provide the bias voltage to the LED backlight only. c. Set BST_OVP = 0 to configure the boost OVP threshold = 18.5 V. Configure the grouped backlight as follows: a. Set IBL[5:0] = 15 mA for the LED backlight current. b. Set the BL_FI and BL_FO code for the fade in and fade out timer (if required). c. Set FOVR = 1 to enable the fading overwritten feature (if required). Configure the individual current sink as follows: a. Set ILED5 = 2 mA for D5 sink current. b. Set the LED5_ON and LED5_OFF code for the blinking timer (if required). Set EN_BL = 1 to enable the LED backlight. Set EN_LED5 = 1 to enable the LED indicator. Boost Switching Frequency The boost regulator of the ADP5350 operates in 1.5 MHz fixed switching frequency and it is synchronized with the switching frequency in battery charger. Boost Current Limit The boost regulator in the ADP5350 includes the peak currentlimit protection circuitry to limit the amount of positive current flowing through the battery to the output. Two current-limit thresholds (600 mA or 300 mA) can be selected using the BST_IPK bit. The programmable current-limit threshold feature allows the use of a small size inductor for low power applications. The LED circuit contains a headroom control circuit to minimize power loss at each current source. Therefore, the minimum feedback voltage is achieved by regulating the output voltage of the boost regulator. If any LED string is opened during normal operation, the current source headroom voltage is pulled to AGND. In this condition, LED open-circuit protection activates when the voltage on the Dx pin is less than 200 mV and the VOUT4 voltage rises to the OVP level. If LED open-circuit protection is triggered, the open LED channel turns off while the other LED channel continues to work, and the LEDx_OPEN bit is set to 1 in the LED_STATUS register. The open LED channel remains disabled to ensure protection against a potential LED open circuit, until the processor clears the fault register by rewriting a 1 to the fault bit or the ADP5350 is power cycled. When one channel is selected for independent LED operation and the bias voltage is separate from the LED backlight group (BST_BL = 1), the LED open-circuit protection has no effect on this channel due to the boost OVP never being detected on this channel. LINEAR LOW DROPOUT (LDO) REGULATORS The ADP5350 integrates three LDO regulators. LDO1 is a low quiescent current LDO that can be used as a supply that is always on for the system. LDO2 and LDO3 are general-purpose LDO regulators. All LDO input power rails are supplied from the VIN123 pin and share the input power of the control circuits with the VIN4 pin. Thus, the VIN123 pin must be tied to the VIN4 pin in all applications. The LDO regulator operates with an input voltage range of 2.7 V to 5.5 V. The wide supply range makes the regulator suitable for cascading configurations where the LDO supply Rev. B | Page 33 of 63 ADP5350 Data Sheet voltage is provided from the system voltage. The LDO output voltage is set by the factory fuse or I2C. THERMAL MANAGEMENT The LDO regulator provides a high power supply rejection ratio (PSRR), low output noise, and excellent line and load transient response with small 1 F ceramic input and output capacitors. To assist with the thermal management of the ADP5350 charger, the battery charger provides an isothermal charging function. As the on-chip power dissipation and die temperature increase, the ADP5350 charger monitors the die temperature and limits the output current when the temperature reaches TSD_W. The die temperature is maintained at TSD_W through the control of the charging current into the battery. A reduction in power dissipation or ambient temperature may allow the charging current to return to its original value, and the die temperature subsequently drops below TSD_W. During isothermal charging, the THERM_LIM flag is set to high. The LDO1, LDO2, and LDO3 fixed output voltages are set by the factory fuse and include the following options: 1.0 V, 1.1 V, 1.2 V, 1.3 V, 1.4 V, 1.5 V, 1.8 V, 2.1 V, 2.3 V, 2.5 V, 2.85 V, 3.0 V, 3.15 V, 3.3 V, 3.6 V, and 4.2 V. Load Switch Mode All LDO regulators can be configured as a load switch via the I2C. The load switch allows power domain isolation and helps to extend the battery life. LDO Output Discharge Each LDO has an output discharge feature that can be selected by the I2C. When the output discharge feature is enabled, the selected LDO output connects the internal 500 load to ground and pulls down the output voltage quickly when the LDO channel is disabled. PGOOD Indicator of LDO1 Output The ADP5350 PGOOD pin can mask various power-good channels, including LDO1, the boost regulator, and VVBUSx by setting Register 0x37, Bit 0. When the PGOOD pin masks the LDO1 power-good output and enables LDO1, the PGOOD pin indicates the LDO1 output voltage power-good signal, and asserts high when the VOUT1 pin voltage reaches up to 90% of the typical voltage with a typical 2 ms deglitch time. The PGOOD signal asserts low when the VOUT1 pin voltage drops to 86.5% of the typical voltage. Isothermal Charging and Thermal Early Warning The early warning bit is set if TSD_W is exceeded. This warning bit allows the system to accommodate power consumption before thermal shutdown occurs. Thermal Shutdown The ADP5350 switching charger features a thermal shutdown threshold detector. If the die temperature exceeds TSD, the ADP5350 charger is disabled, and the TSD_140 bit is set. The ADP5350 charger can be reenabled when the die temperature drops below the TSD falling limit and the TSD_140 bit is reset. To reset the TSD_140 bit, write to the I2C Fault Register 0x0A or cycle the power. Fault Recovery Before performing the following operation, it is important to ensure that the cause of the fault is rectified. To reset the fault bits in the CHARGER_FAULT register, cycle the power on VBUSx or write the corresponding I2C bit high. The default setting of the PG1_LDO1_MASK is a factory fuse trim that is programmable. The LDO1 power-good status can be read via the I2C interface, using Register 0x36, Bit 0. Rev. B | Page 34 of 63 Data Sheet ADP5350 I2C INTERFACE The subaddress content selects the ADP5350 registers to be written to first. The ADP5350 sends an acknowledgement to the master after the 8-bit data byte is written (see Figure 55 for an example of the I2C write sequence to a single register). The ADP5350 increments the subaddress automatically and starts receiving a data byte at the next register until the master sends an I2C stop as shown in Figure 56. The ADP5350 includes an I2C-compatible serial interface to control the battery charging, fuel gauge, boost regulator, and LED driver, and to read back the system status. I2C ADDRESSES The I2C address can be factory programmable. The I2C address options help to avoid conflicts with other I2C slave chipsets in the system. For alternative I2C chip address requirements, contact a local Analog Devices sales or distribution representative. Figure 57 shows the I2C read sequence of a single register. The ADP5350 sends the data from the register denoted by the subaddress and increments the subaddress automatically, sending data from the next register until the master sends an I2C stop condition as shown in Figure 58. SDA AND SCL PINS The ADP5350 has two dedicated I2C interface pins, SDA and SCL. SDA is an open-drain line for receiving and transmitting data. SCL is an input line for receiving the clock signal. Pull up these pins to an external input/output supply using external resistors. DEFAULT RESET The ADP5350 contains one write only register, DEFAULT_SET, to reset all registers to the factory default values. Serial data is transferred on the rising edge of SCL. The read data is generated at the SDA pin in read mode. MASTER STOP 1 0 1 0 0 0 0 0 CHIP ADDRESS 0 SUBADDRESS SP ADP5350 ACK 0 ADP5350 ACK 0 ADP5350 ACK ST ADP5350 RECEIVES DATA 14797-038 0 = WRITE Figure 55. I2C Single Register Write Sequence 1 0 0 0 0 0 CHIP ADDRESS SUBADDRESS REGISTER N ADP5350 RECEIVES DATA TO REGISTER N 0 0 0 ADP5350 RECEIVES DATA TO REGISTER N + 1 ADP5350 RECEIVES DATA TO LAST REGISTER SP ADP5350 ACK 0 ADP5350 ACK 1 ADP5350 ACK 0 ADP5350 ACK 0 ADP5350 ACK ST MASTER STOP 14797-039 0 = WRITE Figure 56. I2C Multiple Register Write Sequence 1 = READ 0 CHIP ADDRESS 0 0 0 0 0 0 0 0 0 1 1 0 ST 0 0 1 SUBADDRESS 0 1 0 0 CHIP ADDRESS 1 1 0 ADP5350 SENDS DATA SP 14797-040 1 ADP5350 NO ACK 0 ADP5350 ACK 1 0 ADP5350 ACK 0 ST ADP5350 ACK 0 = WRITE Figure 57. I2C Single Register Read Sequence 0 0 CHIP ADDRESS 0 0 0 SUBADDRESS REGISTER N S T 0 0 1 0 1 0 0 CHIP ADDRESS 1 0 0 ADP5350 SENDS DATA OF REGISTER N Figure 58. I2C Multiple Register Read Sequence Rev. B | Page 35 of 63 0 0 ADP5350 SENDS DATA OF REGISTER N+1 1 ADP5350 SENDS DATA OF LAST REGISTER MASTER ACK 1 MASTER ACK 0 MASTER ACK 1 ADP5350 ACK 0 ADP5350 ACK 0 ADP5350 ACK S T MASTER STOP S P 14797-041 1 = READ 0 = WRITE ADP5350 Data Sheet INTERRUPTS The ADP5350 provides an interrupt output (the INT pin) for fault conditions. During normal operation, when the INT pin is pulled high, use an external pull-up resistor. When a fault condition occurs, the ADP5350 pulls the INT pin low to alert the I2C host that a fault condition occurred. Many different interrupt sources can trigger the INT pin. By default, no interrupt sources are configured. To select one or more interrupt sources to trigger the INT pin, set the appropriate bits to 1 in the CHARGER_INTERRUPT_ENABLE register and the BOOST_LDO_INTERRUPT_ENABLE register. When the INT pin is triggered, one or more bits in the CHARGER_INTERRUPT_FLAG register and the BOOST_ LDO_INTERRUPT_FLAG register are set to 1. The fault condition that triggered the INT pin can be read from the CHARGER_INTERRUPT_FLAG register and the BOOST_ LDO_INTERRUPT_FLAG register. To clear an interrupt, read the appropriate bit in the CHARGER_INTERRUPT_FLAG register and the BOOST_ LDO_INTERRUPT_FLAG register, or power cycle the ADP5350. Rev. B | Page 36 of 63 Data Sheet ADP5350 CONTROL REGISTER MAP Table 18. Register Map Address (Hex) 0x00 D7 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 Register Name Manufacture and model ID Silicon revision CHARGER_ VBUS_ILIM CHARGER_ TERMINATION_ SETTING CHARGER_ CURRENT_ SETTING CHARGER_ VOLTAGE_ THRESHOLD CHARGER_ TIMER_SETTING CHARGER_ FUNCTION_ SETTING1 CHARGER_ STATUS1 CHARGER_ STATUS2 CHARGER_ FAULT BATTERY_ SHORT BATTERY_ THERMISTOR_ CONTROL V_SOC_0 V_SOC_5 V_SOC_11 V_SOC_19 V_SOC_28 V_SOC_41 V_SOC_55 V_SOC_69 V_SOC_84 V_SOC_100 FILTER_ SETTING1 FILTER_ SETTING2 RBAT_0 RBAT_10 RBAT_20 RBAT_30 RBAT_40 RBAT_60 K_RBAT_CHARGE BAT_TEMP 0x21 0x22 0x23 BAT_SOC VBAT_READ_H VBAT_READ_L Not used 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 D6 D5 MANUF[3:0] D4 D3 D2 Not used Not used D1 Model[3:0] D0 REV[3:0] ILIM[3:0] VTRM[5:0] C_20_EOC Not used IEND[1:0] C_10_EOC ICHG[3:0] VRCH[1:0] VTRK_DEAD[1:0] Not used EN_TEND EN_JEITA DIS_IPK_SD EN_CHG_ TIMER EN_BMON VBUS_OV Not used VBUS_ILIM THR_STATUS[2:0] Not used EN_WD WD_PERIOD RESET_WD EN_EOC EN_TRK EN_CHG EN_THR EN_DCDC THERM_ LIM IPK_STAT CHDONE CHARGER_STATUS[2:0] Not used BATTERY_STATUS[2:0] BAT_SHR TBAT_SHR[2:0] TBAT_LOW VWEAK[2:0] CHG_TMR_PERIOD Not used ILIM_JEITA_ COOL ITRK_DEAD[1:0] IND_PEAK Not used TBAT_ HIGH TSD_140 VBAT_SHR[2:0] R_NTC BETA_NTC[3:0] V_SOC_0[7:0] V_SOC_5[7:0] V_SOC_11[7:0] V_SOC_19[7:0] V_SOC_28[7:0] V_SOC_41[7:0] V_SOC_55[7:0] V_SOC_69[7:0] V_SOC_84[7:0] V_SOC_100[7:0] Not used FILTER_CHARGE[2:0] TSD_130 FILTER_DISCHARGE[2:0] Not used FILT_IDLE[1:0] RBAT_0[7:0] RBAT_10[7:0] RBAT_20[7:0] RBAT_30[7:0] RBAT_40[7:0] RBAT_60[7:0] Not used Not used BAT_TEMP_ SOURCE K_RBAT_SOC[1:0] K_RBAT_CHARGE[3:0] BAT_TEMP[5:0] BAT_SOC[6:0] VBAT_READ[12:5] VBAT_READ[4:0] Rev. B | Page 37 of 63 Not used ADP5350 Address (Hex) 0x24 Data Sheet Register Name FUEL_GAUGE_ MODE D7 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x02C 0x2D 0x2E 0x2F 0x30 0x31 SOC_RESET BST_LED_CTRL BST_CFG IBL_SET ILED2_SET ILED3_SET ILED4_SET ILED5_SET BL_FR LED3_BLINK LED4_BLINK LED5_BLINK LED_STATUS SOC reset 0x32 0x33 LDO_CTRL LDO_CFG 0x34 0x35 0x36 0x37 VID_LDO12 VID_LDO3 PGOOD_STATUS PGOOD_MASK 0x38 CHARGER_ INTERRUPT_ ENABLE CHARGER_ INTERRUPT_ FLAG BOOST_LDO_ INTERRUPT_ ENABLE BOOST_LDO_ INTERRUPT_ FLAG DEFAULT_SET NTC47K_SET 0x39 0x3A 0x3B 0x3C 0x3D D6 D5 Not used Not used EN_BST BST_MODE BST_BL FOVR Not used BL_LED2 Not used BL_LED3 Not used BL_LED4 Not used BL_LED5 Not used BL_FO[3:0] LED3_OFF[3:0] LED4_OFF[3:0] LED5_OFF[3:0] Not used Not used Not used DSCG_ LDO2 VID_LDO2[3:0] Not used Not used Not used DSCG_LDO3 D4 EN_LED5 Not used D3 D2 SLEEP_ UPDATE_ TIME Not used EN_LED4 EN_LED3 BST_OVP IBL[5:0] ILED2[5:0] ILED3[5:0] ILED4[5:0] ILED5[5:0] LED5_ OPEN LED4_ OPEN DSCG_ LDO1 Not used D1 FUEL_GAUGE_ MODE D0 FUEL_ GAUGE_ ENABLE EN_LED2 Not used EN_BL BST_IPK BL_FI[3:0] LED3_ON[3:0] LED4_ON[3:0] LED5_ON[3:0] LED3_OPEN LED2_OPEN LED1_OPEN EN_LDO3 MODE_LDO3 EN_LDO1 MODE_LDO1 EN_LDO2 MODE_LDO2 VID_LDO1[3:0] VID_LDO3[3:0] BATOK PG4_BST BATOK_ PG4_BST_MASK MASK EN_BAT_INT EN_CHG_INT PG1_LDO1 PG1_LDO1_ MASK EN_VIN_INT BAT_INT CHG_INT VIN_INT Not used EN_LED_ OPEN_INT EN_PG4_BST_ INT EN_PG1_ LDO1_INT Not used LED_OPEN_ INT PG4_BST_INT PG1_ LDO1_INT EN_IND_ PEAK_INT EN_THERM_ LIM_INT EN_WD_ INT EN_TSD_ INT VBUSOK VBUSOK_ MASK EN_THR_ INT IND_PEAK_ INT THERM_ LIM_INT WD_INT TSD_INT THR_INT DEFAULT_SET Not used Rev. B | Page 38 of 63 NTC_47K Data Sheet ADP5350 REGISTER BIT DESCRIPTIONS Table 19. Manufacturer and Model ID, Register Address 0x00 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic MANUF[3:0] Model[3:0] Access R R Default 0001 1011 Description The 4-bit manufacturer identification bus. The 4-bit model identification bus. Table 20. Silicon Revision, Register Address 0x01 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic Not used REV[3:0] Access R R Default Description 0011 The 4-bit silicon revision identification bus. Table 21. CHARGER_VBUS_ILIM, Register Address 0x02 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic Not used ILIM[3:0] Access R R/W Default 0000 Description Not used. VBUSx pin input current-limit programming bus. The current into VBUSx can be limited to the following programmed values: 0000 = 100 mA. 0001 = 150 mA. 0010 = 200 mA. 0011 = 300 mA. 0100 = 400 mA. 0101 = 500 mA. 0110 = 600 mA. 0111 = 700 mA. 1000 = 800 mA. 1001 = 900 mA. 1010 = 1000 mA. 1011 = 1100 mA. 1100 = 1200 mA. 1101 = 1300 mA. 1110 = 1400 mA. 1111 = 1500 mA. Table 22. CHARGER_TERMINATION_SETTINGS, Register Address 0x03 Bit Descriptions Bit No. [7:2] Mnemonic VTRM[5:0] Access R/W Default 100011 Description Termination voltage programming bus. The values of the float voltage can be programmed to the following values: 000000 = 3.50 V. 000001 = 3.52 V. 000010 = 3.54 V. 000011 = 3.56 V. 000100 = 3.58 V. 000101 = 3.60 V. 000110 = 3.62 V. 000111 = 3.64 V. 001000 = 3.66 V. 001001 = 3.68 V. 001010 = 3.70 V. 001011 = 3.72 V. 001100 = 3.74 V. 001101 = 3.76 V. 001110 = 3.78 V. 001111 = 3.80 V. 010000 = 3.82 V. Rev. B | Page 39 of 63 ADP5350 Data Sheet Bit No. Mnemonic Access Default [1:0] IEND[1:0] R/W 01 Description 010001 = 3.84 V. 010010 = 3.86 V. 010011 = 3.88 V. 010100 = 3.90 V. 010101 = 3.92 V. 010110 = 3.94 V. 010111 = 3.96 V. 011000 = 3.98 V. 011001 = 4.00 V. 011010 = 4.02 V. 011011 = 4.04 V. 011100 = 4.06 V. 011101 = 4.08 V. 011110 = 4.10 V. 011111 = 4.12 V. 100000 = 4.14 V. 100001 = 4.16 V. 100010 = 4.18 V. 100011 = 4.20 V. 100100 = 4.22 V. 100101 = 4.24 V. 100110 = 4.26 V. 100111 = 4.28 V. 101000 = 4.30 V. 101001 = 4.32 V. 101010 = 4.34 V. 101011 = 4.36 V. 101100 = 4.38 V. 101101 = 4.40 V. 101110 = 4.42 V. 101111 = 4.44 V. 110000 = 4.46 V. 110001 = 4.48 V. 110010 to 111111 = 4.5 V. Termination current programming bus. The values of the termination current can be programmed to the following values: 00 = 25 mA. 01 = 35 mA. 10 = 45 mA. 11 = 55 mA. Table 23. CHARGER_CURRENT_SETTING, Register Address 0x04 Bit Descriptions Bit No. 7 Mnemonic C_20_EOC Access R/W Default 0 6 C_10_EOC R/W 0 Description This bit has priority over the other settings (C_10_EOC and IEND). When this bit is set to high, 1/20 C programming is used. The minimum value is 25 mA. This bit has priority over the other setting (IEND) but not C_20_EOC. When this bit is set to high, 1/10 C programming is used unless C_20_EOC is set to high. The minimum value is 25 mA. Rev. B | Page 40 of 63 Data Sheet ADP5350 Bit No. [5:2] Mnemonic ICHG[3:0] Access R/W Default 1100 [1:0] ITRK_DEAD[1:0] R/W 10 Description Fast charge current programming bus. The values of the constant current charge can be programmed to the following values: 0000 = 25mA. 0001 = 50 mA. 0010 = 75 mA. 0011 = 100 mA. 0100 = 125 mA. 0101 = 150 mA. 0110 = 200 mA. 0111 = 250 mA. 1000 = 300 mA. 1001 = 350 mA. 1010 = 400 mA. 1011 = 450 mA. 1100 = 500 mA. 1101 = 550 mA. 1110 = 600 mA. 1111 = 650 mA. Trickle and weak charge current programming bus. The values of the trickle and weak charge currents can be programmed as per the following values: 00 = 5 mA. 01 = 10 mA. 10 = 20 mA. 11 = 50 mA. Table 24. CHARGER_VOLTAGE_THRESHOLD, Register Address 0x05 Bit Descriptions Bit No. 7 [6:5] Mnemonic Not used VRCH[1:0] Access R R/W Default 11 [4:3] VTRK_DEAD[1:0] R/W 01 [2:0] VWEAK[2:0] R/W 011 Description Not used. Recharge voltage programming bus. The values of the recharge threshold can be programmed as per the following values: 00 = 80 mV. 01 = 140 mV. 10 = 200 mV. 11 = 260 mV. Trickle to fast charge dead battery voltage programming bus. The values of the trickle to fast charge threshold can be programmed to the following values: 00 = 2.4 V. 01 = 2.5 V. 10 = 2.6 V. 11 = 3.3 V. Weak battery voltage rising threshold. The values of the weak battery voltage rising threshold can be programmed to the following values: 000 = 2.7 V. 001 = 2.8 V. 010 = 2.9 V. 011 = 3.0 V. 100 = 3.1 V. 101 = 3.2 V. 110 = 3.3 V. 111 = 3.4 V. Rev. B | Page 41 of 63 ADP5350 Data Sheet Table 25. CHARGER_TIMER_SETTING, Register Address 0x06 Bit Descriptions Bit No. 7 6 Mnemonic Not used EN_TEND Access R R/W Default 5 [4:3] EN_CHG_TIMER CHG_TMR_PERIOD R/W R/W 1 11 2 EN_WD R/W 0 1 WD_PERIOD R/W 0 0 RESET_WD W 0 Description Not used. When low, this bit disables the charge complete timer (tEND), and a 31 ms deglitch timer remains on this function. When high, the trickle/fast charge timer is enabled. Trickle/fast charge timer period. 00 = 15 minutes/150 minutes. 01 = 30 minutes/300 minutes. 10 = 45 minutes/450 minutes. 11 = 60 minutes/600 minutes. 0 = the watchdog timer is disabled even when VBSNS exceeds VTRK_DEAD. 1 = the watchdog timer safety timer is enabled. Watchdog safety timer period. 0 = 32 sec to 40 min. 1 = 64 sec to 40 min. When this bit is high, the watchdog safety timer resets. This bit is reset automatically. 1 Table 26. CHARGER_FUNCTION_SETTING1, Register Address 0x07 Bit Descriptions Bit No. 7 Mnemonic EN_JEITA Access R/W Default 0 6 DIS_IPK_SD R/W 1 5 EN_BMON R/W 0 4 EN_THR R/W 0 3 EN_DCDC R/W 1 2 1 EN_EOC EN_TRK R/W R/W 1 1 0 EN_CHG R/W Factory setting Description When low, this bit disables the JEITA Li-Ion temperature battery charging specification. When high, this bit disables the automatic shutdown of the device if four peak inductor current limits are reached in succession. In addition, when this bit is high, it only flags the IPK_STAT status bit. When this bit is high, the battery monitor is enabled even when the voltage at the VBUSx pins is below VVBUSOK_FALL. When this bit is high, the THR current source is enabled even when the voltage at the VBUSx pins is below VVBUSOK_FALL. When this bit is low, the dc-to-dc converter is disabled. When this bit is high, the dc-to-dc converter is enabled. When this bit is high, end of charge is allowed. When this bit is low, trickle charger is disabled and the dc-to-dc converter is enabled. When this bit is low, charging is disabled. When this bit is high and EN_DCDC = high, charging is enabled. Table 27. CHARGER_STATUS1, Register Address 0x08 Bit Descriptions Bit No. 7 Mnemonic VBUS_OV Access R Default Not applicable 6 5 Not used VBUS_ILIM R R Not applicable 4 THERM_LIM R Not applicable 3 CHDONE R Not applicable Description When high, this bit indicates that the voltage at the VBUSx pins exceeds VVBUS_OV. Not used. When high, this bit indicates that the current into a VBUSx pin is limited by the high voltage blocking FET and the charger is not running at the full programmed ICHG. When high, this bit indicates that the charger is not running at the full programmed ICHG but is limited by the die temperature. When high, this bit indicates the end of charge cycle is reached. This bit latches on, in that it does not reset to low when the VRCH threshold is breached. Rev. B | Page 42 of 63 Data Sheet Bit No. [2:0] ADP5350 Mnemonic CHAGER_STATUS[2:0] Access R Default Not applicable Description Charger status bus. 000 = off. 001 = trickle charge. 010 = fast charge (CC mode). 011 = fast charge (CV mode). 100 = charge complete. 101 = suspend. 110 = trickle, fast, or safety charge timer expired. 111 = battery detection. Table 28. CHARGER_STATUS2, Register Address 0x09 Bit Descriptions Bit No. [7:5] Mnemonic THR_STATUS[2:0] Access R Default Not applicable 4 IPK_STAT R Not applicable 3 [2:0] Not used BATTERY_STATUS[2:0] R R Not applicable Description THR pin status. 000 = off. 001 = battery cold. 010 = battery cool. 011 = battery warm. 100 = battery hot. 111 = thermistor is in normal operating temperature, between the battery cool and battery warm settings. Peak current limit status bit. Set high if four or more peak inductor current limits are reached in succession. Not used. Battery status bus. 000 = battery monitor off. 001 = no battery. 010 = VBSNS < VTRK. 011 = VTRK VBSNS < VWEAK. 100 = VBSNS VWEAK. Table 29. CHARGER_FAULT, Register Address 0x0A Bit Descriptions 1 Bit No. [7:4] 3 2 1 0 1 Mnemonic Not used BAT_SHR IND_PEAK TSD_130 TSD_140 Access R R/W R/W R/W R/W Default 0 0 0 0 Description Not used. When this bit is high, a battery short circuit is detected. When this bit is high, an inductor peak current-limit fault has occurred. When this bit is high, the overtemperature early warning has occurred. When this bit is high, the overtemperature condition is detected. The device shuts down due to an overtemperature condition. To reset the fault bits in the CHARGER_FAULT register, cycle the power on VBUSx, or read and then write the corresponding I2C bit high continuously. Table 30. BATTERY_SHORT, Register Address 0x0B Bit Descriptions Bit No. [7:5] Mnemonic TBAT_SHR[2:0] Access R/W Default 100 Description Battery short timeout timer: 000 = 1 sec 001 = 2 sec 010 = 4 sec 011 = 10 sec 100 = 30 sec 101 = 60 sec 110 = 120 sec 111 = 180 sec Rev. B | Page 43 of 63 ADP5350 Bit No. [4:3] [2:0] Mnemonic Not used VBAT_SHR[2:0] Data Sheet Access R R/W Default Description Not used. Battery short voltage threshold level: 000 = 2.0 V 001 = 2.1 V 010 = 2.2 V 011 = 2.3 V 100 = 2.4 V 101 = 2.5 V 110 = 2.6 V 111 = 2.7 V 100 Table 31. BATTERY_THERMISTOR_CONTROL, Register Address 0x0C Bit Descriptions Bit No. 7 Mnemonic ILIM_JEITA_COOL Access R/W Default 0 6 TBAT_LOW R/W 0 5 TBAT_HIGH R/W 1 4 R_NTC R/W Factory setting [3:0] BETA_NTC 1 R/W Factory setting 1 Description Selects the battery charging current when in the cool temperature range of 0C and 10C (see Table 14). 0 = approximately 50% of programmed charge current. 1 = approximately 10% of programmed charge current. Selects the battery temperature low threshold. When the battery temperature is lower than TBAT_LOW, charging stops. 0 = 0C. 1 = 10C. Selects the battery temperature high threshold. When the battery temperature is higher than TBAT_HIGH, charging stops. 0 = 45C. 1 = 60C. Selects the battery thermistor NTC resistance. 0 = 10 k at 25C. 1 = 100 k or 47 k at 25C. 4-bit programming bus for NTC beta setting. 0000 = 2350. 0001 = 2600. 0010 = 2750. 0011 = 3000. 0100 = 3150. 0101 = 3350. 0110 = 3500. 0111 = 3600. 1000 = 3800. 1001 = 4000. 1010 = 4200. 1011 = 4400. 1100 = 4600. 1101 = 4800. 1110 = 5000. 1111 = 5200. The BETA_NTC bits are trimmed by factory setting; writing these bits in the application is not recommended. Rev. B | Page 44 of 63 Data Sheet ADP5350 Table 32. V_SOC_0, Register Address 0x0D Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_0 Access R/W Default 0x7C Description The battery voltage when SOC is 0%. The default voltage is 3.5 V. Battery voltage (V) = (2.5 + V_SOC_0 x 0.008). Table 33. V_SOC_5, Register Address 0x0E Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_5 Access R/W Default 0x91 Description The battery voltage when SOC is 5%. The default voltage is 3.66 V. Battery voltage (V) = (2.5 + V_SOC_5 x 0.008). Table 34. V_SOC_11, Register Address 0x0F Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_11 Access R/W Default 0x94 Description The battery voltage when SOC is 11%. The default voltage is 3.684 V. Battery voltage (V) = (2.5 + V_SOC_11 x 0.008). Table 35. V_SOC_19, Register Address 0x10 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_19 Access R/W Default 0x99 Description The battery voltage when SOC is 19%. The default voltage is 3.724 V. Battery voltage (V) = (2.5 + V_SOC_19 x 0.008). Table 36. V_SOC_28, Register Address 0x11 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_28 Access R/W Default 0x9E Description The battery voltage when SOC is 28%. The default voltage is 3.764 V. Battery voltage (V) = (2.5 + V_SOC_28 x 0.008). Table 37. V_SOC_41, Register Address 0x12 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_41 Access R/W Default 0xA3 Description The battery voltage when SOC is 41%. The default voltage is 3.804 V. Battery voltage (V) = (2.5 + V_SOC_41 x 0.008) Table 38. V_SOC_55, Register Address 0x13 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_55 Access R/W Default 0xAB Description The battery voltage when SOC is 55%. The default voltage is 3.868 V. Battery voltage (V) = (2.5 + V_SOC_55 x 0.008). Table 39. V_SOC_69, Register Address 0x14 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_69 Access R/W Default 0xB5 Description The battery voltage when SOC is 69%. The default voltage is 3.948 V. Battery voltage (V) = (2.5 + V_SOC_69 x 0.008). Table 40. V_SOC_84, Register Address 0x15 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_84 Access R/W Default 0xC4 Description The battery voltage when SOC is 84%. The default voltage is 4.068 V. Battery voltage (V) = (2.5 + V_SOC_84 x 0.008) Rev. B | Page 45 of 63 ADP5350 Data Sheet Table 41. V_SOC_100, Register Address 0x16 Bit Descriptions Bit No. [7:0] Mnemonic V_SOC_100 Access R/W Default 0xD5 Description The battery voltage when SOC is 100%. The default voltage is 4.204 V. Battery voltage (V) = (2.5 + V_SOC_100 x 0.008). Table 42. FILTER_SETTING1, Register Address 0x17 Bit Descriptions Bit No. 7 [6:4] Mnemonic Not used FILTER_CHARGE Access R R/W Default 100 3 [2:0] Not used FILTER_DISCHARGE R R/W 010 Description Not used. The filter limit (in C rate) of SOC in battery charging mode. The C rate is the battery charge or discharge current rate over the battery capacity. 000 = 0.125 C. 001 = 0.25 C. 010 = 0.5 C. 011 = 0.75 C. 100 = 1 C. 101 = 1.5 C. 110 = 2 C. 111 = 3 C. Not used. The filter limit (in C rate) of SOC in battery discharging mode. The C rate is the battery charge or discharge current rate over the battery capacity. 000 = 0.125 C. 001 = 0.25 C. 010 = 0.5 C. 011 = 0.75 C. 100 = 1 C. 101 = 1.5 C. 110 = 2 C. 111 = 3 C Table 43. FILTER_SETTING2, Register Address 0x18 Bit Descriptions Bit No. [7:2] [1:0] Mnemonic Not used FILTER_IDLE Access R/W R/W Default 000000 00 Description Not used. The filter limit of SOC during battery idle mode. 00 = FILTER_CHARGE/8. 01 = FILTER_CHARGE/16. 10 = FILTER_CHARGE/32. 11 = FILTER_CHARGE/64. Table 44. RBAT_0, Register Address 0x19 Bit Descriptions Bit No. [7:0] Mnemonic RBAT_0 Access R/W Default 0x3F Description The battery internal resistance at 0C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_0 x 32 m. Table 45. RBAT_10, Register Address 0x1A Bit Descriptions Bit No. [7:0] Mnemonic RBAT_10 Access R/W Default 0x3F Description The battery internal resistance at 10C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_10 x 32 m. Rev. B | Page 46 of 63 Data Sheet ADP5350 Table 46. RBAT_20, Register Address 0x1B Bit Descriptions Bit No. [7:0] Mnemonic RBAT_20 Access R/W Default 0x3F Description The battery internal resistance at 20C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_20 x 32 m. Table 47. RBAT_30, Register Address 0x1C Bit Descriptions Bit No. [7:0] Mnemonic RBAT_30 Access R/W Default 0x3F Description The battery internal resistance at 30C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_30 x 32 m. Table 48. RBAT_40, Register Address 0x1D Bit Descriptions Bit No. [7:0] Mnemonic RBAT_40 Access R/W Default 0x3F Description The battery internal resistance at 40C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_40 x 32 m. Table 49. RBAT_60, Register Address 0x1E Bit Descriptions Bit No. [7:0] Mnemonic RBAT_60 Access R/W Default 0x3F Description The battery internal resistance at 60C. The resistance range is 0 m to 8160 m and the default resistance is 2016 m. Resistance value = RBAT_60 x 32 m. Table 50. K_RBAT_CHARGE, Register Address 0x1F Bit Descriptions Bit No. [7:6] [5:4] Mnemonic Not used K_RBAT_SOC Access R R/W Default 00 [3:0] K_RBAT_CHARGE R/W 1000 Description Not used. Battery internal resistance coefficient less than 20% capacity. 00 = RBAT at 0% SOC = RBAT at 20% SOC. 01 = RBAT at 0% SOC = 2 x RBAT at 20% SOC. 10 = RBAT at 0% SOC = 4 xRBAT at 20% SOC. 11 = RBAT at 0% SOC = 8 x RBAT at 20% SOC. Battery internal resistance coefficient for charging. The coefficient = 0.75 + K_RBAT_CHARGE/32. Table 51. BAT_TEMP, Register Address 0x20 Bit Descriptions Bit No. 7 6 Mnemonic Not used BAT_TEMP_SOURCE Access R R/W Default [5:0] BAT_TEMP R/W 11011 Description Not used. Battery temperature source selection bit. 0: from THR input. 1: from I2C. Battery temperature from I2C. The program battery temperature range is between -2C and +61C. Temperature value (C) = (BAT_TEMP - 2). 0 Table 52. BAT_SOC, Register Address 0x21 Bit Descriptions Bit No. 7 [6:0] Mnemonic Not used BAT_SOC Access R R Default Not applicable Description Not used. Battery state of charge. SOC = BAT_SOC %, only valued between 0% and 100%. Rev. B | Page 47 of 63 ADP5350 Data Sheet Table 53. VBAT_READ_H, Register Address 0x22 Bit Descriptions Bit No. [7:0] Mnemonic VBAT_READ[12:5] Access R Default Not applicable Description The battery voltage reading, highest eight bits, unit is mV. VBAT (mV) = (VBAT_READ_H x 32 + VBAT_READ_L/8). Table 54. VBAT_READ_L, Register Address 0x23 Bit Descriptions Bit No. [7:3] Mnemonic VBAT_READ[4:0] Access R [2:0] Not used R Default Not applicable Description The battery voltage reading, lowest 5 bits, unit is mV. VBAT (mV) = (VBAT_READ_H x 32 + VBAT_READ_L/8). Not used. Table 55. FUEL_GAUGE_MODE, Register Address 0x24 Bit Descriptions Bit No. [7:2] 2 Mnemonic Not used SLEEP_UPDATE_TIME Access R R/W Default 0 1 FUEL_GAUGE_MODE R/W 0 0 FUEL_GAUGE_ENABLE R/W 0 Description Not used. Select SOC update time in sleep mode. 0: 5 min. 1: 20 min. Fuel gauge operation mode. 1: enable sleep mode. 0: disable sleep mode. 0: disable fuel gauge. 1: enable fuel gauge. Table 56. SOC_RESET, Register Address 0x25 Bit Descriptions Bit No. 7 [6:0] Mnemonic SOC reset Not used Access W R Default 0 Description Write 1 to reset the BAT_SOC, VBAT_READ_H, and VBAT_READ_L registers. Not used. Table 57. BST_LED_CTRL, Register Address 0x26 Bit Descriptions Bit No. [7:6] 5 Mnemonic Not used EN_BST Access R R/W Default 4 EN_LED5 R/W 0 3 EN_LED4 R/W 0 2 EN_LED3 R/W 0 1 EN_LED2 R/W 0 0 Description Not used. Boost enable signal (only effective when the boost regulator is in standalone operation mode). 0 = disable boost output. 1 = enable boost output. Enable signal for LED5 individual sink (not effective if LED5 is configured as the grouped backlight). 0 = disable individual LED5 current sink. 1 = enable individual LED5 current sink. Enable signal for LED4 individual sink (not effective if LED4 is configured as the grouped backlight). 0 = disable individual LED4 current sink. 1 = enable individual LED4 current sink. Enable signal for LED3 individual sink (not effective if LED3 is configured as the grouped backlight). 0 = disable individual LED3 current sink. 1 = enable individual LED3 current sink. Enable signal for LED2 individual sink (not effective if LED2 is configured as the grouped backlight). 0 = disable individual LED2 current sink. 1 = enable individual LED2 current sink. Rev. B | Page 48 of 63 Data Sheet Bit No. 0 Mnemonic EN_BL ADP5350 Access R/W Default 0 Description The grouped backlight enable signal. 0 = disable the grouped backlight. 1 = enable the grouped backlight. Table 58. BST_CFG, Register Address 0x27 Bit Descriptions Bit No. 7 Mnemonic BST_MODE Access R/W Default 0 6 BST_BL R/W 0 5 FOVR R/W 0 4 [3:2] Not used BST_OVP R R/W 00 1 0 Not used BST_IPK R R/W 0 Description This bit sets the boost regulator operation mode. 0 = LED operation mode. 1 = boost standalone operation mode. This bit configures the boost regulator to provide the bias voltage to all active LED channels or only to the active LED backlight channels. (effective only when the boost regulator is configured in LED operation mode). 0 = set the boost regulator to provide the bias voltage for all active LED channels. In this configuration, the boost regulator provides the adaptive headroom regulation according to all active LED current sources. 1 = set the boost regulator to provide the bias voltage only to the active LED backlight channels. This bit configures the override feature in the backlight fade in and fade out. 0 = the fade in and fade out override is disabled. 1 = the fade in and fade out override is enabled. Not used. This bit sets the overvoltage threshold in the boost output voltage in VOUT4 pin. 00 = 18.5 V. 01 = 15 V. 10 = 10 V. 11 = 5.6 V. Not used. This bit sets the peak current limit for boost regulator. 0 = 600 mA peak current limit. 1 = 300 mA peak current limit. Table 59. IBL_SET, Register Address 0x28 Bit Descriptions Bit No. [7:6] [5:0] Mnemonic Not used IBL[5:0] Access R R/W Default 000000 Description Not used. These bits set the LED current setting for the grouped backlight (LED1). All grouped backlight LED channels follow this current setting. A square law algorithm for 64 levels is used. 000000 = 0 mA. 000001 = 0.005 mA. 000010 = 0.020 mA. ... 111101 = 18.750 mA. 111110 = 19.370 mA. 111111 = 20 mA. Rev. B | Page 49 of 63 ADP5350 Data Sheet Table 60. ILED2_SET, Register Address 0x29 Bit Descriptions Bit No. 7 Mnemonic BL_LED2 Access R/W Default 0 6 [5:0] Not used ILED2[5:0] R R/W 000000 Description This bit sets LED2 as the grouped backlight or individual current sink. 0 = set as individual current sink. 1 = set as grouped backlight. Not used. These bits set the individual LED current setting for LED2. This setting is not effective if LED2 is configured as the grouped LED backlight. A square law algorithm for 64 levels is used. 000000 = 0 mA. 000001 = 0.005 mA. 000010 = 0.020 mA. ... 111101 = 18.750 mA. 111110 = 19.370 mA. 111111 = 20 mA. Table 61. ILED3_SET, Register Address 0x2A Bit Descriptions Bit No. 7 Mnemonic BL_LED3 Access R/W Default 0 6 [5:0] Not used ILED3[5:0] R R/W 000000 Description This bit sets LED3 as the grouped backlight or individual current sink. 0 = set as individual current sink. 1 = set as grouped backlight. Not used. Those bits set the individual LED current setting for LED3. This setting is not effective if LED3 is configured as the grouped LED backlight. A square law algorithm for 64 levels is used. 000000 = 0 mA. 000001 = 0.005 mA. 000010 = 0.020 mA. ... 111101 = 18.750 mA. 111110 = 19.370 mA. 111111 = 20 mA. Table 62. ILED4_SET, Register Address 0x2B Bit Descriptions Bit No. 7 Mnemonic BL_LED4 Access R/W Default 0 6 [5:0] Not used ILED4[5:0] R R/W 000000 Description This bit sets LED4 as the grouped backlight or individual current sink. 0 = set as individual current sink. 1 = set as grouped backlight. Not used. Those bits set the individual LED current setting for LED4. This setting is not effective if LED4 is configured as the grouped LED backlight. A square law algorithm for 64 levels is used. 000000 = 0 mA. 000001 = 0.005 mA. 000010 = 0.020 mA. ... 111101 = 18.750 mA. 111110 = 19.370 mA. 111111 = 20 mA. Rev. B | Page 50 of 63 Data Sheet ADP5350 Table 63. ILED5_SET, Register Address 0x2C Bit Descriptions Bit No. 7 Mnemonic BL_LED5 Access R/W Default 0 6 [5:0] Not used ILED5[5:0] R R/W 000000 Description This bit sets LED5 as the grouped backlight or individual current sink. 0 = set as individual current sink. 1 = set as grouped backlight. Not used. Those bits set the individual LED current setting for LED5. This setting is not effective if LED5 is configured as the grouped LED backlight. A square law algorithm for 64 levels is used. 000000 = 0 mA. 000001 = 0.005 mA. 000010 = 0.020 mA. ... 111101 = 18.750 mA. 111110 = 19.370 mA. 111111 = 20 mA. Table 64. BL_FR, Register Address 0x2D Bit Descriptions Bit No. [7:4] Mnemonic BL_FO[3:0] Access R/W Default 0000 [3:0] BL_FI[3:0] R/W 0000 Description These bits set the fade out timer for the grouped LED backlight. The timer setting applies to the specific time starting from the maximum LED current code fade out to zero. Therefore, the real fade out time is shorter if the maximum LED current code is not being used. 0000 = fade-out disabled. 0001 = 0.3 sec. 0010 = 0.6 sec. ... 1101 = 3.9 sec. 1110 = 4.2 sec. 1111 = 4.5 sec. These bits set the fade in timer for the grouped LED backlight. The timer setting applies to the specific time starting from zero fading into the maximum LED current code. Therefore, the real fade in time is shorter if the maximum LED current code is not being used. 0000 = fade in disabled. 0001 = 0.3 sec. 0010 = 0.6 sec. ... 1101 = 3.9 sec. 1110 = 4.2 sec. 1111 = 4.5 sec. Table 65. LED3_BLINK, Register Address 0x2E Bit Descriptions Bit No. [7:4] Mnemonic LED3_OFF[3:0] Access R/W Default 0000 Description These bits set the off timer for the LED3 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = the blinking feature is disabled. 0001 = 0.250 sec. 0010 = 0.500 sec. 0011 = 0.750 sec. ... 1110 = 3.500 sec. 1111 = 3.750 sec. Rev. B | Page 51 of 63 ADP5350 Bit No. [3:0] Mnemonic LED3_ON[3:0] Data Sheet Access R/W Default 0000 Description These bits set the on timer for the LED3 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = 0.125 sec. 0000 = 0.250 sec. 0010 = 0.375 sec. ... 1110 = 1.875 sec. 1111 = 2.000 sec. Table 66. LED4_Blink, Register Address 0x2F Bit Descriptions Bit No. [7:4] Mnemonic LED4_OFF[3:0] Access R/W Default 0000 [3:0] LED4_ON[3:0] R/W 0000 Description These bits set the off timer for the LED4 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = the blinking feature is disabled. 0001 = 0.250 sec. 0010 = 0.500 sec. 0011 = 0.750 sec. ... 1110 = 3.500 sec. 1111 = 3.750 sec These bits set the on timer for the LED4 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = 0.125 sec. 0000 = 0.250 sec. 0010 = 0.375 sec. ... 1110 = 1.875 sec. 1111 = 2.000 sec. Table 67. LED5_Blink, Register Address 0x30 Bit Descriptions Bit No. [7:4] Mnemonic LED5_OFF[3:0] Access R/W Default 0000 [3:0] LED5_ON[3:0] R/W 0000 Description These bits set the off timer for the LED4 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = the blinking feature is disabled. 0001 = 0.250 sec. 0010 = 0.500 sec. 0011 = 0.750 sec. ... 1110 = 3.500 sec. 1111 = 3.750 sec. These bits set the on timer for the LED5 blinking feature (not effective if this LED channel is configured as the grouped LED backlight). 0000 = 0.125 sec. 0000 = 0.250 sec. 0010 = 0.375 sec. ... 1110 = 1.875 sec. 1111 = 2.000 sec. Rev. B | Page 52 of 63 Data Sheet ADP5350 Table 68. LED_STATUS, Register Address 0x31 Bit Descriptions Bit No. [7:5] 4 Mnemonic Not used LED5_OPEN 1 Access R R Not applicable 3 LED4_OPEN1 R Not applicable 2 LED3_OPEN1 R Not applicable 1 LED2_OPEN1 R Not applicable 0 LED1_OPEN1 R Not applicable 1 Default Description Not used. This bit records the LED5 status 0: LED5 channel is not open 1: LED5 channel is open This bit records the LED4 status 0: LED4 channel is not open 1: LED4 channel is open This bit records the LED3 status 0: LED3 channel is not open 1: LED3 channel is open This bit records the LED2 status 0: LED2 channel is not open 1: LED2 channel is open This bit records the LED1 status 0: LED1 channel is not open 1: LED1 channel is open To reset any bit in this register, power cycle VBUSx or write the corresponding I2C bit high. Table 69. LDO_CTRL, Register Address 0x32 Bit Descriptions Bit No. [7:3] 2 Mnemonic Not used EN_LDO3 Access R R/W Default 1 EN_LDO2 R/W Factory setting 0 EN_LDO1 R/W 1 Factory setting Description Not used. Enable signal for LDO3 (or Load Switch 3) 0 = disable LDO3 (or Load Switch 3) 1 = enable LDO3 (or Load Switch 3) Enable signal for LDO2 (or Load Switch 2) 0 = disable LDO2 (or Load Switch 2) 1 = enable LDO2 (or Load Switch 2) Enable signal for LDO1 (or Load Switch 1) 0 = disable LDO1 (or Load Switch 1) 1 = enable LDO1 (or Load Switch 1) Table 70. LDO_CFG, Register Address 0x33 Bit Descriptions Bit No. 7 6 Mnemonic Not used DSCG_LDO3 Access R R/W Default 5 DSCG_LDO2 R/W 0 4 DSCG_LDO1 R/W 0 3 2 Not used MODE_LDO3 R R/W 0 1 MODE_LDO2 R/W 0 0 Description Not used. This bit configures the output discharge functionality for LDO3 or Load Switch 3 0 = discharge functionality disabled 1 = discharge functionality enabled This bit configures the output discharge functionality for LDO2 or Load Switch 2 0 = discharge functionality disabled 1 = discharge functionality enabled This bit configures the output discharge functionality for LDO1 or Load Switch 1 0 = discharge functionality disabled 1 = discharge functionality enabled Not used. This bit sets LDO3 as an LDO or load switch 0 = LDO mode 1 = load switch mode This bit sets LDO2 as an LDO or load switch 0 = LDO mode 1 = load switch mode Rev. B | Page 53 of 63 ADP5350 Bit No. 0 Mnemonic MODE_LDO1 Data Sheet Access R/W Default 0 Description This bit sets LDO1 as an LDO or load switch 0 = LDO mode 1 = load switch mode Table 71. VID_LDO12, Register Address 0x34 Bit Descriptions Bit No. [7:4] Mnemonic VID_LDO2 Access R/W Default Factory setting [3:0] VID_LDO1 R/W Factory setting Description These bits set the output voltage in LDO2. These bits have no effect when this channel is set as a load switch. 0000 = 4.20 V. 0001 = 3.60 V. 0010 = 3.30 V. 0011 = 3.15 V. 0100 = 3.00 V. 0101 = 2.85 V. 0110 = 2.50 V. 0111 = 2.30 V. 1000 = 2.10 V. 1001 = 1.80 V. 1010 = 1.50 V. 1011 = 1.40 V. 1100 = 1.30 V. 1101 = 1.20 V. 1110 = 1.10 V. 1111 = 1.00 V. These bits set the output voltage in LDO1. These bits have no effect when this channel is set as a load switch. 0000 = 4.20 V. 0001 = 3.60 V. 0010 = 3.30 V. 0011 = 3.15 V. 0100 = 3.00 V. 0101 = 2.85 V. 0110 = 2.50 V. 0111 = 2.30 V. 1000 = 2.10 V. 1001 = 1.80 V. 1010 = 1.50 V. 1011 = 1.40 V. 1100 = 1.30 V. 1101 = 1.20 V. 1110 = 1.10 V. 1111 = 1.00 V. Rev. B | Page 54 of 63 Data Sheet ADP5350 Table 72. VID_LDO3, Register Address 0x35 Bit Descriptions Bit No. [7:4] [3:0] Mnemonic Not used VID_LDO3 Access R R/W Default Factory setting Description Not used. These bits set the output voltage in LDO3. These bits have no effect when this channel is set as a load switch. 0000 = 4.20 V. 0001 = 3.60 V. 0010 = 3.30 V. 0011 = 3.15 V. 0100 = 3.00 V. 0101 = 2.85 V. 0110 = 2.50 V. 0111 = 2.30 V. 1000 = 2.10 V. 1001 = 1.80 V. 1010 = 1.50 V. 1011 = 1.40 V. 1100 = 1.30 V. 1101 = 1.20 V. 1110 = 1.10 V. 1111 = 1.00 V. Table 73. PGOOD_STATUS, Register Address 0x36 Bit Descriptions Bit No. [7:4] 3 Mnemonic Not used VBUSOK Access R R Default Not applicable 2 BATOK R Not applicable 1 PG4_BST R Not applicable 0 PG1_LDO1 R Not applicable Description Not used. This bit shows real-time status of VBUSx voltage. 0 = the voltage at the VBUSx pin is below VVBUSOK or above VVBUS_OV. 1 = the voltage at the VBUSx pin is above VVBUSOK and below VVBUS_OV. This bit shows the real-time status of the battery voltage. 0 = battery voltage is lower than VWEAK. 1 = battery voltage is higher than VWEAK. This bit shows the real-time power-good status for the boost regulator. This bit is effective only in boost standalone fixed output mode. 0 = boost regulator power-good status is low. 1 = boost regulator power-good status is high. This bit shows the real-time power good status for LDO1. This bit is not effective if the LDO regulator is configured as a load switch mode. 0 = LDO1 power-good status is low. 1 = LDO1 power-good status is high. Table 74. PGOOD_MASK, Register Address 0x37 Bit Descriptions Bit No. [7:4] 3 2 Mnemonic Not used VBUSOK_MASK BATOK_MASK Access R R/W R/W Default Factory setting 0 Description Not used. This bit configures the external PGOOD pin. 0 = do not output the VVBUSx voltage status signal to the external PGOOD pin. 1 = output VBUS voltage status signal to the external PGOOD pin. This bit configures the external PGOOD pin. 0 = do not output BATOK signal to the external PGOOD pin. 1 = output the BATOK signal to the external PGOOD pin. Rev. B | Page 55 of 63 ADP5350 Data Sheet Bit No. 1 Mnemonic PG4_BST_MASK Access R/W Default 0 0 PG1_LDO1_MASK 1 R/W Factory setting 1 Description This bit configures the external PGOOD pin. This bit is only effective in boost standalone fixed output mode. 0 = do not output the boost PGOOD signal to the external PGOOD pin. 1 = output the boost PGOOD signal to the external PGOOD pin. This bit configures the external PGOOD pin. This bit is not effective if the LDO regulator is configured as a load switch mode. 0 = do not output the LDO1 PGOOD signal to the external PGOOD pin. 1 = output the LDO1 PGOOD signal to the external PGOOD pin. When the PGOOD pin is selected for PG1_LDO1_MASK, the ADP5350 quiescent current increases to 4 A typically. Table 75. CHARGER_INTERRUPT_ENABLE, Register Address 0x38 Bit Descriptions Bit No. 7 6 5 4 3 2 1 0 Mnemonic EN_IND_PEAK_INT EN_THERM_LIM_INT EN_WD_INT EN_TSD_INT EN_THR_INT EN_BAT_INT EN_CHG_INT EN_VIN_INT Access R/W R/W R/W R/W R/W R/W R/W R/W Default 0 0 0 0 0 0 0 0 Description When high, the inductor peak current-limit interrupt is enabled. When high, the isothermal charging interrupt is allowed. When high, the watchdog alarm interrupt is allowed. When high, the overtemperature 130C warning interrupt is allowed. When high, the THR temperature thresholds interrupt is allowed. When high, the battery voltage thresholds interrupt is allowed. When high, the charger mode change interrupt is allowed. When high, the VBUSx pin voltage thresholds interrupt is allowed. Table 76. CHARGER_INTERRUPT_FLAG, Register Address 0x39 Bit Descriptions Bit No. 7 6 5 Mnemonic IND_PEAK_INT 1 THERM_LIM_INT1 WD_INT1 Access R R R Default 0 0 0 4 3 2 1 0 TSD_INT1 THR_INT1 BAT_INT1 CHG_INT1 VIN_INT1 R R R R R 0 0 0 0 0 1 Description When high, this bit indicates an interrupt caused by an inductor peak current limit. When high, this bit indicates an interrupt caused by isothermal charging. When high, this bit indicates an interrupt caused by the watchdog alarm. The watchdog timer expires within 2 sec or 4 sec depending on the tWD setting of 32 sec or 64 sec, respectively. When high, this bit indicates an interrupt caused by an overtemperature fault. When high, this bit indicates an interrupt caused by THR temperature thresholds. When high, this bit indicates an interrupt caused by battery voltage thresholds. When high, this bit indicates an interrupt caused by a charger mode change. When high, this bit indicates an interrupt caused by VBUSx voltage thresholds. These bits reset to 0 automatically when read. Table 77. BOOST_LDO_INTERRUPT_ENABLE, Register Address 0x3A Bit Descriptions Bit No. [7:3] 2 Mnemonic Not used EN_LED_OPEN_INT Access R R/W Default 1 EN_PG4_BST_INT R/W 0 0 EN_PG1_LDO1_INT R/W 0 0 Description Not used. 0 = LED open events does not trigger the interrupt pin. 1 = LED open events triggers the interrupt pin. 0 = power-good warning on the boost regulator does not trigger the interrupt pin. 1 = power-good warning on the boost regulator triggers the interrupt pin. 0 = power-good warning on LDO1 does not trigger the interrupt pin. 1 = power-good warning on LDO1 triggers the interrupt pin. Rev. B | Page 56 of 63 Data Sheet ADP5350 Table 78. BOOST_LDO_INTERRUPT_FLAG, Register Address 0x3B Bit Descriptions Bit No. [7:3] 2 Mnemonic Not used LED_OPEN_INT 1 Access R R Default 1 PG4_BST_INT1 R 0 0 PG1_LDO1_INT1 R 0 1 Description Not used. When high, this bit indicates an interrupt caused by LED open-circuit faults. When high, this bit indicates an interrupt caused by a power-good warning on the boost regulator. When high, this bit indicates an interrupt caused by a power-good warning on LDO1. 0 These bits reset to 0 automatically when read. Table 79. DEFAULT_SET, Register Address 0x3C Bit Descriptions Bit No. [7:0] Mnemonic DEFAULT_SET Access W Default 0 Description Write 0x7F to this bit to reset all register to default values. Table 80. NTC47K_SET, Register Address 0x3D Bit Descriptions Bit No. [7:1] 0 Mnemonic Not used NTC_47K Access R R/W Default 1 Description Not used. Select battery thermistor NTC resistance, effective when R_NTC = 1. 0 = 100 k at 25C. 1 = 47 k at 25C. Rev. B | Page 57 of 63 ADP5350 Data Sheet APPLICATIONS INFORMATION EXTERNAL COMPONENTS the maximum dc input current typically yields an optimal compromise. Suggested boost inductors are shown in Table 82. Buck Inductor Selection The high switching frequency of the ADP5350 buck converter allows the selection of small chip inductors. Suggested buck inductors are shown in Table 81. The peak-to-peak inductor current ripple, IRIPPLE, is calculated using the following equation: I RIPPLE = The input VIN4 and output VOUT4 voltages determine the switch duty cycle, which in turn determine the inductor ripple current. Calculate the inductor ripple current in a steady state using the following equation: I RIPPLE 4 = VISOS x (VISOS - VCFL1 ) VOUT4 x f SW 4 x L2 Make sure that the peak inductor current, the maximum input current plus half the inductor ripple current is below the rated saturation current of the inductor. Likewise, make sure that the maximum rated rms current of the inductor is greater than the maximum dc input current to the regulator. VISOS x f SW x L1 where: VISOS is the ISOS node output voltage. VCFL1 is the converter input voltage at the CFL1 node. fSW is the switching frequency. L1 is the buck output inductor value. VBUSx Capacitor Selection The minimum dc current rating of the inductor must be greater than the inductor peak current. The inductor peak current, IPEAK, is calculated using the following equation: I PEAK = I CHG + I LOAD _ MAX + VIN4 x (VOUT4 - VIN4 ) I RIPPLE 2 Inductor conduction losses are caused by the flow of current through the inductor, which has an associated internal dc resistance (DCR). Larger inductors have smaller DCR values, which may decrease inductor conduction losses. Inductor core losses are related to the magnetic permeability of the core material. Because the buck regulators are high switching frequency dc-to-dc converters, shielded ferrite core material is recommended for its low core losses and low electromagnetic interference (EMI). Boost Inductor Selection The inductor is an essential part of the boost switching regulator. It stores energy during the on time, and transfers that energy to the output through the output rectifier during the off time. Use inductance in the range of 2 H to 10 H. In general, lower inductance values have higher saturation current and lower series resistance for a given physical size. However, lower inductance results in higher peak current that can lead to reduced efficiency and greater input and/or output ripple and noise. Peak-to-peak inductor ripple current at close to 30% of According to the USB 2.0 specification, USB peripherals have a detectable change in capacitance on VBUSx when VBUSx are attached. The peripheral device VBUSx bypass capacitance must be at least 1 F but not larger than 10 F. The combined capacitance for the VBUSx and CFL1 pins must not exceed 10 F at any temperature or dc bias condition. Suggested VBUSx capacitors are shown in Table 83. CFL1 Capacitor Selection The CFL1 pin serves the ADP5350 as the buck dc-to-dc regulator input capacitor. The rms current rating of the input capacitor current must be larger than the value calculated by the following equation: I C _ RMS = (I CHG + I LOAD _ MAX ) VISOS x (VCFL1 - VISOS ) VCFL1 To minimize supply noise, place the input capacitor as close as possible to the CFL1 pin of the charger. As with the output capacitor, a low ESR capacitor is recommended. The effective capacitance needed for stability, which includes temperature and dc bias effects, is a minimum of 2 F and a maximum of 7 F. A list of suggested capacitors is shown in Table 84. Table 81. Suggested Buck Inductors Vendor Wurth TDK Part Number 74479976215 VLS201612CX-1R5M L (H) 1.5 1.5 Typical DC Current (A) 1.2 1.9 Maximum DCR (m) 125 89 Size 0806 0806 L (H) 4.7 4.7 Typical DC Current (A) 0.9 1.12 Maximum DCR (m) 140 252 Size 0806 0806 Table 82. Suggested Boost Inductors Vendor Wurth TDK Part Number 74479776247A VLS201612CX-4R7M Rev. B | Page 58 of 63 Data Sheet ADP5350 CFL2 Capacitor Selection LDO Capacitor Selection The CFL2 pin is the internal regulator output that provides the power supply for post stage control circuits, including the fuel gauge, boost LED, and LDOs. To ensure stable performance of the internal regulator, the recommended components for the CFL2 capacitor are given in Table 85. Connecting a 1 F capacitor from VIN123 to AGND reduces the circuit sensitivity to the PCB layout, especially when long input traces or high source impedance are encountered. ISOS and ISOB Capacitor Selection Higher output capacitor values reduce the output voltage ripple and improve load transient response. When choosing this value, it is also important to account for the loss of capacitance due to output voltage dc bias. To guarantee the performance of the charger in various operation modes, including trickle charge, CC charge, and CV charge, it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application. The peak-to-peak output voltage ripple for the selected output capacitor and inductor values is calculated using the following equation: VRIPPLE = I RIPPLE 8 x f SW x C OUT Capacitors with lower effective series resistance (ESR) are preferable to guarantee low output voltage ripple, as shown in the following equation: ESRCOUT VRIPPLE I RIPPLE Table 83. Suggested VBUSx Capacitors Vendor Murata TDK Part Number GRM188R61E225K C1608X5R1E225 Value (F) 2.2 2.2 Voltage (V) 25 25 Size 0603 0603 Table 84. Suggested CFL1 Capacitors Vendor Murata TDK Part Number GRM188R60J475K C1608X5R0J475K Value (F) 4.7 4.7 Voltage (V) 6.3 6.3 Size 0603 0603 Voltage (V) 6.3 6.3 Size 0603 0603 Table 85. Suggested CFL2 Capacitors Vendor Murata TDK Part Number GRM188R60J225K C1608X5R0J475K Value (F) 2.2 2.2 Table 86. Suggested ISOS and ISOB Capacitors Vendor Murata TDK Part Number GRM188R60J106K C1608X5R0J106M080AB Value (F) 10 10 Voltage (V) 6.3 6.3 Size 0603 0603 The ADP5350 is designed for operation with small, space-saving ceramic capacitors, but functions with most commonly used capacitors as long as care is taken with regard to the ESR value. The ESR of the output capacitor affects the stability of the LDO control loop. A minimum of 1 F capacitance with an ESR of 1 or less is recommended to ensure stability of the ADP5350. Transient response to changes in load current is also affected by output capacitance. Using a larger value of output capacitance improves the transient response of the ADP5350 to large changes in load current. Table 87. Suggested LDO Capacitors Vendor Murata TDK Value (F) 1 1 Part Number GRM155R60J105KE19D CGB2A3X5R0J105M033BB Voltage (V) 6.3 6.3 Size 0402 0402 Boost Capacitor Selection The ADP5350 requires input and output decoupling capacitors to supply transient currents while maintaining a constant input and output voltage. Use a low ESR input capacitor, 4.7 F or greater, to prevent noise at the VIN4 node. Place the capacitor between the VIN4 pin and PGND4 as close to the ADP5350 as possible. Ceramic capacitors are preferred because of their low ESR characteristics. The output capacitor maintains the output voltage and supplies current to the load while the boost switch is on. The value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the regulator. Use a low ESR output capacitor; ceramic dielectric capacitors are preferred. For very low ESR capacitors, such as ceramic capacitors, the ripple current due to the capacitance is calculated as follows. Because the capacitor discharges during the on time the charge removed from the capacitor is the load current multiplied by the on time. Choose the output capacitor based on the following equation: COUT4 I L 2 x (VOUT4 - VIN4 ) f SW4 x VOUT4 x VRIPPLE4 where: IL2 is the average inductor current. VRIPPLE4 is boost output voltage ripple. Table 88. Suggested Boost Capacitors Vendor Murata TDK Murata TDK Rev. B | Page 59 of 63 Part Number GRM188R61C475ME11 C1608X5R1E475M080AC GRM188R61E106MA73 C1608X5R1E106M080AC Value (F) 4.7 4.7 10 10 Voltage (V) 25 25 25 25 Size 0603 0603 0603 0603 ADP5350 Data Sheet PCB LAYOUT GUIDELINES Poor layout can affect ADP5350 performance, causing EMI and electromagnetic compatibility (EMC) problems, ground bounce, and voltage losses. Poor layout can also affect regulation and stability. A good layout is implemented using the following guidelines: Place the decoupling capacitor, inductor, input capacitor, and output capacitor close to the IC. PGND C8 6.3V/XR5 0402 C11 6.3V/XR5 0402 BATOK C5 6.3V/XR5 0402 SDA C7 6.3V/XR5 0402 C6 6.3V/XR5 0402 SCL nINT 31 30 29 28 27 26 25 SDA SCL VOUT 1 VOUT 2 VIN 123 CFL 2 VOUT 3 nINT D5 24 2 PGOOD D4 23 D3 22 D2 21 3 THR 4 BSNS 5 ISOB 6 7 D1 20 ISOS VIN 4 19 AGND FB4 18 1 8 VOUT 4 17 VBUSA VBUSB SW 4 15 SW 1B 14 10 SW 1A C9 - 10F 6.3V/XR5 0603 PGND 4 16 CFL 1 PGND 1A PGND 1B 13 13 8 ADP5350 12 C3 - 10F 6.3V/XR5 0603 BATOK 1 11 C4 - 10F 6.3V/XR5 0603 32 3 2 PGOOD 9 C10 - 10F 25V/XR5 0603 C2 - 2.2F 6.3V/XR5 0603 L1 - 15H 2016 C1 - 2.2F 25V/XR5 0603 Figure 59. Recommended Layout Rev. B | Page 60 of 63 L2 - 47H 2016 14797-043 Use a ground plane with several vias connecting to the component side ground to further reduce noise interference on sensitive circuit nodes. Use a dedicated trace to connect the BSNS pin to the battery pack output node for accurate sensing of the battery voltage. Use Size 0603 or Size 0402 resistors and capacitors to achieve the smallest possible footprint solution on boards where space is limited. Data Sheet ADP5350 TYPICAL APPLICATION CIRCUITS ADP5350 VBUSA USB 5V SW1A 3MHz BUCK VBUSB C1 2.2F PGND1A CFL1 PGND1B C2 4.7F CFL2 TO MCU INT CHARGE CONTROL AND FUEL GAUGE I2C AND GPIOs PGOOD C3 10F ISOB BSNS 150mAh + Li-Ion BATTERY - RNTC = 47k AT 25C THR BATOK VISOS RNTC VIN4 L2 C9 4.7F C4 10F VOUT4 SW4 4.7H VISOS ISOS C11 2.2F SCL SDA L1 1.5H SW1B LED BOOST PGND4 C10 4.7F FB4 VIN123 VOUT1 150mA LDO (OR LOAD-SWITCH) C6 1F VOUT2 MEMS 150mA LDO (OR LOAD-SWITCH) C7 1F VOUT3 MEMORY C8 1F 150mA LDO D1 LED1 LED2 LED3 D2 LED4 LED5 LED6 D3 D4 D5 (OR LOAD-SWITCH) 14797-044 MCU PROGRAMMABLE LED DRIVER C5 1F AGND Figure 60. Li-Ion Battery Charger Application with LED Panel VBUSA USB 5V ADP5350 C1 2.2F SW1A 3MHz BUCK VBUSB TO MCU PGOOD ISOS I2C AND GPIOs CHARGE CONTROL AND FUEL GAUGE ISOB BSNS THR BATOK RNTC VISOS VIN4 4.7H C9 4.7F SW4 PGND4 VOUT3 C8 1F VOUT2 MEMS C7 1F VOUT1 MCU C6 1F VISOS STANDALONE BOOST FB4 150mA LOAD-SWITCH 150mA LDO 150mA LDO D1 C4 10F 150mAh + Li-Ion BATTERY - RNTC = 47k AT 25C VOUT4 = 12V VOUT4 PROGRAMMABLE LED DRIVER L2 VISOS C3 10F PGND1B C11 2.2F SCL INT L1 1.5H PGND1A CFL1 C2 4.7F CFL2 SDA SW1B RFB1 82k C10 10F OLED RFB2 4.7k D2 D3 D4 D5 (ALWAYS ON) AGND Figure 61. True Shutdown Standalone Boost for OLED Panel Application Rev. B | Page 61 of 63 14797-045 VIN123 C5 1F ADP5350 Data Sheet FACTORY-PROGRAMMABLE OPTIONS Table 89. Fuse-Programmable Trim Options for the ADP5350 Parameter I2C Address R_NTC BETA_NTC EN_CHG EN_LDO2 EN_LDO3 VID_LDO1, VID_LDO2, VID_LDO3 VBUSOK_MASK PG1_LDO1_MASK Value 0x44 0x45 0x64 0x65 10 k 100 k/47 k 2350 2600 2750 3000 3150 3350 3500 3600 3800 4000 4200 4400 4600 4800 5000 5200 Charger is enabled Charger is disabled LDO2 is enabled LDO2 is disabled LDO3 is enabled LDO3 is disabled 4.20 V 3.60 V 3.30 V 3.15 V 3.00 V 2.85 V 2.50 V 2.30 V 2.10 V 1.80 V 1.50 V 1.40 V 1.30 V 1.20 V 1.10 V 1.00 V Do not output the VVBUSx voltage status signal to the external PGOOD pin Output the VVBUSx voltage status signal to external PGOOD pin Do not output the LDO1 PGOOD signal to the external PGOOD pin Output the LDO1 PGOOD signal to external PGOOD pin Rev. B | Page 62 of 63 Default Setting 0x44 100 k/47 k 3800 Charger is disabled LDO2 is disabled LDO3 is disabled 3.3 V Output the VVBUSx voltage status signal to the external PGOOD pin Do not output the LDO1 PGOOD signal to the external PGOOD pin Data Sheet ADP5350 OUTLINE DIMENSIONS 3.400 3.360 3.320 BOTTOM VIEW (BALL SIDE UP) 6 5 4 3 2 1 A BALL A1 IDENTIFIER B 3.350 3.310 3.270 2.50 REF C D E F 0.50 BSC TOP VIEW (BALL SIDE DOWN) 0.390 0.360 0.330 SIDE VIEW COPLANARITY 0.04 SEATING PLANE PKG-004653 0.360 0.320 0.280 0.270 0.240 0.210 05-14-2015-B 0.660 0.600 0.540 Figure 62. 32-Ball Wafer Level Chip Scale Package [WLCSP] (CB-32-1) Dimensions shown in millimeters DETAIL A (JEDEC 95) 5.10 5.00 SQ 4.90 PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 32 25 1 24 0.50 BSC 3.75 3.60 SQ 3.55 EXPOSED PAD 8 17 TOP VIEW 0.80 0.75 0.70 TOP VIEW PKG-004570 SEATING PLANE 0.50 0.40 0.30 9 16 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5 10-20-2017-C PIN 1 INDICATOR 0.30 0.25 0.18 Figure 63. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm x 5 mm Body and 0.75 mm Package Height (CP-32-12) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADP5350ACBZ-1-R7 ADP5350ACPZ-1-R7 ADP5350CB-EVALZ ADP5350CP-EVALZ 1 Temperature Range -40C to +125C -40C to +125C Package Description 32-Ball Wafer Level Chip Scale Package [WLCSP] 32-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Evaluation Board Z = RoHS Compliant Part. (c)2017-2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14797-0-5/18(B) Rev. B | Page 63 of 63 Package Option CB-32-1 CP-32-12