AT87F51 QuickFlash - Atmel Corporation

8TQFP

INDEX

CORNER

P1.0

VCC

P1.1

P1.2

P1.4

P1.3

43 40

18192021

P1.7

P1.6

P1.5

NC 7

121314151617

3837

3635 33

PSEN

XTAL1

GND

XTAL2

GND

P0.0 (AD0)

ALE/PROG

()P3.7RD

EA/VPP

()P3.6WR

(RXD) P3.0 P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P0.2 (AD2)

P0.1 (AD1)

()P3.2INT0

(TXD) P3.1

(T1) P3.5

()P3.3INT1

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P2.5 (A13)

Features

•Compatible with MCS-51™ Products

•4K Bytes of User Programmable QuickFlash™ Memory

•Fully Static Operation: 0 Hz to 24 MHz

•Three-Level Program Memory Lock

•128 x 8-Bit Internal RAM

•32 Programmable I/O Lines

•Two 16-Bit Timer/Counter s

•Six Interrupt Sources

•Programmable Serial Channel

•Low Power Idle and Power Down Modes

Description

The AT87F51 is a low-power, high-performance CMOS 8-bit microc omputer with 4K

bytes of Quick Flash Progra mmable Re ad Onl y Memory . The dev ice is ma nufac tured

using A tmel’s hig h densit y nonvol atile me mory tech nology and is compat ible with the

industry standard MCS-51™ instruction set and pinout. The on-chip QuickFlash

allows the program memory to be user programmed by a conventional nonvolatile

memory programmer. By combining a versatile 8-bit CPU with QuickFlash on a mono-

lithic chi p, the Atmel AT87F 51 is a powerful microcomputer which provides a highl y

flexible and cost effective solution to many embedded control applications.

PDIP

P1.0

P1.1

P0.0 (AD0)

P1.2

()P3.2INT0

ALE/PROG

()P3.7RD P2.3 (A11)

(TXD) P3.1

EA/VPP

()P3.6WR P2.4 (A12)

(RXD) P3.0

P0.7 (AD7)

(T1) P3.5 P2.6 (A14)

RST

P0.6 (AD6)

P1.7

P0.5 (AD5)

P1.6

P0.4 (AD4)

P1.5

P0.3 (AD3)

P1.4

P0.2 (AD2)

P1.3

P0.1 (AD1)

()P3.3INT1

PSEN

XTAL2 P2.2 (A10)

(T0) P3.4 P2.7 (A15)

XTAL1 P2.1 (A9)

GND P2.0 (A8)

P2.5 (A13)

Rev. 1012A–02/98

(continued)

8-Bit

Microcontroller

with 4K Bytes

QuickFlash™

AT87F51

Not Recommended

for New Designs.

Use AT89S51.

Pin Configurations

PLCC

P1.0

VCC

P1.1

P0.0 (AD0)

P1.2

ALE/PROG

()P3.7RD

XTAL1

EA/VPP

()P3.6WR

GND

(RXD) P3.0

P0.7 (AD7)

P2.6 (A14)

P0.6 (AD6)

P0.5 (AD5)

P0.4 (AD4)

P0.3 (AD3)

P1.4

P0.2 (AD2)

P1.3

P0.1 (AD1)

PSEN

XTAL2

()P3.2INT0

(TXD) P3.1

(T1) P3.5

()P3.3INT1

(T0) P3.4 P2.7 (A15)

(A11) P2.3

(A12) P2.4

(A10) P2.2

(A9) P2.1

(A8) P2.0

RST

P1.7

P1.6

P1.5

INDEX

CORNER

P2.5 (A13)

43 40

65444

25 28

181920 24

2122

17 29

Not

Block Diag ram

PORT 2 DRIVERS

PORT 2

LATCH

P2.0 - P2.7

QUICK

FLASH

PORT 0

LATCH

RAM

PROGRAM

ADDRESS

BUFFER

INCREMENTER

PROGRAM

COUNTER

DPTR

RAM ADDR.

INSTRUCTION

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

STACK

POINTER

ACC

TMP2 TMP1

ALU

PSW

TIMING

AND

CONTROL

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

OSC

GND

VCC

PSEN

ALE/PROG

EA / VPP

RST

PORT 0 DRIVERS

P0.0 - P0.7

Not

The AT87F51 provides the following standard features: 4K

bytes of QuickFlash, 128 bytes of RAM, 32 I/O lines, two

16-bit tim er/count ers, a five v ector tw o-level interrup t archi-

tecture, a full duplex serial port, on-chip oscillator and clock

circuitry. In addition, the AT87F 51 is designed with static

logic for operation down to z ero frequency an d supports

two software selectable power saving modes. The Idle

Mode stops the CPU while allowing the RAM,

timer/counters, serial port and interrupt system to continue

func tioning. The Pow er Down M ode save s the RAM c on-

tents bu t freezes the osci llato r disablin g all othe r chi p func-

tions until the next hardware reset.

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an

output port each pin can sink eight T TL inputs. When 1s

are written to port 0 pins, the pins can be used as high-

impedance inputs.

Port 0 may also be configured to be the multiplexed low-

order address/data bus during accesses to external pro-

gram and data memo ry. In th is mode P0 has internal pul -

lups.

Port 0 a lso rece ives the code bytes du ring Qui ckFl ash pr o-

grammin g, an d outp uts the c ode byt es d uring pro gram ver-

ificati on. Ex te rnal pullu ps a re r equ ired during pro gr am ve ri -

fication.

Port 1

Port 1 is a n 8- bit bi dire ction al I/O por t with inter nal pullu ps.

The Port 1 output buffers can sink/sou rce four T TL inputs.

When 1s are written to Port 1 pins they are pulled high by

the internal pullups and can be us ed as inputs. As i nputs,

Port 1 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 1 also receives the low-order address bytes during

QuickFlash programming and verification.

Port 2

Port 2 is a n 8- bit bi dire ction al I/O por t with inter nal pullu ps.

The Port 2 output buffers can sink/sou rce four T TL inputs.

When 1s are written to Port 2 pins they are pulled high by

the internal pullups and can be us ed as inputs. As i nputs,

Port 2 pins that are externally being pulled low will source

current (IIL) because of the internal pullups.

Port 2 emits the high-order address byte during fetches

from external program memory and during accesses to

externa l data memory that us e 16 -b it addre ss es ( MO VX @

DPTR). In this appli cation it uses strong in ternal pullups

when emitting 1s. During accesses to ex ternal data mem-

ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the

contents of the P2 Special Function Register.

Port 2 also r eceives the high-order address bits and some

control signals during QuickFlash programming and verifi-

cation.

Port 3

Port 3 is an 8-b it bidirectiona l I/O port with in ternal pullup s.

The Port 3 output buffers can sink/source four TTL inputs.

When 1s are written to Port 3 pins they are pulled high by

the internal pul lups and can be us ed as inputs. As i nputs,

Port 3 pins that are externally being pulled low will s ource

current (IIL) because of the pullups.

Port 3 also serves the funct ions of var ious s peci al featu res

of the AT87F51 as listed below:

Port 3 also receives some control signals for QuickFlash

programming and verification.

RST

Reset input. A high on this pin for two machine cycles while

the oscill ator is runni ng re se ts the dev ic e.

ALE/PROG

Address Latch Enable output pulse for latching the low byte

of the address during accesses to external me mory. This

pin is als o the program puls e input (PROG) during Quick-

Flash programming.

In normal operation ALE is emitted at a constant rate of 1/6

the osc illator frequ ency, an d may be used for ex terna l tim-

ing or clocking purposes. Note, however, that one ALE

pulse is skipped during each access to external Data Mem-

ory.

If desired, ALE operation can be disabled by setting bit 0 of

SFR loc atio n 8EH. Wi th the b it set, A LE is a ctive o nly dur-

ing a MOVX or MOVC instruction. Otherwise, the pin is

weakly pulled high. Setting the ALE-disable bit has no

effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro-

gram memory.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0 (external interrupt 0)

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR (external data mem ory write strobe)

P3.7 RD (external data memory read strobe)

Not

When the AT87F51 is ex ecuting code from external pro-

gram memory, PSEN is activated twice each machine

cycle, ex cept that two PSEN activations are skipped during

each access to external data memory.

EA/VPP

External Access Enable. EA must be st rapped to GND in

order to enable the device to fetch code from external pro-

gram memory locations starting at 0000H up to FFFFH.

Note, however, that if lock bit 1 is programmed, EA will be

internally latched on reset.

EA should be strapped to VCC for internal program execu-

tions.

This pin also receives the 12-volt programming enable volt-

age (VPP) during QuickFlash programming.

XTAL1

Input to the inverting os cillator ampl ifier and input to the

internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

Oscillator Character istics

XTAL1 and XTA L2 are the input and outp ut, respectively ,

of an invert in g amp lifier whi ch can be con fig ur ed for use as

an on-chip oscillator, as shown in Figure 1. Either a quartz

crystal or ceramic resonator may be used. To drive the

device from an exter na l cl oc k sour c e, XTA L2 shou ld b e lef t

unconnected while XTAL1 is driven as shown in Figure 2.

There are no requirements on the duty cycle of the external

clock signal, since the input to the internal clocking circuitry

is thr ough a d ivide- by-t wo flip-f lop , but min imum and maxi -

mum voltage high and low time specifications must be

observed.

Idle Mode

In idle mode, the CPU puts itself to sl eep while all the on-

chip peripherals remain active. The mode is invoked by

software. T he content of the on-chip RAM and all the spe-

cial functions registers remain unchanged during this

mode. The i dle mode can be terminated by any en abled

interrupt or by a hardware reset.

It should be noted that when idle is terminated by a hard

ware rese t, the devic e normally resum es program execu-

tion, fr om wh ere it le ft off, up to two machine cycl es b efore

the internal reset algorithm takes control. On-chip hardware

inhibi ts access to interna l RAM in th is event, but access to

the port pins is not inhibited. To eliminate the possibility of

an unexpected write to a port pin when Idle is terminated by

reset, the instruction following the one that invokes Idle

should no t be one th at writes to a p ort pin or to external

memory.

Figure 1. Oscillator Connections

Note: C1, C2 = 30 pF ± 10 pF f or Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Figure 2. External Clock Drive Configuration

C2 XTAL2

GND

XTAL1

Status of Exte rnal Pi ns Duri ng Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3

Idle Internal 1 1 Data Data Data Data

Idle External 1 1 Float Data Address Data

Power Down Internal 0 0 Data Data Data Data

Power D own External 0 0 Float Data Data Data

Not

Power Down Mode

In the power down mode the oscillator is stopped, and the

inst ruction that in vokes power down is the las t instr uction

exec uted. The on -chip RAM and Spec ial Funct ion Reg is-

ters retai n their values until the power d own mode is ter mi-

nated. T he only ex it from pow er down is a hardwa re reset .

Reset redefines the SFRs but does not cha nge the on-chip

RAM. The reset should not be activated before VCC is

restored to its normal operating level and must be held

active lo ng en oug h to all ow the oscil la tor to resta r t and st a-

bilize.

Program Memor y Lock Bits

On the chip are three lock bits which can be left unpro-

grammed (U) or can be programmed (P) to obtain the addi-

tional features listed in the table below:

When lock bit 1 is programmed, the logic level at the EA pin

is sam pled and latched during reset. I f the dev ice is po w-

ered up without a reset, the latch initializes to a random

value, and holds that value until reset is activated. It is nec-

essary that the latched value of EA be in agreement with

the current logi c level at th at pin in order for the device to

function properly.

Lock Bi t Protection Modes

Program Lock Bits Protection Type

LB1 LB2 LB3

1 U U U No program lock features.

2 P U U MOVC instructions executed from external program memory are disabled from fetching code

by tes from internal memory, EA is sampl ed and la tched on reset, an d further p rogram ming of the

QuickFlash is disabled.

3 P P U Same as mode 2, also verify is disabled.

4 P P P Same as mode 3, also external execution is disabled.

Programming the QuickFlash

The AT87F51 is shipped with the on-chip QuickFlash mem-

ory array ready to be programmed. The programming inter-

face needs a high-voltage (12-volt) program enable signal

and is compatible with conventional third-party Flash or

EPROM progra mmers.

The AT8 7F51 co de mem ory arra y is prog ramme d byte-by -

byte.

Programming Algorithm: Before programming the

AT87F 51, the addres s, da ta, and cont rol signa ls s hould be

set up according to the QuickFlash programming mode

table and F igure s 3 and 4. To program the AT87F51, take

the following steps:

1. Input the desired memory location on the address

lines.

2. Input the appropriate data byte on the data lines.

3. Activate the correct combination of control signals.

4. Raise EA/VPP to 12V.

5. Pulse ALE / P ROG once to pr ogram a byte in the Quick-

Flash ar ray or the lo ck bits. The byte-write cycle is self-

timed a nd typ ically takes no mor e than 1.5 ms. Re peat

steps 1 through 5, changing the address and data for

the entire array or until the end of the object file is

reached.

Data Polling: The AT87F51 features Data Pol ling to indi-

cate the end of a write cycle. During a write cycle, an

attempted read of the last byte written will result in the com-

plement of the written datum on PO.7. Once the write cycle

has been c om ple ted, true d ata a re valid on al l ou tpu ts, and

the next cy cle may begin . Data Poll ing may be gin any time

after a write cycle has been initiated.

Ready/Busy: The progress of byte programming can also

be monitor ed by th e RDY /B SY out put si gna l. P 3.4 is p ull ed

low af ter ALE goes high during programmin g to indic ate

BUSY. P3.4 is pulled high again when programming is

done to indicate READY.

Program Verify: If lock bits LB1 and LB2 have not been

programmed, the programmed code data can be read back

via the addr ess and data lines for verific ation. The lock bits

cannot be v erified directly. V erification of the lock bits is

achieved by observing that their features are enabled.

Reading the Signature Bytes: Th e signature by tes are

read by the same procedure as a normal verification of

locations 030H, 031H, and 032H, except that P3.6 and

P3.7 must be pul le d to a log ic low. The values ret urned are

as follows.

(030H) = 1EH indicates manufactur ed by Atmel

(031H) = 87H indicates 87F family

(032 H) = 01H in dicates 87F51

Not

Programming Interface

Every code byte in the QuickFlash array can be pro-

grammed by u sing the appropria te combination of co ntrol

signals. The write operation cycle is self-timed and once

initiated, will automatically time itself to completion.

All maj or prog rammi ng ve ndors of fer worl dwide su pport fo r

the Atmel microcontroller series. Please contact your local

programming vendor for the appropriate software revision.

QuickFlash Pro gram ming Modes

Figure 3. Programming the QuickFlash Memory Figure 4. Verifying the QuickFlash Memory

Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7

Write Code Data H L 12V L H H H

Read Code Data H L H H L L H H

Write Lock Bit - 1 H L 12V H H H H

Bit - 2 H L 12V H H L L

Bit - 3 H L 12V H L H L

Read Signature Byte H L H H L L L L

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/OFFFH

SEE FLASH

PROGRAMMING

MODES ABLE

3-24 MHz

A8 - A11 P0

+5V

P2.7

PGM

DATA

PROG

V/V

IH PP

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

VCC

AT87F51

P2.6

P3.6

P2.0 - P2.3

A0 - A7

ADDR.

OOOOH/0FFFH

3-24 MHz

A8 - A11 P0

+5V

P2.7

PGM DATA

(USE 10K

PULLUPS)

VIH

ALE

P3.7

XTAL2 EA

RST

PSEN

XTAL1

GND

AT87F51

SEE FLASH

PROGRAMMING

MODES ABLE

Not

QuickFlash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0 ± 10%

Symbol Parameter Min Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 1.0 mA

1/tCLCL Oscill ator Frequency 324MHz

tAVGL Address Setup to PROG Low 48tCLCL

tGHAX Address Hold After PROG 48tCLCL

tDVGL Data Setup to PR OG Low 48tCLCL

tGHDX Data Hold After PROG 48tCLCL

tEHSH P2.7 (ENABLE) High to VPP 48tCLCL

tSHGL VPP Setup to PROG Low 10 µs

tGHSL(1) VPP Hold After PROG 10 µs

tGLGH PROG Width 1 110 µs

tAVQV Address to Data Valid 48tCLCL

tELQV ENABLE Low to Data Valid 48tCLCL

tEHQZ Data Float After ENABLE 048t

CLCL

tGHBL PROG High to BUSY Low 1.0 µs

tWC Byte Write Cycle Time 2.0 ms

Not

QuickFlash Programming and Veri fication Waveforms

GLGH

GHSL

AVGL

SHGL

DVGL

GHAX

AVQV

GHDX

EHSH

ELQV

BUSY READY

GHBL

EHQZ

P1.0 - P1.7

P2.0 - P2.3

ALE/PROG

PORT 0

LOGIC 1

LOGIC 0

EA/V

P2.7

(ENABLE)

P3.4

(RDY/BSY)

PROGRAMMING

ADDRESS VERIFICATION

ADDRESS

DATA IN DATA OUT

Not

Absolute Maxim u m Ratings*

DC Characteristics

TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted)

Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

Maximum IOL per port pin: 10 mA

Maximum IOL per 8-bit port: Port 0: 26 mA

Ports 1, 2, 3: 15 mA

Maximum tota l IOL for all output pins: 71 mA

If IOL exceeds the test condition, VOL may ex ceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

2. Minimu m VCC for Power Down is 2V.

Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Abs olute

Maximum Ratings” may cause permanent dam-

age to the device . Th is is a stres s rat ing only and

funct ional ope rati on of the de vic e at these or an y

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditi ons for e xtended periods ma y affect de vice

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground.....................................-1.0V to +7.0V

Maximu m Op er ati ng Voltage ...... ...... ..... ...... ...... ............... 6.6V

DC Output Current...................... ...... .......................... 15.0 mA

Symbol Parameter Condition Min Max Units

VIL Input Low Voltage (Except EA)-0.50.2 V

CC - 0.1 V

VIL1 Input Low Voltage (EA)-0.50.2 V

CC - 0.3 V

VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V

VIH1 Input High Voltage (XTA L1, RST) 0.7 VCC VCC + 0.5 V

VOL Out put Low Voltage(1) (Ports 1,2,3) IOL = 1.6 mA 0.45 V

VOL1 Output Low Voltage(1)

(Port 0, ALE, PS EN)IOL = 3.2 mA 0.45 V

VOH Out put High Volt age

(Port s 1,2,3, ALE, PSEN )IOH = -60 µA, VCC = 5V ± 10% 2.4 V

IOH = -25 µA 0.75 VCC V

IOH = -10 µA0.9 V

CC V

VOH1 Output High Voltage

(Port 0 in Exter nal Bus Mo de) IOH = -800 µA, VCC = 5V ± 10% 2.4 V

IOH = -300 µA 0.75 VCC V

IOH = -80 µA0.9 V

CC V

IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA

ITL Logical 1 to 0 Transition Current

(Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA

ILI Input Leakage Current (Port 0, EA)0.45 < V

IN < VCC ±10 µA

RRST Reset Pulldown Resist or 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF

ICC Power Supply Current Active Mode, 12 MHz 20 mA

Idle Mode, 12 MHz 5 mA

Power Down Mode(2) VCC = 6V 100 µA

VCC = 3V 40 µA

Not

AC Characteristics

(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other

outputs = 80 pF)

External Program and Data Memory Characte ri stics

Symbol Parameter 12 MHz Oscillator Variable Oscillator Units

Min Max Min Max

1/tCLCL Oscillator Frequency 0 24 MHz

tLHLL ALE Pulse Width 127 2tCLCL-40 ns

tAVLL Address Valid to ALE Low 43 tCLCL-13 ns

tLLAX Address Hold After ALE Low 48 tCLCL-20 ns

tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns

tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns

tPLPH PSEN Pulse Width 205 3tCLCL-20 ns

tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns

tPXIX Input Instruction Hold After PSEN 00ns

tPXIZ Input Instruction Float After PSEN 59 tCLCL-10 ns

tPXAV PSEN to Address Valid 75 tCLCL-8 ns

tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns

tPLAZ PSEN Low to Address Float 10 10 ns

tRLRH RD Pulse Width 400 6tCLCL-100 ns

tWLWH WR Pulse Widt h 400 6tCLCL-100 ns

tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns

tRHDX Data Hold After RD 00ns

tRHDZ Data Float After RD 97 2tCLCL-28 ns

tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns

tAVDV Address to Valid Data In 585 9tCLCL-165 ns

tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns

tAVWL Address to RD or WR Low 203 4tCLCL-75 ns

tQVWX Data Valid to WR Transition 23 tCLCL-20 ns

tQVWH Data Valid to WR High 433 7tCLCL-120 ns

tWHQX Data Hold After WR 33 tCLCL-20 ns

tRLAZ RD Low to Address Float 0 0 ns

tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns

Not

External Program Memory Read Cycle

External Data Memory Read Cyc le

tLHLL

tLLIV

tPLIV

tLLAX tPXIZ

tPLPH

tPLAZ tPXAV

tAVLL tLLPL

tAVIV

tPXIX

ALE

PSEN

PORT 0

PORT 2

A8 - A15

A0 - A7 A0 - A7

A8 - A15

INSTR IN

LHLL

LLDV

LLWL

LLAX

WHLH

AVLL

RLRH

AVDV

AVWL

RLAZ

RHDX

RLDV

RHDZ

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA IN INSTR IN

Not

External Data Memory Write Cycle

External Clock Drive Wav eforms

External Clock Drive

Symbol Parameter Min Max Units

1/tCLCL Oscillator Frequency 0 24 MHz

tCLCL Clock P e riod 41.6 ns

tCHCX High Time 15 ns

tCLCX Low Time 15 ns

tCLCH Rise Time 20 ns

tCHCL Fall Time 20 ns

LHLL

LLWL

LLAX

WHLH

AVLL

WLWH

AVWL

QVWX

QVWH

WHQX

A0 - A7 FROM RI OR DPL

ALE

PSEN

PORT 0

PORT 2

P2.0 - P2.7 OR A8 - A15 FROM DPH

A0 - A7 FROM PCL

A8 - A15 FROM PCH

DATA OUT INSTR IN

tCHCX tCHCX

tCLCX tCLCL

tCHCL

tCLCH

V - 0.5V

0.45V 0.2 V - 0.1V

0.7 V

Not

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF)

Shift Register Mode Timing Waveforms

Symbol Parameter 12 MHz Osc Variable Oscillator Units

Min Max Min Max

tXLXL Serial Port Cloc k Cyc le Tim e 1.0 12tCLCL µs

tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns

tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns

tXHDX Input Data Hold After Clock Rising Edge 0 0 ns

tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

XHDV

QVXH

XLXL

XHDX

XHQX

ALE

INPUT DATA

CLEAR RI

OUTPUT DATA

WRITE TO SBUF

INSTRUCTION

CLOCK

SET TI

SET RI

VALID VALIDVALID VALIDVALID VALIDVALID VALID

Float Waveforms(1)

Note: 1. For timing purposes, a port pin is no longer floating

when a 1 00 m V ch ang e from load voltage occurs. A

port pin begins to float when 100 mV change from

the loaded VOH/VOL level occurs.

VLOAD+ 0.1V

Timing Reference

Points

LOAD- 0.1V

LOAD VVOL+ 0.1V

VOL - 0.1V

AC Testing Input/O utpu t Waveform s (1)

Note: 1 . A C Inp uts during testin g are driv en at VCC - 0.5V for

a logic 1 and 0.45V for a lo gic 0. Timing meas ure-

ments are made at VIH min. for a logic 1 and VIL

max. for a logic 0.

0.45V

TEST POINTS

V - 0.5V

CC 0.2 V + 0.9V

0.2 V - 0.1V

Not

Ordering Information

Speed

(MHz) Power

Supply Ordering Code Package Operation Range

12 5V ± 20% AT87F51-12AC 44A Commercial

AT87F51-12JC 44J (0°C to 70°C)

AT87F51-12PC 40P6

AT87F51-12AI 44A Industrial

AT87F51-12JI 44J (-40°C to 85°C)

AT87F51-12PI 40P6

16 5V ± 20% AT87F51-16AC 44A Commercial

AT87F51-16JC 44J (0°C to 70°C)

AT87F51-16PC 40P6

AT87F51-16AI 44A Industrial

AT87F51-16JI 44J (-40°C to 85°C)

AT87F51-16PI 40P6

20 5V ± 20% AT87F51-20AC 44A Commercial

AT87F51-20JC 44J (0°C to 70°C)

AT87F51-20PC 40P6

AT87F51-20AI 44A Industrial

AT87F51-20JI 44J (-40°C to 85°C)

AT87F51-20PI 40P6

24 5V ± 20% AT87F51-24AC 44A Commercial

AT87F51-24JC 44J (0°C to 70°C)

AT87F51-24PC 40P6

AT87F51-24AI 44A Industrial

AT87F51-24JI 44J (-40°C to 85°C)

AT87F51-24PI 40P6

Package Type

44A 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)

44J 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

40P6 40-Lead, 0.600” Wide, Plastic Dual Inline Package (PDIP)

Not

Packaging Information

*Controlling dimension: millimeters

1.20(0.047) MAX

10.10(0.394)

9.90(0.386) SQ

12.21(0.478)

11.75(0.458) SQ

0.75(0.030)

0.45(0.018) 0.15(0.006)

0.05(0.002)

0.20(.008)

0.09(.003)

0.80(0.031) BSC

PIN 1 ID

0.45(0.018)

0.30(0.012)

.045(1.14) X 45° PIN NO. 1

IDENTIFY .045(1.14) X 30° - 45° .012(.305)

.008(.203)

.021(.533)

.013(.330)

.630(16.0

)

.590(15.0

)

.043(1.09)

.020(.508)

.120(3.05)

.090(2.29)

.180(4.57)

.165(4.19)

.500(12.7) REF SQ

.032(.813)

.026(.660)

.050(1.27) TYP

.022(.559) X 45° MAX (3X)

.656(16.7)

.650(16.5)

.695(17.7)

.685(17.4)SQ

2.07(52.6)

2.04(51.8) PIN

.566(14.4)

.530(13.5)

.090(2.29)

MAX

.005(.127)

MIN

.065(1.65)

.015(.381)

.022(.559)

.014(.356)

.065(1.65)

.041(1.04)

15 REF

.690(17.5)

.610(15.5)

.630(16.0)

.590(15.0)

.012(.305)

.008(.203)

.110(2.79)

.090(2.29)

.161(4.09)

.125(3.18)

SEATING

PLANE

.220(5.59)

MAX

1.900(48.26) REF

44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)*

44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC)

Dimension in Inches and (Millimeters)

JEDEC STAN DARD MS-018 AC

40P6, 40-Lead, 0.600” Wide, Plastic Dual Inline

Package (PDIP)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-011 AC

Atmel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Atmel Corporation product.

No other circuit patent licenses are implied. Atmel Corporation’s products are not authorized for use as critical components in life support

devices or systems.

Te rms and product names in this document may be trademarks of others.

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1012A–1/98/15M