REV. 0
a
ADN2848
3 V Dual-Loop 50 Mbps to 1.25 Gbps
Laser Diode Driver
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
FUNCTIONAL BLOCK DIAGRAM
CONTROL
DATAP
DATAN
CLKP
CLKN
IMODP
LD
VCC
GND
ASET
IMOD
IBIAS
GNDGND
GND
GND
PAV CAPERCAP
ERSET
PSET
VCC
MPD
IBMON
IMMON
IMPDMON
ALS
FAIL
DEGRADE
CLKSEL
VCC
GND
VCC
ADN2848
IBIAS
LBWSET
IMODN
IMPD
GENERAL DESCRIPTION
The ADN2848 uses a unique control algorithm to control both
the average power and extinction ratio of the laser diode, LD,
after initial factory setup. External component count and PCB
area are low as both power and extinction ratio control are
fully integrated. Programmable alarms are provided for laser fail
(end of life) and laser degrade (impending fail).
FEATURES
50 Mbps to 1.25 Gbps Operation
Single 3.3 V Operation
Bias Current Range 2 mA to 100 mA
Modulation Current Range 5 mA to 80 mA
Monitor Photo Diode Current 50 A to 1200 A
50 mA Supply Current at 3.3 V
Closed-Loop Control of Power and Extinction Ratio
Full Current Parameter Monitoring
Laser Fail and Laser Degrade Alarms
Automatic Laser Shutdown, ALS
Optional Clocked Data
Supports FEC Rates
32-Lead (5 mm × 5 mm) LFCSP Package
APPLICATIONS
SONET OC-1/3/12
SDH STM-0/1/4
Fibre Channel
Gigabit Ethernet
REV. 0–2–
ADN2848–SPECIFICATIONS
NOTES
1
Temperature range is as follows: –40°C to +85°C.
2
Measured into a 25 Ω load using a 0-1 pattern at 622 Mbps.
3
When the voltage on DATAP is greater than the voltage on DATAN, the modulation current flows in the IMODP pin.
4
Guaranteed by design and characterization. Not production tested.
5
I
CCMIN
for power calculation on page 6 is the typical I
CC
given.
6
All V
CC
pins should be shorted together.
Specifications subject to change without notice.
(VCC = 3.0 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.1
Typical values as specified at 25C.)
Parameter Min Typ Max Unit Conditions/Comments
LASER BIAS (BIAS)
Output Current I
BIAS
2100 mA
Compliance Voltage 1.2 V
CC
V
I
BIAS
During ALS 0.1 mA
ALS Response Time 5 sI
BIAS
< 10% of nominal
CCBIAS Compliance Voltage 1.2 V
CC
V
MODULATION CURRENT (IMODP, IMODN)
Output Current I
MOD
580mA
Compliance Voltage 1.5 V
CC
V
I
MOD
During ALS 0.1 mA
Rise Time
2
80 170 ps
Fall Time
2
80 170 ps
Random Jitter
2
11.5 ps RMS
Pulsewidth Distortion
2
15 ps I
MOD
= 40 mA
MONITOR PD (MPD)
Current 50 1200 AAverage Current
Compliance Voltage 1.65 V
POWER SET INPUT (PSET)
Capacitance 80 pF
Monitor Photodiode Current into RPSET Resistor 50 1200 AAverage Current
Voltage 1.1 1.2 1.3 V
EXTINCTION RATIO SET INPUT (ERSET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
ALARM SET (ASET)
Allowable Resistance Range 1.2 25 kΩ
Voltage 1.1 1.2 1.3 V
Hysteresis 5 %
CONTROL LOOP Low Loop Bandwidth Selection
Time Constant 0.22 s LBWSET = GND
2.25 s LBWSET = V
CC
DATA INPUTS (DATAP, DATAN, CLKP, CLKN)
3
V p-p (Single-Ended, Peak-to-Peak) 100 500 mV Data and Clock Inputs Are
Input Impedance (Single-Ended) 50 ΩAC-Coupled
t
SETUP4
(see Figure 1) 50 ps
t
HOLD4
(see Figure 1) 100 ps
LOGIC INPUTS (ALS, LBWSET, CLKSEL)
V
IH
2.4 V
V
IL
0.8 V
ALARM OUTPUTS (Internal 30 kΩ Pull-Up)
V
OH
2.4 V
V
OL
0.8 V
IBMON, IMMON, IMPDMON
IMMON Division Ratio 100 A/A
IMPDMON 1 A/A
Compliance Voltage 0 V
CC
– 1.2 V
SUPPLY
I
CC5
50 mA I
BIAS
= I
MOD
= 0
V
CC6
3.0 3.3 3.6 V
REV. 0
ADN2848
–3–
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
CC
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 V
Digital Inputs
(ALS, LBWSET, CLKSEL) . . . . . . . . . –0.3 V to V
CC
+ 0.3 V
IMODN, IMODP . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
+ 1.2 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
J
max) . . . . . . . . . . . . . . . . . . . 150°C
32-Lead LFCSP Package
Power Dissipation
2
. . . . . . . . . . . . . . . . (T
J
max – T
A
)/θ
JA
W
θ
JA
Thermal Impedance
3
. . . . . . . . . . . . . . . . . . . . . 32°C/W
Lead Temperature (Soldering for 10 sec) . . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2
Power consumption formulae are provided on Page 6.
3
θ
JA
is defined when device is soldered in a 4-layer board.
ORDERING GUIDE
Temperature Package
Model Range Description
ADN2848ACP-32 –40°C to +85°C32-Lead LFCSP
ADN2848ACP-32-RL –40°C to +85°C32-Lead LFCSP
ADN2848ACP-32-RL7 –40°C to +85°C32-Lead LFCSP
DATAP/DATAN
SETUP HOLD
tH
tS
CLKP
Figure 1. Setup and Hold Time
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADN2848 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0–4–
ADN2848
PIN CONFIGURATION
TOP VIEW
16 CLKN
15 CLKP
14 GND1
13 DATAP
VCC2 25
IMODN 26
GND2 27
24 IBMON
12 DATAN
11 VCC1
10 PAVCAP
9 ERCAP
LBWSET 1
ASET 2
ERSET 3
PSET 4
IMPD 5
IMPDMON 6
GND4 7
VCC4 8
IMODP 28
GND2 29
GND2 30
IBIAS 31
CCBIAS 32
23 IMMON
22 GND3
21 VCC3
20 ALS
19 FAIL
18 DEGRADE
17 CLKSEL
ADN2848
PIN FUNCTION DESCRIPTIONS
Pin Number Mnemonic Function
1LBWSET Loop Bandwidth Select
2ASET Alarm Threshold Set Pin
3ERSET Extinction Ratio Set Pin
4PSET Average Optical Power Set Pin
5IMPD Monitor Photodiode Input
6IMPDMON Mirrored Current from Monitor Photodiode—Current Source
7GND4 Supply Ground
8V
CC
4Supply Voltage
9ERCAP Extinction Ratio Loop Capacitor
10 PAVCAP Average Power Loop Capacitor
11 V
CC
1Supply Voltage
12 DATAN Data Negative Differential Terminal
13 DATAP Data Positive Differential Terminal
14 GND1 Supply Ground
15 CLKP Data Clock Positive Differential Terminal, Used if CLKSEL = V
CC
16 CLKN Data Clock Negative Differential Terminal, Used if CLKSEL = V
CC
17 CLKSEL Clock Select (Active = V
CC
), Used if Data Is Clocked into Chip
18 DEGRADE DEGRADE Alarm Output
19 FAIL FAIL Alarm Output
20 ALS Automatic Laser Shutdown
21 V
CC
3Supply Voltage
22 GND3 Supply Ground
23 IMMON Modulation Current Mirror Output—Current Source
24 IBMON Bias Current Mirror Output—Current Source
25 V
CC
2Supply Voltage
26 IMODN Modulation Current Negative Output, Connect via Matching Resistor to V
CC
27 GND2 Supply Ground
28 IMODP Modulation Current Positive Output, Connect to Laser Diode
29 GND2 Supply Ground
30 GND2 Supply Ground
31 I
BIAS
Laser Diode Bias Current Output
32 CCBIAS Extra Laser Diode Bias When AC-Coupled—Current Sink
REV. 0
ADN2848
–5–
GENERAL
Laser diodes have current-in to light-out transfer functions as
shown in Figure 2. Two key characteristics of this transfer func-
tion are the threshold current, I
TH
, and slope in the linear region
beyond the threshold current, referred to as slope efficiency, LI.
ER =
P
AV
=
P1
P0
P1 + P0
2
P
ILI = P
I
I
TH
CURRENT
P1
P
AV
P0
OPTICAL POWER
Figure 2. Laser Transfer Function
Control
A monitor photodiode, MPD, is required to control the LD.
The MPD current is fed into the ADN2848 to control the power
and extinction ratio, continuously adjusting the bias current and
modulation current in response to the laser’s changing threshold
current and light-to-current slope efficiency.
The ADN2848 uses automatic power control, APC, to maintain
a constant average power over time and temperature.
The ADN2848 uses closed-loop extinction ratio control to
allow optimum setting of extinction ratio for every device. Thus
SONET/SDH interface standards can be met over device
variation, temperature, and laser aging. Closed-loop modulation
control eliminates the need to either overmodulate the LD or
include external components for temperature compensation.
This reduces research and development time and second
sourcing issues caused by characterizing LDs.
Average power and extinction ratio are set using the PSET and
ERSET pins, respectively. Potentiometers are connected
between these pins and ground. The potentiometer R
PSET
is
used to change the average power. The potentiometer R
ERSET
is
used to adjust the extinction ratio. Both PSET and ERSET are
kept 1.2 V above GND.
For an initial setup, R
PSET
and R
ERSET
potentiometers may be
calculated using the following formulas.
RV
I
PSET
AV
=12. ()Ω
RV
I
P
ER
ER P
ERSET
MPD CW
CW
AV
12
1
1
.()
_
×−
+×
Ω
where:
I
AV
is the average MPD current.
P
CW
is the dc optical power specified on the laser data sheet.
I
MPD_CW
is the MPD current at that specified P
CW
.
P
AV
is the average power required.
ER is the desired extinction ratio (ER = P1/P0).
Note that I
ERSET
and I
PSET
will change from device to device;
however, the control loops will determine the actual values.
It is not required to know the exact values for LI or MPD
optical coupling.
Loop Bandwidth Selection
For continuous operation, the user should hardwire the LBWSET
pin high and use 1 µF capacitors to set the actual loop band-
width. These capacitors are placed between the PAVCAP and
ERCAP pins and ground. It is important that these capaci-
tors are low leakage multilayer ceramics with an insulation
resistance greater than 100 GΩ or a time constant of 1,000 sec,
whichever is less.
Operation Recommended Recommended
Mode LBWSET PAVCAP ERCAP
Continuous High 1 µF1 µF
50 Mbps to
1.25 Gbps
Optimized Low 47 nF 47 nF
for 1.25 Gbps
Setting LBSET low and using 47 nF capacitors results in a
shorter loop time constant (a 10× reduction over using 1 µF
capacitors and keeping LBWSET high).
Alarms
The ADN2848 is designed to allow interface compliance to
ITU-T-G958 (11/94) section 10.3.1.1.2 (transmitter fail) and
section 10.3.1.1.3 (transmitter degrade). The ADN2848 has two
active high alarms, DEGRADE and FAIL. A resistor between
ground and the ASET pin is used to set the current at which these
alarms are raised. The current through the ASET resistor is a ratio
of 100:1 to the FAIL alarm threshold. The DEGRADE alarm will
be raised at 90% of this level.
Example:
ImAsoI mA
IImA
A
RV
IA
k
FAIL DEGRADE
ASET
FAIL
ASET
ASET
==
== =
== =
50 45
100
50
100 500
12 12
500 24
..
.
*
*The smallest valid value for R
ASET
is 1.2 kΩ, since this corresponds to the I
BIAS
maximum of 100 A.
The laser degrade alarm, DEGRADE, is provided to give a
warning of imminent laser failure if the laser diode degrades
further or environmental conditions continue to stress the LD,
such as increasing temperature.
The laser fail alarm, FAIL, is activated when the transmitter can
no longer be guaranteed to be SONET/SDH compliant. This
occurs when one of the following conditions arise:
•
The ASET threshold is reached.
•
The ALS pin is set high. This shuts off the modulation and
bias currents to the LD, resulting in the MPD current drop-
ping to zero. This gives closed-loop feedback to the system
that ALS has been enabled.
DEGRADE will be raised only when the bias current exceeds
90% of ASET current.
REV. 0–6–
ADN2848
Monitor Currents
IBMON, IMMON, and IMPDMON are current controlled
current sources from V
CC
. They mirror the bias, modulation,
and MPD current for increased monitoring functionality. An
external resistor to GND gives a voltage proportional to the
current monitored.
If the monitoring function IMPDMON is not required, the
IMPD pin must be grounded and the monitor photodiode
output must be connected directly to the PSET pin.
Data and Clock Inputs
Data and clock inputs are ac-coupled (10 nF capacitors recom-
mended) and terminated via a 100 Ω internal resistor between
DATAP and DATAN and also between the CLKP and CLKN
pins. There is a high impedance circuit to set the common-
mode voltage, which is designed to allow for maximum input
voltage headroom over temperature. It is necessary that ac
coupling be used to eliminate the need for matching between
common-mode voltages.
ADN2848
R = 2.5k, DATA
R = 3k, CLK
(TO FLIP-FLOPS)
400A TYP
DATAP
DATAN
V
REG
R
5050
Figure 3. AC Coupling of Data Inputs
For input signals that exceed 500 mV p-p single-ended, it is
necessary to insert an attenuation circuit as shown in Figure 4.
R1
R2
R3
DATAP/CLKP
DATAN/CLKN
RIN
ADN2848
NOTE THAT RIN = 100 = THE DIFFERENTIAL
INPUT IMPEDANCE OF THE ADN2848
Figure 4. Attenuation Circuit
CCBIAS
When the laser is used in ac-coupled mode, the CCBIAS and
the I
BIAS
pins should be tied together (see Figure 7). In dc-
coupled mode, CCBIAS should be tied to V
CC
.
Automatic Laser Shutdown
The ADN2848 ALS allows compliance to ITU-T-G958 (11/94),
section 9.7. When ALS is logic high, both bias and modulation
currents are turned off. Correct operation of ALS can be con-
firmed by the FAIL alarm being raised when ALS is asserted.
Note that this is the only time that DEGRADE will be low
while FAIL is high.
Alarm Interfaces
The FAIL and DEGRADE outputs have an internal 30 kΩ pull-
up resistor that is used to pull the digital high value to V
CC
.
However, the alarm output may be overdriven with an external
resistor allowing alarm interfacing to non-V
CC
levels. Non-V
CC
alarm output levels must be below the V
CC
used for the
ADN2848.
Power Consumption
The ADN2848 die temperature must be kept below 125
o
C. The
LFCSP package has an exposed paddle. The exposed paddle
should be connected in such a manner that it is at the same
potential as the ADN2848 ground pins. The θ
JA
for the package
is shown under the Absolute Maximum Ratings. Power con-
sumption can be calculated using
I
CC
= I
CCMIN
+ 0.3 I
MOD
P = V
CC
I
CC
+ (I
BIAS
V
BIAS_PIN
) + I
MOD
(V
MODP_PIN
+
V
MODN_PIN
)/2
T
DIE
= T
AMBIENT
+ θ
JA
P
Thus, the maximum combination of I
BIAS
+ I
MOD
must be calcu-
lated. Where:
ICCMIN =
50 mA, the typical value of I
CC
provided on Page 2
with I
BIAS
= I
MOD
= 0
T
DIE
= die temperature
T
AMBIENT
= ambient temperature
V
BIAS_PIN
= voltage at I
BIAS
pin
V
MODP_PIN
= average voltage at IMODP pin
V
MODN_PIN
= average voltage at IMODN pin
Laser Disode Interfacing
Many laser diodes designed for 1.25 Gbps operation are pack-
aged with an internal resistor to bring the effective impedance
up to 25 Ω in order to minimize transmission line effects. In
high current applications, the voltage drop across this resistor,
combined with the laser diode forward voltage, makes direct
connection between the laser and the driver impractical in a 3 V
system. AC coupling the driver to the laser diode removes this
headroom constraint.
REV. 0
ADN2848
–7–
ADN2848
LBWSET
ASET
ERSET
PSET
IMPD
IMPDMON
GND4
V
CC
4
IBMON
IMMON
GND3
V
CC
3
ALS
FAIL
DEGRADE
CLKSEL
CLKN
CLKP
GND1
DATAP
DATAN
V
CC
1
PAV CAP
ERCAP
V
CC
2
IMODN
GND2
IMODP
GND2
GND2
I
BIAS
CCBIAS
ALS
FAIL
DEGRADE
CLKN
CLKP
DATAP
DATAN
1.5k
18
24 17
25
32
16
9
V
CC
MPD LD
V
CC
V
CC
V
CC
10nF 10nF 10nF 10nF 10F
GND
V
CC
s SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
1k
1.5k
1.5k
10H
*
*
*
**
1F
1F
10nF
10nF
10nF
10nF
NOTES
* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
*
**
Figure 6. DC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
Caution must be used when choosing component values for ac
coupling to ensure that the time constant (L/R and RC, see
Figure 7) are sufficiently long for the data rate and expected
number of CIDs (consecutive identical digits). Failure to do this
could lead to pattern dependent jitter and vertical eye closure.
For designs with low series resistance, or where external
components become impractical, the ADN2848 supports direct
connection to the laser diode (see Figure 6). In this case, care
must be taken to ensure that the voltage drop across the laser
diode does not violate the minimum compliance voltage on the
IMODP pin.
Optical Supervisor
The PSET and ERSET potentiometers may be replaced with a
dual-digital potentiometer, the ADN2850 (see Figure 5). The
ADN2850 provides an accurate digital control for the average
optical power and extinction ratio and ensures excellent stability
over temperature.
ADN2848
ADN2850
PSET
ERSET
DATAP
DATAN
IMODP
IBIAS
DAC1
DAC2
SDI
SDO
CLK
CS
TX
RX
CLK
CS
VCC
DATAP
DATAN
VCC
VCC
IMPD
IDTONE
IDTONE
Figure 5. Application Using the ADN2850 Dual 10-Bit
Digital Potentiometer with Extremely Low Temperature
Coefficient as an Optical Supervisor
REV. 0–8–
ADN2848
Figure 8. A 1.244 Mbps Optical Eye. Temperature at 25
C.
Average Power = 0 dBm, Extinction Ratio = 10 dB, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
Figure 9. A 1.244 Mbps Optical Eye. Temperature at 85
C.
Average Power = 0 dBm, Extinction Ratio = 10 dBm, PRBS
31 Pattern, 1 Gb Ethernet Mask. Eye Obtained Using a
DFB Laser.
ADN2848
LBWSET
ASET
ERSET
PSET
IMPD
IMPDMON
GND4
VCC4
IBMON
IMMON
GND3
VCC3
ALS
FAIL
DEGRADE
CLKSEL
CLKN
CLKP
GND1
DATAP
DATAN
VCC1
PAV CAP
ERCAP
VCC2
IMODN
GND2
IMODP
GND2
GND2
IBIAS
CCBIAS
ALS
FAIL
DEGRADE
CLKN
CLKP
DATAP
DATAN
1.5k
18
24 17
25
32
16
9
MPD LD
VCC
VCC
10nF 10nF 10nF 10nF 10F
GND
VCCs SHOULD HAVE BYPASS CAPACITORS AS CLOSE
AS POSSIBLE TO THE ACTUAL SUPPLY PINS ON THE
ADN2848 AND THE LASER DIODE USED.
CONSERVATIVE DECOUPLING WOULD INCLUDE 100pF
CAPACITORS IN PARALLEL WITH 10nF CAPACITORS.
LD = LASER DIODE
MPD = MONITOR PHOTODIODE
VCC
*
1k
1.5k
1.5k
10nF
10nF
10nF
10nF
1F
1F
NOTES
* DESIGNATES COMPONENTS THAT NEED TO BE OPTIMIZED FOR THE TYPE OF LASER USED.
** FOR DIGITAL PROGRAMMING, THE ADN2850 OR THE ADN2860 OPTICAL SUPERVISOR CAN BE USED.
10H
*
*
*
*
*
*
*
*
** **
*
Figure 7. AC-Coupled 50 Mbps to 1.25 Gbps Test Circuit, Data Not Clocked
REV. 0
ADN2848
–9–
OUTLINE DIMENSIONS
32-Lead Frame Chip Scale Package [LFCSP]
(CP-32)
Dimensions shown in millimeters
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
0.30
0.23
0.18
12 MAX
0.25 REF
SEATING
PLANE
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.70 MAX
0.65 NOM
1.00
0.90
0.80
1
32
8
9
25
24
16
17
BOTTOM
VIEW
0.50
0.40
0.30
3.50
REF
0.50
BSC
PIN 1
INDICATOR
TOP
VIEW
5.00
BSC SQ
4.75
BSC SQ SQ
2.25
1.70
0.75
PIN 1
INDICATOR
0.60 MAX
0.60 MAX
–10–
–11–
C02746–0–1/03(0)
PRINTED IN U.S.A.
–12–
