ANALOG DEVICES Very Fast, Complete 12-Bit A/D Converter AD578 FEATURES Performance Complete 12-Bit A/D Converter with Reference and Clock Fast Conversion: 3ps (max) Buried Zener Reference for Long Term Stability and Low Gain T.C.: +30ppm/C max Max Nonlinearity: < + 0.012% No Missing Codes Over Temperature Low Power: 875mW Hermetic Package Available Available to MIL-STD-883 Versatility Positive-True Parallel or Serial Logic Outputs Short Cycle Capability Precision + 10V Reference for External Applications Adjustable Internal Clock "2" Models for + 12V Supplies GENERAL DESCRIPTION The AD578 is a high speed 12-bit successive approximation analog-to-digital converter that includes an internal clock, refer- ence and comparator. Its hybrid IC design utilizes MSI digital and linear monolithic chips in conjunction with a 12-bit monolithic DAC to provide superior performance and versatility with IC size, price and reliability. Important performance characteristics of the AD5S78 include a maximum linearity error at + 25C of +0.012%, maximum gain temperature coefficient of + 30ppm/C, typical power dissipation of 875mW and maximum conversion time of 3ys. The fast conversion speeds of 3us (L grade) 4.5ys (K, T grades) and 6us (J, S grades) make the AD578 an excellent choice in a variety of applications where system throughput rates from 166kHz to 333kHz are required. In addition, it may be short cycled to obtain faster conversion speeds at lower resolutions. The design of the AD578 includes scaling resistors that provide analog input signal ranges of +5V, + 10V, 0 to + 10V or 0 to +20V. Adding flexibility and value is the + 10V precision reference which can be used for external applications. The ADS578 is available with either the polymer seal (N) for use in benign environmental applications or hermetic solder- seal (D) for more harsh or rigorous surroundings. Both are contained in a 32-pin side-brazed, ceramic DIP. The AD578S, T are available processed to MIL-STD-883 Level B, Method 5008. SHORT CYCLE DIGITAL GND AD578 FUNCTIONAL BLOCK DIAGRAM AD578 BIT 12 BIT 11 BIT 10 -16V +15 ANALOG GND ZEAOD ADJ 20V SPAN INPUT BITS BITB BIT? 10V SPAN INPUT BIT6 BIPOLAR OFFSET GAIN [REF IN} REF OUT a & b a> 58 3 < a BITS BIT4 BIT3 SERIAL OUT BIT2 SERIAL OUT CONVERT START EOC CLOCK IN CLOCK OUT CLOCK ADJ BITT ITT 12-BIT SAR. +5V COMPARATOR PRODUCT HIGHLIGHTS I. The AD578 is a complete 12-bit A/D converter. No external components are required to perform a conversion. . The fast conversion rate of the AD578 makes it an excellent choice for high speed data acquisition and digital signal proc- essing applications. . The internal buried zener reference is laser trimmed to 10.00V + 1.0% and + ISppm/C typical T.C. The reference is available for external use and can provide up to ImA. . The scaling resistors are included on the monolithic DAC for exceptional thermal tracking. . The component count is minimized, resulting in low bond wire and chip count and high MTBF. . Short cycle and external clock capabilities are provided for applications requiring faster conversion speeds and/or lower resolutions. . The integrated package construction provides high quality and reliability with small size and weight. ANALOG-TO-DIGITAL CONVERTERS 3-57SPECIFICATIONS pica c +250, 150 and +57 ness cers noted Model AD578] AD578K ADS78L ADS578SD! ADS78TD' RESOLUTION 12 Bits * * * * ANALOG INPUTS Voltage Ranges Bipolar +5.0V, +10V * * * * Unipolar Oto + 10V,0to + 20V * * * * Input Impedance Oto +10V, +5V 5kQ * * * * +10V,0t0 +20V 10kQ * * * * DIGITALINPUTS Convert Command? ILSTTL Load * * Clock Input ILSTTL Load * * x * TRANSFER CHARACTERISTICS Gain Error? +0.1% FSR, + 0.25% FSR max * * * * Unipolar Offset* +0.1% FSR, + 0.25% FSR max * * * * Bipolar Error** +0.1% FSR, +0.25% FSR max * * * * Linearity Error, 25C + V/2LSB max * * * * Trin 10 Tax + 3/4LSB * * + 3/4LSB max + 3/4LSB max DIFFERENTIAL LINEARITY ERROR (Minimum resolution for which no missing codes are guaranteed) + 25C 12 Bits * . * * Tin tO Tmax 12 Bits * * . * POWER SUPPLY SENSITIVITY +15V + 10% 0.005%/%AVs max * * * * -15V = 10% 0.005%/%AVs max * * * * +5V + 10% 0.005%/%AV; max * * * * TEMPERATURE COEFFICIENTS Gain + ISppm/C typ * * * * + 30ppm"C max * * + SOppm/C max + 30ppm/C max Unipolar Offset + 3ppm/C typ . * * * + 10ppmC max . * + 15ppm/C max + 10ppm/C max Bipolar Offset + 8ppm/C typ * * * * + 20ppm/C max * * + 25ppm/C max > 20ppm/C max Differentiat Linearity + 2ppmC typ . * . * CONVERSION TIME* (max) 6.0us 4.5ps 3ps 6.0ps 4.5ps PARALLEL OUTPUTS Unipolar Code Binary * * * * Bipolar Code Offset Binary/Twos Complement * * * * Output Drive 2LSTTL Loads * * * * SERIAL OUTPUTS (NRZ FORMAT) Unipolar Code Binary/Complementary Binary * * * * Bipolar Code Offset BinaryComp. Offset Binary * * * * Output Drive ZLSTTL Loads * * * END OF CONVERSION (EOC) Logic 1 During Conversion . * * * Output Drive 8LSTTL Loads * * * * INTERNAL CLOCK* Ourput Drive 2LSTTL Loads * * * * INTERNAL REFERENCE Voltage 10.000 + 100mV * * * * Drift +12ppm/C, + 20ppmvC max * * * * External Current + 1mA max * * * * POWER SUPPLY REQUIREMENTS? Range for Rated Accuracy 4.75 to5.25 and + 13.5to + 16.5 * * * * Supply Current + 15V 3mA typ, 8mA max * * * * -15V 22mA typ, 35mA max * . * * +5V 100mA typ, 140mA max * * * * Power Dissipation 875mW typ * * * * TEMPERATURE RANGE Operating Oto + 70C * * S55Cto + 125C 55C to +: 125C Storage ~ 55C to + 150C * * -65Ct0 + 150C = 65C to +: 150C NOTES Available to MIL-ST D-883, Level B. See ADI Military Products Databook for detail specifications. ? Positive pulse 200ns wide (min) leading edge (0 to 1) resets outputs. Trailing edge initiates conversion. With 50/, 1% fixed resistor in place of gam adjust potentiometer. Adjustable to zero. 5With 500, 1 % resistor berween Ref Out and Bipolar Offset (Pins 24 & 26). SConversion time ts defined as the time between the falling edge of convert start and the falling edge of the EOC. 7 Each grade is specified at the conversion speed shown. {Externally adjustable by a resistor or capacitor see Figure 7). *Specifications same as ADS78J. 3-58 ANALOG-TO-DIGITAL CONVERTERS *For"Z models order AD578ZJ, ZK, ZL( + 11.6V 10 = 16.5V). Specifications subject to change without notice.AD578 THEORY OF OPERATION -15V +18V BIT 12 BIT 11 BIT 10 ANALOG GND ZERG ADJ 20V SPAN INPUT BITS BITS 10V SPAN INPUT BIPOLAR OFFSET BIT? BITE x wi e 4 aS SZ Ss SG < a BITS GAIN (REF IN] BIT4 REF OUT BITS SERIAL OUT SERIAL OUT CONVERT START BIT2 BIT1 art SHORT CYCLE DIGITAL GNO EOC CLOCK IN CLOCK OUT +5 CLOCK ADJ COMPARATOR Figure 1. AD578 Functional Diagram and Pinout The ADS578 is a complete pretrimmed 12-bit A/D converter which requires no external components to provide the successive- approximation analog-to-digital conversion function. A block diagram of the ADS78 is shown in Figure 1. When the control section is commanded to initiate a conversion it enables the clock and resets the successive-approximation register (SAR). The SAR, timed by the clock, sequences through the conversion cycle and returns an end-of-convert flag to the control section. The control section disables the clock and brings the output status flag low. The parallel data bits become valid on the rising edge of the clock pulse starting with t, and ending with t)2 (Figure 2), and accurately represent the input signal to within + 1/2LSB. The temperature-compensated buried Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. The reference is trimmed to 10.00 volts + 1.0%, it is buffered and can supply up to 1.0mA to an external load in addition to the current required to drive the reference input resistor (0.5mA) and bipolar offset resistor (ImA). The thin-film application resistors are trimmed to match the full scale output current of the DAC. There are two 5k0. input scaling resistors to allow either a 10 volt or 20 volt span. The 10kQ. bipolar offset resistor is grounded for unipolar operation or connected to the 10 volt reference for bipolar operation. UNIPOLAR CALIBRATION The AD578 is intended to have a nominal 1/2LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the codes above and below it). Thus, when properly calibrated, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of + 1/2LSB (1.22mV for 10V range). If pin 26 is connected to pin 30, the unit will behave in this manner, within specifications. Refer to Table I and Figure 3 for further clarification. If the offset trim (R1) is used, it should be trimmed as above, although a different offset can be set for a particular system requirement. This circuit will give approximately +25mV of offset trim range. The full scale trim is done by applying a signal 1 1/2LSB below the nominal full scale (9.9963V for a LOV range). Trim R2 to give the last transition (1111 1111 1110 to 1111 1111 111). be 200ns, min =~ CONVERT START 200nse-| fn il [*80ns CLOCK ' m| b160ns w|L 100s eoc += f BIT 2 Cy LU BIT 3 V\VQw J | [ BIT 4 SV Ld os W Lit BIT 6 ANY LI a7 WC CiS are WY LI BITS AWW L | aro WS SOtCSsetCSLLE CLD BIT 11 LJ BIT 12 CT LJ CLOCK INTERNAL. CONNECT CLOCK OUT (1B) TO CLOCK IN (19) EXTERNAL: CONNECT EXTERNAL CLOCK TO CLOCK IN (19) CLOCK SHOULD BE AT LEAST 30% DUTY CYCLE WITH MINIMUM PERIOD, Twin OF t00ns. PL NOTE 'THE RISING EOGE OF CONVERT START PULSE RESETS THE MSB TO ZERO, AND THE LS@s TO ONE. THE TRAILING EDGE INITIATES CONVERSION Figure 2, AD578 3us Timing Diagram BITS 1-12 Figure 3. Unipolar Input Connections ANALOG-TO-DIGITAL CONVERTERS 3-59BIPOLAR OPERATION The connections for bipolar ranges are shown in Figure 4. Again, as for the unipolar ranges, if the offset and gain specifications are sufficient the 1000. trimmer shown can be replaced by a 50M + 1% fixed resistor. The analog input is applied as for the unipolar ranges. Bipolar calibration is similar to unipolar cali- bration. First, a signal 1/2LSB above negative full scale ( 4.9988V for the +5V range) is applied, and R1 is trimmed to give the first transition (0000 0000 0000 to 0000 0000 0001). Then a signal 1 1/2LSB below positive full scale (+ 4.9963V for the + 5V range) is applied and R2 trimmed to give the last transition QUIET 1111 1110 co D111 WT. Figure 4. Bipolar input Connections LAYOUT CONSIDERATION Many data-acquisition components have two or more ground pins which are not connected together within the device. These grounds are usually referred to as the Logic Power Return, Analog Common (Analog Power Return), and Analog Signal Ground. These grounds must be tied together at one point, usually at the system power-supply ground. Ideally, a single solid ground would be desirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths have resistance and inductance, hundreds of millivolts can be generated between the system ground point Analog Input Volts (Center of Quantization Interval) and the ground pin of the AD578. Separate ground returns should be provided to minimize the current flow in the path from sensitive points to the system ground point. In this way supply currents and logic-gate return currents are not summed into the same return path as analog signals where they would cause measurement errors. Each of the ADS78s supply terminals should be capacitively decoupled as close to the AD578 as possible. A large value capacitor such as 10uF in parallel with a 0.1uF capaciter is usually sufficient. Analog supplies are bypassed to the Analog Power Return pin and the logic supply is bypassed to the Digital GND pin. ~15V +5V 16 O.1uF VOuF + + ANALOG OF TOF COMMON O1G O1aF 10.F oe ono 5) + +16 rt Figure 5. Basic Grounding Practice To minimize noise the reference output (pin 24) should be decoupled by a 6.8uF capacitor to pin 30. CLOCK RATE CONTROL The internal clock is preset to a nominal conversion time of 5.6us. It can be adjusted for either faster or slower conversions. For faster conversion connect the appropriate 1% resistor between pin 17 and pin 18 and short pin 18 to pin 19. For slower conversions connect a capacitor between pin 15 and pin 17, The curves in Figure 6 characterize the conversion time for a given resistor or capacitor connection. Note: 12-bit operation with no missing codes is not guaranteed when operating in this mode if a particular grades conversion speed specification has been exceeded. Short Cycle Input A Short Cycle Input, pin 14, permits the timing cycle shown in Figure 2 to be terminated after any number of desired bits has been converted, allowing somewhat shorter conversion times in applications not requiring full 12-bit resolution. Short cycle pin connections and associated maximum 12-, L0-, and 8-bit conversion times are summarized in Table II. Digital Output Code (Binary For Unipolar Ranges; Offset Binary for Bipolar Ranges) Oto +10V Oto +20V -SVto+5V | 10Vto +10V] BI Bl2 Range Range Range Range (MSB) (LSB) +9,9976 + 19.9951 +4.9976 +9.9951 LLVELIITtiidit +9.9952 + 19.9902 +4.9952 +9,9902 PLELILTI11110 + 5.0024 + 10.0049 +0.0024 + 0.0049 100000000001 + 5.0000 + 10.0000 + 0.0000 + 0.0000 100000000000 +0.0024 + 0.0051 ~ 4.9976 -9,9951 000000000001 + 0.0000 + 0.0000 5.0000 10.0000 000000000000 Table!. Digital Output Codes vs. Analog Input for Unipolar and Bipolar Ranges 3-60 ANALOG-TO-DIGITAL CONVERTERSAD578 @) ds 4.5us Gus CONVERSION CONVERSION CONVERSION RATE RATE RATE L GRADE K.T GRADES JS GRADES TO SLOW CONVERSION 8280. 3.320 USE C . . FROM () (2) @) FIGURE 6 CAPACITANCE pF v090 480 330 1 1 i 130-4 ( a 110.04 CAPACITOR w = ao Fz 2 60-4 RESISTOR = S sc+ 3 ' 9 204 1.54 T 200 10k 2k RESISTANCE 3. Figure 6. Conversion Times vs. R or C Values Resolution: Bits! 12 lu 8 Connect Pin 14 to Pin 16 2 4 Conversion Speed (as) 3 25 2 Table I, Short Cycle Connections External Clock An external clock may be connected direcly to the clock input, pin 19. When operating in this mode, the convert start should be held high for a minimum of one clock period in order to reset the SAR and synchronize the conversion cycle. A positive going pulse width of 100 to 200 nanoseconds will provide a continuous string of conversions that start on the first rising edge of the external clock after the EOC output has gone low. External Buffer Amplifier In applications where the AD578 is to be driven from high impedance sources or directly from an analog multiplexer a fast slewing, wideband op amp like the AD711 should be used. GND vs, Yoo S +hV +15 -15V is_|av_|se our 3 , ANALOG INPUT sio4 + oc ie 27 AD?11 AD7506 - AD578 S160] Nv Ris 1s BTSs 3obhs m ale una Figure 7. Input Buffer MICROPROCESSOR INTERFACING The 3s conversion times of the AD578 suggests several different methods of interface to microprocessors. In systems where the AD578 is used for high sampling rates on a single signal which is to be digitally processed, CPU-controlled conversion may be inefficient due to the slow cycle times of most microprocessors. It is generally preferable to perform conversions independently, inserting the resultant digital data directly into memory. This can be done using direct memory access (DMA) which is totally transparent to the CPU. Interface to user-designed DMA hardware is facilitated by the guaranteed data validity on the falling edge of the EOC signal. In many multichannel data acquisition systems, the processor spends a good deal of time waiting for the ADC to complete its cycle. Converters with total conversion times of 25s to 100us are not slow enough to justify use of interrupts, nor fast enough to finish converting during one instruction and are usually timed out with loops, or continuously polled for status. The AD578 allows the microprocessor to time out the converter with just a few dummy instructions. For example, an 8085 system running at a SMHz clock rate will time out an AD578 by pushing a register pair onto the stack and popping the same pair back off the stack. Such a time-out routine only occupies two bytes of program memory but requires 22 clock cyles (4.4ys). The time saved by not having to wait for the converter allows the processor to run much more efficiently particularly in multichannel systems. +8V +15V -15V | 7alS244 ANALOG INPUT 0 - 10V GAIN TRIM 100R START ADDRESS 'ACTIVE LOW! WA i 1 1 i U 1 1 1 1 1 1 1 1 t t 1 1 ! mene ~ OPTIONAL! MGHBYTEN. oo 0 ti=<_SOOSSOSOOOOO ADDRESS. (ACTIVE LOW: 7aLS244 RD Low BYTE ADDRESS 7402 (ACTIVE LOW: 4 Figure 8. AD788085A Interface Connections Clearly, 12 bits of data must be broken up for interface to an 8- bit wide data bus. There are two possible formats: right-justified and left-justified. In a right-justified system, the least-significant 8 bits occupy one byte and the four MSBs reside in the low nybble of another byte. This format is useful when the data from the ADC is being treated as a binary number between 0 and 4095. The left-justified format supplies the eight most-sig- nificant bits in one byte and the 4LSBs in the high nybble of another byte. The data now represents the fractional binary number relating the analog signal to the full-scale voltage. An advantage to this organization is that the most-significant eight bits can be read by the processor as a coarse indication of the true signal value. The full 12-bit word can then be read only when all 12 bits are needed. This allows faster and more efficient control of a process. Figure 8 shows a typical connection to an 8085-type bus, using left-justified data format for unipolar inputs. Status polling is ANALOG-TO-DIGITAL CONVERTERS 3-61optional, and can be read simultaneously with the 4LSBs. If it is desired to right-justify the data, pins 1 through 12 of the AD578 should be reversed, as well as the connections to the data bus and high and low byte address signals. When dealing with bipolar inputs (+5V, + 10V ranges), using the MSB directly yields an offset binary-coded output. If twos complement coding is desired, it can be produced by substituting MSB (pin 13) for the MSB. This facilitates arithmetic operations which are subsequently performed on the ADC output data. SAMPLED DATA SYSTEMS The conversion speed of the AD578 allows accurate digitization of high frequency signals and high throughput rates in multi- channel data acquisition systems. The AD578LD, for example, is capable of a full accuracy conversion in 3s. In order to benefit from this high speed, a fast sample-hold amplifier (SHA) such as the HTC-0300 is required. This SHA has an acquisition time to 0.01% of approximately 300ns, so that a complete sample-con- vert-acquire cycle can be accomplished in approximately 4s. This means a sample rate of 250kKHz can be realized, allowing a signal with no frequency components above 125kHz to be sampled with no loss of information. Note that the EOC signal from the AD578 places the SHA in the hold mode in advance of the actual start of the conversion cycle, and releases the SHA from the HOLD mode only after completion of the conversion. After allowing at least 300ns for the SHA to acquire the next analog value, the converter can again be started. 3-62 ANALOG-TO-DIGITAL CONVERTERS AD578 ORDERING GUIDE* Conversion | Temperature Speed Range Package Option! ADS78JN(JD) 6.0ps Oto + 70C Solder Seal (DH-32B) ADS78KN(KD) | 4.5yus Oto +70C Solder Seal (DH-32B) ADS78LN(LD) | 3.0ps Oto +70C Solder Seal (DH-32B) ADS578SD 6.0us 55C to + 125C | Solder Seal (DH-32B) ADS578SD/883B | 6.0us 55C to + 125C | Solder Seal (DH-32B) ADS78TD/883B | 4.5us 55C to + 125C | Solder Seal (DH-32B) *For + 12V operation Z version order: ADS78ZJN, . . "See Section I4 for package outline information.