Low Skew, 1-to-4, Differential-to-HSTL Fanout Buffer ICS8523 DATA SHEET General Description Features The ICS8523 is a low skew, high performance 1-to-4 Differential-to-HSTL Fanout Buffer. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. * * * Four differential output HSTL compatible outputs * PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL * * Maximum output frequency: 650MHz * * * * * * * Additive phase jitter, RMS: 0.082ps (typical), 100MHz fOUT Guaranteed output and part-to-part skew characteristics make the ICS8523 ideal for those applications demanding well defined performance and repeatability. Block Diagram CLK_EN Pullup Q PCLK Pulldown nPCLK Pullup 1 Translates any single-ended input signal to HSTL levels with resistor bias on nCLK input Additive phase jitter, RMS: 0.190ps (typical), 120MHz fOUT Output skew: 30ps (maximum) Part-to-part skew: 200ps (maximum) 3.3V core, 1.8V output operating supply 0C to 70C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VDD LE 0 CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, HCSL, SSTL Pin Assignment D CLK Pulldown nCLK Pullup Selectable differential CLK, nCLK or LVPECL clock inputs CLK_SEL Pulldown Q0 nQ0 Q1 nQ1 Q2 nQ2 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 ICS8523 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Q3 nQ3 ICS8523CG REVISION E JANUARY 24, 2011 1 2 3 4 5 6 7 8 9 10 1 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Table 1. Pin Descriptions Number Name 1 GND Power Type Description 2 CLK_EN Input Pullup 3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. 4 CLK Input Pulldown Non-inverting differential clock input. 5 nCLK Input Pullup 6 PCLK Input Pulldown 7 nPCLK Input Pullup 8, 9 nc Unused 10 VDD Power Positive supply pin. 11, 12 nQ3, Q3 Output Differential output pair. HSTL interface levels. 13, 18 VDDO Power Output supply pins. 14, 15 nQ2, Q2 Output Differential output pair. HSTL interface levels. 16, 17 nQ1, Q1 Output Differential output pair. HSTL interface levels. 19, 20 nQ0, Q0 Output Differential output pair. HSTL interface levels. Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. Inverting differential clock input. Non-inverting differential LVPECL clock input. Inverting differential LVPECL clock input. No connect. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics Symbol Parameter CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 k RPULLDOWN Input Pulldown Resistor 51 k ICS8523CG REVISION E JANUARY 24, 2011 Test Conditions 2 Minimum Typical Maximum Units (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Function Tables Table 3A. Control Input Function Table Inputs Outputs CLK_EN CLK_SEL Selected Source Q[0:3] nQ[0:3] 0 0 CLK, nCLK Disabled; LOW Disabled; HIGH 0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH 1 0 CLK, nCLK Enabled Enabled 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B. Enabled Disabled nCLK, nPCLK CLK, PCLK CLK_EN nQ[0:3] Q[0:3] Figure 1. CLK_EN Timing Diagram Table 3B. Clock Input Function Table Inputs Outputs CLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3] Input to Output Mode Polarity 0 0 LOW HIGH Differential to Differential Non-Inverting 1 1 HIGH LOW Differential to Differential Non-Inverting 0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting 1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting ICS8523CG REVISION E JANUARY 24, 2011 3 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, JA 73.2C/W (0 lfpm) Storage Temperature, TSTG -65C to 150C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Positive Supply Voltage 3.135 3.3 3.465 V VDDO Output Supply Voltage 1.6 1.8 2.0 V IDD Power Supply Current 50 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions Minimum Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V CLK_EN VDD = VIN = 3.465V 5 A CLK_SEL VDD = VIN = 3.465V 150 A CLK_EN VDD = 3.465V, VIN = 0V -150 A CLK_SEL VDD = 3.465V, VIN = 0V -5 A Table 4C. Differential DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD - 0.85 V nCLK VDD = VIN = 3.465V 5 A CLK VDD = VIN = 3.465V 150 A nCLK VDD = 3.465V, VIN = 0V -150 A CLK VDD = 3.465V, VIN = 0V -5 A NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode input voltage is defined as VIH. ICS8523CG REVISION E JANUARY 24, 2011 4 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Table 4D. LVPECL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter Test Conditions Minimum Typical Maximum Units IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Voltage 0.3 1.0 V VCMR Common Mode Input Voltage; NOTE 1 1.5 VDD V nPCLK VDD = VIN = 3.465V 5 A PCLK VDD = VIN = 3.465V 150 A nPCLK VDD = 3.465V, VIN = 0V -150 A PCLK VDD = 3.465V, VIN = 0V -5 A NOTE 1: Common mode input voltage is defined as VIH. Table 4E. HSTL DC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VOX Output Crossover Voltage VSWING Peak-to-Peak Output Voltage Swing Test Conditions Minimum Typical Maximum Units 0.9 1.4 V 0 0.4 V 40% x (VOH - VOL) + VOL 60% x (VOH - VOL) + VOL V 0.75 1.25 V NOTE 1: Outputs termination with 50 to ground. AC Electrical Characteristics Table 5. AC Characteristics, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = 0C to 70C Symbol Parameter fOUT Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Test Conditions 650MHz Minimum Typical 1.0 Maximum Units 650 MHz 1.6 ns fOUT = 100MHz, Integration Range: 12kHz - 20MHz 0.082 ps fOUT = 120MHz, Integration Range: 12kHz - 20MHz 0.190 ps tsk(o) Output Skew; NOTE 2, 3 30 ps tsk(pp) Part-to-Part Skew; NOTE 3, 4 200 ps tR / tF Output Rise/Fall Time 250 700 ps odc Output Duty Cycle 45 55 % 20% to 80% @ 50MHz NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions. NOTE: All parameters measured at 500MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. ICS8523CG REVISION E JANUARY 24, 2011 5 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. SSB Phase Noise dBc/Hz Additive Phase Jitter @ 100MHz 12kHz to 20MHz = 0.082ps (typical) Offset from Carrier Frequency (Hz) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. ICS8523CG REVISION E JANUARY 24, 2011 The source generator used is, "IFR2042 into a Hewlett Packard 8133A 3GHz Pulse Generator". 6 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Parameter Measurement Information 3.3V5% 1.8V0.2V VDD VDD Qx SCOPE nCLK, nPCLK VDDO V V Cross Points PP CMR CLK, PCLK HSTL nQx GND GND 0V Differential Input Level 3.3V/1.8V Output Load AC Test Circuit Par t 1 nQx nQx Qx Qx nQy nQy Par t 2 Qy Qy tsk(pp) tsk(o) Part-to-Part Skew Output Skew nCLK, nPCLK nQ[0:3] 80% CLK, PCLK 80% VSW I N G nQ[0:3] Q[0:3] 20% 20% tR Q[0:3] tF tPD Propagation Delay ICS8523CG REVISION E JANUARY 24, 2011 Output Rise/Fall Time 7 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Parameter Measurement Information, continued nQ[0:3] Q[0:3] t PW t odc = PERIOD t PW x 100% t PERIOD Output Duty Cycle/Pulse Width/Period Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ended levels. The reference voltage VREF = VCC/2 is generated by the bias resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the VREF in the center of the input voltage swing. For example, if the input clock swing is 2.5V and VCC = 3.3V, R1 and R2 value should be adjusted to set VREF at 1.25V. The values below are for when both the single ended swing and VCC are at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50 applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS driver. When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude, however this only applies to differential signals. For single-ended applications, the swing can be larger, however VIL cannot be less than -0.3V and VIH cannot be more than VCC + 0.3V. Though some of the recommended components might not be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized and guaranteed by using a differential signal. Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8523CG REVISION E JANUARY 24, 2011 8 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3.3V Differential Clock Input Interface Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 3A, the input termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both differential signals must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. 3.3V 3.3V 3.3V 1.8V Zo = 50 Zo = 50 CLK CLK Zo = 50 nCLK Zo = 50 nCLK Differential Input LVHSTL R1 50 IDT LVHSTL Driver R2 50 Differential Input LVPECL R1 50 R2 50 R2 50 Figure 3B. CLK/nCLK Input Driven by a 3.3V LVPECL Driver Figure 3A. CLK/nCLK Input Driven by an IDT Open Emitter LVHSTL Driver 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 Zo = 50 Zo = 50 CLK CLK R1 100 Zo = 50 nCLK R1 84 R2 84 nCLK Zo = 50 Differential Input LVPECL Receiver LVDS Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver Figure 3C. CLK/nCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50 R4 120 Zo = 60 CLK CLK Zo = 60 Zo = 50 nCLK nCLK HCSL *R4 33 R1 50 R2 50 Differential Input SSTL R1 120 R2 120 Differential Input *Optional - R3 and R4 can be 0 Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8523CG REVISION E JANUARY 24, 2011 Figure 3F. CLK/nCLK Input Driven by a 2.5V SSTL Driver 9 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3.3V LVPECL Clock Input Interface The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the PCLK/ nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V Zo = 50 3.3V 3.3V R1 50 R2 50 Zo = 50 PCLK PCLK R1 100 Zo = 50 nPCLK Zo = 50 nPCLK LVPECL Input CML LVPECL CML Built-In Pullup Input Figure 4B. PCLK/nPCLK Input Driven by a Built-In Pullup CML Driver Figure 4A. PCLK/nPCLK Input Driven by a CML Driver 3.3V 3.3V 3.3V 3.3V R3 125 3.3V 3.3V R4 125 R3 84 3.3V LVPECL Zo = 50 Zo = 50 R4 84 C1 PCLK PCLK Zo = 50 C2 Zo = 50 nPCLK nPCLK LVPECL Input LVPECL R1 84 R2 84 R5 100 - 200 R6 100 - 200 R1 125 R2 125 LVPECL Input Figure 4D. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver with AC Couple Figure 4C. PCLK/nPCLK Input Driven by a 3.3V LVPECL Driver 2.5V 3.3V 2.5V R3 120 R4 120 Zo = 60 PCLK Zo = 60 nPCLK SSTL R1 120 R2 120 LVPECL Input Figure 4E. PCLK/nPCLK Input Driven by an SSTL Driver ICS8523CG REVISION E JANUARY 24, 2011 10 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Recommendations for Unused Input and Output Pins Inputs: Outputs: LVCMOS Control Pins HSTL Outputs All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. CLK/nCLK Inputs For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from CLK to ground. PCLK/nPCLK Inputs For applications not requiring the use of a differential input, both the PCLK and nPCLK pins can be left floating. Though not required, but for additional protection, a 1k resistor can be tied from PCLK to ground. HSTL Output Termination VDDO VDD Zo = 50 + Zo = 50 HSTL ICS HiPerClockS HSTL Driv er ICS8523CG REVISION E JANUARY 24, 2011 R1 50 HSTL R2 50 11 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Schematic Example Figure 5 shows a schematic example of the ICS8523. In this example, the input is driven by an IDT HSTL driver. The decoupling capacitors should be physically located near the power pin. For ICS8523, the unused clock outputs can be left floating. Zo = 50 + Zo = 50 3.3V R12 1K U3 1.8V Zo = 50 Ohm Zo = 50 Ohm LVHSTL Driver R9 50 R10 50 R11 1K R2 50 3.3V 1 2 3 4 5 6 7 8 9 10 GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK NC NC VDD Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 20 19 18 17 16 15 14 13 12 11 R1 50 Zo = 50 + 1.8V Zo = 50 1.8V R4 50 C1 0.1u 8523 R3 50 Zo = 50 + 1.8V C2 0.1u Zo = 50 C3 0.1u R6 50 R5 50 Zo = 50 + Zo = 50 R8 50 R7 50 Figure 5. ICS8523 HSTL Buffer Schematic Example ICS8523CG REVISION E JANUARY 24, 2011 12 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Power Considerations This section provides information on power dissipation and junction temperature for the ICS8523. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW * Power (outputs)MAX = 32.6mW/Loaded Output pair If all outputs are loaded, the total power is 4 x 32.6mW = 130.4mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 130.4mW = 303.7mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The maximum recommended junction temperature is 125C. Limiting the internal transistor junction temperature, Tj, to 125C ensures that the bond wire and bond pad temperature remains below 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.304W * 66.6C/W = 90.2C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). Table 6. Thermal Resitance JA for 20 Lead TSSOP, Forced Convection JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W ICS8523CG REVISION E JANUARY 24, 2011 13 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to calculate the power dissipation for the HSTL output pair. HSTL output driver circuit and termination are shown in Figure 6. VDDO Q1 VOUT RL 50 Figure 6. HSTL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX) Pd_L = (VOL_MAX /RL) * (VDDO_MAX - VOL_MAX) Pd_H = (0.9V/50) * (2V - 0.9V) = 19.8mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW ICS8523CG REVISION E JANUARY 24, 2011 14 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Reliability Information Table 7. JA vs. Air Flow Table for a 20 Lead TSSOP JA by Velocity Linear Feet per Minute 0 200 500 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W 98.0C/W 88.0C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 66.6C/W 63.5C/W Transistor Count The transistor count for ICS8523 is: 472 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 20 A 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 6.40 6.60 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 0 8 aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 ICS8523CG REVISION E JANUARY 24, 2011 15 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Ordering Information Table 9. Ordering Information Part/Order Number 8523CG 8523CGT 8523CGLF 8523CGLFT Marking ICS8523CG ICS8523CG ICS8523CGLF ICS8523CGLF Package 20 Lead TSSOP 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP "Lead-Free" 20 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8523CG REVISION E JANUARY 24, 2011 16 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER Revision History Sheet Rev Table Page B T4D T5 5 5 HSTL table - added VSWING row to HSTL DC Characteristics Table. AC Characteristics table - tPD row, added value of 1.3ns to Min.; changed Max. from 2.0ns to 1.6ns. 7/31/01 B 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01 B 3 Updated Figure 1, CLK_EN Timing Diagram. 11/2/01 5 AC Characteristics table - tPD row, changed Min. from 1.3ns to 1.0ns. tsk(pp) row, changed Max. from 150ps to 200ps. 1/11/02 C 1 Revised Features section, Bullet 1,6 - took out 1.8V 5/6/02 C 8-10 C T5 10/25/02 Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. Absolute Maximum Ratings - changed Output rating. HSTL DC Characteristics Table - changed VOH 1V min. to 0.9V min. Power Considerations - changed Total Power Dissipation to reflect VOH change. Calculations changed due to new Total Power Dissipation. Changed LVHSTL to HSTL throughout data sheet. 6/20/03 Features section - added Lead-Free bullet. Updated LVPECL Clock Input Interface section. Added Lead-Free marking to Ordering Information table. 9/13/04 T9 1 9 15 T8 16 Ordering Information Table - in the Part/Order Number and Marking columns, changed die revision from "B" to "C". 3/2/07 T5 6 AC Characteristics Table - changed tR/tF minimum from 300ps to 250ps. 3/13/07 1 Features Section - added Additive Phase Jitter bullets. Pin Assignment has nCLK, nPCLK. Changed CLK, PCLK to nCLK, nPCLK throughout the datasheet. Absolute Maximum Ratings - corrected Outputs Rating. Differential DC Characteristics Table - updated notes. LVPECL DC Characteristics Table - updated notes. AC Characteristics Table - added Buffer Additive Phase Jitter specs. Add thermal note and updated NOTE 4. Added Additive Phase Jitter plot. Corrected Output Duty Cycle/Pulse Width/Period diagram. Updated Wiring the Differential Input to Accept Single-ended Levels application note. Updated 3.3V Differential Clock Input Interface application note. Updated 3.3V LVPECL Clock Input Interface application note. Added HSTL Output Termination diagram. 1/24/11 T4D C C D T4C T4D T5 E Date In the Application Information section, added Schematic Examples. T2 C Description of Change 2 4 5 11 - 12 4 4 5 5 6 8 8 9 10 11 ICS8523CG REVISION E JANUARY 24, 2011 17 (c)2011 Integrated Device Technology, Inc. ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER We've Got Your Timing Solution 6024 Silver Creek Valley Road San Jose, California 95138 Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT Technical Support netcom@idt.com +480-763-2056 DISCLAIMER Integrated Device Technology, Inc. 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