ICS8523CGLF - INTEGRATED DEVICE TECHNOLOGY

DATA SHEET

Low Skew, 1-to-4, Differential-to-HSTL

Fanout Buffer

ICS8523

General Description

The ICS8523 is a low skew, high performance 1-to-4

Differential-to-HSTL Fanout Buffer. The ICS8523 has two selectable

clock inputs. The CLK, nCLK pair can accept most standard

differential input levels. The PCLK, nPCLK pair can accept LVPECL,

CML, or SSTL input levels. The clock enable is internally

synchronized to eliminate runt pulses on the outputs during

asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the

ICS8523 ideal for those applications demanding well defined

performance and repeatability.

Features

•Four differential output HSTL compatible outputs

•Selectable differential CLK, nCLK or LVPECL clock inputs

•CLK, nCLK pair can accept the following differential input levels:

LVPECL, LVDS, HSTL, HCSL, SSTL

•PCLK, nPCLK pair can accept the following differential input

levels: LVPECL, CML, SSTL

•Maximum output frequency: 650MHz

•Translates any single-ended input signal to HSTL levels with

resistor bias on nCLK input

•Additive phase jitter, RMS: 0.082ps (typical), 100MHz fOUT

•Additive phase jitter, RMS: 0.190ps (typical), 120MHz fOUT

•Output skew: 30ps (maximum)

•Part-to-part skew: 200ps (maximum)

•3.3V core, 1.8V output operating supply

•0°C to 70°C ambient operating temperature

•Available in both standard (RoHS 5) and lead-free (RoHS 6)

packages

Pin Assignment

Block Diagram

CLK

nCLK

PCLK

nPCLK

nQ0

nQ1

nQ2

nQ3

CLK_EN

CLK_SEL

Pullup

Pulldown

nPCLK

PCLK

nCLK

CLK

CLK_SEL

CLK_EN

GND

VDD

nQ0

VDDO

nQ1

nQ2

DDO

nQ3

ICS8523

20-Lead TSSOP

6.5mm x 4.4mm x 0.925mm package body

G Package

Top View

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number Name Type Description

1 GND Power Power supply ground.

2 CLK_EN Input Pullup

Synchronizing clock enable. When HIGH, clock outputs follow clock input.

When LOW, Qx outputs are forced low, nQx outputs are forced high.

LVCMOS / LVTTL interface levels.

3 CLK_SEL Input Pulldown Clock select input. When HIGH, selects differential PCLK, nPCLK inputs. When

LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels.

4 CLK Input Pulldown Non-inverting differential clock input.

5 nCLK Input Pullup Inverting differential clock input.

6 PCLK Input Pulldown Non-inverting differential LVPECL clock input.

7 nPCLK Input Pullup Inverting differential LVPECL clock input.

8, 9 nc Unused No connect.

10 VDD Power Positive supply pin.

11, 12 nQ3, Q3 Output Differential output pair. HSTL interface levels.

13, 18 VDDO Power Output supply pins.

14, 15 nQ2, Q2 Output Differential output pair. HSTL interface levels.

16, 17 nQ1, Q1 Output Differential output pair. HSTL interface levels.

19, 20 nQ0, Q0 Output Differential output pair. HSTL interface levels.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

CIN Input Capacitance 4pF

RPULLUP Input Pullup Resistor 51 kΩ

RPULLDOWN Input Pulldown Resistor 51 kΩ

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Function Tables

Table 3A. Control Input Function Table

After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.

In the active mode, the state of the outputs are a function of the CLK, nCLK and PCLK, nPCLK inputs as described in Table 3B.

Figure 1. CLK_EN Timing Diagram

Table 3B. Clock Input Function Table

Inputs Outputs

CLK_EN CLK_SEL Selected Source Q[0:3] nQ[0:3]

0 0 CLK, nCLK Disabled; LOW Disabled; HIGH

0 1 PCLK, nPCLK Disabled; LOW Disabled; HIGH

1 0 CLK, nCLK Enabled Enabled

1 1 PCLK, nPCLK Enabled Enabled

Inputs Outputs

Input to Output Mode PolarityCLK or PCLK nCLK or nPCLK Q[0:3] nQ[0:3]

0 0 LOW HIGH Differential to Differential Non-Inverting

1 1 HIGH LOW Differential to Differential Non-Inverting

0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting

1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting

Biased; NOTE 1 0 HIGH LOW Single-Ended to Differential Inverting

Biased; NOTE 1 1 LOW HIGH Single-Ended to Differential Inverting

Enabled

Disabled

nCLK, nPCLK

CLK, PCLK

CLK_EN

nQ[0:3]

Q[0:3]

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

Table 4C. Differential DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

NOTE 1: VIL should not be less than -0.3V.

NOTE 2: Common mode input voltage is defined as VIH.

Item Rating

Supply Voltage, VDD 4.6V

Inputs, VI-0.5V to VDD + 0.5V

Outputs, VO -0.5V to VDDO + 0.5V

Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)

Storage Temperature, TSTG -65°C to 150°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VDD Positive Supply Voltage 3.135 3.3 3.465 V

VDDO Output Supply Voltage 1.6 1.8 2.0 V

IDD Power Supply Current 50 mA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VIH Input High Voltage 2 VDD + 0.3 V

VIL Input Low Voltage -0.3 0.8 V

IIH Input High Current CLK_EN VDD = VIN = 3.465V 5 µA

CLK_SEL VDD = VIN = 3.465V 150 µA

IIL Input Low Current CLK_EN VDD = 3.465V, VIN = 0V -150 µA

CLK_SEL VDD = 3.465V, VIN = 0V -5 µA

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current nCLK VDD = VIN = 3.465V 5 µA

CLK VDD = VIN = 3.465V 150 µA

IIL Input Low Current nCLK VDD = 3.465V, VIN = 0V -150 µA

CLK VDD = 3.465V, VIN = 0V -5 µA

VPP Peak-to-Peak Voltage; NOTE 1 0.15 1.3 V

VCMR Common Mode Input Voltage; NOTE 1, 2 0.5 VDD – 0.85 V

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Table 4D. LVPECL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

NOTE 1: Common mode input voltage is defined as VIH.

Table 4E. HSTL DC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

NOTE 1: Outputs termination with 50Ω to ground.

AC Electrical Characteristics

Table 5. AC Characteristics, VDD = 3.3V ± 5%, VDDO = 1.8V ±0.2V, TA = 0°C to 70°C

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE: All parameters measured at 500MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross

points.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and

with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

IIH Input High Current nPCLK VDD = VIN = 3.465V 5 µA

PCLK VDD = VIN = 3.465V 150 µA

IIL Input Low Current nPCLK VDD = 3.465V, VIN = 0V -150 µA

PCLK VDD = 3.465V, VIN = 0V -5 µA

VPP Peak-to-Peak Voltage 0.3 1.0 V

VCMR Common Mode Input Voltage; NOTE 1 1.5 VDD V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

VOH

Output High Current;

NOTE 1 0.9 1.4 V

VOL

Output Low Current;

NOTE 1 00.4V

VOX

Output

Crossover Voltage 40% x (VOH – VOL) + VOL 60% x (VOH – VOL) + VOL V

VSWING

Peak-to-Peak

Output Voltage Swing 0.75 1.25 V

Symbol Parameter Test Conditions Minimum Typical Maximum Units

fOUT Output Frequency 650 MHz

tPD Propagation Delay; NOTE 1 ƒ ≤ 650MHz 1.0 1.6 ns

tjit

Buffer Additive Phase Jitter,

RMS; refer to Additive Phase

Jitter Section

fOUT = 100MHz,

Integration Range: 12kHz - 20MHz 0.082 ps

fOUT = 120MHz,

Integration Range: 12kHz - 20MHz 0.190 ps

tsk(o) Output Skew; NOTE 2, 3 30 ps

tsk(pp) Part-to-Part Skew; NOTE 3, 4 200 ps

tR / tFOutput Rise/Fall Time 20% to 80% @ 50MHz 250 700 ps

odc Output Duty Cycle 45 55 %

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator used is, "IFR2042 into a Hewlett Packard

8133A 3GHz Pulse Generator".

Additive Phase Jitter @ 100MHz

12kHz to 20MHz = 0.082ps (typical)

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Parameter Measurement Information

3.3V/1.8V Output Load AC Test Circuit

Output Skew

Propagation Delay

Differential Input Level

Part-to-Part Skew

Output Rise/Fall Time

SCOPE

nQx

HSTL

GND

3.3V±5%

1.8V±0.2V

VDD

VDDO

tsk(o)

nQx

nQy

tPD

nQ[0:3]

Q[0:3]

CLK,

PCLK

nCLK,

nPCLK

nCLK, nPCLK

CLK, PCLK

VDD

GND

VCMR

Cross Points

VPP

tsk(pp)

Part 1

Part 2

nQx

nQy

20%

80% 80%

20%

tRtF

VSWING

nQ[0:3]

Q[0:3]

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Parameter Measurement Information, continued

Output Duty Cycle/Pulse Width/Period

Applications Information

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single

ended levels. The reference voltage VREF = VCC/2 is generated by

the bias resistors R1 and R2. The bypass capacitor (C1) is used to

help filter noise on the DC bias. This bias circuit should be located as

close to the input pin as possible. The ratio of R1 and R2 might need

to be adjusted to position the VREF in the center of the input voltage

swing. For example, if the input clock swing is 2.5V and VCC = 3.3V,

R1 and R2 value should be adjusted to set VREF at 1.25V. The values

below are for when both the single ended swing and VCC are at the

same voltage. This configuration requires that the sum of the output

impedance of the driver (Ro) and the series resistance (Rs) equals

the transmission line impedance. In addition, matched termination at

the input will attenuate the signal in half. This can be done in one of

two ways. First, R3 and R4 in parallel should equal the transmission

line impedance. For most 50Ω applications, R3 and R4 can be 100Ω.

The values of the resistors can be increased to reduce the loading for

slower and weaker LVCMOS driver. When using single-ended

signaling, the noise rejection benefits of differential signaling are

reduced. Even though the differential input can handle full rail

LVCMOS signaling, it is recommended that the amplitude be

reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended

applications, the swing can be larger, however VIL cannot be less

than -0.3V and VIH cannot be more than VCC + 0.3V. Though some

of the recommended components might not be used, the pads

should be placed in the layout. They can be utilized for debugging

purposes. The datasheet specifications are characterized and

guaranteed by using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

tPW

tPERIOD

tPW

tPERIOD

odc = x 100%

nQ[0:3]

Q[0:3]

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

3.3V Differential Clock Input Interface

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and

other differential signals. Both differential signals must meet the VPP

and VCMR input requirements. Figures 3A to 3F show interface

examples for the CLK/nCLK input driven by the most common driver

types. The input interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the

driver termination requirements. For example, in Figure 3A, the input

termination applies for IDT open emitter LVHSTL drivers. If you are

using an LVHSTL driver from another vendor, use their termination

recommendation.

Figure 3A. CLK/nCLK Input Driven by an IDT Open

Emitter LVHSTL Driver

Figure 3C. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3E. CLK/nCLK Input Driven by a

3.3V HCSL Driver

Figure 3B. CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 3D. CLK/nCLK Input Driven by a 3.3V LVDS Driver

Figure 3F. CLK/nCLK Input Driven by a

2.5V SSTL Driver

50Ω

1.8V

Zo = 50Ω

CLK

nCLK

3.3V

LVHSTL

IDT

LVHSTL Driver

Differential

Input

125Ω

84Ω

3.3V

Zo = 50Ω

CLK

nCLK

3.3V

LVPECL Differential

Input

HCSL

*R3 33Ω

*R4 33Ω

CLK

nCLK

3.3V 3.3V

Zo = 50Ω

Differential

Input

50Ω

*Optional – R3 and R4 can be 0Ω

CLK

nCLK

Differential

Input

LVPECL

3.3V

Zo = 50Ω

3.3V

50Ω

3.3V

100Ω

LVDS

CLK

nCLK

3.3V

Receiver

Zo = 50Ω

CLK

nCLK

Differential

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120Ω

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

3.3V LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

differential signals. Both signals must meet the VPP and VCMR input

requirements. Figures 4A to 4E show interface examples for the

PCLK/ nPCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 4A. PCLK/nPCLK Input Driven by a CML Driver

Figure 4C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 4E. PCLK/nPCLK Input Driven by an SSTL Driver

Figure 4B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 4D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

PCLK

nPCLK

LVPECL

Input

CML

3.3V

Zo = 50Ω

3.3V

50Ω

125Ω

84Ω

3.3V

Zo = 50Ω

PCLK

nPCLK

3.3V

LVPECL LVPECL

Input

PCLK

nPCLK

LVPECL

Input

SSTL

2.5V

Zo = 60Ω

2.5V

3.3V

120Ω

PCLK

nPCLK

3.3V

LVPECL

Input

3.3V

Zo = 50Ω

100Ω

CML Built-In Pullup

125

100 - 200

PCLK

nPCLK

3.3V LVPECL

3.3V

Zo = 50Ω

3.3V

LVPECL

Input

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional protection.

A 1kΩ resistor can be used.

CLK/nCLK Inputs

For applications not requiring the use of the differential input, both

CLK and nCLK can be left floating. Though not required, but for

additional protection, a 1kΩ resistor can be tied from CLK to ground.

PCLK/nPCLK Inputs

For applications not requiring the use of a differential input, both the

PCLK and nPCLK pins can be left floating. Though not required, but

for additional protection, a 1kΩ resistor can be tied from PCLK to

ground.

Outputs:

HSTL Outputs

All unused LVHSTL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

HSTL Output Termination

VDDO

Zo = 50

HSTL

ICS HiPerClockS

VDD

Zo = 50

HSTL

HSTL Driver

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Schematic Example

Figure 5 shows a schematic example of the ICS8523. In this

example, the input is driven by an IDT HSTL driver. The decoupling

capacitors should be physically located near the power pin. For

ICS8523, the unused clock outputs can be left floating.

Figure 5. ICS8523 HSTL Buffer Schematic Example

1.8V

LVHSTL Driver

Zo = 50

0.1u

R10

1.8V

R11

Zo = 50 Ohm

8523

10 11

GND

CLK_EN

CLK_SEL

CLK

nCLK

PCLK

nPCLK

VDD nQ3

VDDO

nQ2

nQ1

nQ0

VDDO

Zo = 50

Zo = 50 Ohm

Zo = 50

R12

1.8V

3.3V

0.1u

Zo = 50

3.3V

Zo = 50

0.1u

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS8523.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

• Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW

• Power (outputs)MAX = 32.6mW/Loaded Output pair

If all outputs are loaded, the total power is 4 x 32.6mW = 130.4mW

Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 130.4mW = 303.7mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond

wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θJA * Pd_total + TA

Tj = Junction Temperature

θJA = Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air

flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.304W * 66.6°C/W = 90.2°C. This is well below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 6. Thermal Resitance θJA for 20 Lead TSSOP, Forced Convection

θJA by Velocity

Linear Feet per Minute 0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the HSTL output pair.

HSTL output driver circuit and termination are shown in Figure 6.

Figure 6. HSTL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = (VOH_MAX /RL) * (VDDO_MAX - VOH_MAX)

Pd_L = (VOL_MAX /RL) * (VDDO_MAX - VOL_MAX)

Pd_H = (0.9V/50Ω) * (2V - 0.9V) = 19.8mW

Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32.6mW

VOUT

VDDO

50Ω

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Reliability Information

Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP

Transistor Count

The transistor count for ICS8523 is: 472

Package Outline and Package Dimensions

Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions

Reference Document: JEDEC Publication 95, MO-153

θJA by Velocity

Linear Feet per Minute 0 200 500

Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W

Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W

All Dimensions in Millimeters

Symbol Minimum Maximum

N20

A1.20

A1 0.05 0.15

A2 0.80 1.05

b0.19 0.30

c0.09 0.20

D6.40 6.60

E6.40 Basic

E1 4.30 4.50

e0.65 Basic

L0.45 0.75

α0° 8°

aaa 0.10

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Ordering Information

Table 9. Ordering Information

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

Part/Order Number Marking Package Shipping Packaging Temperature

8523CG ICS8523CG 20 Lead TSSOP Tube 0°C to 70°C

8523CGT ICS8523CG 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C

8523CGLF ICS8523CGLF “Lead-Free” 20 Lead TSSOP Tube 0°C to 70°C

8523CGLFT ICS8523CGLF “Lead-Free” 20 Lead TSSOP 2500 Tape & Reel 0°C to 70°C

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

Revision History Sheet

Rev Table Page Description of Change Date

T4D

HSTL table - added VSWING row to HSTL DC Characteristics Table.

AC Characteristics table - tPD row, added value of 1.3ns to Min.;

changed Max. from 2.0ns to 1.6ns.

7/31/01

B 3 Updated Figure 1, CLK_EN Timing Diagram. 10/17/01

B 3 Updated Figure 1, CLK_EN Timing Diagram. 11/2/01

CT5 5

AC Characteristics table - tPD row, changed Min. from 1.3ns to 1.0ns.

tsk(pp) row, changed Max. from 150ps to 200ps. 1/11/02

C 1 Revised Features section, Bullet 1,6 - took out 1.8V 5/6/02

C 8-10 In the Application Information section, added Schematic Examples. 10/25/02

T4D

11 - 12

Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.

Absolute Maximum Ratings - changed Output rating.

HSTL DC Characteristics Table - changed VOH 1V min. to 0.9V min.

Power Considerations - changed Total Power Dissipation to reflect VOH change.

Calculations changed due to new Total Power Dissipation.

Changed LVHSTL to HSTL throughout data sheet.

6/20/03

Features section - added Lead-Free bullet.

Updated LVPECL Clock Input Interface section.

Added Lead-Free marking to Ordering Information table.

9/13/04

CT8 16 Ordering Information Table - in the Part/Order Number and Marking columns, changed die

revision from “B” to “C”. 3/2/07

D T5 6 AC Characteristics Table - changed tR/tF minimum from 300ps to 250ps. 3/13/07

T4C

T4D

Features Section - added Additive Phase Jitter bullets.

Pin Assignment has nCLK, nPCLK. Changed CLK, PCLK to nCLK, nPCLK throughout

the datasheet.

Absolute Maximum Ratings - corrected Outputs Rating.

Differential DC Characteristics Table - updated notes.

LVPECL DC Characteristics Table - updated notes.

AC Characteristics Table - added Buffer Additive Phase Jitter specs.

Add thermal note and updated NOTE 4.

Added Additive Phase Jitter plot.

Corrected Output Duty Cycle/Pulse Width/Period diagram.

Updated Wiring the Differential Input to Accept Single-ended Levels application note.

Updated 3.3V Differential Clock Input Interface application note.

Updated 3.3V LVPECL Clock Input Interface application note.

Added HSTL Output Termination diagram.

1/24/11

ICS8523 Data Sheet LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-HSTL FANOUT BUFFER

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