Supertex inc.
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Features
►Switch mode controller for boost LED driver
►High output current accuracy
►Constant frequency operation
►Hiccup mode protection for both short circuit
and open circuit conditions
►LED wiring fault detection
Applications
► RGB or white LED backlighting
General Description
The HV9966 is a current mode control LED driver IC designed to control a
boost LED driver in constant frequency mode. The controller uses a peak
current-mode control scheme (with programmable slope compensation)
and includes an internal transconductance amplier to accurately control
the output current over all line and load conditions. The IC also provides
a disconnect switch gate drive output, which can be used to achieve good
PWM rise and fall times for the LED current using an external disconnect
FET.
The HV9966 also provides a TTL compatible, low-frequency PWM dimming
input that can accept an external control signal with a duty ratio of 0-100%
and a frequency of up to a few kilohertz.
The HV9966 includes LED wiring fault detection function which turns off
the boost converter and sends a shutdown signal to the external power
supply in case the cathode of the LED string (or any tap in the LED string)
is shorted to ground. A dedicated power supply input keeps the wiring fault
detection circuitry armed even in the absence of the VCC supply.
Typical Boost Application Circuit
Boost LED Driver with
Low-side LED Wiring Fault Detection
CIN
CCCDD
ROVP2
ROVP1
RCS
RIN
L1
Q1
D1
RR2
RR1
VCC
PWMD
FLAG
DR
DIS
FB
RT DUTY COMP VDD REF
VIN GT CS GND OVP
RS
Q2
HV9966
RSC
CO
R1
R2
R3
RT
ZD1
CVIN
VBST
12V
CVCC
2
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Parameter Value
VDD to GND -0.5V to +16V
GATE, DIS to GND -0.3V to (VCC +0.3V)
VDD to GND -0.3V to +3.8V
VIN to GND -0.3V to +3.8V
DR, RT, FLAG to GND -0.3V to (VIN +0.3V)
REF to GND -0.3V to +1.5V
All other pins to GND -0.3V to (VDD +0.3V)
Junction temperature +150°C
Storage ambient temperature range -65°C to +150°C
Continuous power dissipation (TA = +25°C) 1000mW
Sym Description Min Typ Max Unit Conditions
Input
VCCDC Input DC supply voltage range - 10 12 14 V DC input voltage
ICCSD Shut-down mode supply current - - - 1.5 mA PWMD to GND
UVLORISE,VCC VCC under-voltage lockout threshold * 9.0 - 9.5 V VCC rising
UVLOHYST,VCC VCC under-voltage hysteresis - - 1.0 - V VCC falling
Internal Low Voltage Regulator
VDD Internally regulated voltage - 3.23 3.30 3.37 V PWMD = VDD; fs = 300kHz;
IVDD_EXT = 0 -500μA
UVLORISE,VDD VDD under-voltage lockout threshold * 3.03 3.10 3.17 V VCC rising
UVLOHYST,VDD VDD under-voltage hysteresis - - 0.20 - V VCC falling
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DR
DUTY
RT
CS
GND
GATE
VCC
DIS
FLAG
VIN
PWMD
FB
REF
COMP
OVP
VDD
Pin Description
Product Marking
Y = Last Digit of Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
T
op
M
ar
ki
ng
Bottom Marking
HV9966NG
YWW LLLLLLLL
CCCCCCCCC AAA
16-Lead SOIC (NG)
(top view)
Electrical Characteristics
(The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications are
at TA = 25OC. VCC = 12V, CVCC = 1.0μF, CDD = 1.0μF, CGATE = 1.0nF, CFLT = 500pF, RT = 374kΩ, DUTY = GND unless otherwise noted.)
Typical Thermal Resistance
Package θj-a
16-Lead SOIC 83OC/W
16-Lead SOIC (NG)
Package may or may not include the following marks: Si or
Note:
# Denotes specications guaranteed by design
-G indicates package is RoHS compliant (‘Green’)
Part Number Package Option Packing
HV9966NG-G 16-Lead SOIC (Narrow Body) 45/Tube
HV9966NG-G M934 16-Lead SOIC (Narrow Body) 2500/Reel
Ordering Information
3
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Sym Description Min Typ Max Unit Conditions
PWM Dimming
VPWMD(lo) PWMD input low voltage * - - 1.0 V ---
VPWMD(hi) PWMD input high voltage * 2.0 - - V ---
RPWMD PWMD pull down resistor - 50 100 100 kΩ VPWMD = VDD
Boost FET Driver
ISOURCE GATE short circuit current, sourcing * 0.25 - - A VGATE = 0V
ISINK GATE sinking current * 0.50 - - A VGATE = VCC
TRISE GATE output rise time - - - 70 ns ---
TFALL GATE output fall time - - - 35 ns ---
Disconnect FET Driver
ISOURCE,DIS GATE short circuit current, sourcing * 0.02 - - A VGATE = 0V
ISINK,DIS GATE sinking current * 0.04 - - A VGATE = VCC
TRISE,DIS GATE output rise time - - - 300 ns ---
TFALL,DIS GATE output fall time - - - 150 ns ---
Oscillator
fOSC1 Oscillator frequency - 88 100 112 kHz RT = 374kΩ
fOSC2 Oscillator frequency - 220 250 280 kHz RT = 249kΩ
FOSC Output frequency range # 80 - 300 kHz ---
DMAX Maximum duty cycle at GATE output * 87 - 93 % DUTY = GND
- 67 - 73 % DUTY = VDD
Current Sense
TBLANK Leading edge blanking * 100 - 250 ns ---
TPROP_DELAY1 Delay to Gate falling - - - 200 ns COMP = VDD;
50mV overdrive at CS
RDIV
Internal resistor divider ratio – COMP
to CS # - 0.167 - - ---
VOFFSET Comparator offset voltage # -10 - 10 mV ---
RPULLDOWN Pull down FET resistance * - - 100 Ω---
Over Voltage Protection
VOVP,RISING Over voltage rising trip point * 1.94 2.00 2.06 V OVP rising
VOVP,HYST Over voltage hysteresis - - 0.2 - V OVP falling
TPROP_DELAY Propagation delay time - - - 200 ns 50mV overdrive
Electrical Characteristics (cont.)
(The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications are
at TA = 25OC. VCC = 12V, CVCC = 1.0μF, CDD = 1.0μF, CGATE = 1.0nF, CFLT = 500pF, RT = 374kΩ, DUTY = GND unless otherwise noted.)
Note:
# Denotes specications guaranteed by design
4
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Sym Description Min Typ Max Unit Conditions
Internal Transconductance Opamp
GB Gain-bandwidth product # - 1.0 - MHz 75pF capacitance at COMP
pin
AVOpen loop DC gain - 65 - - dB Output open
VCM Input common-mode range # -0.3 - 1.5 V ---
VOOutput voltage range # 0.7 - VDD-0.7 V AV ≥ 65dB
GmTransconductance - - 500 - μA/V ---
VOFFSET Input offset voltage * -3.0 - 3.0 mV ---
IBIAS Input bias current # - 0.5 1.0 nA ---
ICOMP,DIS Discharging current with pull down FET - 10 - - mA VCOMP = 2.0V
ICOMP,LKG COMP leakage current * - - 10 nA PWMD = GND;
COMP = 2.0V
GBBUFFER Gain-bandwidth of the buffer # 20 - - kHz ---
VIN Pin
UVLO_RISE,VIN VIN under voltage lockout threshold * 2.62 2.76 2.90 V VIN rising
UVLO_HYST,VIN VIN under voltage hysteresis - - 0.20 - V VIN falling
DR and FLAG pins
VREF Comparator reference voltage * 1.58 1.75 1.92 V ---
TPROP_DELAY Propagation delay time - - - 200 ns VDR = VREF +0.1V
VCLAMP,DR Clamp Voltage at DR pin
* 2.00 - 2.50 V Current into DR pin = 50μA
* 2.75 - 3.20 V Current into DR pin = 1mA
ISOURCE,FLAG Source current from FLAG pin - 10 - - mA FLAG = GND
ISINK,FLAG Sink current into FLAG pin - 10 - - mA FLAG = GND
TRISE,FLAG GATE output rise time - - - 40 ns CFLAG = 500pF
TFALL,FLAG GATE output fall time - - - 40 ns CFLAG = 500pF
Wiring Fault Detection (PWMD high)
VREF1 COMP rail comparator detect threshold - - VDD-0.3 - V ---
VREF2 FB low comparator threshold - - 0.1 - V ---
TPROP_DELAY Propagation delay time - - - 200 ns 50mV overdrive
Over Current Protection
KOCP
Multiplication factor for over-current
protection * 1.95 2.00 2.05 - ---
VOCP Minimum voltage at output of gain stage * 0.22 - 0.24 V REF = GND
TBLANK,OCP Blanking time for OCP * 500 - 900 ns ---
TPROP_DELAY Propagation delay time * - - 200 ns 50mV overdrive
Note:
# Denotes specications guaranteed by design
Electrical Characteristics (cont.)
((The * denotes the specications which apply over the full operating ambient temperature range of -40OC < TA < +125OC, otherwise the specications
are at TA = 25OC. VCC = 12V, CVCC = 1.0μF, CDD = 1.0μF, CGATE = 1.0nF, CFLT = 500pF, RT = 374kΩ, DUTY = GND unless otherwise noted.)
5
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Functional Block Diagram
VCC
VDD
CS
GND
COMP
REF
FB
+
-
-
+
+
-
+
-
+
-
+
-
+
-
S
R
Q
S
R
Q
Q
1
2
+
-
+
-
+
-
S
R
Q
Blanking
min
Monoshot
Monoshot
Monoshot Monoshot
Clock
Sync
4 bit
Counter
CLR
EN
/4
8 bit
Counter
CLR
EN
n256
Monoshot
S
R
Q
2.76V/2.56V
2.0V
9.25V/
8.25V
3.1V/
2.9V
VDD - 0.3V
0.1V
POR2 DIM
n16
POR2
OLD
FLAG
n16
CLK
CLK/4
n16
POR2DIM
2.0V/1.8V
FLAGCLK
GTB
DIMFLT
DIM
CLK/4
RST
RST
OV
OV
OC
OLD
FLTCLR1
Fault
Latch
POR1
Latch
Q
R S
DIM
OC
DIM
POR1
DIM DIM
SC
OL1
OL2
RST
OL1
OL2
FLT
CLR1
GTB
POR1
FLT
FLAG
RT
OVP
GT DIS VIN DR
PWMD
Regulator
Note:
Circuit in shaded area is powered off the VIN pin; rest of the circuit is powered off the VDD regulator (powered off VCC for the gate drivers)
6
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
VCC, VDD and Gate Drivers
The external voltage applied at VCC is used to power the IC.
The voltage at this pin is typically 12V+/-15% with a 16V abs
max rating.
An internal linear regulator is used to generate 3.3V at VDD
pin which is used to power the low voltage analog circuit. The
voltage at VDD pin can also be used as a reference to set the
LED current using a resistor divider from VDD to the REF pin.
Both VCC and VDD have built-in UVLO to disable the IC in
case the voltages at the pins are lower than expected.
The gate drivers are powered off directly from the VCC pin.
The switching gate driver currents are supplied from the low
ESR capacitor connected externally at the VCC pin.
GM Amplier and PWM dimming
The GM amplier is used to control the LED current. The current
level is set by the voltage at the REF pin and the LED current is
sensed by a current sense resistor and the voltage across the
sense resistor is fed into the FB pin. The compensation capaci-
tor is connected between COMP and GND.
When PWMD is high, the OTA is allowed to control the voltage
at the COMP pin. When PWMD is low, the OTA is disconnected
from the COMP pin. The leakage current at the COMP pin due
to all circuitry connected to it (ESD protection, pull down tran-
sistor and disconnect switch) should be less than 10nA.
The pull down FET at the COMP pin is used to discharge the
COMP capacitor at startup and during fault conditions.
Boost FET current sense
The current sense pin has a built in 100 - 250ns blanking time.
It also has a pull down FET which is turned on whenever the GT
is off. This is to facilitate slope compensation using an external
resistor/capacitor network. Although most applications with this
IC are expected to be DCM boost circuits which do not need
slope compensation, the pull-down FET is included for to make
the part usable for CCM boost converters as well.
Hiccup timer
Hiccup timing is achieved by using an internal 8-bit counter
which counts 1024 clock cycles. This makes the hiccup time
dependent on the switching frequency.
Startup
When power is initially applied to the IC, POR1 goes high. At
this point, two latches – Fault latch and POR1 latch – are set
and FLT goes high. The POR1 latch output will be high untill the
rst PWM pulse is applied at PWMD. This keeps the counter
cleared and enabled till the PWMD pulse is applied. Once the
rst PWM dimming pulse is applied, the counter is allowed to
count to 256, at which point the gate drivers and COMP pin
are released, and the converter can start regulating the LED
current.
Over-Voltage and Over-Current Fault
Over-voltage is detected using the voltage at the OVP pin.
When the voltage at OVP exceeds 2.0V, over-voltage is trig-
gered and the over-voltage condition is said to exist untill the
voltage at OVP drops below 1.8V (10% lower).
Over-current condition is detected by the over-current compar-
ator, which compares the voltage at the FB pin with two-times
the voltage at the REF pin.
As long as these fault conditions exist, they set the Fault latch,
which turns off the gate drivers and clears the 8-bit counter and
keeps the counter cleared. Once the fault disappers, the coun-
ter is allowed to count and the operation of the IC is identical to
the startup case.
Short Circuit to Chassis Condition
A wiring fault condition occurs during the manufacturing pro-
cess involving large LED strings. Consider a case of three LED
light bars connected in series and driven from the same boost
converter. The input to the boost converter is typically about
120V. Assume each LED light bar has a forward drop of about
80V (25 LEDs with 3.2V/per LED). If one of the connections be-
tween the LED light bars is shorted to ground (see Fig.1), then
the boost converter looses the feedback signal since all the cur-
rent ows through the short bypassing the sense resistor.
Fig.1 : Short Circuit to Chassis
In this case, COMP will rail to VDD and the boost converter
will operate at its maximum power limit. This excessive current
through the rst two light bars could damage the LEDs.
A1
C1
C2
C3
Q2
R2
7
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
This situation needs to be detected and prevented. Note that
turning off the boost converter might not be sufcient in all cas-
es. For example, if C1 was shorted in ground in Fig.1, the LED
string voltage (one string; 80V) is lower than the input voltage
(120V) and turning off the boost converter will not prevent the
short circuit current. Hence, the main solution – besides turning
off the boost converter – is to signal the 120V power supply to
turn off. This is achieved by means of the FLAG output.
In the HV9966, a short cathode condition is detected by sens-
ing the drain voltage of the disconnect FET. However, the drain
voltage of the disconnect FET is zero when PWMD is high. So,
the detection is separated into two cases – PWMD high and
PWMD low – and each case is detected differently.
Detection of Short Circuit to Chassis when
PWMD is High
When a wiring fault condition occurs while the boost converter
is running, FB will go to zero and COMP will rail to VDD. This
is the condition that is used to detect a short circuit to chassis.
However, this condition is also likely to happen at startup.
If the COMP capacitor is low (to achieve a fast transient re-
sponse) and the output capacitor is large, the startup wave-
forms may look as shown below (Fig. 2).
In Fig.2, the rst PWMD pulse is applied at t0.
Since FB is zero, COMP voltage starts ramping up. Giv-
en the large output capacitor, COMP hits VDD before the
output capacitor voltage can meet the LED string volt-
age.
At this point, COMP = VDD and FB<0.1V. This sets signal
OL1. This resets the counter and the counter is ready to
count when PWMD is high.
In this time interval, both OLP1 and OLP2 are high and
the counter is counting.
In this interval, OLP2 = 0 and counter is disabled and so
holds its previous state. Enabling the counter only when
PWMD is high ensures that the delay time is measured
only when PWMD is high, effectively scaling the delay
time by the PWMD duty cycle. If the converter were start-
ed with a low PWM dimming duty cycle, not scaling the
delay time would cause a false detection since the coun-
ter would have reached 256 long before COMP can re-
spond (since COMP responds only when PWMD is HI).
At t5, FB = 0.1V and counter has not yet reached 256.
The programmed delay helps to avoid false detection of an
open circuit condition at startup or due to a transient condition
as described above. Thus, once the condition is detected, the
IC waits for the programmed time and if the counter goes all the
way to 256, then the IC turns off and pulls FLAG down. The IC
can be turned on only by cycling the voltage at VIN.
Detection of Short Circuit to Chassis when
PWMD is Low
When PWMD is off, or VCC is not applied, the wiring fault is de-
tected by sensing the voltage at the drain pin of the disconnect
FET. This part of the IC is powered by the voltage at the VIN
pin and not through the VCC pin. This makes the fault detec-
tion independent of the power sequence of the various supplies
(VCC, VIN and PWMD).
For the scheme to work, one of two things is required – either
one diode per LED light bar (as shown in Fig.1) or a parallel
Zener diode across each LED (which typically exist in many
LEDs used for backlighting applications).
During normal operation (no short to chassis), the drain of the
disconnect FET is pulled to ground when PWMD is high. When
PWMD goes low, this FET is turned off. At that time, the parasit-
ic capacitance at the drain node (node C3 in Fig. 1), is charged
to the output voltage through resistor R1. The voltage at the
drain is then sensed through resistor divider R2/R3 (which may
or may not be used).
There is a built in delay which is equal to 64 switching cycles
(about 640us at 100kHz switching frequency). Resistor R1 is
programmed such that the voltage at DR pin exceeds 2.0V
within this delay time.
t0-t1:
t1-t2:
t2-t3:
t
0
t
1
t
2
t
3
t
4
t
5
t
6
PWMD
COMP
Output
Voltage
FB
t3-t4:
t4-t5:
8
HV9966
Supertex inc.
www.supertex.com
Doc.# DSFP-HV9966
A051412
Case 1: Short circuit to chassis condition occurs during
normal operation
Assuming the antiparallel diodes are used, if there is a wiring
fault condition, then the current through R1 will ow through the
antiparallel diodes into the short and the drain node will not ex-
ceed one or two diode drops above ground. Thus, a fault condi-
tion is detected and it is agged.
Note: If the PWM dimming duty cycle is large enough that the
dimming off-time is less than the delay, then this method of fault
detection will not work. However, the detection will occur under
PWMD high.
Case 2: Short circuit to chassis condition occurs when
VCC is off
In this case, when the 120V boost power supply comes on, the
voltage at VIN is regulated to 4.7V using the external Zener
diode. Once the voltage at VIN is stabilized, the IC waits for 64
cycles of the clock. Once the timer has run out, if the DR pin is
still below 2.0V, then the IC FLAGs a fault.
Note: For ESD protection, back to back diodes are needed be-
tween the VIN and VDD pins. When VCC is applied, the 4.7V at
VIN pin combined with the 5.0V at VDD ensure that the exter-
nal Zener diode will not be powered through VDD. When VCC is
not applied, the voltage at VDD will be 4.7 – 0.6V = 4.1V, which
is lower than its UVLO setting. This will keep the IC off and en-
sure that it is not powered on through the VIN pin.
Pin Description (16-Lead SOIC)
Pin # Name Description
1 DR This pin is connected to the drain of the disconnect FET through a resistor divider and is used to detect
a short circuit to chassis wiring fault.
2 DUTY This pin sets the duty cycle output for the IC. Connecting DUTY to GND programs the maximum duty
cycle to 90%, whereas connecting it to VDD programs the maximum duty cycle to 70%.
3RT This pin sets the frequency of the power circuit. A resistor between RT and GND will program the circuit
in constant frequency mode. The switching frequency is synchronized to the PWMD turn on edge.
4 CS This pin is used to sense the source current of the external power FET. It includes a built-in 100ns (min)
blanking time.
5 GND Ground return for all the low power analog internal circuitry as well as the gate drivers. This pin must be
connected to the return path from the input.
6 GATE This is the GATE driver output for the switching FET.
7 VCC This pin is the power supply input to the IC.
8 DIS This pin is used to drive an external disconnect FET which disconnects the load from the circuit during
a fault condition or during PWM dimming to achieve a very high dimming ratio.
9 VDD This pin is the output of the low voltage regulator. A low ESR capacitor should be connected from this
pin to GND.
10 OVP
This pin provides the over voltage protection for the converter. When the voltage at this pin exceeds
2.0V, the gate output of the HV9966 is turned off and DIS goes low. The IC will turn on when the voltage
at the pin goes below 1.8V.
11 COMP Stable closed loop control can be accomplished by connecting a compensation network between COMP
and GND.
12 REF The voltage at this pin sets the output current level. The current reference can be set using a resistor
divider from the VDD pin.
13 FB This pin provides output current feedback to the HV9966 by using a current sense resistor.
14 PWMD When this pin is pulled to GND (or left open), switching of the HV9966 is disabled. Then an external TTL
high level is applied to it, switching will resume.
15 VIN
This pin is powered from the input of the boost power supply so that the logic powered by the VCC pin
is enabled even if there is no VCC at the IC. This pin is used to power the wiring fault detection circuit in
the IC. An external 3.0V or 3.3V Zener diode is typically used.
16 FLAG This is an active-low, open drain pin which is used to disable the boost power supply in case of a wiring
fault.
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives
an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability
to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and
specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)
©2012
Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Supertex inc.
1235 Bordeaux Drive, Sunnyvale, CA 94089
Tel: 408-222-8888
www.supertex.com
9
HV9966
(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV9966
A051412
16-Lead SOIC (Narrow Body) Package Outline (NG)
9.90x3.90mm body, 1.75mm height (max), 1.27mm pitch
Symbol A A1 A2 b D E E1 e h L L1 L2 θ θ1
Dimension
(mm)
MIN 1.35* 0.10 1.25 0.31 9.80* 5.80* 3.80*
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0O5O
NOM - - - - 9.90 6.00 3.90 - - - -
MAX 1.75 0.25 1.65* 0.51 10.00* 6.20* 4.00* 0.50 1.27 8O15O
JEDEC Registration MS-012, Variation AC, Issue E, Sept. 2005.
* This dimension is not specied in the JEDEC drawing.
Drawings are not to scale.
Supertex Doc. #: DSPD-16SONG, Version G041309.
Top View
Side View View A-A
View B
A
A
Seating
Plane
16
1Seating
Plane
Gauge
Plane
L
L1
L2
θ1
θ
View B
h
h
b
AA2
A1
e
E
E1
D
Note 1
(Index Area
D/2 x E1/2)
Note:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be:
a molded mark/identier; an embedded metal marker; or a printed indicator.
