EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown PRODUCT FEATURES Datasheet General Description Features The EMC2102 is an SMBus, closed-loop, RPM-based fan controller/driver with hardware (HW) thermal shutdown and reset controller. The EMC2102 is packaged in a thermally enhanced, compact, 5x5, 28pin lead-free RoHS compliant QFN package. The EMC2102 utilizes Beta Compensation (an implementation of the BJT or transistor model for thermal diodes) and Resistance Error Correction (REC) to accurately monitor three external temperature zones. These features allow great accuracy for CPU substrate thermal diodes on multiple process geometries as well as with discrete diode-connected transistors. Both Beta Compensation and REC can be disabled on the EMC2102 to maintain accuracy when monitoring AMD thermal diodes. The EMC2102 includes a closed-loop RPM based Fan Control Algorithm that integrates a linear fan driver capable of sourcing 600mA of current. The fan control algorithm is designed to work with fans that operate up to 16,000 RPMs. The EMC2102 provides a stand-alone HW thermal shutdown block. The HW thermal shutdown logic can be configured for a few common configurations based on the strapping level of the SHDN_SEL pin on the PCB. The HW thermal shutdown point can be set in 1C increments by using a discrete resistor divider implemented on the TRIP_SET pin. The EMC2102 also provides 5V supply `power good' function with a threshold of 4.5V. This function is provided on the RESET# pin. SMSC EMC2102 Designed to support 45nm, 65nm, and 90nm CPU Diodes Supports BJT and transistor models for diode channels Closed-Loop RPM Based Fan Controller -- Accepts External Clock Source To Achieve 2% Accuracy Integrated Linear Fan Driver HW Thermal Shutdown (SYS_SHDN#) -- 600mA Drive Capability -- 1C Incremental Set Points For Thermal Shutdown -- Cannot be disabled by software Provides Reset Function (RESET#) On 5V Supply Three Remote Thermal Zones -- 1C Accuracy (60C to 100C) -- 1C Resolution Resistance Error Correction On Thermal Diode Channels -- Eliminates Temperature Offset Due To Series Resistance From PCB Traces And Thermal `Diode' Thermally Enhanced, 28-pin, 5x5 QFN Lead-free RoHS Compliant Package Operates From Single 3.0 - 3.6V Supply -- 5V Supply For Linear Fan Driver Software Configurable ALERT# Signal For Diode Fault, Fan Stall Or System Warning Notebook Computers Desktop Computers Embedded Applications Applications DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet ORDER NUMBER: EMC2102-DZK FOR 28-PIN QFN LEAD-FREE ROHS COMPLIANT PACKAGE (ADDRESS - 011_1101) 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Revision 2.02 (05-17-07) 2 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table of Contents Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Chapter 2 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 Pin Layout for EMC2102. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Pin Description for EMC2102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 3.2 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Chapter 4 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 16 16 17 17 Chapter 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 5.2 5.3 Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.3 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Programming the RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 TACH Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 20 20 21 21 23 23 5.3.2.1 Stalled Fan23 5.4 5.5 5.6 5.7 5.8 5.3.3 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.4 FAN_MODE Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.5 32.768KHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Side Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Overcurrent Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Thermal Shutdown (TSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 TRIP_SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Internal HW_SHDN Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 25 25 25 26 26 26 26 28 28 29 30 Chapter 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.1 6.2 6.3 6.4 6.5 6.6 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown Temperature Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMSC EMC2102 3 DATASHEET 31 32 33 34 34 35 36 Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Step Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 38 39 40 40 41 42 43 43 44 44 44 45 46 Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Appendix A TACH Reading Table - 2000 RPM Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Appendix B TACH Reading Table - 500RPM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision 2.02 (05-17-07) 4 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet List of Figures Figure 1.1 Figure 2.1 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 7.1 EMC2102 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 EMC2102 Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 EMC2102 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RPM based Fan Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 EMC2102 Critical/Thermal Shutdown Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 HW_SHDN Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5V Reset Controller Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . 47 SMSC EMC2102 5 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet List of Tables Table 2.1 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 5.1 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5.2 FAN_MODE Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.3 CLK_SEL Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 5.4 SHDN_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 6.1 EMC2102 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 6.2 Temperature data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 6.4 Critical/Thermal Shutdown Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.5 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.6 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 6.7 Conversion Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6.8 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.9 Interrupt Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 6.10 Interrupt Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.11 Interrupt Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 6.12 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 6.13 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.14 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6.15 Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 6.16 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 6.17 Fan Control Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.18 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 6.19 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.20 Fan TACH Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.21 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 6.22 Fan Step Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.23 Minimum Fan Drive Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6.24 Valid TACH Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.25 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.26 TACH Reading Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 6.27 Example TACH Reading for Specific Fan Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 6.28 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 6.29 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7.1 TACH Count to RPM (2k Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 7.2 TACH Count to RPM (500 Range) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Revision 2.02 (05-17-07) 6 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet RESET# SYS_SHDN# THERMTRIP# VDD_3V SHDN_SEL Chapter 1 Block Diagram VDD_5V TRIP_SET Reset Generator Critical / Thermal Shutdown Logic DP1 DN1 DP2 DN2 External Temp Diodes DP3 DN3 Ext Temp Limit Registers Analog Mux 11 bit ADC Internal Temp Diode SMDATA ALERT# POWER_OK Voltage Reading Voltage -> Temperature Converison Register Set and Logic FAN_MODE CLK_IN TACH Monitor TACH High Side Fan Driver CLK_SEL Automatic Fan Control Algorithms FAN (2) 8-bit DAC SMCLK Ext. Temp Registers Bandgap Reference VDD_5V (2) SMBus Slave Protocol Figure 1.1 EMC2102 Block Diagram SMSC EMC2102 7 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 2 Pinout TACH VDD_5V FAN FAN VDD_5V SMCLK SMDATA 28 27 26 25 24 23 22 Pin Layout for EMC2102 VDD_3V 1 21 N/C DN1 2 20 GND DP1 3 19 ALERT# DN2 4 DP2 5 17 CLK_SEL DN3 6 16 RESET# DP3 7 15 N/C POWER_OK 14 18 CLK_IN THERMTRIP# 13 SYS_SHDN# 12 TRIP_SET 11 FAN_MODE 10 N/C SHDN_SEL 9 EMC2102 5 x 5 QFN 8 2.1 Figure 2.1 EMC2102 Pin Diagram Revision 2.02 (05-17-07) 8 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 2.2 Pin Description for EMC2102 Table 2.1 Pin Description PIN NAME FUNCTION TYPE 1 VDD_3V Supply Connection of 3.3V. Power 2 DN1 Negative (cathode) Analog Input for External Diode 1. AIO 3 DP1 Positive (anode) Analog Input for External Diode 1. AIO 4 DN2 Negative (cathode) Analog Input for External Diode 2. AIO 5 DP2 Positive (anode) Analog Input for External Diode 2. AIO 6 DN3 Negative (cathode) Analog Input for External Diode 3. AIO 7 DP3 Positive (anode) Analog Input for External Diode 3. AIO 8 N/C Not internally connected. N/A SHDN_SEL Determines HW Shutdown temperature channel (see Table 5.4, "SHDN_SEL Pin Configuration".) DIT 10 FAN_MODE Selects power-up default for fan drive setting. DIT 11 TRIP_SET Voltage input to determine HW Shutdown threshold temperature AI 12 SYS_SHDN# Active low Critical System Shutdown output OD (5V) 13 THERMTRIP# Active low Critical temperature limit signal from the CPU or chipset. IP 14 POWER_OK Active high power good input. DI (5V) 15 N/C Not internally connected. N/A 16 RESET# Active low reset output. DO 17 CLK_SEL Selects internal oscillator or external clock. DI (5V) 18 CLK_IN 32.768KHz clock input. DI (5V) 19 ALERT# Active low interrupt. OD (5V) 20 GND GND connection. Power 21 N/C Not internally connected. N/A 22 SMDATA SMBus data input/output. DIOD (5V) - requires external upllup resistor 23 SMCLK SMBus clock input. DI (5V) - requires external pull-up resistor 9 SMSC EMC2102 9 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 2.1 Pin Description (continued) PIN NAME FUNCTION TYPE VDD_5V 5V supply input for the linear fan driver. Both VDD_5V pins should be connected to same 5V supply. Power 25 FAN Linear fan drive signal. Both FAN pins should be connected together. AO 26 FAN Linear fan drive signal. Both FAN pins should be connected together. AO VDD_5V 5V supply input for the linear fan driver. Both VDD_5V pins should be connected to same 5V supply. Power TACH Input from the tachometer pin of the fan. DI (5V) 24 27 28 The pin type are described in detail below. All pins labelled with (5V) are 5V tolerant.: Power - this pin is used to supply power to the device. DI - Digital Input - this pin is used as a digital input. This pin is 5V tolerant. AI - Analog Input - this pin is used as an input for analog signals. AO - Analog Output - this pin is used as an output for analog signals. AIO - Analog Input / Output - this pin is used as an I/O for analog signals. DO - Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current and doesn't require a pull-up resistor. DIOD - Open Drain Digital Input / Output - this pin is used as an digital I/O. It is open drain and requires a pull-up resistor. This pin is 5V tolerant. OD - Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. DIT - Tri-stated Digital Input - this pin is a digital input that supports 3 logic levels at the input: logic high, logic low, or high impedance (open). IP - Digital Input - this pin has an internal 30uA pull-up current to VDD_3V. Revision 2.02 (05-17-07) 10 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 3 Electrical Specifications 3.1 Absolute Maximum Ratings Table 3.1 Absolute Maximum Ratings Voltage on VDD_5V Pins and 5V tolerant pins (see Table 2.1, "Pin Description") -0.3 to 6.5 V Voltage on VDD_3V pin -0.3 to 4 V Voltage on FAN pins -0.3 to VDD_5V + 0.3 V Voltage on any other pin to GND -0.3 to VDD_3V + 0.3 V Package Power Dissipation 0.9 up to TA = 85C Note 3.2 W Junction to Ambient (JA) Note 3.3 37 C/W Operating Ambient Temperature Range 0 to 85 C Operating Die Temperature Range 0 to 125 C Storage Temperature Range -55 to 150 C ESD Rating, All Pins, HBM 2000 V These ratings are absolute maximum values. Exceeding these values or operating at these values for an extended period of time may cause permanent damage to the device. 3.2 Note 3.1 All voltages are relative to ground. Note 3.2 The Package Power Dissipation specification assumes a thermal via design consisting of four 20mil vias connected to the ground plane with a 3.1mm x 3.1mm thermal landing. Note 3.3 Junction to Ambient (JA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the JA is approximately 60C/W including localized PCB temperature increase. Electrical Specifications Table 3.2 Electrical Specifications VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS DC Power 3.3V Supply Voltage VDD_3V 3 3.3 3.6 V 5V Supply Voltage VDD_5V 4.6 5 5.5 V 750 uA Fan Driver enabled uA Fan Driver enabled Supply Current from VDD_3V pin IDD3 500 Supply Current from VDD_5V pin IDD5 200 SMSC EMC2102 11 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 3.2 Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNIT CONDITIONS External Temperature Monitors Temperature Accuracy Temperature Resolution 1 1.5 C 60C < TDIODE < 100C 30C < TDIE < 85C (Note 3.4) 1 3 C 0C < TDIODE < 125C, 0C < TDIE < 115C (Note 3.4) 1 C Diode decoupling capacitor 2200 pF Connected across external 2N3904 diode or AMD diode (Note 3.5) 470 pF Connected across CPU or GPU thermal diode (Note 3.5) 100 Ohm Series resistance in DP and DN lines CFILTER Resistance Error Corrected RSERIES Internal Temperature Monitor Temperature Accuracy 3 C Temperature Resolution 1 C (Note 3.4 ) Reset Generator Reset Voltage VRESET 4.3 4.4 4.5 V Hysteresis VRESET 100 mV Time Delay tRESET 220 ms VDD_5V rising edge 3V < VDD_3V < 3.6V High Side Fan Driver Output High Voltage from 5V supply VOH_5V VDD_5 V - 0.4 V Fan Drive Current ISOURCE 600 mA Overcurrent Limit IOVER 1500 mA Momentary Current drive at startup for < 2 seconds ISHORT 800 mA Sourcing current, Thermal shutdown not triggered, FAN_OUT = 0V Short circuit delay tDFS 2 s Output Capacitive Load CLOAD ESR on CLOAD RESR DC Short Circuit Current Limit 0 100 uF 2 Ohm ISOURCE = 600mA, VDD_5V = 5V RPM Based Fan Controller Revision 2.02 (05-17-07) 12 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 3.2 Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6V - 5.5V, TA = 0C to 85C all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC TACH Range TACH Setting Accuracy SYMBOL MIN TACH 480 TYP MAX UNIT 16000 RPM CONDITIONS TACH 1 2 % External oscillator 32.768kHz TACH 5 7.5 % Internal Oscillator 40C < TDIE < 100C Thermal Shutdown Thermal Shutdown Threshold TSDTH 150 C Thermal Shutdown Hysteresis TSDHYST 50 C SMBus and Digital I/O pins Output High Voltage Output Low Voltage 3.3 VDD _3V 0.4 VOH 2 mA current drive V VOL 0.5 V 4mA current sink Note 3.4 TDIE refers to the internal die temperature and may not match TA due to self heating of the device. The internal temperature sensor will return TDIE. Note 3.5 Contact SMSC for Application Notes and guidelines when measuring GPU processor diodes and CPU processor diodes. SMBus Electrical Specifications Table 3.3 SMBus Electrical Specifications VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0C to 85C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP MAX UNITS CONDITIONS SMBus Interface Input High Voltage VIH Input Low Voltage VIL Input High/Low Current Input Capacitance IIH / IIL 2.0 V -1 CIN Output Low Sink Current 0.8 V 1 uA 5 pF 4 mA SMDATA = 0.5V SMBus Timing Clock Frequency Spike Suppression SMSC EMC2102 fSMB 10 tSP 400 kHz 50 ns 13 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 3.3 SMBus Electrical Specifications (continued) VDD_3V = 3V to 3.6V, VDD_5V = 4.6 to 5.5V, TA = 0C to 85C Typical values are at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN tBUF 1.3 us Setup Time: Start tSU:STA 0.6 us Setup Time: Stop tSU:STP 0.6 us Data Hold Time tHD:DAT 0.6 6 us Data Setup Time tSU:DAT 0.6 72 us Clock Low Period tLOW 1.3 us Clock High Period tHIGH 0.6 us Clock/Data Fall time tFALL 300 ns Min = 20+0.1CLOAD ns Clock/Data Rise time tRISE 300 ns Min = 20+0.1CLOAD ns CLOAD 400 pF per bus line Bus free time Start to Stop Capacitive Load Revision 2.02 (05-17-07) TYP MAX 14 DATASHEET UNITS CONDITIONS SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 4 System Management Bus Interface Protocol The EMC2102 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported, however the EMC2102 will not stretch the clock signal. . TLOW THIGH THD:STA TSU:STO TRISE SMCLK THD:STA TFALL THD:DAT TSU:STA TSU:DAT SMDTA TBUF S P S S - Start Condition P - Stop Condition P Figure 4.1 SMBus Timing Diagram The EMC2102 is SMBus 2.0 compatible and supports Send Byte, Read Byte, Receive Byte and Write Byte as valid protocols as shown below. It will respond to the Alert Response Address protocol but is not in full compliance. All of the below protocols use the convention in Table 4.1. Table 4.1 Protocol Format DATA SENT TO DEVICE DATA SENT TO THE HOST # of bits sent 4.1 # of bits sent Write Byte The Write Byte is used to write one byte of data to the registers as shown below Table 4.2: Table 4.2 Write Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK REGISTER DATA ACK STOP 1 7 1 1 8 1 8 1 1 SMSC EMC2102 15 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 4.2 Read Byte The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3. Table 4.3 Read Byte Protocol START SLAVE ADDRESS W R ACK Register Address ACK START Slave Address RD ACK Register Data NACK STOP 1 7 1 1 8 1 1 7 1 1 8 1 1 4.3 Send Byte The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4. Table 4.4 Send Byte Protocol START SLAVE ADDRESS WR ACK REGISTER ADDRESS ACK STOP 1 7 1 1 8 1 1 4.4 Receive Byte The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5. Table 4.5 Receive Byte Protocol START SLAVE ADDRESS RD ACK REGISTER DATA NACK STOP 1 7 1 1 8 1 1 4.5 Alert Response Address The ALERT# output can be used as a processor interrupt or as an SMBALERT. When it detects that the SMBALERT pin is asserted, the host will send the Alert Response Address (general address of 000_1100b) on the bus. All devices with active interrupts will respond with their client address as shown in Table 4.6. .. Table 4.6 Alert Response Address Protocol START ALERT RESPONSE ADDRESS RD ACK DEVICE ADDRESS NACK STOP 1 7 1 1 8 1 1 Revision 2.02 (05-17-07) 16 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet The EMC2102 will respond to the ARA command if the ALERT# pin has been asserted but will not immediately release the ALERT# pin. The ALERT# pin is released under the following conditions. 1. The Interrupt Status Registers are read and the error condition has been removed. 2. The specific error condition is masked from asserting the ALERT# pin. 4.6 SMBus Address The EMC2102-1 is addressed on the SMBus as 011_1101b. Attempting to communicate with the EMC2102 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents. 4.7 SMBus Time-out The EMC2102 includes an SMBus time-out feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface. SMSC EMC2102 17 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 5 General Description The EMC2102 monitors three external temperature channels. Two of the external temperature channels can employ both Beta Compensation (an implementation of the BJT or transistor model for thermal diodes) and Resistance Error Correction for use with thermal diodes while the third channel is hardwired to measure a discrete diode connected NPN or PNP transistor. The temperature data is available over a standard 2-wire serial interface using SMBus read commands. The temperature monitoring is described in more detail in Section 5.1, "Temperature Monitoring". The EMC2102 integrates a closed-loop RPM based Fan Control Algorithm. A host writes the desired fan speed into a register of the EMC2102 via the SMBus and the integrated fan controller will maintain the fan at the desired speed using fan speed feedback from the TACH output from a 3-wire fan. The fan control algorithm controls an integrated 5V, 600mA, linear fan driver. The fan control algorithm functionality is described in more detail in Section 5.3, "RPM based Fan Control Algorithm" The EMC2102 provides the system with a hardware based critical/thermal shutdown function. This critical/thermal shutdown function integrates critical signals from both the CPU and power supply and the analog circuitry to monitor a specific temperature channel based on the system configuration. The critical/thermal shutdown temperature threshold is configured on the PCB through a simple discrete resistor divider. The Critical/Thermal Shutdown function is described in more detail in Section 5.7, "Critical/Thermal Shutdown". An example of a typical system configuration for the EMC2102 is provided in Figure 5.1. Revision 2.02 (05-17-07) 18 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 3.3V 5V VDD_3V VDD_5V EMC2102 SMBCLK SMBDATA SMCLK ALERT ALERT# 3.3V SMDATA TACH FAN CPU TACHOMETER FAN VCC DP 1 DN1 Thermal diode DP 2 GPU Thermal diode DN2 DIMM DP3 Thermal diode DN3 3.3V CLK_SEL CLK_IN 32.768KHz Clock 3.3V 3.3V FAN_MODE SHDN_SEL TRIP_SET 3.3V SYS_SHDN SYS_SHDN# THERMTRIP POWER_OK POWER_OK RESET# RESET THERMTRIP# Figure 5.1 EMC2102 System Diagram SMSC EMC2102 19 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.1 Temperature Monitoring External diode channels one and two can be configured to monitor either discrete thermal diodes or a CPU / GPU thermal diode. External diode channel three is always configured to monitor a discrete diode-connected transistor (such as a 2N3904) or an AMD thermal diode. Each channel can enable the Resistance Error Correction functionality and external diode channels one and two can adjust the Beta Compensation settings (disabling it if desired). The disabling of these features is only recommended in two situations: 1. An AMD thermal diode is being monitored. The AMD thermal diode is physically a 2-terminal diode and will not function with either Beta Compensation or Resistance Error Correction. Because of this, when an EMC2102 temperature channel is interfacing an AMD thermal diode, both Beta Compensation and Resistance Error Correction must be disabled. 2. A discrete diode connected transistor (such as 2N3904) is used. In this configuration, Beta Compensation must be disabled, but Resistance Error Correction should remain enabled. 5.1.1 Resistance Error Correction The EMC2102 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC2102 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path. 5.1.2 Beta Compensation The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. This correction is done by implementing the BJT or transistor model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC2102 corrects for this beta variation to eliminate any error which would normally be induced. 5.1.3 Fault Queue To avoid spurious interrupts and Critical/Thermal Trip events induced by thermal spikes and noise injection, the selected Thermal / Critical Shutdown Temperature channel (see Section 5.7.2) is filtered through a fault queue. This fault queue requires that a user-defined number of consecutive out-of-limit errors be recorded before it will cause an interrupt or trigger the Critical/Thermal trip event. The fault queue only applies to the measurement channels that will cause the SYS_SHDN# pin to be asserted including any software configured channels (see Section 5.7). In addition, the fault queue applies to all enabled channels simultaneously and will trigger the SYS_SHDN# pin if there are the desired number of consecutive measurements with any or all channels exceeding their corresponding limits. Revision 2.02 (05-17-07) 20 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.2 Fan Control Modes of Operation The EMC2102 has two modes of operation for the High Side Fan Driver. They are: 1. Manual Mode - in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see Section 6.12) will instantly update the fan drive. The Manual Mode is enabled by clearing the EN bit in the Fan Configuration Register (see Section 6.13). Whenever the Manual Mode is enabled the current drive will be changed to what was last written into the Fan Driver Setting Register. Setting the drive value to 00h will disable the High Side Fan Driver for lower power operation. 2. Using RPM based Fan Control Algorithm - in this mode of operation, the user determines a target TACH count and the drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. Table 5.1 Fan Controls Active for Operating Mode MANUAL MODE ALGORITHM Fan Driver Setting (read / write) Fan Driver Setting (read only) EDGES[1:0] EDGES[1:0] (Fan Configuration) - UPDATE[2:0] (Fan Configuration) - LEVEL (Spin Up Configuration) - SPINUP_TIME[1:0] (Spin Up Configuration) - Fan Step - Fan Minimum Drive Valid TACH Count Valid TACH Count - TACH Target TACH Reading TACH Reading 5.3 RPM based Fan Control Algorithm The EMC2102 includes a RPM based Fan Control Algorithm that controls an integrated linear High Side Fan Driver. This fan control algorithm automatically approaches and maintains the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. Figure 5.2, "RPM based Fan Control Algorithm" shows a simple flow diagram of the RPM based Fan Control Algorithm operation. The desired TACH count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan revolution. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000RPMs, then the user would input the hexidecimal equivalent of 655 (29h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs (see Equation [4] in Section 6.19). SMSC EMC2102 21 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet The EMC2102's RPM based Fan Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2102 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768KHz clock source or with it's own internal 32.768KHz oscillator depending on the required accuracy. S e t T A C H T a rge t C o u nt M e a su re F a n S p e e d S pin U p R e q u ire d ? Yes P erform S p in U p R o u tin e No Yes M a inta in F a n D riv e TACH R ea d in g = TACH T arg e t? No Yes R e d u ce F a n D rive TACH R ea d in g < TACH T arg e t? No R a m p R a te C o n trol In c re a se F an D rive Figure 5.2 RPM based Fan Control Algorithm Revision 2.02 (05-17-07) 22 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.3.1 Programming the RPM based Fan Control Algorithm The RPM based Fan Control Algorithm powers-up enabled and active. The following registers control the algorithm. The EMC2102 fan control registers are preloaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. 1. Set the Valid TACH Count Register to the minimum TACH count that indicates the fan is spinning. 2. Set the Spin Up Configuration Register to the spin up level and Spin Time desired. 3. Set the Fan Step Register to the desired step size. 4. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 5. Set the Update Time, and Edges options in the Fan Configuration Register. 6. Set the TACH Target Register to the desired TACH count. 5.3.2 TACH Measurement In both modes of operation, the TACH measurement will work normally. Any TACH count that is higher than the Valid TACH Count (see Section 6.17) will flag a stalled fan and trigger an interrupt. The EMC2102 includes a TACH measurement circuit. The TACH signal must be valid at all times to ensure proper operation. The TACH measurement circuitry is programmable to detect the fan speed of a variety of fan configurations and architectures including 1-pole, 2-pole (default), 3-pole, and 4-pole fans. APPLICATION NOTE: The TACH measurement works independently of the drive settings. If the device is put into manual mode and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the TACH measurement may signal a Stalled Fan condition and assert an interrupt. 5.3.2.1 Stalled Fan If the TACH counter exceeds the user-programmable Valid TACH Count setting then it will flag the fan as stalled and trigger an interrupt. If the RPM based Fan Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid TACH level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. 5.3.3 Whenever the Manual Mode is enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 6.21, "Spin Time") to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Manual Mode, whenever the drive value is changed from 00h, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time to allow the fan opportunity to reach a valid speed without generating unnecessary interrupts. In Manual Mode, whenever the TACH count exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set. When the RPM based Fan Control Algorithm, the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check. Spin Up Routine The EMC2102 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. During Manual Mode, the Spin Up Routine will not control the fan drive settings under any conditions. SMSC EMC2102 23 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet When the RPM based Fan Control Algorithm is running, the Spin Up Routine is initiated under the following conditions: APPLICATION NOTE: When the device is operating in manual mode, the FAN_SPIN status bit may be set if the fan drive is set at a level that is lower than the fan can operate (including zero drive). If the FAN_SPIN interrupt is unmasked, then this condition will trigger an errant interrupt. 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 6.18, "TACH Target Register" and Section 6.17, "Valid TACH Count Register"). 2. At power-up if the FAN_MODE setting is `1' or `open' indicating 75% drive or 60% drive respectively. If the FAN_MODE setting is `0' indicating 0% drive, then the Spin Up Routine is not initiated until another condition is met. 3. The RPM based Fan Control Algorithm is started and the FAN_MODE setting is `0' indicating 0% drive prior to algorithm control. 4. The RPM based Fan Control Algorithm's measured TACH count is greater than the Valid TACH Count. When the Spin Up Routine is operating, the fan driver is set to full scale for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set a a user defined level (60% or 75% drive). After the Spin Up Routine has finished, the EMC2102 measures the TACH. If the measured TACH count is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 5.3 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above. 100% (optional) 40% through 75%% Fan Step New Target Count Algorithm controlled drive Prev Target Count = FFh 1/4 of Spin Up Time Update Time Spin Up Time Target Count Changed Check TACH Target Count Reached Figure 5.3 Spin Up Routine Revision 2.02 (05-17-07) 24 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.3.4 FAN_MODE Pin The FAN_MODE pin is used to determine the fan driver output levels at power-up before the EMC2102 has been programmed. After power-up, the fan driver will be set at the selected drive until the RPM based Fan Control Algorithm is started or disabled. The level on the pin determines the function as shown in Table 5.2, "FAN_MODE Pin Functions". Table 5.2 FAN_MODE Pin Functions FAN_MODE FUNCTION 0 5.3.5 Fan Driver set at 0% drive open Fan Driver set at 60% drive after Spin Up Routine 1 Fan Driver set at 75% drive after Spin Up Routine 32.768KHz Clock Source The EMC2102 allows the user to choose between supplying an external 32.768KHz clock or use of the internal 32.768KHz oscillator to measure the TACH signal. This clock source is used by the RPM based Fan Control Algorithm to calculate the current fan speed. This fan controller accuracy is directly proportional to the accuracy of the clock source. To enable the external clock source, the CLK_SEL pin must be pulled to VDD_3V at power-up (see Table 5.3). The CLK_SEL pin is must be in a known state at all times (either pulled high or pulled low) and is latched upon power-up. Table 5.3 CLK_SEL Pin Functions CLK_SEL 5.4 FUNCTION 0 Internal oscillator used 1 External clock used Watchdog Timer The EMC2102 contains an internal Watchdog Timer. Once the device has powered up the watchdog timer monitors the bus traffic for signs of activity. The Watchdog Timer starts when the VDD_5V supply has reached its operating point. The Watchdog Timer only starts immediately after power-up and once it has been triggered or deactivated will not restart. If four (4) seconds elapse without the system host programming the device, then the following will occur: 1. The WATCH status bit will be set. 2. The High Side Fan Driver will be set to full scale drive. It will remain at full scale drive until one of the two conditions listed below are met. If the Watchdog Timer is triggered, the following two operations will disable the timer and return the device to normal operation. 1. Writing the RPM based Fan Control Algorithm TACH Target Register will disable the Watchdog Timer regardless of the value. If a value is written that is greater than the Valid TACH Count Register setting (other than FFh), the fan drive setting will be set based on the FAN_MODE pin SMSC EMC2102 25 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet condition (0%, 60% or 75% drive). If a value of FFh is written, then the fan driver will be disabled until a valid setting is written. 2. Disabling the RPM based Fan Control Algorithm by clearing the EN bit will disable the Watchdog Timer. The fan driver will be set to the programmed setting written in the Fan Driver Setting Register. Writing any other configuration registers will not disable the Watchdog Timer. If the VDD_5V supply drops below the reset threshold, then the Watchdog Timer will be stopped but not reset. 5.5 High Side Fan Driver The EMC2102's fan controller integrates a 5V, 600mA, linear high side fan driver to directly drive a 5V fan. By fully integrating the linear fan driver, the typical requirement for the discrete pass device and other external linearization circuitry is completely eliminated. The linear fan driver is driven by an 8-bit DAC providing better than 20mV resolution between steps. 5.5.1 Overcurrent Limit The High Side Fan Driver contains circuitry to allow for significant overcurrent levels to accommodate transient conditions on the FAN pins. The overcurrent limit is dependent upon the output voltage with the limit dropping as the voltage nears 0V. If the fan driver current detects a short-circuit condition for longer than 2 seconds, then the I_SHORT status bit is set and an interrupt generated. Additionally, the fan driver will be disabled (by setting the drive level to 00h). In both Manual Mode and when using the RPM based Fan Control Algorithm, the device will attempt to restart the fan after a time equal to the spin-up time programmed in the Fan Spin Up Configuration Register (see Section 6.14, "Fan Spin Up Configuration Register"). If the High Side Fan Driver is configured to operate in Manual Mode, when it attempts to restart the fan after a overcurrent condition, it will set the Fan Drive Setting Register to the most recently written value (prior to the overcurrent condition). If the High Side Fan Driver is configured to use the RPM based Fan Control Algorithm, it will invoke the Spin Up Routine described in Section 5.3.3, "Spin Up Routine". If the overcurrent condition persists, the fan driver will continue to attempt to restart the fan until the overcurrent condition is removed or the High Side Fan Driver is disabled by setting the TACH Target to FFh (when using the RPM based Fan Control Algorithm) or by writing the Fan Setting Register to a value of 00h (when operating in Manual Mode) 5.6 Internal Thermal Shutdown (TSD) The EMC2102 contains an internal thermal shutdown circuit that monitors the internal die temperature. If the die temperature exceeds the Thermal Shutdown Threshold (see Table 3.2, "Electrical Specifications"), then the following will occur: 1. The High Side Fan Driver is disabled. It will remain disabled until the internal temperature drops below the threshold temperature minus 50C. 2. The TSD Status bit will be set and the ALERT pin asserted. This signal cannot be masked. 3. The SYS_SHDN pin is asserted. 5.7 Critical/Thermal Shutdown The EMC2102 provides a hardware Critical/Thermal Shutdown function for systems. Figure 5.4, "EMC2102 Critical/Thermal Shutdown Block Diagram" is a block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function in the EMC2102 consists of both analog and digital functions. It accepts digital inputs from the CPU (THERMTRIP#) and power supply Revision 2.02 (05-17-07) 26 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet (POWER_OK) and configuration information from the fixed states of the SHDN_SEL pins as described in Section 5.7.2, "SHDN_SEL Pin". In addition, each of the temperature limits can be configured to act as inputs to the Critical / Thermal Shutdown independent of the hardware shutdown operation. The analog portion of the Critical/Thermal Shutdown function monitors a specific remote temperature channel (configured with the SHDN_SEL pin). This measured temperature is then compared with the TRIP_SET point. This TRIP_SET point is created by the system designer with a simple resistor divider and is discussed in detail in Section 5.7.1, "TRIP_SET". Critical Shutdown Logic H/W Set Sensor S/W Set Sensor SMBus Traffic SYS1 - SYS3 Temperature Conversion and Limit Registers Configuration Register SW_SHDN S/W Set Sensor `0' or `open' H/W Critical Sensor SHDN_SEL PIN Decode Temperature Conversion `1' 3.3V HW_SHDN TRIP_SET Voltage Conversion SYS_SHDN# Thermal_SHDN Thermal Shutdown From CPU / Chipset From the Power Supply THERMTRIP# ThermTrip_ SHDN POWER_OK ThermTrip# Power_OK ThermTrip_SHDN 0 0 0 0 1 1 1 0 0 1 1 0 Figure 5.4 EMC2102 Critical/Thermal Shutdown Block Diagram SMSC EMC2102 27 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.7.1 TRIP_SET The EMC2102's TRIP_SET pin is an analog input to the Critical/Thermal Shutdown block which sets the Thermal Shutdown temperature. The system designer creates a voltage level at this input through a simple resistor divider between the 3.3V supply and GND. This input voltage is valid between 0V and 1.5V which corresponds to Thermal Shutdown temperature setpoints between 75C and 106C as described in the following equation. Where: TTRIP is the desired trip point temperature T TRIP - 75 TRIP_SET Pin Voltage = ---------------------------21 [1] TRIPSET is the voltage on the TRIP_SET pin 5.7.2 SHDN_SEL Pin The EMC2102 has one `strappable' input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown. This pin has 3 possible states and is monitored and decoded by the EMC2102 at power-up. The three possible states are 0 (tied to GND), 1 (tied to 3.3V) or High-Z (open). The states of this pin determine which remote temperature channel and configuration is used by the Critical/Thermal Shutdown function. The different configurations of SHDN_SEL pin are described in Table 5.4 A channel that is configured via the SHDN_SEL pin for the Critical/Thermal Shutdown is locked and none of the configuration registers associated with it can be updated via the SMBus. The other two temperature channels, however, are still configurable via the SMBus. Table 5.4 SHDN_SEL Pin Configuration SHDN_SEL FUNCTION NAME REMOTE CHANNEL INPUT TO THERMAL SHUTDOWN 0 Intel Mode 1 Channel 1 is configured and locked with both Beta Compensation and Resistance Error Correction enabled which is optimized for an Intel thermal diode. 3 Channel 3 is configured and locked with Resistance Error Correction enabled which is optimal for interfacing a discrete diodeconnected NPN transistor. NA The Critical/Thermal Shutdown function will not assert SYS_SHDN# based on a temperature channel. This does not include software configured inputs (see Section 6.4, "Configuration Register") High-Z 1 Revision 2.02 (05-17-07) Diode Mode Disabled, 28 DATASHEET CRITICAL/THERMAL SHUTDOWN DETAILS SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.7.3 Internal HW_SHDN Signal The HW_SHDN output from the Critical/Thermal Shutdown Monitor is a logical indicator of the temperature state of the chosen external diode channel. HW_SHDN is an internal signal routed as an input to the Thermal / Critical Shutdown logic. The HW_SHDN output is set to logic `1' when the indicated temperature exceeds the temperature threshold (TP) established by the TRIP_SET input pin (as shown in Figure 5.5, "HW_SHDN Operation") for a number of consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the temperature drops below TP, then it will be set to a logic `0' state. Temperature Exceeds TP Measurements End Temperature drops to TP or below TP Temperature not defined HW_SHDN After 4th measurement, HW_SHDN set Figure 5.5 HW_SHDN Operation SMSC EMC2102 29 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 5.8 5V Reset Controller The EMC2102 also provides a `power-good' reset controller for the system's 5V supply rail. The reset controller will set the RESET# pin to a logic `0' after power-up and set the RESET# pin to a logic `1' 220ms after the VDD_5V supply rises above its threshold voltage (see Table 3.2, "Electrical Specifications"). If the VDD_5V supply drops below the reset threshold, then the RESET# pin will be set to `0' immediately. VDD_5V Reset Threshold (4.4V) Reset Threshold hysteresis (4.3V) VDD_3V or pull-up voltage 220ms RESET# Figure 5.6 5V Reset Controller Timing Revision 2.02 (05-17-07) 30 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 6 Register Set 6.1 Register Map The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect. Table 6.1 EMC2102 Register Set ADDR R/W REGISTER NAME FUNCTION DEFAULT VALUE LOCK PAGE Temperature Registers 00h R Internal Temp Reading Stores the integer data of the Internal Temp Reading 00h No Page 33 01h R External Diode 1 Temp Reading Stores the integer data of External Diode 1 00h No 02h R External Diode 2 Temp Reading Stores the integer data of External Diode 2 00h No 03h R External Diode 3 Temp Reading Stores the integer data of External Diode 3 00h No 04h R Critical/Thermal Shutdown Temperature Stores the calculated Critical/Thermal Shutdown temperature high limit derived from the voltage on TRIP_SET. 7Fh No Page 34 Page 33 Configuration and control 20h R/W Configuration Configures the Thermal / Critical Shutdown masking options and software lock 80h SWL Page 34 21h R/W Conversion Rate Configures the conversion rate 02h SWL Page 35 22h R-C Interrupt Status Register 1 Stores the status bits for temperature channels 80h No Page 36 23h R-C Interrupt Status Register 2 Stores the status bits for the thermal shutdown and RPM based Fan Control Algorithm 00h No Page 37 24h R/W Interrupt Mask Register Controls the masking of interrupts on all maskable channels 10h No Page 37 03h SWL Diode Configuration 30h R/W External Diode 1 Beta Configuration Configures the beta compensation settings for External Diode 1 31h R/W External Diode 2 Beta Configuration Configures the beta compensation settings for External Diode 2 03h SWL 32h R/W External Diode REC Configuration Configures the Resistance Error Correction functionality for all external diodes 07h SWL SMSC EMC2102 31 DATASHEET Page 38 Page 39 Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 6.1 EMC2102 Register Set (continued) ADDR REGISTER NAME R/W FUNCTION DEFAULT VALUE LOCK PAGE Temperature Limit Registers 41h R/W External Diode 1 Temp High Limit High limit for External Diode 1 55h (+85C) SWL 42h R/W External Diode 2 Temp High Limit High limit for External Diode 2 55h (+85C) SWL 43h R/W External Diode 3 Temp High Limit High limit for External Diode 3 55h (+85C) SWL Always displays the most recent fan driver input setting. If the RPM based Fan Control Algorithm is disabled, allows direct user control of the fan driver. 00h No Page 40 Fan Control Registers 51h R/W Fan Driver Setting Page 40 52h R/W Fan Configuration Sets configuration values for the RPM based Fan Control Algorithm CBh No Page 41 53h R/W Fan Spin Up Configuration Sets the configuration values for Spin Up Routine of the High Side Fan Driver 01h SWL Page 42 54h R/W Fan Step Sets the maximum change per update for the High Side Fan Driver 10h SWL Page 43 55h R/W Fan Minimum Drive Sets the minimum drive value for the High Side Fan Driver 80h SWL Page 43 56h R/W Fan Valid TACH Count Holds the minimum TACH value that indicates the fan is spinning properly F5h SWL Page 44 57h R/W TACH Target Holds the target TACH count for the fan FAh No Page 44 58h R TACH Reading Holds the TACH count for the fan FFh No Page 44 Revision Registers FDh R Product ID Stores the unique Product ID 14h No Page 45 FFh R Revision Revision 00h No Page 46 During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD_3V supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect. 6.1.1 Lock Entries The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set. Revision 2.02 (05-17-07) 32 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.2 Temperature Data Registers Table 6.2 Temperature data Registers ADDRESS REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 00h Internal Diode Sign 64 32 16 8 4 2 1 00h 01h External Diode 1 Sign 64 32 16 8 4 2 1 00h 02h External Diode 2 Sign 64 32 16 8 4 2 1 00h 03h External Diode 3 Sign 64 32 16 8 4 2 1 00h The temperature measurement range is from 0C to +191C. The data format can be selected between pure 2's complement format which displays data from 0C to +127C, or in offset 2's complement format that displays data over the entire data range. The temperature format is shown below: Table 6.3 Temperature Data Format 2'S COMPLEMENT FORMAT TEMPERATURE (C) BINARY HEX OFFSET 2'S COMPLEMENT FORMAT BINARY HEX Diode Fault 1000 0000 80h 1000 0000 80h <= 0 0000 0000 00h 1100 0000 C0h 1 0000 0001 01h 1100 0001 C1h 63 0011 1111 3Fh 1111 1111 FFh 64 0100 0000 40h 0000 0000 00h 65 0100 0001 41h 0000 0001 01h 127 0111 1111 7Fh 0011 1111 3Fh 128 (Note 6.1) 0111 1111 7Fh 0100 0000 40h 190 0111 1111 7Fh 0111 1110 7Eh 191 0111 1111 7Fh 0111 1111 7Fh Note 6.1 In 2's complement format, any temperature above +127C will be displayed as +127C If the High Side Fan Driver is active, then self-heating of the large current drive device will affect the internal temperature reading. Therefore, it is not recommended that the Internal temperature channel be used to monitor the ambient air temperature. SMSC EMC2102 33 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.3 Critical/Thermal Shutdown Temperature Register Table 6.4 Critical/Thermal Shutdown Temperature Register ADDRESS REGISTER 04h Critical/Therm al Shutdown Temperature B7 Sign B6 64 B5 B4 32 B3 16 B2 8 B1 4 2 B0 1 DEFAULT 7Fh (+127C) The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents of the register reflect the calculated temperature based on the TRIP_SET voltage. This register is updated at the end of every monitoring cycle based on the current value of TRIP_SET. The register value reflects the exact threshold temperature. The data format will match the selected format of the temperature data registers as shown in Table 6.3, "Temperature Data Format". 6.4 Configuration Register Table 6.5 Configuration Register ADDRESS REGISTER 20h Configuration B7 B6 QUEUE[1:0] B5 B4 B3 B2 SYS3 SYS2 SYS1 FORMAT B1 - B0 LOCK DEFAULT 80h The Configuration Register controls the basic functionality of the EMC2102. The bits are described below. The Configuration Register is software locked. Bit 7-6 - QUEUE[1:0] - determines how many consecutive out-of-limit errors must occur on the hardware selected and software enabled temperature channels before the SYS_SHDN# pin is asserted (see Table 5.2, "FAN_MODE Pin Functions"). The queue applies to all enabled channels simultaneously and will trigger the SYS_SHDN# pin if there are four consecutive measurements with any or all channels exceeding their corresponding limits. Table 6.6 Fault Queue QUEUE1:0] 1 0 NUMBER OF FAULTS 0 0 1 0 1 2 1 0 4 (default) 1 1 8 Bit 5 - SYS3 - enables the high temperature limit for the External Diode 3 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7, "Critical/Thermal Shutdown"). `0' (default) - the External Diode 3 channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. Revision 2.02 (05-17-07) 34 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet `1' - the External Diode 3 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 4 - SYS2 - enables the high temperature limit for the External Diode 2 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7, "Critical/Thermal Shutdown"). `0' (default) - the External Diode 2 channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. `1' - the External Diode 2 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 3 - SYS1 - enables the high temperature limit for the External Diode 1 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 5.7). `0' (default) - the External Diode 1channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. `1' - the External Diode 1 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The ALERT# pin will be asserted normally. Bit 2 - FORMAT - determines the data format that is displayed in the Temperature Data Registers. The data format for the Critical Thermal Shutdown Threshold Register will not be changed. If the temperature data format is changed, the limit register values must be changed to match the newer format. `0' (default) - the temperature data will be in standard 2's complement format. `1' - the temperature data will be in offset 2's complement format. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. 6.5 `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them. Conversion Rate Register Table 6.7 Conversion Rate Register ADDRESS REGISTER 21h Conversion Rate B7 - B6 - B5 - B4 - B3 - B2 - B1 B0 CONV[1:0] DEFAULT 02h The Conversion Rate Register controls the conversion rate of the temperature monitoring as well as the fault queue. The Conversion Rate Register is software locked. Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases. SMSC EMC2102 35 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 6.8 Conversion Rate CONV[1:0] 6.6 1 0 CONVERSION RATE 0 0 1 / sec 0 1 2 / sec 1 0 4 / sec (default) 1 1 8 / sec Interrupt Status Register 1 Table 6.9 Interrupt Status Register 1 ADDRESS REGISTER 22h Interrupt Status Register 1 B7 B6 B5 B4 B3 B2 B1 B0 RESET TSD ERR3 TRD3 ERR2 TRD2 ERR1 TRD1 DEFAULT 80h The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits are set to a logic `1' (other than the RESET pin) then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. The bits that cause the ALERT# pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. Bit 7 - RESET - this bit mirrors the output of the RESET# pin. When the RESET# pin is set to a logic `0' (indicating that the VDD_5V supply is lower than the reset threshold), this bit is set to a logic `1' as well. This bit will not cause the ALERT# pin to be asserted. Bit 6 - TSD - this bit is asserted `1' if there is a thermal shutdown condition. This bit cannot be masked. Bit 5 - ERR3 - this bit is asserted `1' if there is a diode fault on External Diode 3. Bit 4 - TRD3 - this bit is asserted `1' if the External Diode 3 Temperature measurement exceeds the high limit. Bit 3 - ERR2 - this bit is asserted `1' if there is a diode fault on External Diode 2. Bit 2 - TRD2 - this bit is asserted `1' if the External Diode 2 Temperature measurement exceeds the high limit. Bit 1 - ERR1 - this bit is asserted `1' if there is a diode fault on External Diode 1. Bit 0 - TRD1 - this bit is asserted `1' if the External Diode 1 Temperature measurement exceeds the high limit. Revision 2.02 (05-17-07) 36 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.7 Interrupt Status Register 2 Table 6.10 Interrupt Status Register 2 ADDRESS REGISTER 23h Interrupt Status Register 2 B7 B6 B5 PWROK THERM B4 HWS - B3 B2 B1 B0 WATCH FAN_S PIN FAN_S TALL I_SHO RT DEFAULT 00h The Interrupt Status Registers report the operating condition of the EMC2102. If any of the bits (except the PWROK, THERM, and HWS bits) are asserted then the ALERT# pin will be asserted low. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. Bit 7 - PWROK - this bit is set if the POWER_OK pin is set to a logic `1' state. When this bit is set, it will not cause the ALERT# pin to be asserted. Bit 6 - THERM - this bit is set if the THERMTRIP# pin is set to a logic `0' state. When this bit is set, it will not cause the ALERT# pin to be asserted however will coincide with SYS_SHDN# pin being asserted. The THERMTRIP# pin can only cause the SYS_SHDN# pin to be asserted if the POWER_OK pin is set to a logic `1' (see Figure 5.4, "EMC2102 Critical/Thermal Shutdown Block Diagram"). Bit 5 - HWS - this bit is set if the internal HW_SHDN signal is set (see Section 5.7.3, "Internal HW_SHDN Signal") based on the TRIP_SET voltage and the SHDN_SEL pin conditions. When this bit is set, it will not cause the ALERT# pin to be asserted however will coincide with SYS_SHDN# pin being asserted. Bit 3 - WATCH - this bit is asserted `1' if the Watchdog Timer circuit does not detect the fan being programmed within 4 seconds after power-up. This bit cannot be masked. Bit 2 - FAN_SPIN - this bit is asserted `1' if the Spin up Routine for Fan cannot detect a valid TACH within its maximum time window. This bit can be masked from asserting the ALERT# pin. Bit 1 - FAN_STALL - this bit is asserted `1' if the TACH measurement on fan detects a stalled fan. This bit can be masked from asserting the ALERT# pin. Bit 0 - I_SHORT - this bit is asserted `1' if the High Side Fan Driver circuit detects a short circuit condition. This bit cannot be masked. 6.8 Interrupt Mask Register Table 6.11 Interrupt Mask Register ADDRESS REGISTER 24h Interrupt Mask B7 - B6 - B5 - B4 B3 B2 B1 B0 SPIN_ MASK STALL_ MASK EXT3_ MSK EXT2_ MSK EXT1_ MSK DEFAULT 10h The Interrupt Mask Register controls the masking for each temperature channel and the TACH monitor. When a channel is masked, it will not cause the ALERT# pin to be asserted when an error condition is detected. Bit 4 - SPIN_MASK - masks the FAN_SPIN bit from asserting the ALERT# pin. `0' - the FAN_SPIN bit will assert the ALERT# pin if set in the Interrupt Status Register 2. `1' - (default) - the FAN_SPIN bit will not assert the ALERT# pin though will still update the Interrupt Status Register 2 normally. SMSC EMC2102 37 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Bit 3 - STALL_MASK - masks the FAN_STALL bit from asserting the ALERT# pin. `0' (default) - the FAN_STALL bit will assert the ALERT# pin if set in the Interrupt Status Register 2. `1' - the FAN_STALL bit will not assert the ALERT# pin though will still update the Interrupt Status Register 2 normally. Bit 2 - EXT3_MASK - masks the ERR3 and TRD3 bits from asserting the ALERT# pin. `0' (default) - the ERR3 and TRD3 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR3 and TRD3 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally. Bit 1 - EXT2_MASK - masks the ERR2 and TRD2 bits from asserting the ALERT# pin. `0' (default) - the ERR2 and TRD2 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR2 and TRD2 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally. Bit 0 - EXT1_MASK - masks the ERR1 and TRD1 bits from asserting the ALERT# pin. 6.9 `0' (default) - the ERR1 and TRD1 bits will assert the ALERT# pin if they are set in the Interrupt Status Register 1. `1' - the ERR1 and TRD1 bits will not assert the ALERT# pin though they will still update the Interrupt Status Register 1 normally. Beta Configuration Registers Table 6.12 Beta Configuration Registers ADDRESS REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 30h External Diode 1 Beta Configuration - - - - - BETA1[2:0] 03h 31h External Diode 2 Beta Configuration - - - - - BETA2[2:0] 03h The Beta Configuration Registers control advanced temperature measurement features for each External Diode channel. The Beta Configuration Registers are software locked. When the External Diode 1 Channel is selected by the SHDN_SEL pin to be the hardware shutdown input channel (see Table 5.4, "SHDN_SEL Pin Configuration"), the External Diode 1 Beta Configuration Register becomes read only. Writing to the register will have no affect and reading from it will always reflect the current beta settings (05h). For the External Diode 3 Channel, the beta compensation setting is fixed at `111b' indicating that the beta compensation is disabled. Bit 2 - 0 - BETAx[2:0] - hold a value that corresponds to a range of betas that the Beta Compensation circuitry can compensate for. The Beta Configuration Registers activate the Beta Compensation circuitry if any value besides 111 is written. The register should be set with a value corresponding to the lowest expected value of beta for the PNP transistor being used as a temperature sensing device. See Figure 6.13, "Beta Compensation Look Up Table" for supported beta ranges. The default setting is calibrated for 65nm CPU's. For 90nm CPU's the optimal beta setting is 04h. Revision 2.02 (05-17-07) 38 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet When the Beta Compensation circuitry is disabled, the diode channels will function with default current levels and will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904 transistor or AMD thermal diode. All of the Beta Configuration Registers are Software Locked. Table 6.13 Beta Compensation Look Up Table BETAX[2:0] 2 1 0 0 0 0 0.1111 0 0 1 0.1765 0 1 0 0.25 0 1 1 0.333 (default) 1 0 0 0.4285 1 0 1 1.0 1 1 0 2.333 1 1 1 Disabled 6.10 MINIMUM BETA REC Configuration Register Table 6.14 REC Configuration Register ADDRESS REGISTER 32h REC Configuration B7 B6 B5 B4 B3 - - - - - B2 B1 B0 REC3 REC2 REC1 DEFAULT 07h The REC Configuration Register determines whether Resistance Error Correction is used for each external diode channel. The REC Configuration Register is software locked. If either the External Diode 1 channel or External Diode 3 channel is selected by the SHDN_SEL pin to be the hardware shutdown input channel (see Table 5.4, "SHDN_SEL Pin Configuration"), then the corresponding RECx bit will be locked. Writing to the bit will have no affect and reading from it will always report the current setting. Bit 2 - REC3 - Controls the Resistive Error Correction functionality of External Diode 3 `0' - the REC functionality for External Diode 3 is disabled `1' (default) - the REC functionality for External Diode 3 is enabled. Bit 1 - REC2 - Controls the Resistive Error Correction functionality of External Diode 1 `0' - the REC functionality for External Diode 2 is disabled `1' (default) - the REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Controls the Resistive Error Correction functionality of External Diode 1 `0' - the REC functionality for External Diode 1 is disabled `1' (default) - the REC functionality for External Diode 1 is enabled. SMSC EMC2102 39 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.11 Temperature Limit Registers Table 6.15 Temperature Limit Registers ADDRESS REGISTER B7 B6 B5 B4 B3 B2 B1 B0 DEFAULT 41h External Diode 1 High Limit Sign 64 32 16 8 4 2 1 55h (+85C) 42h External Diode 2 High Limit Sign 64 32 16 8 4 2 1 55h (+85C) 43h External Diode 3 High Limit Sign 64 32 16 8 4 2 1 55h (+85C) The EMC2102 contains high limits for all temperature channels.If any particular temperature channel exceeds the high limit then the appropriate status bit is set. Each temperature channel software limit can be individually enabled to assert the SYS_SHDN# pin if the temperature exceeds this limit. All Temperature Limit Registers are Software Locked. 6.12 Fan Driver Setting Register Table 6.16 Fan Driver Setting Register ADDRESS 51h REGISTER Fan Driver Setting B7 128 B6 64 B5 32 B4 16 B3 8 B2 4 B1 2 B0 1 DEFAULT 00h The Fan Driver Setting Register always displays the current setting of the High Side Fan Driver. If the RPM based Fan Control Algorithm is disabled, this register can be written to manually control the fan driver (manual mode). See Section 5.2, "Fan Control Modes of Operation". If this register is written to while the RPM based Fan Control Algorithm is active, it will not affect the current output drive. The value that is written will be retained however and used as the current drive if the RPM based Fan Control algorithm is disabled. Reading from this register will report the current fan speed setting regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. The contents of the register represent the weighting of each bit in determining the final output voltage. The output voltage is given by Equation [2]. VALUE FAN_OUT = --------------------- x VDD_5V 255 Revision 2.02 (05-17-07) 40 DATASHEET [2] SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.13 Fan Configuration Register Table 6.17 Fan Control Configuration Register ADDRESS REGISTER 52h FAN Configuration B7 B6 EN B5 LIMIT2K - B4 B3 EDGES[1:0] B2 B1 B0 DEFAULT UPDATE[2:0] CBh The Fan Configuration Register controls the general operation of the RPM based Fan Control Algorithm used for the High Side Fan Driver. Bit 7 - EN - enables the RPM based Fan Control Algorithm. `0' - the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' (default) - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register. Bit 6 - LIMIT2K - Adjusts the range of reported and programmed TACH count values. `0' - the range of reported and programmable TACH values allows for a minimum speed of approximately 500 RPM with reduced resolution to report lower speed values. The TACH Reading count value is multiplied by a value of factor of `1x'. `1' (default) - the range of reported and programmable TACH values allows for a minimum speed of approximately 2000 RPM with increased resolution to report higher speed values. he TACH Reading count value is multiplied by a value of factor of `4x'. Bit 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACH signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate TACH measurement, the minimum number of poles may be increased, however the TACH measurement will be artificially higher than expected as denoted in the Effective TACH multiplier. Additionally, some fans have more than 2-poles and therefore require more edges to be measured as shown in the Number of Fan Poles The EDGES[1:0] bits are shown in Table 6.18, "Minimum Edges for Fan Rotation". Table 6.18 Minimum Edges for Fan Rotation EDGES[1:0] 1 0 MINIMUM TACH EDGES NUMBER OF FAN POLES EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0 0 3 1 pole 0.5 0 1 5 2 poles (default) 1 0 7 3 poles 1.5 1 1 9 4 poles 2 2 Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 6.19, "Update Time". SMSC EMC2102 41 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 6.19 Update Time UPDATE[2:0] 2 1 0 UPDATE TIME 0 0 0 100ms 0 0 1 200ms 0 1 0 300ms 0 1 1 400ms (default) 1 0 0 500ms 1 0 1 800ms 1 1 0 1200ms 1 1 1 1600ms 6.14 Fan Spin Up Configuration Register Table 6.20 Fan TACH Configuration Register ADDRESS REGISTER 53h Fan Spin Up Configuration B7 - B6 - B5 B4 - - B3 - B2 LEVEL B1 B0 SPINUP_TIM E [1:0] DEFAULT 01h The Fan Spin Up Configuration Register controls the settings of Spin Up Routine used by the RPM based Fan Control Algorithm. The Fan Spin Up Configuration Register is software locked. Bit 2 - LEVEL - determines the spin up level that is used whenever the Spin Up Routine is initiated after power-up `0' (default) - the spin up level will be 60% of full scale. `1' - the spin up level will be 75% of full scale. Bit 1 -0 - SPINUP_TIME[2:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 5.3.3, "Spin Up Routine"). If a valid TACH is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM based Fan Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 6.21, "Spin Time". Table 6.21 Spin Time SPINUP_TIME[1:0] 1 0 TOTAL SPIN UP TIME 0 0 250 ms 0 1 500 ms (default) Revision 2.02 (05-17-07) 42 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 6.21 Spin Time (continued) SPINUP_TIME[1:0] 6.15 1 0 TOTAL SPIN UP TIME 1 0 1 sec 1 1 2 sec Fan Step Register Table 6.22 Fan Step Register ADDRESS REGISTER 54h Fan Step B7 - B6 - B5 B4 32 B3 16 8 B2 4 B1 2 B0 1 DEFAULT 10h The Fan Step Register, along with the Update Time, controls the ramp rate of the fan driver response calculated by the RPM based Fan Control Algorithm. The value of the register represents the maximum step size the fan driver will take between update times (see Section 6.13, "Fan Configuration Register"). The Fan Step Register setting can be translated to a maximum voltage step as shown in Equation [2]. If the necessary fan driver delta is larger than the Fan Step, it will be capped at the Fan Step setting and updated every Update Time ms. The Fan Step Register is software locked. 6.16 Fan Minimum Drive Register Table 6.23 Minimum Fan Drive Register ADDRESS REGISTER 55h Fan Minimum Drive B7 128 B6 64 B5 32 B4 16 B3 8 B2 4 B1 2 B0 1 DEFAULT 80h The Fan Minimum Drive Register stores the minimum drive setting for the RPM based Fan Control Algorithm. The RPM based Fan Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed is set at FFh (see Section 6.18, "TACH Target Register") During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Register is software locked. SMSC EMC2102 43 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.17 Valid TACH Count Register Table 6.24 Valid TACH Count Register ADDRESS 56h REGISTER Valid TACH Count B7 B6 B5 B4 B3 2048 1024 512 256 128 B2 B1 64 32 B0 16 DEFAULT F5h The Valid TACH Count Register stores the maximum TACH count to indicate that the fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [4] for translating the count to an RPM. If the TACH count exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. If a TACH Target Count is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count Register is software locked. 6.18 TACH Target Register Table 6.25 TACH Reading Registers ADDRESS 57h REGISTER TACH Target B7 B6 B5 B4 B3 2048 1024 512 256 128 B2 B1 B0 64 32 16 DEFAULT FAh The TACH Target Register holds the target TACH count that is maintained by the RPM based Fan Control Algorithm. If the algorithm is enabled, setting the Fan Target to FFh will immediately disable the High Side Fan Driver. Setting the Fan Target to any other value will cause the algorithm to invoke the Spin Up Routine after which it will function normally. 6.19 TACH Reading Register Table 6.26 TACH Reading Register ADDRESS 58h REGISTER Fan TACH B7 B6 B5 B4 B3 2048 1024 512 256 128 B2 B1 B0 64 32 16 DEFAULT FFh The TACH Reading Register contents describe the current TACH setting of the fan. The data represents the fan speed as the number of 32.768kHz clock periods that occur for a single revolution of the fan. Equation [3] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [4] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. Revision 2.02 (05-17-07) 44 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet where: poles = number of poles of the fan (typically 2) period = period of oscillation (30.5175us is the period for a 32.768khz clock) 1 (n - 1) 1 1 RPM = ------------------------------ x ---------------------------------- x ------------------ x 1e6 x 60 x --1 ( 2 x poles ) period y COUNT x ----m [3] n = number of edges measured (typically 5) m = TACH multiplier term set by LIMIT2K `0' = 1 `1' = 4 y = Scaling factor set by EDGES[1:0] bits 1,966,080 x m RPM = -------------------------------------COUNT COUNT = TACH Reading Register value . (in decimal) Table 6.27 Example TACH Reading for Specific Fan Speeds TACH READING REGISTER LIMIT2K RPM F6h 0 500 FFh (Note 6.2) 1 1920 3Dh 0 2000 F5h 1 2000 0Fh 0 8000 3Dh 1 8000 07h 0 16000 1Eh 1 16000 Note 6.2 6.20 If the LIMIT2K bit is set, the minimum fan speed that can be measured is approximately 1920RPM. Any fan speed lower than this value will be reported as FFh. Product ID Register Table 6.28 Product ID Register ADDRESS REGISTER FDh Product ID Register (EMC2102-1) B7 0 B6 0 B5 B4 0 1 B3 0 B2 1 B1 0 B0 0 DEFAULT 14h The Product ID Register contains a unique 8 bit word that identifies the product. SMSC EMC2102 45 DATASHEET Revision 2.02 (05-17-07) [4] RPM-Based Fan Controller with HW Thermal Shutdown Datasheet 6.21 Revision Register Table 6.29 Revision Register ADDRESS FFh REGISTER Revision B7 0 B6 0 B5 0 B4 0 B3 0 B2 0 B1 0 B0 0 DEFAULT 00h The Revision Register contains a 8 bit word that identifies the die revision. Revision 2.02 (05-17-07) 46 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Chapter 7 Package Drawing Figure 7.1 EMC2102 28-Pin 5x5mm QFN Package Outline and Parameters SMSC EMC2102 47 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Appendix A TACH Reading Table - 2000 RPM Range Table 7.1 TACH Count to RPM (2k Range) (continued) Table 7.1 TACH Count to RPM (2k Range) (continued) REGISTER READING HEX REGISTER READING HEX Table 7.1 TACH Count to RPM (2k Range) DEC REGISTER READING HEX DEC RPM DEC RPM RPM 480 1Eh 16384 960 3Ch 8192 16 01h 491520 496 1Fh 15855 976 3Dh 8058 32 02h 245760 512 20h 15360 992 3Eh 7928 48 03h 163840 528 21h 14895 1008 3Fh 7802 64 04h 122880 544 22h 14456 1024 40h 7680 80 05h 98304 560 23h 14043 1040 41h 7562 96 06h 81920 576 24h 13653 1056 42h 7447 112 07h 70217 592 25h 13284 1072 43h 7336 128 08h 61440 608 26h 12935 1088 44h 7228 144 09h 54613 624 27h 12603 1104 45h 7123 160 0Ah 49152 640 28h 12288 1120 46h 7022 176 0Bh 44684 656 29h 11988 1136 47h 6923 192 0Ch 40960 672 2Ah 11703 1152 48h 6827 208 0Dh 37809 688 2Bh 11431 1168 49h 6733 224 0Eh 35109 704 2Ch 11171 1184 4Ah 6642 240 0Fh 32768 720 2Dh 10923 1200 4Bh 6554 256 10h 30720 736 2Eh 10685 1216 4Ch 6467 272 11h 28913 752 2Fh 10458 1232 4Dh 6383 288 12h 27307 768 30h 10240 1248 4Eh 6302 304 13h 25869 784 31h 10031 1264 4Fh 6222 320 14h 24576 800 32h 9830 1280 50h 6144 336 15h 23406 816 33h 9638 1296 51h 6068 352 16h 22342 832 34h 9452 1312 52h 5994 368 17h 21370 848 35h 9274 1328 53h 5922 384 18h 20480 864 36h 9102 1344 54h 5851 400 19h 19661 880 37h 8937 1360 55h 5783 416 1Ah 18905 896 38h 8777 1376 56h 5715 432 1Bh 18204 912 39h 8623 1392 57h 5650 448 1Ch 17554 928 3Ah 8474 1408 58h 5585 464 1Dh 16949 944 3Bh 8331 1424 59h 5523 SMSC EMC2102 48 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 7.1 TACH Count to RPM (2k Range) (continued) Table 7.1 TACH Count to RPM (2k Range) (continued) Table 7.1 TACH Count to RPM (2k Range) (continued) REGISTER READING HEX REGISTER READING HEX REGISTER READING HEX DEC RPM DEC RPM DEC RPM 1440 5Ah 5461 1936 79h 4062 2432 98h 3234 1456 5Bh 5401 1952 7Ah 4029 2448 99h 3213 1472 5Ch 5343 1968 7Bh 3996 2464 9Ah 3192 1488 5Dh 5285 1984 7Ch 3964 2480 9Bh 3171 1504 5Eh 5229 2000 7Dh 3932 2496 9Ch 3151 1520 5Fh 5174 2016 7Eh 3901 2512 9Dh 3131 1536 60h 5120 2032 7Fh 3870 2528 9Eh 3111 1552 61h 5067 2048 80h 3840 2544 9Fh 3091 1568 62h 5016 2064 81h 3810 2560 A0h 3072 1584 63h 4965 2080 82h 3781 2576 A1h 3053 1600 64h 4915 2096 83h 3752 2592 A2h 3034 1616 65h 4867 2112 84h 3724 2608 A3h 3015 1632 66h 4819 2128 85h 3696 2624 A4h 2997 1648 67h 4772 2144 86h 3668 2640 A5h 2979 1664 68h 4726 2160 87h 3641 2656 A6h 2961 1680 69h 4681 2176 88h 3614 2672 A7h 2943 1696 6Ah 4637 2192 89h 3588 2688 A8h 2926 1712 6Bh 4594 2208 8Ah 3562 2704 A9h 2908 1728 6Ch 4551 2224 8Bh 3536 2720 AAh 2891 1744 6Dh 4509 2240 8Ch 3511 2736 ABh 2874 1760 6Eg 4468 2256 8Dh 3486 2752 ACh 2858 1776 6Fh 4428 2272 8Eh 3461 2768 ADh 2841 1792 70 4389 2288 8Fh 3437 2784 AEh 2825 1808 71h 4350 2304 90h 3413 2800 AFh 2809 1824 72h 4312 2320 91h 3390 2816 B0h 2793 1840 73h 4274 2336 92h 3367 2832 B1h 2777 1856 74h 4237 2352 93h 3344 2848 B2h 2761 1872 75h 4201 2368 94h 3321 2864 B3h 2746 1888 76h 4165 2384 95h 3299 2880 B4h 2731 1904 77h 4130 2400 96h 3277 2896 B5h 2716 1920 78h 4096 2416 97h 3255 2912 B6h 2701 Revision 2.02 (05-17-07) 49 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 7.1 TACH Count to RPM (2k Range) (continued) Table 7.1 TACH Count to RPM (2k Range) (continued) Table 7.1 TACH Count to RPM (2k Range) (continued) REGISTER READING HEX REGISTER READING HEX REGISTER READING HEX DEC RPM DEC RPM DEC RPM 2928 B7h 2686 3424 D6h 2297 3920 F5h 2006 2944 B8h 2671 3440 D7h 2286 3936 F6h 1998 2960 B9h 2657 3456 D8h 2276 3952 F7h 1990 2976 BAh 2643 3472 D9h 2265 3968 F8h 1982 2992 BBh 2628 3488 DAh 2255 3984 F9h 1974 3008 BCh 2614 3504 DBh 2244 4000 FAh 1966 3024 BDh 2601 3520 DCh 2234 4016 FBh 1958 3040 BEh 2587 3536 DDh 2224 4032 FCh 1950 3056 BFh 2573 3552 DEh 2214 4048 FDh 1943 3072 C0h 2560 3568 DFh 2204 4064 FEh 1935 3088 C1h 2547 3584 E0h 2194 4080 FFh 1928 3104 C2h 2534 3600 E1h 2185 3120 C3h 2521 3616 E2h 2175 3136 C4h 2508 3632 E3h 2165 3152 C5h 2495 3648 E4h 2156 3168 C6h 2482 3664 E5h 2146 3184 C7h 2470 3680 E6h 2137 3200 C8h 2458 3696 E7h 2128 3216 C9h 2445 3712 E8h 2119 3232 CAh 2433 3728 E9h 2110 3248 CBh 2421 3744 EAh 2101 3264 CCh 2409 3760 EBh 2092 3280 CDh 2398 3776 ECh 2083 3296 CEh 2386 3792 EDh 2074 3312 CFh 2374 3808 EEh 2065 3328 D0h 2363 3824 EFh 2057 3344 D1h 2352 3840 F0h 2048 3360 D2h 2341 3856 F1h 2040 3376 D3h 2329 3872 F2h 2031 3392 D4h 2318 3888 F3h 2023 3408 D5h 2308 3904 F4h 2014 SMSC EMC2102 50 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Appendix B TACH Reading Table - 500RPM Range Table 7.2 TACH Count to RPM (500 Range) (continued) Table 7.2 TACH Count to RPM (500 Range) DEC REGISTER READING HEX DEC REGISTER READING HEX RPM Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM RPM 464 1Dh 4237 928 3Ah 2119 16 01h 122880 480 1Eh 4096 944 3Bh 2083 32 02h 61440 496 1Fh 3964 960 3Ch 2048 48 03h 40960 512 20h 3840 976 3Dh 2014 64 04h 30720 528 21h 3724 992 3Eh 1982 80 05h 24576 544 22h 3614 1008 3Fh 1950 96 06h 20480 560 23h 3511 1024 40h 1920 112 07h 17554 576 24h 3413 1040 41h 1890 128 08h 15360 592 25h 3321 1056 42h 1862 144 09h 13653 608 26h 3234 1072 43h 1834 160 0Ah 12288 624 27h 3151 1088 44h 1807 176 0Bh 11171 640 28h 3072 1104 45h 1781 192 0Ch 10240 656 29h 2997 1120 46h 1755 208 0Dh 9452 672 2Ah 2926 1136 47h 1731 224 0Eh 8777 688 2Bh 2858 1152 48h 1707 240 0Fh 8192 704 2Ch 2793 1168 49h 1683 256 10h 7680 720 2Dh 2731 1184 4Ah 1661 272 11h 7228 736 2Eh 2671 1200 4Bh 1638 288 12h 6827 752 2Fh 2614 1216 4Ch 1617 304 13h 6467 768 30h 2560 1232 4Dh 1596 320 14h 6144 784 31h 2508 1248 4Eh 1575 336 15h 5851 800 32h 2458 1264 4Fh 1555 352 16h 5585 816 33h 2409 1280 50h 1536 368 17h 5343 832 34h 2363 1296 51h 1517 384 18h 5120 848 35h 2318 1312 52h 1499 400 19h 4915 864 36h 2276 1328 53h 1480 416 1Ah 4726 880 37h 2234 1344 54h 1463 432 1Bh 4551 896 38h 2194 1360 55h 1446 448 1Ch 4389 912 39h 2156 1376 56h 1429 Revision 2.02 (05-17-07) 51 DATASHEET SMSC EMC2102 RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM 1392 57h 1412 1888 76h 1041 2384 95h 825 1408 58h 1396 1904 77h 1033 2400 96h 819 1424 59h 1381 1920 78h 1024 2416 97h 814 1440 5Ah 1365 1936 79h 1016 2432 98h 808 1456 5Bh 1350 1952 7Ah 1007 2448 99h 803 1472 5Ch 1336 1968 7Bh 999 2464 9Ah 798 1488 5Dh 1321 1984 7Ch 991 2480 9Bh 793 1504 5Eh 1307 2000 7Dh 983 2496 9Ch 788 1520 5Fh 1293 2016 7Eh 975 2512 9Dh 783 1536 60h 1280 2032 7Fh 968 2528 9Eh 778 1552 61h 1267 2048 80h 960 2544 9Fh 773 1568 62h 1254 2064 81h 953 2560 A0h 768 1584 63h 1241 2080 82h 945 2576 A1h 763 1600 64h 1229 2096 83h 938 2592 A2h 759 1616 65h 1217 2112 84h 931 2608 A3h 754 1632 66h 1205 2128 85h 924 2624 A4h 749 1648 67h 1193 2144 86h 917 2640 A5h 745 1664 68h 1182 2160 87h 910 2656 A6h 740 1680 69h 1170 2176 88h 904 2672 A7h 736 1696 6Ah 1159 2192 89h 897 2688 A8h 731 1712 6Bh 1148 2208 8Ah 890 2704 A9h 727 1728 6Ch 1138 2224 8Bh 884 2720 AAh 723 1744 6Dh 1127 2240 8Ch 878 2736 ABh 719 1760 6Eg 1117 2256 8Dh 871 2752 ACh 714 1776 6Fh 1107 2272 8Eh 865 2768 ADh 710 1792 70 1097 2288 8Fh 859 2784 AEh 706 1808 71h 1087 2304 90h 853 2800 AFh 702 1824 72h 1078 2320 91h 847 2816 B0h 698 1840 73h 1069 2336 92h 842 2832 B1h 694 1856 74h 1059 2352 93h 836 2848 B2h 690 1872 75h 1050 2368 94h 830 2864 B3h 686 SMSC EMC2102 52 DATASHEET Revision 2.02 (05-17-07) RPM-Based Fan Controller with HW Thermal Shutdown Datasheet Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM Table 7.2 TACH Count to RPM (500 Range) (continued) DEC REGISTER READING HEX RPM 2880 B4h 683 3376 D3h 582 3872 F2h 508 2896 B5h 679 3392 D4h 580 3888 F3h 506 2912 B6h 675 3408 D5h 577 3904 F4h 504 2928 B7h 671 3424 D6h 574 3920 F5h 502 2944 B8h 668 3440 D7h 572 3936 F6h 500 2960 B9h 664 3456 D8h 569 3952 F7h 497 2976 BAh 661 3472 D9h 566 3968 F8h 495 2992 BBh 657 3488 DAh 564 3984 F9h 493 3008 BCh 654 3504 DBh 561 4000 FAh 492 3024 BDh 650 3520 DCh 559 4016 FBh 490 3040 BEh 647 3536 DDh 556 4032 FCh 488 3056 BFh 643 3552 DEh 554 4048 FDh 486 3072 C0h 640 3568 DFh 551 4064 FEh 484 3088 C1h 637 3584 E0h 549 4080 FFh 482 3104 C2h 633 3600 E1h 546 3120 C3h 630 3616 E2h 544 3136 C4h 627 3632 E3h 541 3152 C5h 624 3648 E4h 539 3168 C6h 621 3664 E5h 537 3184 C7h 617 3680 E6h 534 3200 C8h 614 3696 E7h 532 3216 C9h 611 3712 E8h 530 3232 CAh 608 3728 E9h 527 3248 CBh 605 3744 EAh 525 3264 CCh 602 3760 EBh 523 3280 CDh 599 3776 ECh 521 3296 CEh 597 3792 EDh 518 3312 CFh 594 3808 EEh 516 3328 D0h 591 3824 EFh 514 3344 D1h 588 3840 F0h 512 3360 D2h 585 3856 F1h 510 Revision 2.02 (05-17-07) 53 DATASHEET SMSC EMC2102 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: EMC2102-DZK EMC2102-DZK-TR