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LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
LMH6622 Dual Wideband, Low Noise, 160 MHz, Operational Amplifiers
1 Features 3 Description
The LMH6622 is a dual high speed voltage feedback
1• VS= ±6 V, TA= 25°C, Typical Values Unless operational amplifier specifically optimized for low
Specified noise. A voltage noise specification of 1.6nV/√Hz, a
• Bandwidth (AV= +2) 160 MHz current noise specification 1.5pA/√Hz, a bandwidth of
• Supply Voltage Range ±2.5 V to ±6 V; 160 MHz, and a harmonic distortion specification that
exceeds 90 dBc combine to make the LMH6622 an
+ 5 V to +12 ideal choice for the receive channel amplifier in
• Slew Rate 85V/μsADSL, VDSL, or other xDSL designs. The LMH6622
• Supply Current 4.3 mA/amp operates from ±2.5 V to ±6 V in dual supply mode
• Input Common Mode Voltage −4.75 V to +5.7 V and from +5 V to +12 V in single supply configuration.
The LMH6622 is stable for AV≥2 or AV≤ −1. The
• Output Voltage Swing (RL= 100 Ω) ±4.6 V fabrication of the LMH6622 on TI's advanced VIP10
• Input Voltage Noise 1.6 nV/√Hz process enables excellent (160 MHz) bandwidth at a
• Input Current Noise 1.5 pA/√Hz current consumption of only 4.3 mA/amplifier.
Packages for this dual amplifier are the 8-lead SOIC
• Linear Output Current 90 mA and the 8-lead VSSOP.
• Excellent Harmonic Distortion 90 dBc
Device Information(1)
2 Applications PART NUMBER PACKAGE BODY SIZE (NOM)
• xDSL Receiver LMH6622 SOIC (8) 4.90 mm × 3.91 mm
• Low Noise Instrumentation Front End LMH6622 VSSOP (8) 3.00 mm × 3.00 mm
• Ultrasound Preamp (1) For all available packages, see the orderable addendum at
the end of the datasheet.
• Active Filters
• Cellphone Basestation
XDSL Analog Front End
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
Table of Contents
8.3 Feature Description................................................. 16
1 Features.................................................................. 18.4 Device Functional Modes........................................ 16
2 Applications ........................................................... 19 Application and Implementation ........................ 17
3 Description............................................................. 19.1 DSL Receive Channel Applications........................ 17
4 Revision History..................................................... 29.2 Receive Channel Noise Calculation........................ 19
5 Pin Configuration and Functions......................... 39.3 Differential Analog-to-Digital Driver......................... 20
6 Specifications......................................................... 49.4 Typical Application ................................................. 21
6.1 Absolute Maximum Ratings ...................................... 410 Power Supply Recommendations ..................... 22
6.2 Handling Ratings....................................................... 410.1 Driving Capacitive Load........................................ 22
6.3 Recommended Operating Conditions....................... 411 Layout................................................................... 22
6.4 Thermal Information.................................................. 411.1 Layout Guidelines ................................................. 22
6.5 ±6 V Electrical Characteristics.................................. 511.2 Layout Examples................................................... 23
6.6 ±2.5 V Electrical Characteristics............................... 612 Device and Documentation Support................. 25
6.7 Typical Performance Characteristics ........................ 912.1 Trademarks........................................................... 25
7 Parameter Measurement Information ................ 14 12.2 Electrostatic Discharge Caution............................ 25
7.1 Test Circuits............................................................ 14 12.3 Glossary................................................................ 25
8 Detailed Description............................................ 16 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................. 16 Information........................................................... 25
8.2 Functional Block Diagram....................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E Page
• Changed data sheet flow and layout to conform with new TI standards. Added the following sections: Device
Information Table, Application and Implementation; Power Supply Recommendations; Layout; Device and
Documentation Support; Mechanical, Packaging, and Ordering Information ........................................................................ 1
• Changed RGto RC. Changed AVfrom +10 to +9 for Figure 38............................................................................................ 20
• Changed RGto RC. Changed AVfrom +10 to +9 for Figure 39............................................................................................ 20
Changes from Revision C (March 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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SNOS986E –DECEMBER 2001–REVISED JULY 2014
5 Pin Configuration and Functions
8-Pin SOIC and VSSOP
D and DGK Packages
(Top View)
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
OUT A 1 O ChA Output
-IN A 2 I ChA Inverting Input
+IN A 3 I ChA Non-inverting Input
V- 4 I V- Supply Pin
+IN B 5 I ChB Non-inverting Input
-IN B 6 I ChB Inverting Input
OUT B 7 I ChB Output
V+ 8 I V+ Supply Pin
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
MIN MAX UNIT
VIN Differential ±1.2 V
Supply Voltage (V+– V−) 13.2 V
Voltage at Input Pins V++0.5, V
V−−0.5
SOLDERING INFORMATION
Infrared or Convection (20 sec) 235 °C
Wave Soldering (10 sec) 260 °C
Junction Temperature (3) +150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65° +150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2000(2)
pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC specification JESD22- 200(2)
C101, all pins(3)
(1) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(2) Human body model, 1.5 kΩin series with 100 pF. Machine model, 0 Ωin series with 200 pF.
(3) JEDEC document JEP157 states that 200-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions(1)
MIN MAX UNIT
Supply Voltage (V+– V−) ±2.25 ±6 V
Temperature Range(2)(3) −40 +85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(3) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
6.4 Thermal Information LMH6622 LMH6622
THERMAL METRIC(1) Package D Package DGK UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance(2) 166° 211° °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly onto a PC board.
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6.5 ±6 V Electrical Characteristics
Unless otherwise specified, TJ= 25°C, V+= 6 V, V−=−6 V, VCM = 0 V, AV= +2, RF= 500 Ω, RL= 100 Ω. Some limits apply at
the temperature extremes as noted in the table. TEMPERATURE ROOM
EXTREMES TEMPERATURE
PARAMETER TEST CONDITIONS UNIT
MIN(1) TYP(2) MAX(1) MIN(1) TYP(2) MAX(1)
DYNAMIC PERFORMANCE
fCL −3dB BW VO= 200 mVPP 160 MHz
BW0.1dB 0.1dB Gain Flatness VO= 20 0mVPP 30 MHz
SR Slew Rate(3) VO= 2 VPP 85 V/μs
TS Settling Time VO= 2 VPP to ±0.1% 40 ns
VO= 2 VPP to ±1.0% 35
Tr Rise Time VO= 0.2 V Step, 10% to 90% 2.3 ns
Tf Fall Time VO= 0.2 V Step, 10% to 90% 2.3 ns
DISTORTION and NOISE RESPONSE
enInput Referred Voltage f = 100 kHz nV/√Hz
1.6
Noise
inInput Referred Current f = 100 kHz pA/√Hz
1.5
Noise
DG Differential Gain RL= 150 Ω, RF= 470 Ω, NTSC 0.03%
DP Differential Phase RL= 150 Ω, RF= 470 Ω, NTSC 0.03 deg
HD2 2nd Harmonic Distortion fc= 1 MHz, VO= 2 VPP,−90
RL= 100 ΩdBc
fc= 1 MHz, VO= 2 VPP,−100
RL= 500 Ω
HD3 3rd Harmonic Distortion fc= 1 MHz, VO= 2 VPP,−94
RL= 100 ΩdBc
fc= 1 MHz, VO= 2 VPP,−100
RL= 500 Ω
MTPR Upstream VO= 0.6 VRMS,
26 kHz to 132 kHz −78
(see Figure 33)dBc
Downstream VO= 0.6 VRMS,
144 kHz to 1.1 MHz −70
(see Figure 33)
INPUT CHARACTERISTICS
VOS Input Offset Voltage VCM = 0 V −2 +2 −1.2 +0.2 +1.2 mV
TC VOS Input Offset Average Drift VCM = 0 V(4) −2.5 μV/°C
IOS Input Offset Current VCM = 0V −1.5 1.5 −1−0.04 1 μA
IBInput Bias Current VCM = 0V 15 4.7 10 μA
RIN Input Resistance Common Mode 17 MΩ
Differential Mode 12 kΩ
CIN Input Capacitance Common Mode 0.9 pF
Differential Mode 1.0 pF
CMVR Input Common Mode CMRR ≥60dB −4.75 −4.5 V
Voltage Range 5.5 +5.7
CMRR Common-Mode Rejection Input Referred, dB
75 80 100
Ratio VCM =−4.2 V to +5.2 V
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the slowest of the rising and falling slew rates.
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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±6 V Electrical Characteristics (continued)
Unless otherwise specified, TJ= 25°C, V+= 6 V, V−=−6 V, VCM = 0 V, AV= +2, RF= 500 Ω, RL= 100 Ω. Some limits apply at
the temperature extremes as noted in the table. TEMPERATURE ROOM
EXTREMES TEMPERATURE
PARAMETER TEST CONDITIONS UNIT
MIN(1) TYP(2) MAX(1) MIN(1) TYP(2) MAX(1)
TRANSFER CHARACTERISTICS
AVOL Large Signal Voltage Gain VO= 4 VPP 70 74 83 dB
XtCrosstalk f = 1 MHz −75 dB
OUTPUT CHARACTERISTICS
VOOutput Swing No Load, Positive Swing 4.6 4.8 5.2
No Load, Negative Swing −4.4 −5.0 −4.6 V
RL= 100 Ω, Positive Swing 3.8 4.0 4.6
RL= 100 Ω, Negative Swing −3.8 −4.6 −4
ROOutput Impedance f = 1 MHz 0.08 Ω
ISC Output Short Circuit Sourcing to Ground 100 135
Current ΔVIN = 200 mV(5),(6) mA
Sinking to Ground 100 130
ΔVIN =−200 mV(5),(6)
IOUT Output Current Sourcing, VO= +4.3 V mA
90
Sinking, VO=−4.3 V
POWER SUPPLY
+PSRR Positive Power Supply Input Referred, 74 80 95
Rejection Ratio VS= +5 V to +6 V dB
−PSRR Negative Power Supply Input Referred, 69 75 90
Rejection Ratio VS=−5 V to −6 V
ISSupply Current (per No Load mA
6.5 4.3 6
amplifier)
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(6) Short circuit test is a momentary test. Output short circuit duration is infinite for VS≤±2.5 V, at room temperature and below. For VS>
±2.5 V, allowable short circuit duration is 1.5ms.
6.6 ±2.5 V Electrical Characteristics
Unless otherwise specified, TJ= 25°C, V+ = 2.5 V, V−=−2.5 V, VCM = 0 V, AV= +2, RF= 500 Ω, RL= 100 Ω. Some limits
apply at the temperature extremes as noted in the table.
PARAMETER TEST CONDITIONS TEMPERATURE ROOM UNIT
EXTREMES TEMPERATURE
MIN(1) TYP(2) MAX(1) MIN(1) TYP(2) MAX(1)
DYNAMIC PERFORMANCE
fCL −3 dB BW VO= 200 mVPP 150 MHz
BW0.1dB 0.1dB Gain Flatness VO= 200 mVPP 20 MHz
SR Slew Rate (3) VO= 2 VPP 80 V/μs
TSSettling Time VO= 2 VPP to ±0.1% 45 ns
VO= 2 VPP to ±1.0% 40
TrRise Time VO= 0.2 V Step, 10% to 90% 2.5 ns
TfFall Time VO= 0.2 V Step, 10% to 90% 2.5 ns
(1) All limits are specified by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the slowest of the rising and falling slew rates.
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±2.5 V Electrical Characteristics (continued)
Unless otherwise specified, TJ= 25°C, V+ = 2.5 V, V−=−2.5 V, VCM = 0 V, AV= +2, RF= 500 Ω, RL= 100 Ω. Some limits
apply at the temperature extremes as noted in the table.
PARAMETER TEST CONDITIONS TEMPERATURE ROOM UNIT
EXTREMES TEMPERATURE
MIN(1) TYP(2) MAX(1) MIN(1) TYP(2) MAX(1)
DISTORTION and NOISE RESPONSE
enInput Referred Voltage f = 100 kHz nV/√Hz
1.7
Noise
inInput Referred Current f = 100 kHz pA/√Hz
1.5
Noise
HD2 2nd Harmonic Distortion fc = 1 MHz, VO= 2VPP,−88
RL= 100 ΩdBc
fc = 1 MHz, VO= 2VPP,−98
RL= 500 Ω
HD3 3rd Harmonic Distortion fc = 1 MHz, VO= 2 VPP, RL=−92
100 ΩdBc
fc = 1 MHz, VO= 2 VPP, RL=−100
500 Ω
MTPR Upstream VO= 0.4VRMS, 26kHz to
132kHz −76
(see Figure 33)dBc
Downstream VO= 0.4 VRMS,
144 kHz to 1.1 MHz −68
(see Figure 33)
INPUT CHARACTERISTICS
VOS Input Offset Voltage VCM = 0 V −2.3 +2.3 −1.5 +0.3 +1.5 mV
TC VOS Input Offset Average Drift VCM = 0 V(4) −2.5 μV/°C
IOS Input Offset Current VCM = 0 V −2.5 2.5 −1.5 +0.01 1.5 μA
IBInput Bias Current VCM = 0 V 15 4.6 10 μA
RIN Input Resistance Common Mode 17 MΩ
Differential Mode 12 kΩ
CIN Input Capacitance Common Mode 0.9 pF
Differential Mode 1.0 pF
CMVR Input Common Mode CMRR ≥60dB −1.25 −1V
Voltage Range 2 +2.2
CMRR Common Mode Rejection Input Referred, dB
75 80 100
Ratio VCM =−0.7 V to +1.7 V
TRANSFER CHARACTERISTICS
AVOL Large Signal Voltage Gain VO= 1 VPP 74 82 dB
XtCrosstalk f = 1 MHz −75 dB
(4) Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
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±2.5 V Electrical Characteristics (continued)
Unless otherwise specified, TJ= 25°C, V+ = 2.5 V, V−=−2.5 V, VCM = 0 V, AV= +2, RF= 500 Ω, RL= 100 Ω. Some limits
apply at the temperature extremes as noted in the table.
PARAMETER TEST CONDITIONS TEMPERATURE ROOM UNIT
EXTREMES TEMPERATURE
MIN(1) TYP(2) MAX(1) MIN(1) TYP(2) MAX(1)
OUTPUT CHARACTERISTICS
VOOutput Swing No Load, Positive Swing 1.2 1.4 1.7
No Load, Negative Swing −1−1.5 −1.2 V
RL= 100 Ω, Positive Swing 1 1.2 1.5
RL= 100 Ω, Negative Swing −0.9 −1.4 −1.1
ROOutput Impedance f = 1 MHz 0.1 Ω
ISC Output Short Circuit Sourcing to Ground 100 137
Current ΔVIN = 200 mV(5)(6) mA
Sinking to Ground 100 134
ΔVIN =−20 0mV(5)(6)
IOUT Output Current Sourcing, VO= +0.8 V mA
90
Sinking, VO=−0.8 V
POWER SUPPLY
+PSRR Positive Power Supply Input Referred, 72 78 93 dB
Rejection Ratio VS= +2.5 V to +3 V
−PSRR Negative Power Supply Input Referred, dB
70 75 88
Rejection Ratio VS=−2.5 V to −3 V
ISSupply Current (per No Load 6.4 4.1 5.8 mA
amplifier)
(5) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(6) Short circuit test is a momentary test. Output short circuit duration is infinite for VS≤±2.5 V, at room temperature and below. For VS>
±2.5 V, allowable short circuit duration is 1.5ms.
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FREQUENCY
(Hz)
1
k100k 10M
-5
-1
2
NORMALIZED GAIN (dB)
10
k1
M
-4
-3
-2
0
1
5
3
4
100M
AV = -1, BW = 187MHz
AV = -2, BW = 110MHz
AV = -10, BW =
30MHz
VSS = ±6V
RF = 500:
VIN =
100mVPP
AV = -5, BW =
45MHz
FREQUENCY
(Hz)
1
k100k 10M
-5
-1
2
NORMALIZED GAIN (dB)
10
k1
M
-4
-3
-2
0
1
5
3
4
100M
AV = +2, BW = 166MHz
AV = +3, BW = 96MHz
AV = +10, BW = 21MHz
VSS = ±6V
RF = 500:
VIN =
100mVPP
AV = +5, BW = 45MHz
1k 100k 10M 500
M
FREQUENCY (Hz)
-5
-2
+1
NORMALIZED GAIN
(dB)
100M
1M
10k
+4
+2
0
-1
-4
+3
-3
+
5VS = ±2.5V
AV = +2
VIN = 700mVPP, BW = 33MHz
VIN = 450mVPP, BW = 50MHz
VIN = 200mVPP, BW = 103MHz
VIN = 100mVPP, BW = 154MHz
VIN = 14mVPP, BW = 186MHz
11k 1M
0.1
1
10
100
10k
100 10M
FREQUENCY (Hz)
100k
10
100
10
1
0.1
VOLTAGE NOISE (nV/ Hz)
CURRENT NOISE (pA/ Hz)
VS = ±2.5V
VOLTAGE
CURRENT
11k 1M
0.1
1
10
100
10k
100 10M
FREQUENCY (Hz)
100k
10
100
10
1
0.1
VOLTAGE NOISE (nV/ Hz)
CURRENT NOISE (pA/ Hz)
VS = ±6V
VOLTAGE
CURRENT
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6.7 Typical Performance Characteristics
Figure 1. Current and Voltage Noise vs. Frequency Figure 2. Current and Voltage Noise vs. Frequency
Figure 3. Frequency Response vs. Input Signal Level Figure 4. Frequency Response vs. Input Signal Level
Figure 6. Non-Inverting Amplifier Frequency Response
Figure 5. Inverting Amplifier Frequency Response
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0.01 11000
OUTPUT SOURCING CURRENT
(mA)
0.5
0.
9
2.5
VOUT REFERENCED TO V+ (V)
100
10
0.1
2.3
1.5
0.7
2.1
1.7
1.3
1.1
1.9
VS = ±2.5V
VS = ±6V
0.01 11000
OUTPUT SINKING CURRENT (mA)
0.5
0.9
2.5
VOUT REFERENCED TO V- (V)
100
10
0.1
2.3
1.5
0.7
2.1
1.7
1.3
1.1
1.9
VS = ±2.5V
VS = ±6V
10k 100k 1M 10M 100M
FREQUENCY (Hz)
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
dB
VS = ±2.5V
VS = ±6V VS = ±2.5V
VS = ±6V
+PSRR
-PSRR
1k 10k 100k 1M
FREQUENCY
(Hz)
-100
-95
-90
-85
-80
-75
-70
-65
-60
-55
-50
dB
2M
1k 100k 10
M500M
FREQUENCY
(Hz)
-10
20
50
GAIN (dB)
100M
1M
10k
80
60
40
30
0
70
10
90 270°
234°
198°
162°
126°
90°
54°
18°
-18°
-54°
-90°
PHASE (°)
GAIN
PHASE -30°C
-30°C
25°C
85°C
25°C
85°C
100
k1M 10M 100
M
FREQUENCY
(Hz)
-
100
-90
-
80
-
70
-
60
-
50
-40
-
30
-20
-
10
0
CROSSTALK (dB)
VS = ±2.5V
VS = ±6V
VS = ±6V
VS = ±2.5V
CHANNEL 1 OUTPUT
CHANNEL 2 OUTPUT
VS = ±6V, ±2.5V
VIN = 200mVpp
AV = +2
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Typical Performance Characteristics (continued)
Figure 8. Crosstalk vs. Frequency
Figure 7. Open Loop Gain and Phase Response
Figure 10. CMRR vs. Frequency
Figure 9. PSRR vs. Frequency
Figure 11. Positive Output Swing vs. Source Current Figure 12. Negative Output Swing vs. Sink Current
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0500 1000 1500 2000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VIN (mVPP)
VS = ±6V
f = 1MHz
AV = +2
RL = 100:
HD3
HD2
0200 400 600 800 1000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VIN (mVPP)
HD2
HD3
VS =
±2.5V
f = 1MHz
AV = +2
RL = 100:
500mV/DIV 100nS
INPUT
1V/DIV
OUTPUT
500mV/DIV 100nS
INPUT
1V/DIV
OUTPUT
50mV/DIV 100nS
INPUT
100mV/DIV
OUTPUT
50mV/DIV 100nS
INPUT
100mV/DIV
OUTPUT
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Typical Performance Characteristics (continued)
Figure 13. Non-Inverting Small Signal Pulse Response Figure 14. Non-Inverting Small Signal Pulse Response
VS= ±2.5 V, RL= 100 Ω, AV= +2, RF= 500 ΩVS= ±6 V, RL= 100 Ω, AV= +2, RF= 500 Ω
Figure 15. Non-Inverting Large Signal Pulse Response Figure 16. Non-Inverting Large Signal Pulse Response
VS= ±2.5 V, RL= 100 Ω, AV= +2, RF= 500 ΩVS= ±6 V, RL= 100 Ω, AV= +2, RF= 500 Ω
Figure 17. Harmonic Distortion vs. Input Signal Level Figure 18. Harmonic Distortion vs. Input Signal Level
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-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VS = ±2.5V
VIN = 1VPP
AV = +2
RL = 500:
HD2
HD3
0500 1000 1500 2000
FREQUENCY (kHz)
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VS = ±6V
VIN = 1VPP
AV = +2
RL = 500:
HD2
HD3
0500 1000 1500 2000
FREQUENCY (kHz)
0500 1000 1500 2000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VIN (mVPP)
HD3
HD2
VS = ±6V
f = 1MHz
AV = +2
RL = 500:
0200 400 600 800 1000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
VIN (mVPP)
HD2
HD3
VS = ±2.5V
f = 1MHz
AV = +2
RL = 500:
0500 1000 1500 2000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
FREQUENCY (kHz)
VS = ±2.5V
VIN = 1VPP
AV = +2
RL = 100:
HD2
HD3
0500 1000 1500 2000
-120
-100
-80
-60
-40
-20
0
HARMONIC DISTORTION -dBc
FREQUENCY (kHz)
VS = ±6V
VIN = 1VPP
AV = +2
RL = 100:
HD2
HD3
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
Typical Performance Characteristics (continued)
Figure 19. Harmonic Distortion vs. Frequency Figure 20. Harmonic Distortion vs. Frequency
Figure 21. Harmonic Distortion vs. Input Signal Level Figure 22. Harmonic Distortion vs. input Signal Level
Figure 23. Harmonic Distortion vs. Input Frequency Figure 24. Harmonic Distortion vs. Input Frequency
12 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
102.8 104.8 106.8 108.8 110.8 112.8
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
MTPR (dBc)
FREQUENCY (kHz)
VS = ±6V
VO = 0.611VRMS
RF = 500:
RG = 174:
RL = 437:
551.3 553.3 555.3 557.3 559.3 561.3
-80
-70
-60
-50
-40
-30
-20
-10
0
MTPR (dBc)
FREQUENCY (kHz)
VS = ±6V
VO = 0.597VRMS
RF = 500:
RG = 174:
RL = 437:
551.3 553.3 555.3 557.3 559.3 561.3
-70
-60
-50
-40
-30
-20
-10
0
MTPR (dBc)
FREQUENCY (kHz)
VS = ±2.5V
VO = 0.396VRMS
RF = 500:
RG = 174:
RL = 437:
102.8 104.8 106.8 108.8 110.8 112.8
-80
-70
-60
-50
-40
-30
-20
-10
0
MTPR (dBc)
FREQUENCY (kHz)
VS = ±2.5V
VO = 0.407VRMS
RF = 500:
RG = 174:
RL = 437:
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
Typical Performance Characteristics (continued)
Figure 25. Full Rate ADSL (DMT) Upstream MTPR Figure 26. Full Rate ADSL (DMT) Downstream MTPR
@ VS= ±2.5 V @ VS= ±2.5 V
Figure 27. Full Rate ADSL (DMT) Upstream MTPR Figure 28. Full Rate ADSL (DMT) Downstream MTPR @ VS=
±6 V
@ VS= ±6 V
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMH6622
RG100:
-
+
PF
-
+
50:
154:
56.7:
154:
604:604:
RGRF
-
+50:
50:
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
7 Parameter Measurement Information
7.1 Test Circuits
Figure 29. Non-Inverting Amplifier
Figure 30. CMRR
Figure 31. Voltage Noise
RG= 1 Ωfor f ≤100 kHz, RG= 20 Ωfor f > 100 kHz
14 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
+
+
+
+
-
-
-
-
VOUT
RF
RF
RL
RG
VIN
RG100:
-
+
1k:
1PF
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
Test Circuits (continued)
Figure 32. Current Noise
RG= 1 Ωfor f ≤100 kHz, RG= 20 Ωfor f > 100 kHz
Figure 33. Multitone Power Ratio, RF= 500 Ω, RG= 174 Ω, RL= 437 Ω
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMH6622
ADC
DAC
DAC
LMH6643 LMH6672
BUFFER/FILTER LINE DRIVER
HYBRID
COUPLER
LMH6622
TELEPHONE LINE
RECEIVE PRE-AMP
ADC
1 : N
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
8 Detailed Description
8.1 Overview
The LMH6622 is a dual high speed voltage operational amplifier specifically optimized for low noise. The
LMH6622 operates from ±2.5 V to ±6 V in dual supply mode and from +5 V to +12 V in single supply
configuration.
8.2 Functional Block Diagram
Figure 34. xDSL Analog Front End
8.3 Feature Description
• 4.5 V to 12 V supply range
• Large linear output current of 90 mA
• Excellent harmonic distortion of 90 dBc
8.4 Device Functional Modes
• Single or dual supplies
• Traditional voltage feedback topology for maximum flexibility
16 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
UPSTREAM DOWNSTREAM
4.5kHz 30kHz 135kHz 160kHz 1.1MHz
FREQUENCY
POTS
POWER SPECTRUM
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
9 Application and Implementation
9.1 DSL Receive Channel Applications
Figure 35. ADSL Signal Description
The LMH6622 is a dual, wideband operational amplifier designed for use as a DSL line receiver. In the receive
band of a Customer Premises Equipment (CPE) ADSL modem it is possible that as many as 255 Discrete Multi-
Tone (DMT) QAM signals will be present, each with its own carrier frequency, modulation, and signal level. The
ADSL standard requires a line referred noise power density of -140 dBm/Hz within the CPE receive band of 100
KHz to 1.1 MHz. The CPE driver output signal will leak into the receive path because of full duplex operation and
the imperfections of the hybrid coupler circuit. The DSL analog front end must incorporate a receiver pre-amp
which is both low noise and highly linear for ADSL-standard operation. The LMH6622 is designed for the twin
performance parameters of low noise and high linearity.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Links: LMH6622
V1 = 0and V2 =
1
2VT1
-
V1 = VAand
1
2V2 =
1
4VA
-
VOUT = -RF V1
R1
V2
R2
+
RS = RL
N2
-
R2
R2
-VA/2
VT1
1:N 1/2RL
1/2RL
R+
R1
+
-
+
1/2RS
1/2RS
R+
V2
RF
RF
LMH6622
+
-
R1
OUT
IN
LMH6672
-VOUT
+VOUT
VS
+VA/2
V1
DAC +
DAC -
ADC +
ADC -
-
VTN
+
IN OUT
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
DSL Receive Channel Applications (continued)
Applications ranging from +5 V to +12 V or ±2.5 V to ±6 V are fully supported by the LMH6622. In Figure 36, the
LMH6622 is used as an inverting summing amplifier to provide both received pre-amp channel gain and driver
output signal cancellation, that is, the function of a hybrid coupler.
Figure 36. ADSL Receive Applications Circuit
The two RSresistors are used to provide impedance matching through the 1:N transformer.
where
• RLis the impedance of the twisted pair line
• N is the turns ratio of the transformer (1)
The resistors R2and RFare used to set the receive gain of the pre-amp. The receive gain is selected to meet the
ADC full-scale requirement of a DSL chipset.
Resistor R1and R2along with RFare used to achieve cancellation of the output driver signal at the output of the
receiver.
Since the LMH6622 is configured as an inverting summing amplifier, VOUT is found to be,
(2)
The expression for V1and V2can be found by using superposition principle.
When VS= 0,
(3)
When VA= 0,
(4)
18 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
e2TotalOutput = 2 e2o
iinv = inon-inv = in
e2o = A2n [V2n + i2non-inv R+2 + 4kT R+] + i2inv R2F + 4kT RF An
F
n
1 2
R
A 1
R / R
= +
RF
=2NR2VS
VOUT
2
RF
=4NR2VS
VOUT
TN S T1 TN S
1 1 1
V V and V V V
2 N 2N
RF
=2R2VT1
VOUT
-
=RF
VOUT -- VT1
VA
VA
2R2
4R2
2R1
V1 = VAand
1
2V2 =
1
4VA
-
1
2VT1
-
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
DSL Receive Channel Applications (continued)
Therefore,
(5)
And then,
(6)
Setting R1= 2*R2to cancel unwanted driver signal in the receive path, then we have
(7)
We can also find that,
(8)
And then
(9)
In conclusion, the peak-to-peak voltage to the ADC would be,
(10)
9.2 Receive Channel Noise Calculation
The circuit of Figure 36 also has the characteristic that it cancels noise power from the drive channel.
The noise gain of the receive pre-amp is found to be:
(11)
Noise power at each of the output of LMH6622:
where
• Vnis the Input referred voltage noise
• inis the Input referred current noise
• inon-inv is the Input referred non-inverting current noise
• iinv is the Input referred inverting current noise
• k is the Boltzmann’s constant, K = 1.38 x 10−23
• T is the Resistor temperature in k
• R+is the source resistance at the non-inverting input to balance offset voltage, typically very small for this
inverting summing applications (12)
For a voltage feedback amplifier,
(13)
Therefore, total output noise from the differential pre-amp is:
(14)
The factor '2 ' appears here because of differential output.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Links: LMH6622
10k 1M 1G
FREQUENCY (Hz)
0.0
8.0
16
24
GAIN (dB)
100
M
10M
100k
20
12
4.0
2.0
6.0
10
14
18
22
VS= ±5.0V
AV= +9
RC= 110Ω
RF= 500Ω
RL= 1kΩ
100 10k 10M
FREQUENCY (Hz)
30n
38n
46n
54n
1M
100k
1k
50n
42n
34n
32n
36n
40n
44n
48n
52n VS= ±5.0V
AV= +9
RC= 110Ω
RF= 500Ω
RL= 1kΩ
OUTPUT REFERED NOISE (V/ Hz)
AV =2RF
RC
RIN 1
=N2RS
-
+
-
+
RS
VS
1 : N
RIN RC
110:
RF 500:
RF 500:
+VOUT/2
-VOUT/2
LMH6622
LMH6622
TO ADC
x
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
9.3 Differential Analog-to-Digital Driver
Figure 37. Circuit for Differential A/D Driver
The LMH6622 is a low noise, low distortion high speed operational amplifier. The LMH6622 comes in either
SOIC-8 or VSSOP-8 packages. Because two channels are available in each package the LMH6622 can be used
as a high dynamic range differential amplifier for the purpose of driving a high speed analog-to-digital converter.
Driving a 1 kΩload, the differential amplifier of Figure 37 provides 20 dB gain, a flat frequency response up to 6
MHz, and harmonic distortion that is lower than 80 dBc. This circuit makes use of a transformer to convert a
single-ended signal to a differential signal. The input resistor RIN is chosen by the following equation,
(15)
The gain of this differential amplifier can be adjusted by RCand RF,
(16)
See Figure 38 and Figure 39 below for plots related to the discussion of Figure 37.
Figure 38. Frequency Response Figure 39. Total Output Referred Noise Density
20 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
-
R2
R2
-VA/2
VT1
1:N 1/2RL
1/2RL
R+
R1
+
-
+
1/2RS
1/2RS
R+
V2
RF
RF
LMH6622
+
-
R1
OUT
IN
LMH6672
-VOUT
+VOUT
VS
+VA/2
V1
DAC +
DAC -
ADC +
ADC -
-
VTN
+
IN OUT
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
9.4 Typical Application
See Figure 40 for application circuit.
Figure 40. ADSL Receive Applications Circuit
9.4.1 Design Requirements
All normal precautions / considerations with Op Amps apply
9.4.2 Detailed Design Procedure
• Use power supply decoupling capacitors close to supply pins
• Beware of junction temperature rise at elevated ambient temperature and / or heavy output(s) load current
especially at higher supply voltages
• Ground plane near sensitive input pins can be removed to minimize parasitic capacitance
9.4.3 Application Curves
See Figure 38 and Figure 39.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: LMH6622
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
10 Power Supply Recommendations
10.1 Driving Capacitive Load
Capacitive Loads decrease the phase margin of all op amps. The output impedance of a feedback amplifier
becomes inductive at high frequencies, creating a resonant circuit when the load is capacitive. This can lead to
overshoot, ringing and oscillation. To eliminate oscillation or reduce ringing, an isolation resistor can be placed
between the load and the output. In general, the bigger the isolation resistor, the more damped the pulse
response becomes. For initial evaluation, a 50 Ωisolation resistor is recommended.
11 Layout
11.1 Layout Guidelines
11.1.1 Circuit Layout Considerations
Texas Instruments suggests the copper patterns on the evaluation boards listed below as a guide for high
frequency layout. These boards are also useful as an aid in device testing and characterization. As is the case
with all high-speed amplifiers, accepted-practice RFdesign technique on the PCB layout is mandatory. Generally,
a good high frequency layout exhibits a separation of power supply and ground traces from the inverting input
and output pins. Parasitic capacitances between these nodes and ground will cause frequency response peaking
and possible circuit oscillations (see SNOA367, Application Note OA-15, for more information). High quality chip
capacitors with values in the range of 1000 pF to 0.1 μF should be used for power supply bypassing. One
terminal of each chip capacitor is connected to the ground plane and the other terminal is connected to a point
that is as close as possible to each supply pin as allowed by the manufacturer's design rules. In addition, a
tantalum capacitor with a value between 4.7 μF and 10 μF should be connected in parallel with the chip
capacitor. Signal lines connecting the feedback and gain resistors should be as short as possible to minimize
inductance and microstrip line effect. Input and output termination resistors should be placed as close as
possible to the input/output pins. Traces greater than 1 inch in length should be impedance matched to the
corresponding load termination.
Symmetry between the positive and negative paths in the layout of differential circuitry should be maintained so
as to minimize the imbalance of amplitude and phase of the differential signal.
DEVICE PACKAGE EVALUATION BOARD P/N
LMH6622MA SOIC-8 LMH730036
LMH6622MM VSSOP-8 LMH730123
Component value selection is another important parameter in working with high speed/high performance
amplifiers. Choosing external resistors that are large in value compared to the value of other critical components
will affect the closed loop behavior of the stage because of the interaction of these resistors with parasitic
capacitances. These parasitic capacitors could either be inherent to the device or be a by-product of the board
layout and component placement. Moreover, a large resistor will also add more thermal noise to the signal path.
Either way, keeping the resistor values low will diminish this interaction. On the other hand, choosing very low
value resistors could load down nodes and will contribute to higher overall power dissipation and worse
distortion.
22 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
11.2 Layout Examples
11.2.1 SOIC Layout Example
Figure 41. LMH6622 Layout Example - SOIC
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMH6622
LMH6622
SNOS986E –DECEMBER 2001–REVISED JULY 2014
www.ti.com
Layout Examples (continued)
11.2.2 VSSOP Layout Example
Figure 42. LMH6622 Layout Example - VSSOP
24 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6622
LMH6622
www.ti.com
SNOS986E –DECEMBER 2001–REVISED JULY 2014
12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMH6622
PACKAGE OPTION ADDENDUM
www.ti.com 14-Nov-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6622MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
22MA
LMH6622MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
22MA
LMH6622MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A80A
LMH6622MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A80A
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 14-Nov-2017
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6622MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6622MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6622MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6622MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6622MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMH6622MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
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ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-
compliance with the terms and provisions of this Notice.
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