TE Com: Ave/-20/AL PAL20X10A Series AmPAL20L10B/-20/AL XOR Registered 24-pin TTL Programmable Array Logic DISTINCTIVE CHARACTERISTICS @ XOR gates on registered outputs @ Efficlent implementation of counters @ Popular 24-pin architectures: 20L10, 20X10, 20X8, 20X4 = Programmable replacement for high-speed TTL logic @ Power-up reset for initialization MIL: A cH Advanced Micro Devices = Register preioad for testability Easy design with PALASM software Programmable on standard PAL device programmers 24-pin SKINNYDIP and 28-pin PLCC packages save space GENERAL DESCRIPTION The PAL20X10A Series offers Exclusive-OR gates pre- ceding each flip-flop. The XOR gate combines two sum terms, each composed of two product terms. This extra level of logic is very efficient for counter applications. The combinatorial member of the family, the PAL20L10, offers three product terms per output with no XOR gate. A fourth product term provides the enable term. While the registered devices are offered in only one perform- ance option, the 20L10 is offered in four performance grades. Note that three of these options follow the old AMD part numbering system while the fourth follows the old MMI part numbering system, as do the registered devices. The family utilizes Advanced Micro Devices advanced bipolar process and fuse-link technology. The devices provide user-programmable logic for replacing conven- tional SSI/MSI gates and flip-flops at a reduced chip count. The family allows the systems engineer to implement the design on-chip, by opening fuse links to configure AND and OR gates within the device, according to the desired logic function. Complex interconnections be- tween gates, which previously required time-consuming layout, are lifted from the PC board and placed on sili- con, where they can be easily modified during prototyp- ing or production. The PAL device implements the familiar Boolean logic transfer function, the sum of products. The PAL device is a programmable AND array driving a fixed OR array. The AND array is programmed to create custom product terms, while the OR array sums selected terms at the outputs. In addition, the PAL device provides the fotiow- ing options: - Variable input/output pin ratio Programmable three-state outputs Registers with feedback Product terms with all fuses opened assume the logical HIGH state; product terms connected to both true and complement of any single input assume the logical LOW state. Registers consist of D-type flip-flops that are loaded on the LOW-to-HIGH transition of the clock. Un- used input pins should be tied to Vcc or GND. The entire PAL device family is supported by the PALASM software package. The PAL family is pro- grammed on conventional PAL device programmers with appropriate personality and socket adapter mod- ules. See the Programmer Reference Guide for ap- proved programmers. Once the PAL device is pro- grammed and verified an additional fuse may be opened fo prevent pattern readout. This feature secures proprie- tary circuits. PRODUCT SELECTOR GUIDE DEDICATED PRODUCT TERMS/ tep lec DEVICE INPUTS OUTPUTS OUTPUT FEEDBACK ENABLE (ns) | (mA) AmPAL20L10B 15 210 AmPAL20L10-20 12 8 comb. 3 vO prog. 20 165 AmPAL20L10AL 2 comb. 3 - prog. 25 105 PAL20L10A 30 165 PAL20X10A 10 10 reg. 4, XOR reg. pin 30 (ts) | 180 PAL20X8A 10 8 reg. 4, XOR reg. pin 30 180 2 comb. 3 vO prog. PAL20X4A 10 4 reg. 4, XOR reg. pin 30 180 6 comb. 3 vo prog. PAL, PALASM, and SKINNYDIP are registered trademarks of Advanced Micro Devices. Publication # 10308 Rev. B Amendment This part s covered by various U.S. and foreign patents owned by Advanced Micro Devices. . Issue Date: January 1990 2-188BLOCK DIAGRAMS PAL20L10 Inputs 12 Programmable AND Array (40 x 40} 0; Oo Oa VO4 Os 106 VvO7 Oa VOg O10 10303-001A PAL20X10 CLK Inputs 10 <paa Programmable AND Array (40 x 40) 4 ES 10303-002A PAL20X10A Series/AMPAL20L10 2-189BLOCK DIAGRAMS PAL20X8 inputs CLK <padl Programmable AND Array (40 x 40) ts Cr 1 CT t 2 I ul pie 3/6 ale sb U 4 g er O2 O3 O4 VO10 10303-D03A PAL20X4 CLK Inputs OE Vv 10 Y Programmable AND Array (40 x 40) 3 3 3 ; ; 3 3 3 & 4 & 4 Kr K Vy Ly EEG ae 5 6 & 8 8 QO vO, VO2 VO3 O4 Os Os O7 VOg VOg VO10 10303-004A 2-190 PAL20X10A Series/AmPAL20L10CONNECTION DIAGRAMS Top View SKINNYDIP/FLATPACK (Note 1} [_] 1+ as T] Vcc 1, CJ 2 23[_] (NOTE 12) 12 }3 22[_] (NOTE 11) V5 Cl 4 21 | (NOTE 10) 1, (5 20 [_] NOTE 9) ae 19 [_] (NOTE 8) 1, C47 18 [_] (NOTE 7) 1, js 17 [_] {NOTE 6) 1, C9 16 |_] (NOTE 5) 1, L_}10 15 [_] {NOTE 4) le J 14 {NOTE 3) end [7] 12 13 {NOTE 2) 10303-005A Note | 20L10 20X10 20X8 20X4 1 lo CLK CLK CLK 2 14 OE OE OE 3 0; O1 VO; VO; 4 O02 O2 O2 VO2 5 Os Os O3 VO 6 WOa Oa Oa Os 7 VvOs Os Os Os 8 VOs Os Os Os 9 VO7 O7 O7 O7 10 /Os Os Oa er 11 Os Os Og Og 12 O10 Or0 O10 VOr0 PIN DESIGNATIONS PLCC (except AmMPAL20L10) = 8 oa 232 2 4 3 2 1 28 27 26 nc[_|s 25 [_](NOTE 10) laL_]e 24[ J (NOTE 9} LY? 23 _] (NOTE 8) nc[_] 22[_] (NOTE7) 'sL_J9 21{__] wore 6) 8 3 = a a a es vr w E 2 = PLCC AmPAL20L10 only ote 3) [7] (note 4) [| 10303-006A 10303-007A rg} (NOTE 11) NG (NOTE 10) {NOTE 9} CLK Clock 1 (NOTE 8} GND Ground : nore | input f (NOTE 6) vO Input/Output Ne NOTES NC No Connect mores) O Output 1213 (14 s 16 m OE Output Enable 7 3 aa 2 Voc Supply Voltage 222 10303-008A Note: Pin 1 is marked for orientation. PAL20X10A Series/AmPAL20L10 2-191ORDERING INFORMATION Commercial Products (MMI Marking Only) AMD commercial programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: Family Type . Number of Array inputs Output Type Number of Outputs Speed Operating Conditions Package Type . Optional Processing ya-saoop PAL 20 X 10A CNS a, FAMILY TYPE PAL = Programmable Array Logic b. NUMBER OF ARRAY INPUTS c. OUTPUT TYPE X = XOR Registered h. OPTIONAL PROCESSING Blank = Standard Processing g. PACKAGE TYPE NS = 24-Pin 300-mil Plastic L = Active-Low Combinatorial NL AMAL an ape tt = 28-Pin Plastic Leade d. NUMBER OF OUTPUTS Chip Carrier (PL 028) JS = 24-Pin 300-mil Ceramic e. SPEED SKINNYDIP (CD3024) A = 30nstpp f. OPERATING CONDITIONS C = Commercial (0C to +75C) Valid Combinations PAL20L10A PAL20X10A CNS, CNL, PAL20X8A CJS PAL20X4A Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, and to check on newly released combinations. Note: Marked with MMI logo. 2-192 PAL20X10A SeriesORDERING INFORMATION Commercial Products (AMD Marking Only) AMD commercial programmable logic products are available with several ordering options. The order number (Valid Combination) is farmed by a combination of: a. b. c. d. yas AmPAL 20 a. FAMILY TYPE AmPAL = Programmabie Array Logic b. NUMBER OF ARRAY INPUTS c. OUTPUT TYPE L = Active-Low Combinatorial d. NUMBER OF OUTPUTS Family Type Number of Array Inputs Output Type Number of Outputs Speed Power Package Type Operating Conditions Optional Processing L10ALP Cc i. OPTIONAL PROCESSING Blank = Standard Processing h. OPERATING CONDITIONS C = Commercial (0C to +75C) g. PACKAGE TYPE P= 24-Pin 300-mil Plastic SKINNYDIP (PD3024) &. eee on t J = 28-Pin Plastic Leaded = S'PD Chip Carrier (PL 028) B = 1Snstpp D = 24-Pin 300-mil Ceramic A = 25ns tep SKINNYDIP (CD3024) f POWER Blank = Full Power (165-210 mA Icc) L = Low Power (105 mA Icc) Valid Combinations AmPAL20L10 | B, -20, PC, JC, AL DC Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availabitity of specific valid combinations, and to check on newly released combinations. Note: Marked with AMD lago. AmPAL20L10 2-193ORDERING INFORMATION APL Products AMD programmable logic products for Aerospace and Defense applications are available with several ordering op- tions. APL (Approved Products List) products are fully compliant with MIL-STD-883 requirements. The order number (Valid Combination) is formed by a combination of: yoarenaos Family Type Number of Array Inputs Output Type . Number of Outputs Speed Operating Conditions . Package Type . Device Ciass PAL 20 X 10A M JS /883B a. FAMILY TYPE PAL = Programmable Array Logic b. NUMBER OF ARRAY INPUTS OUTPUT TYPE X = XOR Registered L = Active-Low Combinatorial d. NUMBER OF OUTPUTS h. DEVICE CLASS /883B= Class B g. PACKAGE TYPE JS = 24-Pin 300-mil Ceramic SKINNYDIP (CD3024) W = 24-Pin Ceramic Flatpack (CFLO24) L = 28-Pin Ceramic e. SPEED A = 35n8 ted f. OPERATING CONDITIONS M = Military (55C to +125C) Valid Combinations PAL20L10A PAL20X10A MJS/883B, MW/883B, PAL20X8A ML/883B PAL20X4A Group A Tests Leadless Chip Carrier (CL 028) Valid Combinations The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations, and to obtain additional data on AMD's standard military grade products. Note: Marked with MMI logo. Group A Tests consist of Subgroups: 1, 2,3, 7, 8 9, 10, 11. Military Burn-in Military burn-in is in accordance with the current revision of MIL-STD-883, Test Methods 1015, Conditions A through E. Test conditions are selected at AMD's option. 2-194 PAL20X10A SeriesFUNCTIONAL DESCRIPTION Four different devices are available in the 20X10 Series, including both registered and combinatorial devices. All parts are produced with a fuse link at each input to the AND gate array, and connections may be selectively re- moved by applying appropriate voltages to the circuit. Utilizing an easily-implemented programming algo- rithm, these products can be rapidly programmed to any customized pattern. Information on approved program- mers can be found in the Programmer Reference Guide. Extra test words are pre-programmed during manufac- turing to ensure extremely high field programming yields, and provide extra test paths to achieve excellent parametric correlation. Variable Input/Output Pin Ratio The registered devices have ten dedicated input lines, and each combinatorial output is an /O pin. The 20L10 has twelve dedicated input lines, and only eight of the ten combinatorial outputs are I/O pins. Buffers for de- vice inputs have complementary outputs to provide user-programmable input signal polarity. Unused input pins should be tied to Vcc or GND. Programmable Three-State Outputs Each output has a three-state output buffer with three- state contro!. On combinatorial outputs, a product term controls the buffer, allowing enable and disable to be a function of any product of device inputs or output feed- back. The combinatorial output provides a bidirectional VO pin, and may be configured as a dedicated input if the buffer is always disabled. On registered outputs, an input pin controls the enabling of the three-state outputs. Registers with Feedback Registered outputs are provided for data storage and synchronization. Registers are composed of D-type flip- flops that are loaded on the LOW-to-HIGH transition of the clock input. Power-Up Reset All flip-flops power-up to a logic LOW for predictable system initialization. Outputs of the PAL20X10A Series will be HIGH due to the active-low outputs. The Vcc rise must be monotonic and the reset delay time is 1000 ns maximum. Register Preload The register on the PAL20X10A Series can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, making it unnec- essary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and ob- serving proper recovery. Security Fuse After programming and verification, a PAL20X10 Series design can be secured by programming the security fuse. Once programmed, this fuse defeats readback of the internal programmed pattern by a device program- mer, securing proprietary designs from competitors. When the security fuse is programmed, the array will read as if every fuse is intact. For the AmPAL20L10, the array will read as if every fuse is programmed. Pinouts All members of the PAL20X10 Family have the same SKINNYDIP pinouts independent of technology, per- formance, and operating conditions. Because the 24-pin SKINNYDIP requires four no-connects when mapped into the 28-pin PLCC/LCC packages, the PLCC/LCC pinouts can vary. Two different PLCC pinouts are offered. The AmPAL20L10 and all future devices will follow the JEDEC electronics committees standard pinout (JEDEC pinout) with no-connects on pins 1, 8, 15, and 22. The older PAL20X10A Series devices retain their original pinouts, with no-connects on pins 5, 8, 11, and 19. A different LCC pinout is offered for military prod- ucts. The older PAL20X10A Series devices retain their original pinouts, with no-connects on pins 4, 11, 18, and 25. Series Com! Mii PLCC Lec No-connects No-connects. AmPAL20L10 1, 8, 15, 22 N/A B/-20/AL (JEDEC) PAL20X10A Series | 5, 8, 11, 19 4,11, 18, 25 (ine. PAL20L10A) Quality and Testability The PAL20X10 Series offers a very high level of built-in quality. Extra programmable fuses provide a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest pro- gramming yields and post-programming functional yields in the industry. Technology The PAL20X10A Series is fabricated with AMDs ad- vanced junction-isolated bipolar process. The array connections are formed with proven TiW fuses for reli- able operation. The AMPAL20L 10 is fabricated with the IMOX oxide- isolated bipolar process using proven PtSi fuses. PAL20X10A Series/AMPAL20L10 2-195LOGIC DIAGRAM SKINNYDIP (PLCC, PAL20L10A only) Pinouts See Connection Diagrams for LCC and AmMPAL20L10 PLCC Pinouts 20L10 0 34 #%7 8 #1112 1516 1920 2324 2728 3132 3536 39 GND 0 34 78 1112 1516 1920 2324 2728 3132 3536 39 (15) 10303-009A 2-196 PAL20X10A Series/AMPAL20L10LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts See Connection Diagrams for LCC Pinout 20X10 34 7 8 112 1516 1920 2324 2728 3132 3536 39 GND 0 34 78 112 1516 1920 2324 2728 3132 353% 39 10303-010A PAL20X10A Series/AMPAL20L 10 2-197LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts See Connection Diagrams for LCC Pinout 20X8 CLK | 1 0 #34 #7 8 #%112 1516 1920 2324 2728 3132 35 36 [24]Vcc 23] 04g Og Og 07 O06 18] Os 17]O4 16}O3 Og 14] vo, holt (14) (16) ano [12/4 0 34 #78 1112 1516 1920 2324 2728 3132 3536 39 (15) 10303-011A 2-198 PAL20X10A Series/AMPAL20L10LOGIC DIAGRAM SKINNYDIP (PLCC) Pinouts , ee Connection Diagrams for LCC Pinout 20X4 CLK | 1 [24] 0 34 #78 #11112 #1516 1920 2324 2728 3132 35 36 39 Vec 0 34 #7 8 #112 +1516 1920 2324 2728 3132 3536 39 10303-012A PAL20X10A Series/AmMPAL20L10 2-199ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature -65C to +150C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied -55C to +125C Operating in Free Air 0C to +75C Supply Voltage with Supply Voltage (Vcc) Respect to Ground -0.5V 1047.0 V with Respect to Ground +4.75 V to +5.25 V DC Input Voltage 1.5 V to Voc + 0.5 V Operating ranges define those limits between which the func- DC Output or I/O Pin Voltage -0.5V to Vec+0.5V tionality of the device is guaranteed. Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min. | Max. | Unit Von Output HIGH Voltage fon = -3.2 MA Vin = Vin or Vit 2.4 v Vcc = Min. Voi Output LOW Voltage lo =24mA Vin=Vinor Vic 0.5 Vv Voc = Min. Vin Input HIGH Voltage Guaranteed Snput Logical HIGH 2.0 v Voltage for all Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 1) Vi Input Clamp Voltage lin = -18 MA, Voc = Min. -1.5 Vv liq Input HIGH Current Vin = 2.4 V, Vcc = Max. (Note 2) 25 | pA A Input LOW Current Vin = 0.4 V, Vec = Max. (Note 2) -250 | pA li Maximum Input Current Vin = 5.5 V, Vcc = Max. 100 | pA lozH Off-State Output Leakage Vout = 2.4 V, Vcc = Max. 100 | pA Current HIGH Vin = Vin or Vic (Note 2) loze Off-State Output Leakage Vout = 0.4 V, Voc = Max. -100 | pA Current LOW Vin = Vinor Vi (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vcc = Max. -30 | -130 | mA (Note 3) 20X10A, Vin = 0 V, Outputs Open 20X8A, 180 lee Supply Current {lout = 0 MA), Voc = Max.| 20X4A mA 20L10A 165 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. W/O pin leakage is the worst case of I, and fozi (or lin and lozH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-200 PAL20X10A Series (Coml)SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1) Parameter Symbol | Parameter Description Min. {| Max. | Unit tpp Input or Feedback to 20L10A, 20X8A, 30 ns Combinatorial Output 20X4A ts Setup Time from Input or Feedback to Clock 30 ns ty Hold Time 0 ns tco Clock to Output or Feedback 15 ns tw , LOW 20X10A, 20X8A,| 25 ns twr Clock Width HIGH 20X4 15 ns Maximum External Feedback | 1/(ts + tco) 22.2 MHz fax Frequency (Note 2) No Feedback 1/(twH + tw.) 25 MHz tezx GE to Output Enable 20 ns texz OE to Output Disable 20 ns tea Input to Output Enable Using Product Term Control 20L10A, 20X8A, 30 ns {er Input to Output Disable Using Product Term Control 20X4A 30 ns Notes: 1. See Switching Test Circuit for test conditions. 2. These parameters are not 100% tested, but are ca where frequency may be affected. culated at initial characterization and at any time the design is modified PAL20X10A Series (Coml) 2-201ABSOLUTE MAXIMUM RATINGS Storage Temperature -65C to +150C Ambient Temperature with Power Applied -55C to +125C Supply Voltage with Respect to Ground 0.5 Vto+7.0 V DC Input Voitage -15V to55V DC Output or /O Pin Voltage -0.5V to5.5V Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. Absolute Maximum Ratings are for system design reference; parameters given are not tested. OPERATING RANGES Military (M) Devices (Note 1) Ambient Temperature (Ta) Operating in Free Air 55C Min. Operating Case (Tc) Temperature 125C Max. Supply Voltage (Vcc) with Respect to Ground +4.50 V to +5.50 V Operating ranges define those limits between which the func- tionality of the device is guaranteed. Note: 1. Military products are tested at Tc = +25C, +125C, and -55C per MIL-STD-883. DC CHARACTERISTICS over MILITARY operating ranges unless otherwise specified (Note 2) Parameter Symbol Parameter Description Test Conditions Min. | Max. | Unit Vou Output HIGH Voltage low =-2 MA Vin = Vin or Vit 2.4 Vv Vcc = Min. Vor Output LOW Voltage loo =12MA Vin=VinorVic 0.5 Vv Vec = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 Vv Voltage for all Inputs (Note 3) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voltage for all Inputs (Note 3) Vi Input Clamp Voltage lin = 18 MA, Vcc = Min. -1.5 Vv Ny Input HIGH Current Vin = 2.4 V, Voc = Max. (Note 4) 25 | pA he Input LOW Current Vin = 0.4 V, Voc = Max. (Note 4) -250 | WA I Maximum Input Current Vin = 5.5 V, Voc = Max. 1 mA lozH Off-State Output Leakage Vout = 2.4 V, Vcc = Max. 100} pA Current HIGH Vin = Vin or Vit (Note 4) lozt Off-State Output Leakage Vout = 0.4 V, Veco = Max. -100 | pA Current LOW Vin = Vinor Vit (Note 4) Isc Output Short-Circuit Current Vout = 0.5 V, Voc = Max. (Note 5) -30 | -130 ] mA 20X10A, Vin= 0 V, Outputs Open | 20X8A, 180 lec Supply Current (lour = 0 mA), Voc = Max. 20X4A mA 20L10A 165 Notes: 2. For APL Products, Group A, Subgroups 1, 2, and 3 are tested per MIL-STD-883, Method 5005, unless otherwise noted. 3. Vit and Vip are input conditions of output tests and are not themselves directly tested. Vit and ViH are absolute voltages with respect to device ground and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. 4. 1/0 pin leakage is the worst case of li and lozt (or I and lozy). an Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. 2-202 PAL20X10A Series (Mil)SWITCHING CHARACTERISTICS over MILITARY operating ranges (Note 1) Parameter Symbol Parameter Description Min. | Max. | Unit tpp Input or Feedback to 20L10A, 20X8A, 35 ns Combinatorial Output 20X4A ts Setup Time from Input or Feedback to Clock 40 ns ty Hold Time 0 ns tco Clock to Output or Feedback 25 ns we ; LOW 20X10A, 20X8A, 35 ns twa Clock Width HIGH 20X4A 20 ns Maximum External Feedback | 1/(ts + tco) 15.4 MHz fax Frequency (Note 2) No Feedback T/(twu + tw) 18.2 MHz tpzx OE to Output Enable (Note 3) 25 ns texz OE to Output Disable (Note 3) 25 ns tea Input to Output Enable Using Product 35 ns Term Control (Note 3) 201.10A, 20X8A, ter Input to Output Disable Using Product 20X4A 35 ns Term Control (Note 3) Notes: 1. 2. 3. See Switching Test Circuit for test conditions. For APL products Group A, Subgroups 9, 10, and 11 are tested per MIL-STD-883, Method 5005, unless otherwise noted. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. These paramaters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where these parameters may be affected. PAL20X10A Series (Mil) 2-203ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Storage Temperature -65C to +150C Commercial (C) Devices Ambient Temperature with Ambient Temperature (Ta) Power Applied ~55C to +125C Operating in Free Air 0C to +75C Supply Voltage with Supply Voltage (Vcc) Respect to Ground 0.5 V to +7.0V with Respect to Ground +4.75 V to +5.25 V OC Input Voltage 70.5 Vito +5.5 V Operating ranges define those limits between which the func- DC Output or VO Pin Voltage -0.5 V to Vcc Max. tionality of the device is guaranteed. DC tnput Current -30 mA to +5 mA Stresses above those listed under Absolute Maximum Rat- ings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maxi- mum Ratings for extended periods may affect device reliabil- ity. Programming conditions may differ. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified Parameter Symbol! Parameter Description Test Conditions Min. | Max. | Unit Vou Output HIGH Voltage low = -3.2 MA Vin = Vin oF Vit 2.4 Vv Vcc = Min. VoL Output LOW Voltage lo =24mA Vin=Vinor Vit 0.5 Vv Vcc = Min. Vin Input HIGH Voltage Guaranteed Input Logical HIGH 2.0 55 Vv Voltage for ali Inputs (Note 1) Vit Input LOW Voltage Guaranteed Input Logical LOW 0.8 Vv Voitage for all Inputs (Note 1) Vi Input Clamp Voltage lin = 18 MA, Vcc = Min. 1.2 Vv hy Input HIGH Current Vin = 2.7 V, Veco = Max. (Note 2) 25 | pA Ie Input LOW Current Vin = 0.4 V, Voc = Max. (Note 2) -100 LA I Maximum Input Current Vin = 5.5 V, Vec = Max. 1] mA lozH Off-State Output Leakage Vout = 2.7 V, Vec = Max. 100 } pA Current HIGH Vin = Vin or Vit (Note 2) loz Off-State Output Leakage Vout = 0.4 V, Vcc = Max. -100 | pA Current LOW Vin = Vin or Vit (Note 2) Isc Output Short-Circuit Current Vout = 0.5 V, Vcc = Max. (Note 3) -30 ~90 | mA 20L10B 210 lec Supply Current Vin = 0 V, Outputs Open F501 40-20 165 | mA (lout = 0 MA) Vcc = Max. F301. 10AL 105 Notes: 1. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. I/O pin leakage is the worst case of Ii_ and lozt (or lin and lozn). 3. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second. Vout = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 2-204 AmPAL20L10 (Coml)CAPACITANCE (Note 1) Parameter Symbol Parameter Description Test Conditions Typ. Unit Cw Input Capacitance | Pins 1, 13 Vin = 2.0 V Voc = 5.0 V 11 Others Ta = +25C 6 pF Cout Output Capacitance Vout = 2.0 V f=1MHz 9 Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2) Parameter 20L10B 20L10-20 20L10AL Symbol | Parameter Description Min. | Max. | Min. | Max.| Min. | Max.| Unit tpp Input or Feedback to 15 20 25 ns Combinatorial Output tea input to Output Enable Using 18 20 25 ns Product Term Control ter Input to Output Disable Using 15 20 25 ns Product Term Control Notes: 2. See Switching Test Circuit for test conditions. AmPAL20L10 (Coml) 2-205SWITCHING WAVEFORMS Input or Feedback Vr tep Combinatorial Vv Output T 12015-010A Combinatorial Output tWH Clack Vr twe 12015-011A Clock Width VT OE tpxz je tpzx Output i VT 12015-014A OE to Output Disable/Enable Notes: 1Vrat5V 2. Input pulse amplitude 0 V to 3.0 V. 3. Input rise and fall times 2-5 ns typical. input or Feedback Vr ts tH Clock Vr tco Registered Output Vr 12015-0124 Registered Output Input VT ter TEA \\ \k Von- 0.5V 7 Output vo + o5VWAN t 12015-013A Input to Output Disable/Enable 2-206 PAL20X10A Series/AMPAL20L10KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Wilt be Change Changing from H to L from H to L May Wilt be Change Changing from L to H from Lte H Dont Care; Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance Off State KS000010-PAL SWITCHING TEST CIRCUIT Vec S1 Ri Output Test Point : Tq . = ~ 10303-013A Commercial Milita ercial ry Measured Specification S, CL Ri Ro R, Ro Output Value tep, tco Closed 15V tpzx, tea ZH: Open 50 pF 15V Z- L: Closed 20092 | 39002 | 39002 | 7500 texz, ter H->Z: Open 5 pF H + Z: Von- 0.5 V LZ: Closed L>Z:VoL+05V PAL20X10A Series/AmPAL20L10 2-207INPUT/OUTPUT EQUIVALENT SCHEMATICS Input Typical Output o Vcc Voc 12350-020A 40 Q NOM Output Input, Program/Verify/ vo 5 ari Pins Test Circuitry Preload Circuitry 10303-014A 2-208 PAL20X10A Series/AmPAL20L10OUTPUT REGISTER PRELOAD The preload function allows the register to be loaded preload a LOW in the flip-flop. Leave combinatorial from the output pins. This feature aids functional testing outputs floating. of sequential designs by allowing direct setting of output . states. The procedure for. preloading follows. 5. Lower pin 10 to Vir. 1, Raise Voc to Vecu. 6. Remove Vitp/Vinp from all registered output pins. 2. Set GE to Viup to disable output registers. 7. Lower OE to Vip to enable the output registers. 3. Raise pin 10 to Vin to enter preload mode. 8. Verify VoL/Vou atall registered output pins. Note that because of the output inverter, a register that has 4. Apply either Vine or Vip to all registered outputs. Use been preloaded HIGH will provide a LOW at the Vine to preload a HIGH in the flip-flop; use Vitp to output. Parameter Symbol Parameter Description Min. Rec. Max. | Unit ViuH Super-level input voltage 19 20 21 Vv Vite Low-level input voltage 0 0 0.5 Vv VinP High-level input voltage 2.4 5.0 5.5 Vv Vecu Power supply during preload 45 Vv to Delay time 100 200 1000 ns to to to to to OE / N ViHP _ Vip Pin 10 yj N a po _| _/ \ a oo ViHP Registered Vou Output \ VoL Ad VILP 10303-015A Output Register Preload Waveform PAL20X10A Series/AMPAL20L10 2-209POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will be HIGH due to the inverting output buffer. This feature is valuable in simplifying state ma- chine initialization. A timing diagram and parameter ta- ble are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways Vcc can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: 1. The Vcc rise must be monotonic. 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feed- back setup times are met. Parameter Symbol Parameter Description Max. Unit tpr Power-up Reset Time 1000 ns ts Input or Feedback Setup Time See Switching tw. Clock Width LOW Characteristics 4V Vee Power tpr + Registered V Active-Low / /7 Output t r+ ts Clock \\t 12350-024A Power-Up Reset Waveform 2-210 PAL20X10A Series/AMPAL20L10