TLE42754
Low Dropout Linear Fixed Voltage Regulator
Data Sheet, Rev. 1.0, May 2008
Automotive Power
Type Package Marking
TLE42754D PG-TO252-5 TLE42754D
TLE42754G PG-TO263-5 TLE42754G
PG-TO252-5
PG-TO263-5
Data Sheet 2 Rev. 1.0, 2008-05-29
Low Dropout Linear Fixed Voltage Regulator
TLE42754
1Overview
Features
• Output Voltage 5 V ± 2%
• Ouput Current up to 450 mA
• Very low Current Consumption
• Power-on and Undervoltage Reset with Programmable Delay Time
• Reset Low Down to VQ = 1 V
• Very Low Dropout Voltage
• Output Current Limitation
• Reverse Polarity Protection
• Overtemperature Protection
• Suitable for Use in Automotive Electronics
• Wide Temperature Range from -40 °C up to 150 °C
• Input Voltage Range from -42 V to 45 V
• Green Product (RoHS compliant)
• AEC Qualified
Description
The TLE42754 is a monolithic integrated low-dropout voltage
regulator in a 5-pin TO-package, especially designed for automotive
applications. An input voltage up to 42 V is regulated to an output
voltage of 5.0 V. The component is able to drive loads up to
450 mA. It is short-circuit proof by the implemented current limitation
and has an integrated overtemperature shutdown. A reset signal is
generated for an output voltage VQ,rt of typically 4.65 V. The power-on
reset delay time can be programmed by the external delay capacitor.
Dimensioning Information on External Components
An input capacitor CI is recommended for compensation of line
influences. An output capacitor CQ is necessary for the stability of the
control loop.
Data Sheet 3 Rev. 1.0, 2008-05-29
TLE42754
Overview
Circuit Description
The control amplifier compares a reference voltage to a voltage that is proportional to the output voltage and drives
the base of the series transistor via a buffer. Saturation control as a function of the load current prevents any
oversaturation of the power element. The component also has a number of internal circuits for protection against:
• Overload
• Overtemperature
• Reverse polarity
TLE42754
Block Diagram
Data Sheet 4 Rev. 1.0, 2008-05-29
2 Block Diagram
Figure 1 Block Diagram
Reset
Generator
Bandgap
Reference
Pr otection
Circuits
GND D
Q
RO
I
TLE42754
Data Sheet 5 Rev. 1.0, 2008-05-29
TLE42754
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment TLE42754D (PG-TO252-5) and TLE42754G (PG-TO263-5)
Figure 2 Pin Configuration (top view)
3.2 Pin Definitions and Functions TLE42754D (PG-TO252-5) and TLE42754G (PG-
TO263-5)
Pin Symbol Function
1I Input
for compensating line influences, a capacitor to GND close to the IC terminals is
recommended
2RO Reset Output
open collector output; external pull-up resistor to a positive potential required;
leave open if the reset function is not needed
3GND TLE42754G (PG-TO263-5) only: Ground
internally connected to tab
4D Reset Delay Timing
connect a ceramic capacitor to GND for adjusting the reset delay time;
leave open if the reset function is not needed
5Q Output
block to GND with a capacitor close to the IC terminals, respecting the values given
for its capacitance CQ and ESR in the table “Functional Range” on Page 7
TAB GND Ground
connect to heatsink area
AEP02580
15
ROΙDQ
GND
GND
RO
Ι
IEP02528
D
Q
P-TO252-5 (D-PAK) P-TO263-5 (D²-PAK)
TLE42754
General Product Characteristics
Data Sheet 6 Rev. 1.0, 2008-05-29
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
-40 °C ≤ Tj ≤ 150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Input
4.1.1 Voltage VI-42 45 V –
Output
4.1.2 Voltage VQ-0.3 7 V –
Reset Output
4.1.3 Voltage VRO -0.3 25 V –
Reset Delay
4.1.4 Voltage VD-0.3 7 V –
Temperature
4.1.5 Junction Temperature Tj-40 150 °C–
4.1.6 Storage Temperature Tstg -50 150 °C–
ESD Absorption
4.1.7 ESD Absorption VESD,HBM -2 2 kV Human Body
Model (HBM)2)
2) ESD HBM Test according JEDEC JESD22-A114
4.1.8 VESD,CDM -500 500 V Charge Device
Model (CDM)3)
3) ESD CDM Test according AEC/ESDA ESD-STM5.3.1-1999
4.1.9 -750 750 V Charge Device
Model (CDM)3) at
corner pins
Data Sheet 7 Rev. 1.0, 2008-05-29
TLE42754
General Product Characteristics
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
4.2.1 Input Voltage VI5.5 42 V –
4.2.2 Output Capacitor’s Requirements
for Stability
CQ22 – µF –1)
1) the minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%
ESR(CQ)–3Ω–2)
2) relevant ESR value at f=10kHz
4.2.3 Junction Temperature Tj-40 150 °C–
TLE42754
General Product Characteristics
Data Sheet 8 Rev. 1.0, 2008-05-29
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Value Unit Conditions
Min. Typ. Max.
TLE42754D (PG-TO252-5)
4.3.4 Junction to Case1)
1) not subject to production test, specified by design
RthJC –3.7–K/W–
4.3.5 Junction to Ambient1) RthJA –27–K/W
2)
2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The Product
(Chip+Package) was simulated on a 76.2 x 114.3 x 1.5 mm³ board with 2 inner copper layers (2 x 70µm Cu, 2 x 35µm Cu).
Where applicable a thermal via array under the exposed pad contacted the first inner copper layer.
4.3.6 – 110 – K/W footprint only3)
3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The Product
(Chip+Package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 1 copper layer (1 x 70µm Cu).
4.3.7 – 57 – K/W 300 mm2 heatsink area
on PCB3)
4.3.8 – 42 – K/W 600 mm2 heatsink area
on PCB3)
TLE42754G (PG-TO263-5)
4.3.9 Junction to Case1) RthJC –3.7–K/W–
4.3.10 Junction to Ambient1) RthJA –27–K/W
2)
4.3.11 – 70 – K/W footprint only3)
4.3.12 – 42 – K/W 300 mm2 heatsink area
on PCB3)
4.3.13 – 33 – K/W 600 mm2 heatsink area
on PCB3)
Data Sheet 9 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5 Block Description and Electrical Characteristics
5.1 Voltage Regulator
The output voltage VQ is controlled by comparing a portion of it to an internal reference and driving a PNP pass
transistor accordingly. The control loop stability depends on the output capacitor CQ, the load current, the chip
temperature and the poles/zeros introduced by the integrated circuit. To ensure stable operation, the output
capacitor’s capacitance and its equivalent series resistor ESR requirements given in the table “Functional
Range” on Page 7 have to be maintained. For details see also the typical performance graph “Output Capacitor
Series Resistor ESR(CQ) versus Output Current IQ” on Page 12. As the output capacitor also has to buffer
load steps it should be sized according to the application’s needs.
An input capacitor CI is strongly recommended to compensate line influences. Connect the capacitors close to the
component’s terminals.
A protection circuitry prevent the IC as well as the application from destruction in case of catastrophic events.
These safeguards contain an output current limitation, a reverse polarity protection as well as a thermal shutdown
in case of overtemperature.
In order to avoid excessive power dissipation that could never be handled by the pass element and the package,
the maximum output current is decreased at input voltages above VI=28V.
The thermal shutdown circuit prevents the IC from immediate destruction under fault conditions (e.g. output
continuously short-circuited) by switching off the power stage. After the chip has cooled down, the regulator
restarts. This leads to an oscillatory behaviour of the output voltage until the fault is removed. However, junction
temperatures above 150 °C are outside the maximum ratings and therefore significantly reduce the IC’s lifetime.
The TLE42754 allows a negative supply voltage. In this fault condition, small currents are flowing into the IC,
increasing its junction temperature. This has to be considered for the thermal design, respecting that the thermal
protection circuit is not operating during reverse polarity conditions.
Figure 3 Voltage Regulator
Bandgap
Reference
GND
QI
BlockDiagram_VoltageR egulator.vsd
Satu ration Con tro l
Cu rre n t L imitation
Temperature
Shutdown
C
Q
ESR
C}LOAD
Supply
C
I
Regulated
Output Voltage
I
Q
I
I
TLE42754
Block Description and Electrical Characteristics
Data Sheet 10 Rev. 1.0, 2008-05-29
Electrical Characteristics Voltage Regulator
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.1.1 Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 450 mA
9V < VI < 28 V
5.1.2 Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 400 mA
6V < VI < 28 V
5.1.3 Output Voltage VQ4.9 5.0 5.1 V 1 mA < IQ < 200 mA
6V < VI < 40 V
5.1.4 Output Current Limitation IQ,max 450 – 1100 mA VQ = 4.8V
5.1.5 Load Regulation
steady-state
∆VQ,load -30 -15 – mV IQ= 5 mA to
400 mA
VI = 8 V
5.1.6 Line Regulation
steady-state
∆VQ,line –515mVVI = 8 V to 32 V
IQ = 5 mA
5.1.7 Dropout Voltage1)
Vdr = VI - VQ
1) measured when the output voltage VQ has dropped 100mV from the nominal value obtained at VI = 13.5V
Vdr – 250 500 mV IQ = 300 mA
5.1.8 Power Supply Ripple Rejection2)
2) not subject to production test, specified by design
PSRR –60–dBfripple = 100 Hz
Vripple = 0.5 Vpp
5.1.9 Temperature Output Voltage Drift dVQ/dT–0.5–mV/K–
5.1.10 Overtemperature Shutdown
Threshold
Tj,sd 151– 200°C Tj increasing2)
5.1.11 Overtemperature Shutdown
Threshold Hysteresis
Tj,sdh –20–°CTj decreasing2)
Data Sheet 11 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Typical Performance Characteristics Voltage Regulator
Output Voltage VQ versus
Junction Temperature Tj
Output Current IQ versus
Input Voltage VI
Power Supply Ripple Rejection PSRR versus
ripple frequency fr)
Line Regulation ∆VQ,line versus
Input Voltage Change ∆VI)
01_VQ_TJ.VSD
4,60
4,70
4,80
4,90
5,00
5,10
5,20
-40 0 40 80 120 160
T
j [°C]
V
Q
[V]
V
I
= 13.5 V
I
Q
= 50 mA
02_IQ_VI.VSD
0
100
200
300
400
500
600
700
800
900
1000
0 1020304050
V
I
[V]
I
Q,max
[mA]
T
j
= -40 °C
T
j
= 150 °C
T
j
= 25 °C
03_PSRR_FR.VSD
0
10
20
30
40
50
60
70
80
90
100
0,01 0,1 1 10 100 1000
f
[kHz]
PSRR
[dB]
T
j
= 150 °C
T
j
= 25 °C
T
j
= -40 °C
I
Q
= 10 mA
C
Q
= 22 µF
ceramic
V
I
= 13.5 V
V
ripple
= 0.5 Vpp
04_DVQ_DVI.VSD
0
1
2
3
4
5
6
7
8
9
0 10203040
V
I
[V]
∆
V
Q
[mV]
T
j = 150 °C
T
j = 25 °C
T
j = -40 °C
TLE42754
Block Description and Electrical Characteristics
Data Sheet 12 Rev. 1.0, 2008-05-29
Load Regulation ∆VQ,load versus
Output Current Change ∆IQ
Output Capacitor Series Resistor ESR(CQ) versus
Output Current IQ
Dropout Voltage Vdr versus
Junction Temperature Tj
05_DVQ_DIQ.VSD
-25
-20
-15
-10
-5
0
0 100 200 300 400 500
I
Q
[mA]
∆
V
Q
[mV]
V
I
= 8 V
T
j
= -40 °C
T
j
= 25 °C
T
j
= 150 °C
06_ESR_IQ.VSD
0,01
0,1
1
10
100
1000
0 100 200 300 400 500
I
Q [mA]
ESR(C
Q
)
[Ω]
CQ
= 22 µF
Tj
= -40..150 °C
V
I
= 6..28 V
Stable
Region
Unstable
Region
07_VDR_TJ.VSD
0
50
100
150
200
250
300
350
400
450
500
-40 0 40 80 120 160
T
j
[°C]
V
DR
[mV]
I
Q
= 400 mA
I
Q
= 300 mA
I
Q
= 100 mA
I
Q
= 10 mA
Data Sheet 13 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.2 Current Consumption
Electrical Characteristics Current Consumption
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.1 Current Consumption
Iq = II - IQ
Iq–150200µAIQ = 1 mA
Tj = 25 °C
5.2.2 – 150 220 µA IQ = 1 mA
Tj = 85 °C
5.2.3 – 5 10 mA IQ = 250 mA
5.2.4 – 15 25 mA IQ = 400 mA
TLE42754
Block Description and Electrical Characteristics
Data Sheet 14 Rev. 1.0, 2008-05-29
Typical Performance Characteristics Current Copnsumption
Current Consumption Iq versus
Output Current IQ (IQ low)
Current Consumption Iq versus
Output Current IQ
Current Consumption Iq versus
Input Voltage VI
08_IQ_IQ_IQLOW.VSD
0
1
2
3
4
5
6
7
0 50 100 150 200
I
Q
[mA]
I
q
[mA]
T
j
= 150 °C
T
j
= 25 °C
V
I
= 13.5 V
09_IQ_IQ.VSD
0
5
10
15
20
25
30
0 100 200 300 400 500
I
Q
[mA]
I
q
[mA]
T
j
= 150 °C
T
j
= 25 °C
V
I
= 13.5 V
10_IQ_VI.VSD
0
10
20
30
40
50
60
0 10203040
V
I
[V]
I
q
[mA]
R
LOAD
= 12.5 Ω
R
LOAD
= 500 Ω
Data Sheet 15 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
5.3 Reset Function
The reset function provides several features:
Output Undervoltage Reset:
An output undervoltage condition is indicated by setting the Reset Output RO to “low”. This signal might be used
to reset a microcontroller during low supply voltage.
Power-On Reset Delay Time:
The power-on reset delay time trd allows a microcontoller and oscillator to start up. This delay time is the time frame
from exceeding the reset switching threshold VRT until the reset is released by switching the reset output “RO” from
“low” to “high”. The power-on reset delay time trd is defined by an external delay capacitor CD connected to pin D
charged by the delay capacitor charge current ID,ch starting from VD=0V.
If the application needs a power-on reset delay time trd different from the value given in Item 5.3.6, the delay
capacitor’s value can be derived from the specified values in Item 5.3.6 and the desired power-on delay time:
with
•CD: capacitance of the delay capacitor to be chosen
•trd,new: desired power-on reset delay time
•trd: power-on reset delay time specified in this datasheet
For a precise calculation also take the delay capacitor’s tolerance into consideration.
Reset Reaction Time:
The reset reaction time avoids that short undervoltage spikes trigger an unwanted reset “low” signal. The reset
reaction rime trr considers the internal reaction time trr,int and the discharge time trr,d defined by the external delay
capacitor CD (see typical performance graph for details). Hence, the total reset reaction time becomes:
with
•trr: reset reaction time
•trr,int: internal reset reaction time
•trr,d: reset discharge
Reset Output Pull-Up Resistor RRO:
The Reset Output RO is an open collector output requiring an external pull-up resistor to a voltage VIO, e.g. VQ. In
Table “Electrical Characteristics Reset Function” on Page 18 a minimum value for the external resistor RRO
is given for the case it is connected to VQ or to a voltage VIO < VQ. If the pull-up resistor shall be connected to a
voltage VIO > VQ, use the following formula:
CD
trd new,
trd
---------------- 47nF×=
trr trd int,trr d,
+=
RRO
5kΩ
VQ
-----------VIO
×=
TLE42754
Block Description and Electrical Characteristics
Data Sheet 16 Rev. 1.0, 2008-05-29
Figure 4 Block Diagram Reset Function
GND
QI
BlockDiagram_Res et.vsd
Supply
RO
V
DST
Int.
Supply
I
D,ch
I
DR,dsch
V
RT
Control
D
C
D
Reset
C
Q
VDD
Micro-
Controller
GND
I
RO
R
RO
Data Sheet 17 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Figure 5 Timing Diagram Reset
V
I
t
V
Q
t
V
RT
V
RO
T i min g Di a g r a m_ Re se t. v
s
t
V
RO,low
1 V
1V
t
rr,total
t
rd
Ther m al
Shutdown
Input
Voltage Dip
t
rr,total
t
rd
t
rd
t < t
rr,total
t
rd
Under-
voltage
Spike at
output
Over-
load
t
rr,total
V
DRL
V
DU
t
V
D
TLE42754
Block Description and Electrical Characteristics
Data Sheet 18 Rev. 1.0, 2008-05-29
Electrical Characteristics Reset Function
VI = 13.5 V, -40 °C ≤ Tj ≤ 150 °C, all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Output Undervoltage Reset
5.3.1 Output Undervoltage Reset
Switching Thresholds
VRT 4.5 4.65 4.8 V VQ decreasing
Reset Output RO
5.3.2 Reset Output Low Voltage VRO,low –0.20.4V1V ≤ VQ ≤ VRT ;
IRO = 0.2 mA
5.3.3 Reset Output
Sink Current Capability
IRO,max 0.2 – – mA 1 V ≤ VQ ≤ VRT ;
VRO = 5 V
5.3.4 Reset Output
Leakage Current
IRO,leak –010µAVRO = 5 V
5.3.5 Reset Output External
Pull-up Resistor to VQ
RRO 5––kΩ1V ≤ VQ ≤ VRT ;
VRO ≤ 0.4 V
Reset Delay Timing
5.3.6 Power On Reset Delay Time trd 10 16 22 ms CD = 47 nF
5.3.7 Upper Delay
Switching Threshold
VDU –1.8–V–
5.3.8 Lower Delay
Switching Threshold
VDRL –0.65–V–
5.3.9 Delay Capacitor
Charge Current
ID,ch –5.5–µAVD = 1 V
5.3.10 Delay Capacitor
Reset Discharge Current
ID,dch – 100 – mA VD = 1 V
5.3.11 Delay Capacitor
Discharge Time
trr,d – 0.5 1 µs Calculated Value:
trr,d = CD*(VDU -
VDRL)/ ID,dch
CD = 47 nF
5.3.12 Internal Reset Reaction Time trr,int –47µsCD = 0 nF1)
1) parameter not subject to production test; specified by design
5.3.13 Reset Reaction Time trr,total – 4.5 8 µs Calculated Value:
trr,total = trr,int + trr,d
CD = 47 nF
Data Sheet 19 Rev. 1.0, 2008-05-29
TLE42754
Block Description and Electrical Characteristics
Typical Performance Characteristics
Undervoltage Reset Switching Threshold
VRT versus Tj
Power On Reset Delay Time trd versus
Junction Temperature Tj
Power On Reset DelayTime trd versus
Capacitance CD
Internal Reset Reaction Time trr,int versus Junction
Temperature Tj
11_VRT_T J.VSD
4,4
4,5
4,6
4,7
4,8
4,9
5
-40 0 40 80 120 160
T
j
[°C]
V
RT
[V]
12_TRD_TJ.VSD
0
2
4
6
8
10
12
14
16
18
20
-40 0 40 80 120 160
Tj
[°C]
trd
[ms]
C
D
= 47 nF
13_TRD_CD.VSD
0
10
20
30
40
50
60
70
80
90
0 50 100 150 200 250
CD
[nF]
trd
[ms]
T
j
= -40 °C
T
j
= 25 °C
T
j
= 150 °C
14_TRRINT_T J.VSD
0
0,5
1
1,5
2
2,5
3
3,5
-40 0 40 80 120 160
Tj
[°C]
trr,int
[µs]
TLE42754
Block Description and Electrical Characteristics
Data Sheet 20 Rev. 1.0, 2008-05-29
Delay Capacitor Discharge Time trr,d versus
Junction Temperature Tj
15_TRRD_TJ.VSD
0
0,1
0,2
0,3
0,4
0,5
0,6
-40 0 40 80 120 160
Tj
[°C]
trr,d
[µs]
CD
= 47 nF
Data Sheet 21 Rev. 1.0, 2008-05-29
TLE42754
Package Outlines
6 Package Outlines
Figure 6 PG-TO252-5
1) Includes mold flashes on each side.
4.56 0.25
M
A
6.5
5.7 MAX.
±0.1
per side
0.15 MAX.
-0.2
6.22
±0.5
9.98
(4.24) 1
A
1.14
5 x 0.6
±0.15
0.8
±0.1
+0.15
-0.05
0.1
B
-0.04
+0.08
0...0.15
0.51 MIN.
0.5
B
2.3 -0.10
0.5
+0.05
-0.04
+0.08
(5)
-0.01
0.9 +0.20
B
1)
All metal surfaces tin plated, except area of cut.
TLE42754
Package Outlines
Data Sheet 22 Rev. 1.0, 2008-05-29
Figure 7 PG-TO263-5
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
BA0.25
M
±0.2
GPT09113
10
8.5
1)
(15)
±0.2
9.25 ±0.3
1
0...0.15
5 x 0.8
±0.1
±0.1
1.27
4.4
B
0.5
±0.1
±0.3
2.7
4.7 ±0.5
2.4
1.7
0...0.3 A
1)
7.55
4 x
All metal surfaces tin plated, except area of cut.
Metal surface min. X = 7.25, Y = 6.9
Typical
1)
0.1 B
0.1
0.05
8˚ MAX.
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
Edition 2008-05-29
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2008 Infineon Technologies AG
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties
and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights
of any third party.
Information
For further information on technology, delivery terms and conditions and prices, please contact the nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous substances. For information on the types in
question, please contact the nearest Infineon Technologies Office.
Infineon Technologies components may be used in life-support devices or systems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
