SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
High-Impedance State During Power Up
and Power Down
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
Ioff and Power-Up 3-State Support Hot
Insertion
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK),
Ceramic Flat (W) Packages, and Ceramic
(J) DIPs
description
These octal buffers and line drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The ’LVT244B is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low ,
the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54LVT244B is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT244B is characterized for operation from –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
SN54LVT244B ...J OR W PACKAGE
SN74LVT244B . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
SN54LVT244B . . . FK PACKAGE
(TOP VIEW)
2Y4
1A1
1OE
1Y4
2A2 2OE
2Y1
GND
2A1 VCC
SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
(each 4-bit buffer)
INPUTS OUTPUT
OE AY
L H H
LLL
H X Z
logic symbol†
2
1A1 4
1A2 6
1A3 8
1A4
EN
1
1Y1
18
1Y2
16
1Y3
14
1Y4
12
11
2A1 13
2A2 15
2A3 17
2A4
EN
19
2Y1
9
2Y2
7
2Y3
5
2Y4
3
1OE 2OE
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
218
1Y1
1OE
1A1
416
1Y2
1A2
614
1Y3
1A3
812
1Y4
1A4
19
11 9 2Y1
2OE
2A1
13 7 2Y2
2A2
15 5 2Y3
2A3
17 3 2Y4
2A4
SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO: SN54LVT244B 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74LVT244B 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2): SN54LVT244B 48 mA. . . . . . . . . . . . . . . . . . . . . . .
SN74LVT244B 64 mA. . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVT244B SN74LVT244B
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current –24 –32 mA
IOL Low-level output current 48 64 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications
of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT244B SN74LVT244B
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
VOH
VCC = 2.7 V, IOH = –8 mA 2.4 2.4
V
V
OH
VCC =3V
IOH = –24 mA 2
V
V
CC =
3
V
IOH = –32 mA 2
VCC =27V
IOL = 100 µA 0.2 0.2
V
CC =
2
.
7
V
IOL = 24 mA 0.5 0.5
VOL
IOL = 16 mA 0.4 0.4
V
V
OL
VCC =3V
IOL = 32 mA 0.5 0.5
V
V
CC =
3
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
II
Control inputs VCC = 3.6 V, VI = VCC or GND ±1±1
µA
I
I
Data in
p
uts
VCC =36V
VI = VCC 1 1 µ
A
Data
inp
u
ts
V
CC =
3
.
6
V
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
IOZH VCC = 3.6 V, VO = 3 V 5 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V –5 –5 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 µA
VCC
=
3.6 V,
Outputs high 0.19 0.19
ICC
VCC
=
3
.
6
V
,
IO = 0, Outputs low 5 5 mA
VI = VCC or GND Outputs disabled 0.19 0.19
∆ICC‡VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND 0.3 0.2 mA
CiVI = 3 V or 0 4 4 pF
CoVO = 3 V or 0 7 7 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT244B SN74LVT244B
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
A
Y
1 3.6 3.9 1.1 2.3 3.5 3.8
ns
tPHL
A
Y
1.2 3.4 3.6 1.3 2.1 3.3 3.6
ns
tPZH
OE
Y
1 4.6 5.5 1.1 2.5 4.5 5.3
ns
tPZL
OE
Y
1.3 4.5 5.1 1.4 2.7 4.4 4.9
ns
tPHZ
OE
Y
1.8 4.5 4.7 1.9 2.8 4.4 4.5
ns
tPLZ
OE
Y
1.7 4.5 4.6 1.8 2.9 4.4 4.4
ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT244B, SN74LVT244B
3.3-V ABT OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS354F – FEBRUARY 1994 – REVISED APRIL 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input 1.5 V 2.7 V
0 V
1.5 V 1.5 V
2.7 V
0 V
2.7 V
0 V
1.5 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
1.5 V 1.5 V 2.7 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
3 V
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
≈ 0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 . 5 n s, t f≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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Copyright 2000, Texas Instruments Incorporated
